JP2006050145A - Transimpedance amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transimpedance amplifier capable of realizing high sensitivity and a wide input dynamic range and of realizing instantaneous response corresponding to burst data. <P>SOLUTION: The transimpedance amplifier has a transimpedance amplifier core circuit 210, in which an input terminal is connected to a signal input terminal; a transimpedance amplifier core circuit 220, in which the same configuration as that of the circuit 210 is provided and an input terminal is opened; an intermediate stage buffer circuit 230, in which the output terminals of both the circuits 210, 220 are each connected to a differential input terminal; and a hysteresis comparator 251 in which the differential output terminal of the intermediate stage buffer circuit is connected to a differential input terminal. The amplifier is provided with a gain switch deciding circuit 250 for switching gains of both the circuit 210, 220. Both the circuits 210, 220 are each allowed to be provided with a feedback resistance, and the values of the feedback resistance are switched by the hysteresis comparator 251 of the circuit 250, in response to the differential output signal of the circuit 230. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a transimpedance amplifier that receives a current signal photoelectrically converted by a light receiving element in a light receiving circuit and converts and amplifies it into a voltage signal, and more particularly to a transimpedance amplifier that can handle an input current having a large dynamic range. is there.

  This transimpedance amplifier is an optical receiver circuit that converts an optical signal into an electrical signal in an optical transmission circuit such as an optical transmission system, optical interconnection, or passive optical network (hereinafter referred to as PON) system that enables high-speed data transmission. Applies to

  The transimpedance amplifier receives a current Iin obtained by photoelectrically converting a received optical signal by a light receiving element, converts the current Iin into a voltage Vout by a transimpedance gain (proportional to the value of a feedback resistor), and outputs the voltage Vout. However, when the input current Iin increases, the amplitude of the output voltage Vout is saturated and waveform distortion occurs.

  In order to achieve both high sensitivity and wide dynamic range characteristics, the conventional transimpedance amplifier reduces the transimpedance gain by reducing the value of the feedback resistance when the input current Iin increases, so that even when a large current is input, An output voltage Vout with little distortion is obtained.

  FIG. 7 shows a basic configuration of a conventional transimpedance amplifier 300 (see, for example, Non-Patent Document 1). The transimpedance amplifier 300 includes a gain switching circuit 312 and an amplification circuit 311. The transimpedance amplifier 300 receives the output current Iin of the light receiving element 100, converts the voltage, and performs signal amplification. The gain switching circuit 312 has a configuration in which a feedback resistor RF and a diode D1 are connected in parallel.

  In the transimpedance amplifier 300, when the input current Iin increases, the voltage difference between the input terminal and the output terminal of the amplifier circuit 311 increases, and the diode D1 inserted in parallel with the feedback resistor RF is turned on, which is equivalent. When the value of the feedback resistor is lowered, the transimpedance gain is lowered so that the output voltage Vout is not saturated at a large current.

  FIG. 8 shows a basic configuration of another conventional transimpedance amplifier 400 configured to switch a plurality of feedback resistors rather than based on ON / OFF of a diode as a gain switching circuit (see, for example, Patent Document 1). The transimpedance amplifier 400 includes a gain switching circuit 412 and an amplifier circuit 411. The transimpedance amplifier core circuit 410 performs input signal conversion of the output current Iin of the light receiving element 100 to perform signal amplification, and a transimpedance amplifier core circuit. The gain switching determination circuit 420 controls the switching of the gain switching circuit 412 according to the output voltage Vout 410.

  In this transimpedance amplifier 400, the gain switching circuit 412 includes a plurality of feedback resistors connected in series, and the switching signal obtained by monitoring the DC level of the output voltage Vout of the amplifier circuit 411 by the gain switching determination circuit 420. Thus, the value of the feedback resistor is switched by turning on / off the switch of the gain switching circuit 412.

Saruwatari, Sugawara, Ibe, "Optical receiver for 156 Mbps burst signal", IEICE General Conference, Proceedings, 1997, B-10-128 Japanese Patent No. 3259707 (Japanese Patent Laid-Open No. 2000-252774)

  Incidentally, an optical transmission system that enables high-speed data transmission, particularly a PON system, requires high sensitivity, a wide input dynamic range, and burst response.

  FIG. 10A shows the configuration of the PON system. In the PON system, a plurality of home side devices (ONUs) 5021 to 502n are connected to one station side device (OLT) 501, and the connection is connected by a passive device such as an optical coupler 503. Reference numeral 504 denotes an optical fiber.

  For this reason, the upstream (from ONU to OLT) data from each of the home-side devices 5021 to 502n has different optical powers when reaching the station-side device 501 due to the difference in each route. For this reason, a wide dynamic range is required for the optical receiving circuit of the station side apparatus 501.

  In the PON system of FIG. 10 (a), while one home device is sending data (packet period), other home devices cannot send data. It is necessary to shorten the time. As shown in FIG. 10B, a specific bit called a preamble 511 is prepared at the head of the packet 510 and is used for packet synchronization by the station side device 501. The signal amplitude is different for each packet 510.

  In order to increase the transmission efficiency, it is necessary to synchronize packets with a short preamble bit. For this purpose, an optical receiver circuit capable of instantaneously switching the gain with a short preamble bit is required. For this reason, the optical receiving circuit is required to have a transimpedance amplifier capable of instantaneous response and having a wide dynamic range.

  In this regard, the conventional transimpedance amplifier 300 described with reference to FIG. 7 has a configuration in which the diode D1 is inserted in parallel with the feedback resistor RF. Therefore, when the input current Iin increases, the DC transfer characteristic of the output voltage Vout is improved. A large distortion occurs, and the duty of the waveform of the output voltage Vout deteriorates. When the duty characteristic is deteriorated, there is a problem that a code error occurs and the transmission characteristic is deteriorated.

  In addition, the conventional transimpedance amplifier 400 described with reference to FIG. 8 can solve the problem of distortion of the DC transfer characteristic, but the gain switching determination circuit 420 normally determines the output voltage Vout of the transimpedance amplifier 400. The high level and the low level are held by the high level hold circuit and the low level hold circuit, respectively, and the switching determination is performed by identifying that the potential difference has become a certain level or more by the comparator 423 or the like. It takes less time response.

  That is, the high level hold circuit is composed of an operational amplifier 421, a capacitor C1, and a diode D2, and the low level hold circuit is composed of an operational amplifier 422, a capacitor C2, and a diode D3. Although it is necessary to give C2 a large capacity, in that case, it takes time until the capacitors C1 and C2 are charged, and instantaneous response becomes difficult. Further, when the capacitors C1 and C2 are configured in the LSI, the layout area becomes large.

  Further, in order to realize a high sensitivity and a wide dynamic range, when the number of feedback resistors of the gain switching circuit 412 increases to two or more, it is necessary to grasp the gain state in the gain switching determination algorithm, As the circuit configuration becomes more complex, the instantaneous response is lowered. As an example of a circuit for grasping the gain state, a holding circuit 430 that holds a state by a logic circuit using SR latch circuits 431 and 432 and an AND circuit 433 as shown in FIG. 9 is known.

  As described above, the conventional transimpedance amplifier that realizes a wide input dynamic range with high sensitivity has a problem that it is difficult to realize an instantaneous response corresponding to burst data.

  An object of the present invention is to provide a transimpedance amplifier capable of realizing a high sensitivity and a wide input dynamic range and realizing an instantaneous response corresponding to burst data.

  The invention according to claim 1 is a first transimpedance amplifier core circuit having an input terminal connected to a signal input terminal, and a second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit. A transimpedance amplifier core circuit; a differential intermediate stage buffer circuit in which each output terminal of the first and second transimpedance amplifier core circuits is connected to a differential input terminal; and a differential of the intermediate stage buffer circuit A gain switching determination circuit for switching a gain of the first and second transimpedance amplifier core circuits, the output terminal having a hysteresis comparator connected to the differential input terminal, and a voltage input to the signal input terminal A transimpedance amplifier that converts the signal into a signal, amplifies it, and outputs it from the intermediate buffer circuit; Each of the first and second transimpedance amplifier core circuits includes a feedback resistor, and the hysteresis comparator of the gain switching determination circuit is configured to output the first and second transimpedance amplifier core circuits according to a differential output signal of the intermediate buffer circuit. The value of the feedback resistance of the transimpedance amplifier core circuit of 2 is switched.

  According to a second aspect of the present invention, in the transimpedance amplifier according to the first aspect, the first and second transimpedance amplifier core circuits include a MOS transistor as a switch for switching a value of the feedback resistor. And

  According to a third aspect of the present invention, in the transimpedance amplifier according to the second aspect, the MOS transistor comprises an NMOS transistor whose substrate terminal is connected to ground lower than the source potential.

  According to a fourth aspect of the present invention, in the transimpedance amplifier according to the first aspect, the hysteresis comparator of the gain switching determination circuit has a function of initializing its output by an external control signal.

  According to a fifth aspect of the present invention, in the transimpedance amplifier according to any one of the first to third aspects, the first and second transimpedance amplifier core circuits are interlocked with switching of the value of the feedback resistor. Thus, the open loop gain can be switched.

  According to the first aspect of the present invention, in a high-sensitivity and wide dynamic range transimpedance amplifier, gain switching can be instantaneously performed so that waveform distortion does not occur even if the input current changes greatly. In other words, since a hysteresis comparator is used for amplitude level detection for gain switching determination, a level hold circuit with a slow response time is not required, instantaneous gain switching determination is possible, and instantaneous response corresponding to burst data is possible. . Further, as in the invention according to claim 2, the value of the feedback resistor is switched by using the MOS transistor as a switch, and the MOS transistor is made an NMOS transistor as in the invention according to claim 3, thereby reducing the parasitic capacitance. Since the bandwidth can be improved, high-speed operation is possible. Further, according to the invention of claim 4, since the hysteresis comparator is initialized by the external control signal, an appropriate gain can be obtained for each packet having a different signal amplitude by giving the external control signal between the packets in the packet data. Control becomes possible. Further, according to the invention of claim 5, the open loop gain can be switched.

  In the present invention, by using a comparator having hysteresis characteristics in the gain switching determination circuit, the output amplitude of the transimpedance amplifier is detected not by a hold circuit that requires a long response time but by the hysteresis width of the comparator, and gain is instantaneously obtained. When the switching amplitude is determined and the input amplitude exceeds the set hysteresis width, the output level of the comparator is held. As described above, the gain switching determination circuit using the hysteresis comparator instantaneously identifies the output voltage for performing the gain switching determination and maintains the current gain state. Further, the switch for switching the feedback resistance value of the gain switching circuit is constituted by an NMOS transistor, the substrate potential of the NMOS transistor is set to ground (GND) lower than the source potential, the parasitic capacitance of the switch is reduced, and the band of the transimpedance amplifier is reduced. And improve sensitivity. Further, in the PON system, since the signal amplitude is different for each packet, it is necessary to switch the gain corresponding to the amplitude of each packet. Therefore, the hysteresis comparator of the gain switching determination circuit needs to be initialized for each packet. However, since the input voltage of the hysteresis comparator is not inverted, initialization is performed by adding a function for returning the hysteresis comparator to the initial state by an external reset signal.

  FIG. 1 is a circuit diagram of a transimpedance amplifier 200 according to one embodiment of the present invention. The transimpedance amplifier 200 includes a first transimpedance amplifier core circuit 210 having an input terminal connected to the light receiving element 100, and a second transimpedance amplifier having the same configuration as the transimpedance amplifier core circuit 210 and having an input terminal opened. Core circuit 220, intermediate stage buffer circuit 230 for inputting output voltages V1 and V2 of first and second transimpedance amplifier core circuits 210 and 220 to differential input terminals, and differential output voltage of intermediate stage buffer circuit 230 An output buffer circuit 240 that inputs V3 and V4 and outputs differential output voltages Voutp and Voutn, and first and second transimpedance amplifier cores that receive the differential output voltages V3 and V4 of the intermediate buffer circuit 230 In the gain switching circuits 211 and 221 of the circuits 210 and 220, And a gain switching determination circuit 250 outputs a switching signal.

  Next, the operation of the transimpedance amplifier 200 shown in FIG. 1 will be described. Details of the gain switching determination circuit 250 of the transimpedance amplifier 200 are shown in FIG. 2, and an outline of the operation is shown in FIG. The gain switching determination circuit 250 includes a hysteresis comparator 251.

  Since the output voltage V1 of the first transimpedance amplifier core circuit 210 and the output voltage V2 of the second transimpedance amplifier core circuit 220 are input to the intermediate stage buffer circuit 230, the intermediate stage buffer circuit 230 As shown in FIG. 3A, when the current Iin input from the light receiving element 100 to the first transimpedance amplifier core circuit 210 increases, the potential difference (V4−V3) between the normal voltage V3 and the inverted voltage V4. A differential voltage output is obtained such that

  When the differential output voltage of the intermediate buffer circuit 230 is input to the hysteresis comparator 251 of the gain switching determination circuit 250 and the potential difference (V4−V3) of the differential output voltage exceeds a preset hysteresis width, the hysteresis comparator 251 makes a gain switching determination and changes the switching signal (FIGS. 3B and 3C).

  In the transimpedance amplifier 200, the differential output of the intermediate buffer circuit 230 does not invert. Therefore, as shown in FIG. 3C, once the hysteresis width is exceeded, the output level is adjusted unless signal inversion occurs. If the characteristic of the hysteresis comparator 251 that holds is used, the output of the intermediate buffer circuit 230 can be held, so that it is not necessary to prepare a separate circuit. Note that the hysteresis comparator 251 may be initialized with a reset function described later.

  FIG. 4A is a circuit diagram of a gain switching determination circuit 250A of another example of the transimpedance amplifier 200 according to the present invention, and particularly shows a case where there are a plurality of gain switching stages.

  The gain switching determination circuit 250A includes a first hysteresis comparator 252 that performs a first gain switching determination, a second hysteresis comparator 253 that performs a second gain switching determination, and a switch 254, and includes a first hysteresis. The input terminal of the comparator 252 is directly connected to the differential output terminal of the intermediate stage buffer circuit 230, and the input terminal of the second hysteresis comparator 253 is connected to the differential output terminal of the intermediate stage buffer circuit 230 via the switch 254. ing. The switch 254 is turned on / off by a first switching signal that is an output of the first hysteresis comparator 252.

  FIG. 4B shows an outline of the operation of the gain switching determination circuit 250A. The first hysteresis comparator 252 performs gain switching determination and performs first gain switching. After the switch 252 is turned on by the first gain switching signal, when the input current Iin is further increased and the amplitude of the output voltage V1 of the transimpedance amplifier core circuit 210 is further increased, the second hysteresis comparator 253 causes the second hysteresis comparator 253 to Make a gain switching decision.

  Since the differential output voltage of the intermediate stage buffer circuit 230 is not inverted, the output level is maintained after the output of the hysteresis comparator 252 or the outputs of the hysteresis comparators 252 and 253 is switched once. For this reason, even when gain switching is performed in a plurality of stages, the functions of both gain switching determination and state holding can be realized by using this configuration. Note that the hysteresis comparators 251 to 253 may be initialized with a reset function described later.

  Specific examples of the gain switching circuit and the open loop gain switching circuit of the transimpedance amplifier core circuits 210 and 220 according to the present invention are shown below.

  FIG. 5A is a circuit diagram of the gain switching circuits 211 and 221 in the transimpedance amplifier core circuits 210 and 220. The gain switching circuits 211 and 221 include feedback resistors RF1, RF2, and RF3 that determine transimpedance gain, and load resistors RL1, RL2, and RL3 that determine open loop gain. Switch to the desired resistance value as a switch. The NMOS transistors MN1 to MN4 as switches for switching the feedback resistance and the load resistance can also be realized by PMOS transistors if the logic of the switching signal is inverted.

  FIG. 5B is a circuit diagram of another example of the gain switching circuits 211 and 221. The source of the NMOS transistor MN4 is connected to the drain instead of the source of the NMOS transistor MN3. By doing so, it is possible to reduce the influence of the parasitic capacitance of the NMOS transistor MN4 at the time of the maximum load resistance.

  FIG. 5C shows the relationship between the switching signal and the gate voltages (Hi, Lo) of the NMOS transistors MN1 to MN4. The first and second switching signals generated by the gain switching determination circuit 250A shown in FIG. 4 (a) are sent to the gain switching circuits 211 and 221 and resistance switching is performed by switches using NMOS transistors, and the gain is increased. There are 3 types (Large, Medium, Small).

  Further, in FIGS. 5A and 5B, the substrate terminals of the NMOS transistors MN1 and MN2 used as switches for switching the feedback resistors are connected to the ground (GND) instead of the source, and the substrate potential is lower than the source potential. It is said. By doing so, the depletion layer is expanded, the parasitic capacitance between the drain and source of the NMOS transistor can be reduced, and high-speed operation can be obtained.

  FIG. 6 shows a circuit of a hysteresis comparator with a reset function that can be used as the hysteresis comparators 251 to 253 of the gain determination circuit 250 described above. R1 to R6 are resistors, Q3 to Q8 are NPN transistors, MP1 and MP2 are PMOS transistors, and Ia and Ib are current sources. In this hysteresis comparator with reset function, in order to return the hysteresis comparator output to the initial value by the reset signal RESET given from the outside, circuits (PMOS transistors MP1, MP2) for forcibly returning the potential of the hysteresis comparator to the initial value are added. ing. The PMOS transistors MP1 and MP2 can also be realized by NMOS transistors if the logic of the reset signal is inverted.

  When the voltage V4 at the inverting input terminal IN exceeds a certain potential difference with respect to the voltage V3 at the non-inverting input terminal IP, the normal output terminal OP is higher than the inverting output terminal ON. Output voltage. Conversely, when the voltage V3 of the normal input terminal IP exceeds a certain potential difference with respect to the voltage V4 of the inverting input terminal IN, the inverting output terminal ON outputs a high voltage to the normal output terminal OP.

  However, since the differential output of the intermediate buffer circuit 230 is not inverted, the voltage at the inverted output terminal ON does not automatically return to a higher voltage (initial state) than the voltage at the normal output terminal OP.

  Therefore, by adding a reset signal RESET to the reset terminal, a circuit (PMOS transistors MP1, MP2) that forcibly gives the internal voltage so that the inverted output terminal ON becomes a higher voltage than the normal output terminal OP has been added. . As a result, the voltages at both output terminals OP and ON can be returned to the initial values.

  In the PON system, since the signal amplitude differs for each packet, it is necessary to frequently switch the gains of the transimpedance amplifier core circuits 210 and 220 corresponding to the amplitude of each packet. For this reason, the hysteresis comparator 251, 252, or 253 of the gain switching determination circuit 250 needs to be initialized for each packet, but cannot be initialized because the input voltage of the hysteresis comparator is not inverted. Therefore, if these hysteresis comparators are provided with a reset function as described above, the hysteresis comparators can be forcibly returned to the initial state by an external reset signal to perform initialization.

It is a circuit diagram of the transimpedance amplifier which is one Example of this invention. FIG. 2 is a circuit diagram of a gain switching determination circuit in the transimpedance amplifier of FIG. 1. FIG. 2 is an operation explanatory diagram of the transimpedance amplifier of FIG. 1. 1A is a circuit diagram of a gain switching determination circuit when the feedback resistance value is switched over a plurality of values in the transimpedance amplifier of FIG. 1, and FIG. (a), (b) is a circuit diagram of the specific example of the part of the gain switching circuit in a transimpedance amplifier core circuit, (c) is operation explanatory drawing. It is a circuit diagram of the specific example of the hysteresis comparator with a reset function used for a gain switching determination circuit. It is a circuit diagram of the conventional transimpedance amplifier. It is a circuit diagram of the transimpedance amplifier of another example conventionally. In the conventional transimpedance amplifier, it is a circuit diagram of the specific example of the holding circuit which grasps | ascertains the present gain state. (a) is a figure which shows the structure of a PON system, (b) is explanatory drawing of packet data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100: Light receiving element 200: Transimpedance amplifier of a present Example, 210: 1st transimpedance amplifier core circuit, 211: Amplifier circuit, 212: Gain switching circuit, 220: 2nd transimpedance amplifier core circuit, 221: Amplification Circuit: 222: gain switching circuit; 230: intermediate buffer circuit; 240: output buffer circuit; 250, 250A: gain switching determination circuit; 251 to 253: hysteresis comparator; 300: conventional transimpedance amplifier; : Gain switching circuit 400: another conventional transimpedance amplifier, 410: transimpedance amplifier core circuit, 411: amplification circuit, 412: gain switching circuit, 420: gain switching determination circuit, 421 and 422: operational amplifier, 423: comparator 430: holding circuit, 431, 432: FF circuit, 433: AND circuit 501: station side device, 5021 to 502n: home side device, 503: optical coupler, 504: optical fiber, 510: packet, 511: preamble

Claims (5)

A first transimpedance amplifier core circuit having an input terminal connected to a signal input terminal; a second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit; A differential intermediate stage buffer circuit in which each output terminal of the first and second transimpedance amplifier core circuits is connected to a differential input terminal, and the differential output terminal of the intermediate stage buffer circuit is a differential input terminal A gain switching determination circuit having a connected hysteresis comparator and switching the gains of the first and second transimpedance amplifier core circuits, converting a current input to the signal input terminal into a voltage signal, amplifying the voltage signal, and amplifying the voltage signal; A transimpedance amplifier that outputs from an intermediate stage buffer circuit,
Each of the first and second transimpedance amplifier core circuits includes a feedback resistor,
The hysteresis comparator of the gain switching determination circuit switches a value of the feedback resistor of the first and second transimpedance amplifier core circuits according to a differential output signal of the intermediate buffer circuit. Impedance amplifier. The transimpedance amplifier according to claim 1,
The first and second transimpedance amplifier core circuits each include a MOS transistor as a switch for switching the value of the feedback resistor. The transimpedance amplifier according to claim 2,
The transimpedance amplifier, wherein the MOS transistor comprises an NMOS transistor whose substrate terminal is connected to ground lower than the source potential. The transimpedance amplifier according to claim 1,
The transimpedance amplifier, wherein the hysteresis comparator of the gain switching determination circuit has a function of initializing its output by an external control signal. The transimpedance amplifier according to any one of claims 1 to 3,
The transimpedance amplifier, wherein the first and second transimpedance amplifier core circuits are configured such that an open loop gain is switched in conjunction with switching of a value of the feedback resistor.

Images