JP2006040233A - Information processing system and image processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent malfunction from occurring at the time of starting-up of an integrated circuit connected through a system bus. <P>SOLUTION: In the image processing system 1 having ASIC-A3 (ASIC:Application Specific Integrated Circuit) and ASIC-B4 connected through a system bus, when the supply of voltage is performed so that ASIC-B4 to which supply of voltage from a power source IC 192 is stopped is made to start up, a current is prevented from being supplied from the ASIC-A3 connected to a system bus 140 to the ASIC-B4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus and an image processing apparatus.

2. Description of the Related Art Conventionally, it is known that an integrated circuit system is configured by connecting a plurality of integrated circuits (for example, ASIC: Application Specific Integrated Circuit) having an arithmetic processor or the like via a common system bus. In such an integrated circuit system, a specific integrated circuit connected to the system bus may be required to be disconnected from the system bus, for example, for version upgrade. When a specific integrated circuit is disconnected from the system bus, the output signal output from the integrated circuit to be disconnected to the system bus is in a high impedance state (integrated circuit It is known that the output terminal is connected to the internal circuit in the same state) (see, for example, Patent Document 1).
JP-A-6-337742

  In recent years, it has been desired to reduce the power consumption of the entire system by stopping the supply of power to an integrated circuit that does not need to be operated among a plurality of integrated circuits connected to the system bus. . However, when power is supplied so that an integrated circuit whose power supply has been stopped is operated again, current may flow from another integrated circuit connected to the system bus via the system bus. May flow up to a predetermined voltage instead of 0V. As a result, there is a problem that the stopped integrated circuit does not start properly and the integrated circuit malfunctions.

  The present invention has been made in view of the above problems, and in the information processing apparatus or image processing apparatus having the first integrated circuit and the second integrated circuit connected via the system bus, power supply is provided. When the power is supplied so that the second integrated circuit that has been stopped is operated again, current is not supplied from the first integrated circuit connected to the system bus to the second integrated circuit. An object of the present invention is to prevent a malfunction from occurring when the second integrated circuit is activated.

  To achieve the above object, the present invention provides an information processing apparatus having a first integrated circuit and a second integrated circuit connected via a system bus, and supplies a voltage to the second integrated circuit. Voltage supply means; detection means for detecting whether or not a voltage supplied to the second integrated circuit by the voltage supply means is equal to or lower than a predetermined voltage; and a voltage supplied to the second integrated circuit is equal to or lower than the predetermined voltage. When the detection means detects that there is a current, the output terminal of the system bus to the second integrated circuit is set to a high impedance state so that current is not supplied from the first integrated circuit to the second integrated circuit via the system bus. And a setting means.

  The present invention also provides an image processing apparatus having a first integrated circuit and a second integrated circuit connected via a system bus, the image input being provided in the second integrated circuit for inputting an image signal. Means, an image processing means provided in the second integrated circuit for processing an image signal inputted by the image input means, a voltage supply means for supplying a voltage to the second integrated circuit, and a second by the voltage supply means. Transmitting means for transmitting to the first integrated circuit a signal indicating whether or not the voltage supplied to the integrated circuit is equal to or lower than a predetermined voltage; and a voltage provided in the first integrated circuit and lower than the predetermined voltage from the transmitting means. When the signal indicating the state is received, the output terminal of the system bus to the second integrated circuit is set high so that no current is supplied from the first integrated circuit to the second integrated circuit via the system bus. Impedance state And having a constant section.

  According to the present invention, in the information processing apparatus or the image processing apparatus having the first integrated circuit and the second integrated circuit connected via the system bus, the second integrated circuit whose power supply is stopped is again connected. When power is supplied so as to be operated, current is not supplied from the first integrated circuit connected to the system bus to the second integrated circuit, so that a malfunction occurs when the second integrated circuit is activated. It can be prevented from occurring.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the image processing apparatus.

  In FIG. 1, reference numeral 1 denotes an image processing apparatus, which processes image data received from a host computer 113 which is an external apparatus via an interface such as a network, in an image processing section 2 described later, and in the image processing section 2. For example, the image forming unit 115 forms image data that has undergone image processing on a recording sheet as a toner image or an ink image.

  In FIG. 1, reference numeral 3 denotes an ASIC-A provided in the image processing unit 2 for controlling the entire image processing unit 2. The ASIC-A3 includes a CPU 108 for controlling the entire image processing unit 2, a PLL oscillator 150 for generating a reference operation clock for driving each unit of the ASIC-A3, and a ROM 105 connected to the ASIC-A3. ROM controller 117 for reading data from RAM, RAM controller 118 for controlling transmission / reception of data to / from RAM 106 connected to ASIC-A4, and the like. The CPU 108, the ROM controller 107, and the RAM controller 118 in the ASIC-A3 are connected to an ASIC-A system bus 103 for transmitting and receiving data to an ASIC-B4 described later.

  In FIG. 1, reference numeral 4 denotes an ASIC-B provided in the image processing unit 2, which processes image data received from the host computer 113 and transmits image data to be image-formed to an image forming unit 115 described later. . Reference numeral 192 denotes a power supply IC, which supplies power to the ASIC-A3 through the power supply line 191 and supplies power to the ASIC-B4 through the power supply line 193, the FET switch 197, and the power supply line 194. It is. Here, the FET switch 197 is a switch for switching whether or not the power supply voltage is supplied from the power supply IC 192 to the ASIC-B4, and for supplying power supplied from the ASIC-A via the control signal line 195. Whether to supply the power supply voltage is switched according to the control signal.

  Reference numeral 101 denotes a host I / F unit (host interface unit) for performing communication between the image processing apparatus 1 and the host computer 113, and print code data described in a printer-specific language (page description language) from the host computer 113. In addition to receiving image data, the image processing apparatus 1 transmits a status signal indicating the apparatus state of the image processing apparatus 1 to the host computer 113. A scanner I / F unit 102 performs an interface for inputting image data input from the scanner unit 114 included in the image processing apparatus 1 to the image processing unit 2. Here, the scanner unit 114 reads a document image on a document as an image signal, and inputs the read image signal to the image processing unit 2 via the scanner I / F 102. An image identification unit 104 is used to determine the type of image data (image signal), that is, whether it is a color image, a monochrome image, a text image, an image image, or graphic data. Reference numeral 105 denotes a ROM (Read Only Memory), which stores a control program for controlling the entire image processing unit 2. The CPU 108 that controls the image processing unit 2 controls the image processing unit 2 based on a control program read from the ROM 105 via the ROM controller 117. Reference numeral 106 denotes a RAM (Random Access Memory), which is used as a work memory when the CPU 108 performs various processes. The RAM 106 stores image data input from the host I / F unit 101 through the ASIC-B system bus 116, the system bus 140, and the ASIC-A system bus 103 that are electrically connected to each other. It is also used as a buffer for the purpose. Note that the input image data includes image data from the host computer 113 input via the host I / F 101 and image data from the scanner unit 114 input via the scanner I / F 102. Access to the RAM 106 is controlled by the RAM controller 118. Reference numeral 107 denotes an operation panel, which performs a copying operation (operation in which image data input from the scanner unit 114 is formed as an image on a sheet by the image forming unit 115) or a printing operation (image data input from the host computer 113 is converted into an image). When the forming unit 115 performs an operation for forming an image on a sheet, the operator (user) of the image processing apparatus 2 performs various settings (for example, setting of the number of copies in the copying operation and setting of the enlargement / reduction ratio). ). Note that the operation panel 107 displays the copy operation status during the copy operation (progress status for the set number of copies) and the print operation status during the print operation (the number of print copies set by the printer driver in the host computer 113). The operator (user) can be notified of the operation status of the image processing apparatus 2 (such as the progress status) and the operation status of the image processing apparatus 2 (such as a paper jam error status in the image forming unit 115). A compression / decompression unit 109 compresses the image data read by the scanner unit 114 to be stored in the RAM 106 and outputs the compressed image data stored in the RAM 106 at the image forming unit 115. The process of decompressing is performed. The compression / decompression unit 109 expands image data described in a page description language received from the host computer 113 via the host I / F unit 101 into image data that can be formed by the image forming unit 115. In the process, the image data is temporarily compressed or expanded. Reference numeral 110 denotes an image data rotator, for example, for rotating image data read by the scanner unit 114 by 90 degrees, 180 degrees, and 270 degrees. Reference numeral 111 denotes an engine I / F unit for outputting image data to the image forming unit 115. 103 is an ASIC-A3 system bus, 116 is an ASIC-B4 system bus, and both are connected to each other by a system bus 140. An external storage device 121 provided outside the image processing unit 2 is controlled by the external storage device controller 120. The external storage device 121 stores image data from the host computer 113 input via the host I / F 101, image data from the scanner unit 114 input via the scanner I / F 102, and the like. Reference numeral 150 denotes a PLL oscillator built in the ASIC-A3. Reference numeral 160 denotes a PLL oscillator built in the ASIC-B4. Each oscillator operates the ASIC-B4 based on a reference clock supplied from the outside of the ASIC. A clock signal having a predetermined cycle is generated and supplied to the internal module of the ASIC-B4. The internal module of the ASIC-B4 operates using a clock signal with a predetermined period from the PLL oscillator 160 as a reference signal. In the PLL oscillator 160, the voltage supplied to the ASIC-B4 from the voltage supply unit including the power supply IC 192 and the FET switch 197 is changed from the ground voltage to the predetermined voltage (the power supply voltage Vdd of the power supply IC 192). As a result, a clock signal having a predetermined period is output.

  Reference numeral 170 denotes a reset IC for ASIC-A3, and reference numeral 180 denotes a reset IC for ASIC-B4. The reset IC 170 detects whether or not the power supply voltage (Vdd) supplied from the power supply IC 192 to the ASIC-A3 is equal to or lower than a predetermined reset voltage lower than the power supply voltage (Vdd) that can be supplied by the power supply IC. When the power supply voltage (Vdd) supplied from the power supply IC 192 to the ASIC-A3 is equal to or lower than a predetermined reset voltage, the reset IC 170 notifies the ASIC-A3 of a signal indicating the reset state and is larger than the reset voltage. Notifies the ASIC-A3 of a signal indicating the reset release state. The reset IC 180 detects whether or not the power supply voltage (Vdd) supplied from the power supply IC 192 to the ASIC-B4 is equal to or lower than a predetermined reset voltage lower than the power supply voltage (Vdd) that can be supplied by the power supply IC 192. . The reset IC 180 notifies the ASIC-B4 and the ASIC-A3 of a signal indicating a reset state when the power supply voltage (Vdd) supplied from the power supply IC 192 to the ASIC-B4 is equal to or lower than a predetermined reset voltage, and resets the reset voltage. When the voltage is larger than the voltage, a signal indicating the reset release state is notified to the ASIC-B4 and the ASIC-A3.

  The ASIC-A3 and the ASIC-B4 are provided together with the system bus (the ASIC-A system bus 103, the system bus 140, and the ASIC-B system bus 116 are electrically connected) on the same board. .

  Next, details of the ASIC-A3 will be described with reference to FIG.

  In FIG. 2, the ASIC-A 3 includes an I / O buffer unit 201 and a functional logic unit 202. The functional logic unit 202 includes functional blocks connected to each other via the ASIC-A system bus 103 such as the CPU 108, the ROM controller 117, and the RAM controller 118 shown in FIG. The output signal 204 in the ASIC-A 3 is transmitted from the functional logic unit 202 to the system bus 140 via the bidirectional buffer 208 of the I / O buffer unit 201. Here, the signal output from the ASIC-A3 via the bidirectional buffer 108 corresponds to the data signal 403 that is bidirectionally transmitted and received on the system bus 140 described later.

  The output signal 206 in the ASIC-A3 is transmitted from the functional logic unit 202 to the system bus 140 via the output buffer 212 of the I / O buffer unit 201. Here, the signal output from the ASIC-A3 via the output buffer 212 is a transaction start signal 400, an address signal 401, and a read / write signal transmitted from the ASIC-A3 to the ASIC-B4 on the system bus 140 described later. It corresponds to the signal 402. That is, only one output buffer 212 shown in FIG. 2 is described as a representative of the plurality of output buffers 212 included in the I / O buffer unit 201. The transaction start signal 400, the address signal 401, the read Assume that an output buffer 212 corresponding to each write signal 402 is provided.

  Reference numeral 205 denotes a bidirectional buffer output enable signal that sets whether or not to output the output signal 204 via the bidirectional buffer 208, and is output from the functional logic unit 202 to the OR gate 220 of the I / O buffer unit 201. Signal. Reference numeral 207 denotes a bidirectional buffer output enable signal for setting whether or not to output the output signal 206 via the output buffer 212, and is output from the functional logic unit 202 to the OR gate 221 of the I / O buffer unit 201. Signal.

  Reference numeral 213 denotes an input buffer that receives a reset signal from the reset IC 170 that detects the power supply voltage of the ASIC-A3 and outputs a signal from the reset IC 170 to the functional logic unit 202 and the OR gates 220 and 221. An input buffer 216 receives a signal from the reset IC 180 that detects the power supply voltage of the ASIC-B 4 and outputs a signal from the reset IC 180 to the functional logic unit 202 and the OR gates 220 and 221.

  Here, in the OR gate 220, any one of three types of signals (a signal 214 from the reset IC 170, a signal 215 from the reset IC 180, and a bidirectional buffer output enable signal 205 from the functional logic unit 202) is inactive. (“H (high)” in the low active signal), the output of the output signal 204 from the bidirectional output buffer 208 is enabled. Therefore, the functional logic unit 202 permits output from the bidirectional buffer (the bidirectional buffer output enable signal is “L”), and a voltage higher than the reset voltage is supplied from the power supply IC 192 to the ASIC-A3 (reset). If the signal 214 is “L”) and the ASIC-B 4 is supplied with only a voltage equal to or lower than the reset voltage from the power supply IC 192 (the reset signal 215 is “H”), the OR gate 220 outputs a three-state output buffer. A disable signal is output to 222. As a result, the output buffer 222 is electrically disconnected from the signal line to which the output signal 204 of the ASIC-A system bus 103 is transmitted and the signal line to which the data signal 403 of the system bus is transmitted (high impedance state). ). In this case, no current is supplied to the ASIC-B4 from the I / O buffer unit 201 which is the end of the system bus 103 of the ASIC-A3. Therefore, when the reset state of the ASIC-B4 is released, the ASIC-B4 is released. It is possible to prevent the power supply voltage of −B4 from rising from the ground potential and causing the PLL oscillator 160 to malfunction.

  Similarly to the OR gate 220, the OR gate 221 has any of three types of signals (a signal 214 from the reset IC 170, a signal 215 from the reset IC 180, and an output buffer output enable signal 207 from the functional logic unit 202). If one of them is inactive (“H (high)” in the low active signal), the output of the output signal 206 from the output buffer 221 is enabled. Therefore, the functional logic unit 202 permits output from the output buffer (the output buffer output enable signal is “L”), and a voltage larger than the reset voltage is supplied from the power supply IC 192 to the ASIC-A3 (reset signal 214). Is “L”), if the voltage less than or equal to the reset voltage is supplied from the power supply IC 192 to the ASIC-B4 (the reset signal 215 is “H”), the OR gate 221 to the three-state output buffer 212 Disable signal is output. As a result, the output buffer 212 has a signal line to which the output signal 206 of the ASIC-A system bus 103 is transmitted and a signal line to which the transaction start signal 400 of the system bus, the address signal 401 or the read / write signal 402 is transmitted. It is assumed that it is electrically disconnected (high impedance state). In this case, no current is supplied to the ASIC-B4 from the I / O buffer unit 201 which is the end of the system bus 103 of the ASIC-A3. Therefore, when the reset state of the ASIC-B4 is released, the ASIC-B4 is released. It is possible to prevent the power supply voltage of −B4 from rising from the ground potential and causing the PLL oscillator 160 to malfunction.

  Here, the cause of malfunction of the PLL oscillator 160 and the like when starting the ASIC-B4 will be described with reference to FIGS.

  FIG. 7 is a diagram illustrating the power supply terminal voltage of the ASIC-B4 when the output terminal of the ASIC-A3 to the system bus 140 is in a low impedance state when the power supply to the ASIC-B4 is stopped. FIG. 8 is a diagram illustrating the power supply terminal voltage of the ASIC-B4 when the output terminal of the ASIC-A3 to the system bus 140 is in a high impedance state when the power supply to the ASIC-B4 is stopped.

  In FIG. 7, the I / O buffer unit 201 sets the bidirectional buffer 208 and the output buffer 212 to a state where the ASIC-A3 system bus 103 and the system bus 140 are electrically connected (low impedance state). A current can be supplied from the output terminal of the ASIC-A system bus 103 of A3 to the ASIC-B4 via the system bus 140. In such a state, even if the power supply from the power supply IC 192 to the ASIC-B4 is stopped, the power supply terminal voltage of the ASIC-B4 does not become 0 V, and is input from the ASIC-A3 via the system bus 140. As a result, the power supply terminal voltage is increased by a predetermined voltage. In such a state, when power supply from the power supply IC 192 to the ASIC-B4 is started in order to activate the ASIC-B4, the power supply terminal voltage of the ASIC-B4 rises from a predetermined voltage. The PLL oscillator 160 or the like designed on the premise of starting up may malfunction (for example, not oscillate at a constant frequency).

  On the other hand, in FIG. 8, the I / O buffer unit 201 sets the bidirectional buffer 208 and the output buffer 212 to a state where the ASIC-A3 system bus 103 and the system bus 140 are not electrically connected (high impedance state). Therefore, no current is supplied from the output terminal of the ASIC-A system bus of the ASIC-A3 to the ASIC-B4 via the system bus 140. In such a state, when power supply from the power supply IC 192 to the ASIC-B4 is stopped, the power supply terminal voltage of the ASIC-B4 becomes 0 V, and a predetermined voltage is generated by the current input from the ASIC-A3 via the system bus 140. As a result, the power supply terminal voltage is not increased. In such a state, when power supply from the power supply IC 192 to the ASIC-B4 is started to activate the ASIC-B4, the power supply terminal voltage of the ASIC-B4 rises from 0V and rises from 0V. The PLL oscillator 160 or the like designed on the premise of this does not malfunction. Note that when the current flows from the ASIC-A3 to the ASIC-B via the system bus 140, the power supply terminal voltage of the ASIC-B4 becomes higher than 0V by a predetermined voltage because the ASIC-B4 system bus 116 and the ASIC- This is because the B4 power supply terminal can be electrically connected at any point on the circuit.

  Here, in order to prevent malfunction of the functional logic (for example, PLL oscillator) of the ASIC-B4, the output terminal from the ASIC-A3 to the system bus 140 is set to the high impedance state when the ASIC-B4 is in the sleep state. The buffer IC 196 is provided in the middle of the system bus 140 that connects the ASIC-A3 and the ASIC-B4, and when power is supplied to the SIC-B4, it is linked with the control signal 195 that turns off the FET switch. It is also effective to make the buffer IC 196 in a high impedance state (see FIG. 9). However, in this method, it is necessary to provide the buffer IC 196 on the system bus 140, which is disadvantageous from the viewpoint of cost and downsizing, so the above-described method is more preferable.

  Next, the connection structure of ASIC-A3 and ASIC-B4 is demonstrated using FIG.

  In FIG. 3, reference numeral 140 denotes a system bus, which is a signal line for accessing the functional logic unit in the ASIC-B4 from the ASIC-A3. A write signal 400, an address signal 402, and a data signal 403.

  FIG. 4 is a timing chart of output signals of the signal lines in a write transaction for writing data from the ASIC-A3 to the ASIC-B4 based on the connection configuration shown in FIG.

  In FIG. 4, the system clock indicates a clock signal having a predetermined period generated from the PLL oscillator 150, and each of T1, T2,... Corresponds to one period. Each unit of the ASIC-A3 operates using the system clock as a reference signal. In the T1 cycle of FIG. 4, the ASIC-A3 determines a transaction start signal 400 indicating the start of a transaction, and transmits an address signal 401 and a read / write signal 402 onto the system bus 140. In the subsequent T2 cycle, the ASIC-A3 transmits the data signal 403 onto the system bus 140. Then, since the ready signal from ASIC-B4 to ASIC-A3 is not determined in the periods T2, T3, and T4, ASIC-A3 enters a standby state while holding the write data on the system bus 140. In the T5 cycle, the ASIC-B4 determines the ready signal 404 indicating that the signal from the ASIC-A3 is ready to be received. Then, the ASIC-B4 takes in the write data 403 from the ASIC-A3 at the end of the T5 cycle. With the above operation, the write transaction cycle from the ASIC-A3 to the ASIC-B4 is completed.

  Next, FIG. 5 shows a timing chart of a read transaction for reading data from the ASIC-B4 to the ASIC-A3.

  In the T1 cycle of FIG. 5, the ASIC-A3 determines a transaction start signal 400 indicating the start of a transaction, and transmits an address signal 401 and a read / write signal 402 onto the system bus 140. In the subsequent T2, T3, and T4 periods, since the ready signal from the ASIC-B4 to the ASIC-A3 is not determined, the ASIC-A3 enters a standby state while holding the write data on the system bus 140. In the T5 cycle, the ASIC-B4 determines a ready signal 404 indicating that data can be transmitted to the ASIC-A3. Then, the ASIC-A3 takes in the read data 403 from the ASIC-B4 at the end of the T5 cycle. With the above operation, the read transaction cycle from the ASIC-B4 is completed.

  Next, the non-operation state of the ASIC-B4 will be described with reference to the flowchart of FIG.

  In recent years, it has been desired to reduce the power consumption of the entire system by stopping the supply of power to an integrated circuit that does not need to be operated among a plurality of integrated circuits connected to the system bus. . In the image processing apparatus 1, an image is formed on a sheet by the image forming unit 115 based on image data input to the host I / F unit 101 and the scanner I / F unit 102. The image processing apparatus 1 does not always operate, and the image data processing in the ASIC-B4 and the image forming process in the image forming unit 115 do not perform any operations. It is often shorter than the time waiting for image data to be input to the host I / F unit 101 or the scanner I / F unit 102. Further, continuing to supply power to the ASIC-B 4 and the image forming unit 115 during the standby time continuously consumes power, which is not desirable from the viewpoint of power saving. Accordingly, when the image data is not input to the image processing apparatus 1 for a predetermined time (for example, 15 minutes), the operation of shifting the image processing apparatus 1 to the non-operation state (hereinafter referred to as the sleep state) is illustrated in the flowchart of FIG. It explains using.

  FIG. 6 is a flowchart showing the transition of the operation state of the image processing apparatus controlled by the CPU 108 of the ASIC-A3.

  In step S601, the CPU 108 determines whether or not the image processing apparatus 1 is in a sleep state. If the image processing apparatus 1 is in a sleep state, the process proceeds to step S604, and the image processing apparatus 1 is in a preparation state (hereinafter referred to as standby). State), the process proceeds to step S602. Here, the sleep state refers to a state in which the power supply voltage is not supplied from the power supply IC 192 to the ASIC-B4 and the power supply voltage is not supplied to the image forming unit 115, and the standby state refers to the state in which the power supply IC 192 supplies the ASIC. A state in which the power supply voltage is supplied to -B4 and the power supply voltage is also supplied to the image forming unit 115.

  In step S602, the CPU 108 inputs image data from the host computer 113 to the host I / F unit 101 in order to determine whether or not the image processing apparatus 1 in the standby state needs to be shifted to the sleep state. Determine whether or not. Specifically, the CPU 108 makes a determination based on a signal from the host computer 113 input to the ASIC-A 3 via the signal line 198. When the CPU 108 determines that the image data from the host computer 113 input to the ASIC-A3 via the signal line 198 or a control command related to image formation is not input for a predetermined time (for example, 15 minutes). The process proceeds to step S603. On the other hand, when the time during which the control command related to image data or image formation is not input is less than the predetermined time, the CPU 108 executes step S602 again.

  In step S603, the CPU 108 transmits a signal for shifting the FET switch to the OFF state via the control signal line 195. The FET switch 197 that has received the signal switches from a state in which power is supplied from the power supply IC 192 to the ASIC-B4 to a state in which it is not supplied. In addition, the ASIC-A3 sends a control signal for stopping the power supply from the power supply (not shown) to the image forming unit 115 before the ASIC-B4 is shifted to the power supply stop state. Via ASIC-B4. Note that, as described above, the I / O buffer unit 201 of the ASIC-A3 is connected to the ASIC-B4 after the image processing apparatus 1 shifts to the sleep state (the power from the ASIC-B4 is stopped). When the reset signal becomes “L”), the output terminals of the bidirectional buffer 208 and the output buffer 212 are set to a high impedance state.

  On the other hand, if it is determined in step S601 that the image processing apparatus 1 is in the sleep state, in step S604, the CPU 108 determines whether there is an input of a control command related to image data or image formation from the host computer 113. The determination is based on the signal from If the CPU 108 determines that there is input of a control command related to image data or image formation, the CPU 108 proceeds to step S605 in order to shift the image processing apparatus 1 from the sleep state to the standby state.

  In step S <b> 605, the CPU 108 starts supplying power from the power supply IC 192 to the ASIC-B <b> 4 by transmitting a signal for shifting the FET switch to the ON state via the control signal line 195. Also, the ASIC-A3 transmits a control signal for starting power supply from the power supply (not shown) to the image forming unit 115 via the system bus 140 after the ASIC-B4 is shifted to the power supply state. -Send to B4.

  In step S606, the CPU 108 transmits a predetermined command to the ASIC-B4 in order to cause the image processing apparatus 1 that has shifted to the standby state to form an image on the paper, thereby transferring the image data in the ASIC-B4. Image processing and image formation on the sheet of image data in the image forming unit 115 are performed.

  As described above, according to this embodiment, in the image processing apparatus 1 having the first integrated circuit (ASIC-A3) and the second integrated circuit (ASIC-B4) connected via the system bus, When an attempt is made to supply a voltage so that the second integrated circuit (ASIC-B4), from which the supply of voltage from the power supply IC 192 has been stopped, is operated again, the first integrated circuit (ASIC-) connected to the system bus 140 By preventing current from being supplied from A3) to the second integrated circuit (ASIC-B4), it is possible to prevent malfunction from occurring when the second integrated circuit (ASIC-B4) is started.

  The first integrated circuit (ASIC-A3) controls whether or not voltage is supplied to the second integrated circuit (ASIC-B4) by the voltage supply means (power supply IC192 and FET switch 197). Since the signal is transmitted, the voltage supply means (the power supply IC 192 and the FET switch 197) switches whether to supply the voltage to the second integrated circuit (ASIC-B4) based on the control signal from the ASIC-A3. It is possible to appropriately prevent a malfunction from occurring when the second integrated circuit (ASIC-B4) is started based on the control signal from the first integrated circuit (ASIC-A3).

  As mentioned above, although preferred embodiment of invention was described, it cannot be overemphasized that this invention is not limited to these, and a various deformation | transformation is possible.

It is a block diagram which shows the structure of an image processing apparatus. It is a block diagram which shows the detail of ASIC-A3. It is a figure which shows the connection structure of ASIC-A3 and ASIC-B4. It is a timing chart of the output signal of each signal line in the write transaction. It is a timing chart of the read transaction which reads the data from ASIC-B4 to ASIC-A3. It is a flowchart which shows transfer of the operation state of an image processing apparatus. It is a figure which shows the power supply terminal voltage of ASIC-B4 in the case of making the output terminal to the system bus 140 of ASIC-A3 into a low impedance state when the power supply to ASIC-B4 is stopped. It is a figure which shows the power supply terminal voltage of ASIC-B4 in the case of making the output terminal to the system bus 140 of ASIC-A3 into a high impedance state when the power supply to ASIC-B4 is stopped. It is a block diagram which shows the structure of an image processing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 2 Image processing part 3 ASIC-A
4 ASIC-B
101 Host I / F Unit 102 Scanner I / F Unit 103 ASIC-A System Bus 108 CPU
113 Host Computer 114 Scanner Unit 115 Image Forming Unit 116 ASIC-B System Bus 117 ROM Controller 140 System Bus 192 Power Supply IC
197 FET switch 204, 206 Output signal 205 Bidirectional buffer output enable signal 207 Output buffer output enable signal 208 Bidirectional buffer 212 Output buffer 220, 221 OR gate 222 Output buffer 400 Transaction start signal 401 Address signal 402 Read / write signal 403 Data signal

Claims (12)

An information processing apparatus having a first integrated circuit and a second integrated circuit connected via a system bus,
Voltage supply means for supplying a voltage to the second integrated circuit;
Detecting means for detecting whether or not a voltage supplied to the second integrated circuit by the voltage supplying means is a predetermined voltage or less;
When the detection means detects that the voltage supplied to the second integrated circuit is equal to or lower than a predetermined voltage, a current flows from the first integrated circuit to the second integrated circuit via the system bus. Setting means for setting an output terminal of the system bus to the second integrated circuit to be in a high impedance state so as not to be supplied;
An information processing apparatus comprising: The first integrated circuit has control signal transmission means for transmitting a control signal for controlling whether or not to supply a voltage to the second integrated circuit by the voltage supply means,
The information processing apparatus according to claim 1, wherein the voltage supply unit switches whether to supply a voltage to the second integrated circuit, based on a control signal from the control signal transmission unit. The second integrated circuit has PLL oscillation means for outputting a clock signal having a predetermined cycle as a reference signal for driving the second integrated circuit,
The said PLL oscillation means outputs the clock signal of the said predetermined period according to the voltage supplied to the said 2nd integrated circuit from the said voltage supply means changing from a ground voltage to a predetermined voltage. The information processing apparatus according to either 1 or 2.   4. The information processing apparatus according to claim 1, wherein the first integrated circuit and the second integrated circuit are provided together with the system bus on the same substrate. An image processing apparatus having a first integrated circuit and a second integrated circuit connected via a system bus,
Image input means provided in the second integrated circuit for inputting an image signal;
An image processing means provided in the second integrated circuit for processing an image signal input by the image input means;
Voltage supply means for supplying a voltage to the second integrated circuit;
Transmitting means for transmitting to the first integrated circuit a signal indicating whether or not the voltage supplied to the second integrated circuit by the voltage supplying means is a predetermined voltage or less;
When the signal provided in the first integrated circuit and indicating that the voltage state is equal to or lower than the predetermined voltage is received from the transmission unit, the second signal is transmitted from the first integrated circuit via the system bus. Setting means for setting an output terminal of the system bus to the second integrated circuit to be in a high impedance state so that no current is supplied to the integrated circuit;
An image processing apparatus comprising: An image signal transmission unit that is provided in the second integrated circuit and transmits an image signal image-processed by the image processing unit;
6. The image processing apparatus according to claim 5, further comprising an image forming unit that forms an image on a recording medium based on the image signal transmitted from the image signal transmitting unit. The first integrated circuit has control signal transmission means for transmitting a control signal for controlling whether or not to supply a voltage to the second integrated circuit by the voltage supply means,
7. The voltage supply unit according to claim 5, wherein the voltage supply unit switches whether to supply a voltage to the second integrated circuit based on a control signal from the control signal transmission unit. Image processing apparatus. A determination unit provided in the first integrated circuit, for determining whether an image signal is input to the image input unit;
The control signal transmitting unit stops the voltage supply to the second integrated circuit in response to the determination unit determining that the image signal is not input to the image input unit for a predetermined time. Transmitting a control signal to the voltage supply means, and starting the voltage supply to the second integrated circuit in response to the determination by the determination means that the image signal is input to the image input means. The image processing apparatus according to claim 7, wherein a control signal is transmitted to the voltage supply unit.   The image processing apparatus according to claim 5, wherein the image input unit inputs an image signal received from an external apparatus. An original reading means for reading an original image as an image signal;
The image processing apparatus according to claim 5, wherein the image input unit inputs the image signal read by the document reading unit. The second integrated circuit has PLL oscillation means for outputting an oscillation clock signal having a predetermined period as a reference signal for driving the second integrated circuit,
The said PLL oscillation means outputs the clock signal of the said predetermined period according to the voltage supplied to the said 2nd integrated circuit from the said voltage supply means changing from a ground voltage to a predetermined voltage. The image processing device according to any one of 5 to 10. 12. The image processing apparatus according to claim 5, wherein the first integrated circuit and the second integrated circuit are provided together with the system bus on the same substrate.

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