JP2006033061A - Delay circuit, semiconductor integrated circuit, phase regulation circuit, dll circuit and pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a delay circuit in which a large delay time can be attained and the delay time can be controlled finely. <P>SOLUTION: A plurality of stages of inverters 1-n are connected in series, potential VDDH is supplied to the substrate electrode of each P-ch transistor 1a-na, a switch 1c-nc is connected to the source electrode of each P-ch transistor 1a-na, potential VDDH or VDDL can be selected as potential supplied to its source electrode, or at least one of the potential VDDH and VDDL can be regulated freely. Depending on the regulation of the potential VDDH or VDDL and potential selection by the switch 1c-nc, reverse bias or forward bias is applied to the P-ch transistor 1a-na, thus attaining a large delay time or controlling the delay time finely. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a delay circuit, a semiconductor integrated circuit, a phase adjustment circuit, a DLL circuit, and a PLL circuit capable of finely controlling a delay time in a digital circuit.

Conventional Example 1
As a conventional delay circuit, there is one that separates a substrate potential and a source potential of a P-ch transistor constituting an inverter and controls the separated substrate potential to make the delay time variable (for example, Patent Documents). 1).
Conventional example 2
As a conventional delay circuit, a plurality of stages of inverters are connected in series, a substrate potential and a source potential of P-ch transistors constituting each inverter are separated, and a plurality of separated substrate potentials are controlled, thereby delay time. Is variable (see, for example, Patent Document 1).

JP 2002-520979 A

Since the conventional delay circuit is configured as described above, there is a problem that a large delay time cannot be obtained in the configuration including the single-stage inverter as in Conventional Example 1.
Further, in the configuration including the inverter having a plurality of stages as in Conventional Example 2, although a large delay time can be obtained, there is a problem that the delay time cannot be finely controlled.

  The present invention has been made to solve the above-described problems, and can provide a delay circuit, a semiconductor integrated circuit, a phase adjustment circuit, a DLL capable of obtaining a large delay time and finely controlling the delay time. An object is to obtain a circuit and a PLL circuit.

  The delay circuit according to the present invention includes a series circuit formed by connecting a plurality of logic gates in series, a first potential supply circuit for supplying a first potential to the substrate electrode of each P-ch transistor, And a first switch group connected to the source electrode of each P-ch transistor and selecting the first potential or the second potential as the potential supplied to the source electrode. And at least one of the first potential supplied from the first potential supply circuit and the second potential supplied from the second potential supply circuit is adjustable.

  According to the present invention, a large delay time can be obtained and the delay time can be finely controlled according to the potential adjustment of the first or second potential and the potential selection by the first switch group. There is.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a delay circuit according to Embodiment 1 of the present invention. In FIG. 1, an inverter (logic gate) 1 includes a P-ch transistor 1a and an N-ch transistor 1b. And the drain electrodes are connected to each other. Similarly, the inverters (logic gates) 2 to n are composed of P-ch transistors 2a to 2na and N-ch transistors 2b to nb, and the gate electrodes and the drain electrodes are connected to each other. These inverters 1 to n form a series circuit in which a plurality of stages are connected in series, and delay an input digital signal by passing through the plurality of stages of inverters 1 to n.

  Further, the substrate potential and the source potential of the P-ch transistors 1a to na are separated and the separated substrate potentials are made common. The substrate electrodes of the P-ch transistors 1a to na are commonly connected to a power source and configured to be supplied with a potential VDDH (first potential) (first potential supply circuit). The source electrodes of the P-ch transistors 1a to na are connected to the switches (first switch group) 1c to nc, and are supplied from the potential VDDH or the power source (second potential supply circuit). Potential) is selected.

Further, the substrate potential and the source potential of the N-ch transistors 1b to nb are separated and the separated substrate potentials are made common. The substrate electrodes of the N-ch transistors 1b to nb are commonly connected to the ground and configured to be supplied with the potential VSSL (third potential) (third potential supply circuit). The source electrodes of the N-ch transistors 1a to nb are connected to switches (second switch groups) 1d to nd, and are supplied from the potential VSSL or the ground (fourth potential supply circuit). Potential) is selected.
Further, the potential VDDH and the potential VSSL are adjustable.

Next, the operation will be described.
In FIG. 1, the potential VDDH is selected as the common substrate potential of the plurality of P-ch transistors 1a to na, and the potential VDDH or the potential VDDL is selected for each of the plurality of separated source electrodes of the P-ch transistors 1a to na. The switches 1c to nc are added, the potential VSSL is applied to the common substrate potential of the plurality of N-ch transistors 1b to nb, and the potential VSSL or each of the plurality of separated source electrodes of the N-ch transistors 1b to nb is applied. The switches 1d to nd for selecting the potential VSSH are added. Compared to VDDH = VDDL and VSSL = VSSH for supplying the same potential to the normal substrate electrode and source electrode, in the state of VDDH> VDDL and VSSL <VSSH to which a reverse bias is applied, each of the separated source electrodes The switches 1c to nc and 1d to nd added to the delay time increase in accordance with the number connected to the potentials VDDL and VSSH, and are separated in the state of VDDH <VDDL and VSSL> VSSH to which forward bias is applied. Further, the switches 1c to nc and 1d to nd added to each of the plurality of source electrodes reduce the delay time according to the number connected to the potentials VDDL and VSSH.

  When it is desired to increase the delay time by utilizing this property, it is possible to apply a reverse bias and increase the number of switches connected to the potentials VDDL and VSSH by the switches 1c to nc and 1d to nd. In order to reduce the delay time, it is possible to apply a forward bias and increase the number of connections to the potentials VDDL and VSSH by the switches 1c to nc and 1d to nd.

  The reverse bias potential of the P-ch transistor and the N-ch transistor is ΔVDD = VDDH-VDDL, ΔVSS = VSSH-VSSL, the number of separated source electrodes is N, and the number of switches connected to the potentials VDDL and VSSH is M. If each is defined, the delay circuit of the first embodiment obtains a delay time in which the number of switches connected to the potentials VDDL and VSSH is proportional to M (M ≦ N), compared with the delay circuit of the first conventional example. Can do. That is, a larger delay time difference can be obtained with ΔVDD and ΔVSS smaller than those of the conventional example 1, and the delay time can be controlled with finer resolution than the conventional example 2.

In the above description, the configuration in which the source electrodes of all the P-ch transistors and N-ch transistors constituting the delay circuit are separated and a switch is added to all the separated source electrodes has been described. However, the same effect can be expected with a configuration in which some of the source electrodes are fixed to the potentials VDDL and VSSH or the common substrate potentials VDDH and VSSL without adding a separate switch. As an example of this, the source electrode and substrate electrode of the N-ch transistor constituting the delay circuit are not separated, but are shared with the ground potential VSS, and the above-described switch is added only to the P-ch transistor constituting the delay circuit. The structure which performs is considered. Similarly, the source electrode and the substrate electrode of the P-ch transistor constituting the delay circuit are not separated, but are shared with the power supply potential VDD, and the above-described switch is added only to the N-ch transistor constituting the delay circuit. Configuration is also conceivable.
In the above description, the potential VDDH and the potential VSSL are adjustable. However, the potential VDDL and the potential VSSH may be adjustable, and the potential VDDH and the potential VDDL may be adjusted. It is sufficient that at least one of the potentials and at least one of the potential VSSL and the potential VSSH can be adjusted, and the same effect can be expected.
Furthermore, in the above description, a configuration using a general CMOS inverter in which a P-ch transistor and an N-ch transistor are paired as the logic gate constituting the delay circuit has been described. The same effect can be expected with any circuit.

Embodiment 2. FIG.
FIG. 2 is a circuit diagram showing a selector of a delay circuit according to the second embodiment of the present invention. In the figure, a P-ch transistor (first P-ch transistor) 1e has a source electrode connected to a power supply, and a potential. The configuration is such that VDDH is supplied. The P-ch transistor (second P-ch transistor) 1f is configured such that the source electrode is connected to the power source and the potential VDDL is supplied. The drain electrodes of the P-ch transistors 1e and 1f are commonly connected to the source electrode of the P-ch transistor 1a in FIG. The P-ch transistor 1f has a gate electrode that directly inputs a selection signal and operates according to the selection signal. The P-ch transistor 1e has a gate electrode that receives a selection signal through an inverter 1g and selects the selection signal. It operates according to the inverted signal of the signal. As described above, the selectors configured by the transfer gates shown in FIG. 2 are used as the switches 1c to nc of the delay circuit shown in FIG.

  FIG. 3 is a circuit diagram showing a selector of a delay circuit according to the second embodiment of the present invention. In the figure, an N-ch transistor (first N-ch transistor) 1h has a source electrode connected to the ground, and a potential. VSSL is configured to be supplied. The N-ch transistor (second N-ch transistor) 1i is configured such that the source electrode is connected to the ground and the potential VSSH is supplied. The drain electrodes of the N-ch transistors 1h and 1i are commonly connected to the source electrode of the N-ch transistor 1b in FIG. The N-ch transistor 1i has a gate electrode that directly receives a selection signal and operates according to the selection signal. The N-ch transistor 1h has a gate electrode that receives a selection signal through an inverter 1j and selects the selection signal. It operates according to the inverted signal of the signal. As described above, the selectors configured by the transfer gates shown in FIG. 3 are used as the switches 1d to nd of the delay circuit shown in FIG.

Next, the operation will be described.
In FIG. 2, when the selection signal is “1”, “0” and “1” are applied to the respective gate inputs of the P-ch transistors 1e and 1f, so that the P-ch transistor 1e is turned on and P-ch is turned on. The transistor 1f is turned off, and the potential VDDH is supplied from the common drain electrode PS / B to the source electrode of the P-ch transistor 1a in FIG. On the other hand, when the selection signal is “0”, “1” and “0” are applied to the respective gate inputs of the P-ch transistors 1e and 1f, so that the P-ch transistor 1e is turned off and the P-ch transistor 1f is turned off. Is turned on, and the potential VDDL is supplied from the common drain electrode PS / B to the source electrode of the P-ch transistor 1a in FIG. As described above, since the P-ch transistors 1e and 1f are used for the selector of the power supply potential, the potential supplied to the common drain electrode PS / B becomes the potential VDDH or the potential VDDL, and the potential is deteriorated. Can be eliminated.

  In FIG. 3, when the selection signal is “1”, “0” and “1” are applied to the respective gate inputs of the N-ch transistors 1h and 1i. The transistor 1i is turned on, and the potential VSSH is supplied from the common drain electrode NS / B to the source electrode of the N-ch transistor 1b in FIG. On the other hand, when the selection signal is “0”, “0” and “1” are applied to the respective gate inputs of the N-ch transistors 1h and 1i, so that the N-ch transistor 1h is on and the N-ch transistor 1i is turned on. Is turned off, and the potential VSSL is supplied from the common drain electrode NS / B to the source electrode of the N-ch transistor 1b in FIG. As described above, since the N-ch transistors 1h and 1i are used as the selector for the ground potential, the potential supplied to the common drain electrode NS / B becomes the potential VSSH or the potential VSSL, and the potential is deteriorated. Can be eliminated.

Embodiment 3 FIG.
FIG. 4 is a circuit diagram showing a selector of the delay circuit according to the third embodiment of the present invention. In the figure, a P-ch transistor (second P-ch transistor) 1k has a substrate electrode connected to a power source and a potential. The configuration is such that VDDH is supplied. Other configurations are the same as those in FIG.

  FIG. 5 is a circuit diagram showing a selector of the delay circuit according to the third embodiment of the present invention. In FIG. 5, an N-ch transistor (second N-ch transistor) 11 has a substrate electrode connected to the ground, and a potential. VSSL is configured to be supplied. Other configurations are the same as those in FIG.

Next, the operation will be described.
The operation in FIG. 4 is the same as the operation in FIG. As described above, since the P-ch transistors 1e and 1k are used for the selector of the power supply potential, the potential supplied to the common drain electrode PS / B becomes the potential VDDH or the potential VDDL, and the potential is deteriorated. Can be eliminated. Further, when VDDH ≧ VDDL, a reverse bias is applied to the P-ch transistor 1k, so that the threshold voltage of the P-ch transistor 1k rises, and the off-leakage current of the P-ch transistor 1k when the selection signal is “1”. It becomes possible to suppress.

  The operation in FIG. 5 is the same as the operation in FIG. As described above, since the N-ch transistors 1h and 1l are used as the selector for the ground potential, the potential supplied to the common drain electrode NS / B becomes the potential VSSH or the potential VSSL, and the potential is deteriorated. Can be eliminated. Further, when VSSH ≧ VSSL, a reverse bias is applied to the N-ch transistor 11, so that the threshold voltage of the N-ch transistor 11 rises and the off-leakage current of the N-ch transistor 11 when the selection signal is “0” is It becomes possible to suppress.

  In the above description, the potential VDDH is supplied to the substrate electrode of the P-ch transistor 1k or the potential VSSL is supplied to the substrate electrode of the N-ch transistor 1l. Furthermore, the potential VDDL may be supplied to the substrate electrode of the P-ch transistor 1e, or the potential VSSH may be supplied to the substrate electrode of the N-ch transistor 1h. When VDDH ≦ VDDL, P-ch The threshold voltage of the transistor 1e increases, and it becomes possible to suppress the off-leak current of the P-ch transistor 1e when the selection signal is “1”, or the threshold voltage of the N-ch transistor 1h when VSSH ≦ VSSL. And the off-leak current of the N-ch transistor 1h when the selection signal is “0” can be suppressed.

Embodiment 4 FIG.
FIG. 6 is a circuit diagram showing the selector of the delay circuit according to the fourth embodiment of the present invention. In the figure, P-ch transistor 1e is configured such that the source electrode is connected to the power supply and potential VDDH is supplied. It is a thing. The N-ch transistor 1m is configured such that the drain electrode is connected to the power supply, the potential VDDL is supplied, and the substrate electrode is connected to the ground. The drain electrode of the P-ch transistor 1e and the source electrode of the N-ch transistor 1m are commonly connected to the source electrode of the P-ch transistor 1a in FIG. The P-ch transistor 1f and the N-ch transistor 1m share the gate electrode and directly input the inverted signal of the selection signal, and operate according to the inverted signal of the selection signal. As described above, the selectors configured by the transfer gates shown in FIG. 6 are used as the switches 1c to nc of the delay circuit shown in FIG.

  FIG. 7 is a circuit diagram showing the selector of the delay circuit according to the fourth embodiment of the present invention. In the figure, N-ch transistor 1h is configured such that the source electrode is connected to the ground and potential VSSL is supplied. It is a thing. The P-ch transistor 1n is configured such that the drain electrode is connected to the ground, the potential VSSH is supplied, and the substrate electrode is connected to the power source. The drain electrode of the N-ch transistor 1h and the source electrode of the P-ch transistor 1n are commonly connected to the source electrode of the N-ch transistor 1b in FIG. The N-ch transistor 1h and the P-ch transistor 1n share the gate electrodes and directly input an inverted signal of the selection signal, and operate according to the inverted signal of the selection signal. As described above, the selectors configured by the transfer gates shown in FIG. 7 are used as the switches 1d to nd of the delay circuit shown in FIG.

Next, the operation will be described.
In FIG. 6, when the inverted signal of the selection signal is “0”, “0” is applied to the respective gate inputs of the P-ch transistor 1e and the N-ch transistor 1m, so that the P-ch transistor 1e is turned on. The N-ch transistor 1m is turned off, and the potential VDDH is supplied from the common electrode PS / B to the source electrode of the P-ch transistor 1a in FIG. On the other hand, when the inverted signal of the selection signal is “1”, “1” is applied to the respective gate inputs of the P-ch transistor 1e and the N-ch transistor 1m, so that the P-ch transistor 1e is turned off and N− The ch transistor 1m is turned on, and the potential VDDL is supplied from the common electrode PS / B to the source electrode of the P-ch transistor 1a in FIG. Thus, since the N-ch transistor 1m is used for the selector of the potential VDDL and the P-ch transistor 1e is used for the selector of the potential VDDH, the potential supplied to the common electrode PS / B is the potential VDDL. Is selected, VDDL-Vthn is lowered by the threshold voltage Vthn of the N-ch transistor 1m, and when the potential VDDH is selected, the potential is not deteriorated and becomes the potential VDDH, thereby eliminating the potential deterioration. it can.

  In FIG. 7, when the inverted signal of the selection signal is “0”, “0” is applied to the respective gate inputs of the N-ch transistor 1h and the P-ch transistor 1n, so that the N-ch transistor 1h is turned off. The P-ch transistor 1n is turned on, and the potential VSSH is supplied from the common electrode PS / B to the source electrode of the N-ch transistor 1b in FIG. On the other hand, when the inverted signal of the selection signal is “1”, “1” is applied to the respective gate inputs of the N-ch transistor 1h and the P-ch transistor 1n, so that the N-ch transistor 1h is turned on and P− The ch transistor 1n is turned off, and the potential VSSL is supplied from the common electrode PS / B to the source electrode of the N-ch transistor 1b in FIG. As described above, since the P-ch transistor 1n is used as the selector for the potential VSS and the N-ch transistor 1h is used as the selector for the potential VSSL, the potential supplied to the common electrode PS / B is the potential VSSH. Is selected, VSSH + Vthp increased by the threshold voltage Vthp of the P-ch transistor 1n. When the potential VSSL is selected, there is no potential deterioration and the potential VSSL is obtained, and the potential deterioration can be eliminated.

In the fourth embodiment, the inverters 1g and 1j for inverting the selection signal are not required as in the second and third embodiments, and the circuit configuration can be simplified.
In addition, since the N-ch transistor 1m is used for selecting the potential VDDL and the P-ch transistor 1n is used for selecting the potential VSSH, when realizing VDDH ≧ VDDL and VSSH ≧ VSSL, the threshold voltages Vthn and Vthp are satisfied. Therefore, even when VDDH = VDDL and VSSH = VSSL, the relationships VDDH> VDDL and VSSH> VSSL are naturally realized, and it is not necessary to supply different types of potentials to the power supply potential and the ground potential. . Further, even when different types of potentials of VDDH and VDDL or VSSH and VSSL are supplied, these potential differences can be further expanded by Vthn or Vthp. Can be amplified.

In the above description, FIG. 6 shows a configuration in which the potential VDDH is supplied to the source electrode of the P-ch transistor 1e and the potential VDDL is supplied to the drain electrode of the N-ch transistor 1m. However, conversely, the potential VDDL may be supplied to the source electrode of the P-ch transistor 1e, and the potential VDDH may be supplied to the drain electrode of the N-ch transistor 1m, and similar effects can be obtained.
Further, FIG. 7 shows a configuration in which the potential VSSL is supplied to the source electrode of the N-ch transistor 1h and the potential VSSH is supplied to the drain electrode of the P-ch transistor 1n. The potential VSSH may be supplied to the source electrode of the N-ch transistor 1h, and the potential VSSL may be supplied to the drain electrode of the P-ch transistor 1n, and similar effects can be obtained.

Embodiment 5. FIG.
FIG. 8 is a circuit diagram showing a delay circuit according to Embodiment 5 of the present invention. In the figure, inverters 11 to 18 correspond to a series circuit of inverters 1 to n in FIG. Is delayed by passing through the plural stages of inverters 11-18. The switches 21 to 28 correspond to the switches 1c to nc in FIG. 1, and are configured such that the potential VDDH or the potential VDDL is selected according to the selection signal.
The priority encoder (first priority encoder) 30 encodes a control signal (first control signal) CNTL input corresponding to the delay time, and selects a selection signal (first selection) for operating the switches 21 to 28. Signal) is generated and supplied to the switches 21-28.

Next, the operation will be described.
Hereinafter, for ease of explanation, a case where the number of gate stages constituting the delay circuit is eight will be described with reference to FIG.
When VDDH ≧ VDDL, when the potential VDDL is selected by the switches 21 to 28 added to the source electrode of the P-ch transistor, the P-ch transistor constituting the delay circuit is reverse-biased, and the potential VDDH is selected. In this case, the delay time increases due to the increase of the threshold voltage Vthp. The priority encoder 30 specifies the number of inverters 11 to 18 that increase the delay value according to the value of the control signal CNTL.
FIG. 9 is a table showing the relationship between the selection signal for the priority encoder and the selection signal for the switch. When the selection signal is “0”, VDDH is selected, and when the selection signal is “1”, VDDL is selected. FIG. 8 shows an example in which the control signal CNTL = "4" is input, and shows a case where the right four of the eight stages of inverters 11 to 18 select VDDL. The output of the priority encoder 30 designates the number of inverter stages whose delay is increased by reverse bias, and it is possible to arbitrarily determine which inverter is physically selected by connecting the output of the selection signal. .

  When VDDH <VDDL, when the potential VDDL is selected by the switches 21 to 28 added to the source electrode of the P-ch transistor, the P-ch transistor constituting the delay circuit is forward biased and the potential VDDH is selected. The delay time is reduced due to the drop in the threshold voltage Vthp. The priority encoder 30 designates the number of inverters 11 to 18 that decrease the delay value according to the value of the control signal CNTL. In FIG. 9, VDDH is selected when the selection signal is “0”, and VDDL is selected when the selection signal is “1”. FIG. 8 shows an example in which the control signal CNTL = "4" is input, and shows a case where the right four of the eight stages of inverters 11 to 18 select VDDL. The output of the priority encoder 30 designates the number of inverter stages whose delay is reduced by forward bias, and which inverter is physically selected can be arbitrarily determined by the connection of the output of the selection signal. .

As described above, according to the fifth embodiment, the delay time of the delay circuit can be switched digitally, and the delay time can naturally be varied by changing the potential difference between VDDH and VDDL. It is. With these two types of delay switching, fine delay value switching can be achieved.
In the fifth embodiment, an inverter is used as the logic gate constituting the delay circuit and the number of gate stages is eight. However, there is no need to limit the logic gate to an inverter, and any logic can be used. The same effect can be obtained even if a gate is used. Of course, there is no restriction on the number of gates.
As the switches 21 to 28, any one of the selectors shown in FIGS. 2, 4, and 6 can be applied.

Embodiment 6 FIG.
FIG. 10 is a circuit diagram showing a delay circuit according to the sixth embodiment of the present invention. In the figure, switches 31 to 38 correspond to the switches 1d to nd of FIG. The potential VSSH is configured to be selected.
The priority encoder (second priority encoder) 40 encodes a control signal (second control signal) CNTL input corresponding to the delay time and operates a selection signal (second selection) for operating the switches 31 to 38. Signal) is generated and supplied to the switches 31-38. Other configurations are the same as those in FIG.

Next, the operation will be described.
Hereinafter, for ease of explanation, a case where the number of gate stages constituting the delay circuit is eight will be described with reference to FIG.
In the case of VSSH ≧ VSSL, when the potential VSSH is selected by the switches 31 to 38 added to the source electrode of the N-ch transistor, the N-ch transistor constituting the delay circuit is reverse-biased, and the potential VSSL is selected. In this case, the delay time increases due to the increase of the threshold voltage Vthn. The priority encoder 40 designates the number of inverters 11 to 18 that increase the delay value according to the value of the control signal CNTL. In FIG. 9, when the selection signal is “0”, VSSL is selected, and when the selection signal is “1”, VSSH is selected. FIG. 10 shows an example in which the control signal CNTL = "4" is input, and shows a case where the right four of the eight stages of inverters 11 to 18 have selected VSSH. The output of the priority encoder 40 designates the number of inverter stages whose delay is increased by reverse bias, and it is possible to arbitrarily determine which inverter is physically selected by connecting the output of the selection signal. .

When VSSH <VSSL, when the potential VSSH is selected by the switches 31 to 38 added to the source electrode of the N-ch transistor, the N-ch transistor constituting the delay circuit is forward-biased and the potential VSSL is selected. As a result, the delay time decreases due to the drop in the threshold voltage Vthn. The priority encoder 40 designates the number of inverters 11 to 18 that decrease the delay value according to the value of the control signal CNTL. In FIG. 9, when the selection signal is “0”, VSSL is selected, and when the selection signal is “1”, VSSH is selected. FIG. 10 shows an example in which the control signal CNTL = "4" is input, and shows a case where the right four of the eight stages of inverters 11 to 18 have selected VSSH. The output of the priority encoder 40 designates the number of inverter stages whose delay is reduced by forward bias, and it is possible to arbitrarily determine which inverter is physically selected by connecting the output of the selection signal. .

As described above, according to the sixth embodiment, the delay time of the delay circuit can be switched digitally, and the delay time can naturally be varied by changing the potential difference between VSSH and VSSL. It is. With these two types of delay switching, fine delay value switching can be achieved.
In the sixth embodiment, an inverter is used as the logic gate constituting the delay circuit and the number of gate stages is eight. However, there is no need to limit the logic gate to an inverter, and any logic The same effect can be obtained even if a gate is used. Of course, there is no restriction on the number of gates.
As the switches 31 to 38, any one of the selectors shown in FIGS. 3, 5, and 7 can be applied.

Embodiment 7 FIG.
FIG. 11 is a circuit diagram showing a delay circuit according to Embodiment 7 of the present invention. In the figure, inverters 11-18, switches 21-28 and priority encoder 30 shown in FIG. 8 are added to switch 31 shown in FIG. To 38, and the priority encoder 40 is combined.

Next, the operation will be described.
Hereinafter, in order to facilitate the description, a case where the number of gate stages constituting the delay circuit is eight will be described with reference to FIG.
When VDDH ≧ VDDL and VSSH ≧ VSSL, the potential VDDL is selected by the switches 21 to 28 added to the source electrode of the P-ch transistor, and the potential VSSH is selected by the switches 31 to 38 added to the source electrode of the N-ch transistor. Is selected, a reverse bias is applied to the P-ch transistor and the N-ch transistor constituting the delay circuit, and the delay time is increased by the increase of the threshold voltages Vthp and Vthn as compared with the case where the potential VDDH or the potential VSSL is selected. . The priority encoders 30 and 40 designate the number of inverters 11 to 18 that increase the delay value according to the value of the control signal CNTL (CNTL-VDD, CNTL-VSS). In FIG. 9, when the selection signal is “0”, VDDH or VSSL is selected, and when the selection signal is “1”, VDDL or VSSH is selected. FIG. 11 shows an example in which the control signals CNTL-VDD = “3” and CNTL-VSS = “6” are input. The right three of the eight-stage inverters 11 to 18 are VDDL and the right six Shows a case where VSS is selected. The outputs of the priority encoders 30 and 40 specify the number of inverter stages to increase the delay by reverse bias, and it is possible to arbitrarily determine which inverter is physically selected by connecting the output of the selection signal. It is.

  When VDDH <VDDL and VSSH <VSSL, the potential VDDL is selected by the switches 21 to 28 added to the source electrode of the P-ch transistor, and the potential VSSH is set by the switches 31 to 38 added to the source electrode of the N-ch transistor. Is selected, forward bias is applied to the P-ch transistor and the N-ch transistor constituting the delay circuit, and the delay time is reduced by lowering of the threshold voltages Vthp and Vthn than when the potential VDDH or the potential VSSL is selected. . The priority encoders 30 and 40 designate the number of inverters 11 to 18 that decrease the delay value according to the value of the control signal CNTL (CNTL-VDD, CNTL-VSS). In FIG. 9, when the selection signal is “0”, VDDH or VSSL is selected, and when the selection signal is “1”, VDDL or VSSH is selected. FIG. 11 shows an example in which the control signals CNTL-VDD = “3” and CNTL-VSS = “6” are input. The right three of the eight-stage inverters 11 to 18 are VDDL and the right six Shows a case where VSS is selected. The outputs of the priority encoders 30 and 40 specify the number of inverter stages whose delay is reduced by forward bias, and it is possible to arbitrarily determine which inverter is physically selected by connecting the output of the selection signal. It is.

As described above, according to the seventh embodiment, the delay time of the delay circuit can be digitally switched, and the potential difference among VDDH, VDDL, VSSH, and VSSL is changed to vary the delay time in an analog manner. Of course it is also possible. With these two types of delay switching for each of the power supply potential and the ground potential, fine delay value switching can be made possible.
Also, the combination of VDDH ≧ VDDL and VSSH <VSSL, or the combination of VDDH <VDDL and VSSH ≧ VSSL, the P-ch transistor of the logic gate constituting the delay circuit is reverse biased, the N-ch transistor is forward biased, or The combination of forward bias for the P-ch transistor and reverse bias for the N-ch transistor can be realized, and the delay time can be controlled more finely.
In the seventh embodiment, an inverter is used as the logic gate constituting the delay circuit and the number of gate stages is eight. However, there is no need to limit the logic gate to an inverter, and any logic The same effect can be obtained even if a gate is used. Of course, there is no restriction on the number of gates.

Embodiment 8 FIG.
12 is a circuit diagram showing a semiconductor integrated circuit using a delay circuit according to the eighth embodiment of the present invention. In the figure, the delay circuits 51 and 52 on the entire chip / function block 50 are the same as those in the first embodiment. 7 corresponds to any one of the delay circuits shown in FIG. 7, and is inserted between the latches 53 and 54 or between the latches 55 and 56 at a place where a malfunction due to the hold may occur. The result determination circuit 57 determines a match comparison between the execution result and the expected value when a predetermined process is executed for the entire chip / functional block 50, and the delay time control circuit 58 determines the result by the result determination circuit 57. The delay time by the delay circuits 51 and 52 is controlled so that the delay time by the delay circuits 51 and 52 is minimized without causing malfunction due to hold.

Next, the operation will be described.
In the eighth embodiment, the delay circuit shown in the first to seventh embodiments is applied to hold measures in a semiconductor integrated circuit.
As shown in FIG. 12, in the entire chip / function block 50, the number of logic gates is small as between the latch 53 and the latch 54, and the clock supplied to the entire chip / function block 50 is shorter than the delay time between the latch 53 and the latch 54. If there is a possibility that the skew value becomes larger, there is a possibility that a malfunction due to hold may occur. As a countermeasure against this hold, a method of inserting a delay between the latch 53 and the latch 54 so that the delay time between the latch 53 and the latch 54 is longer than the clock skew value can be considered. However, if a delay more than necessary is inserted, the circuit scale is increased and the setup is adversely affected. Therefore, it is necessary to insert the minimum necessary delay.

  In the eighth embodiment, in the entire chip / functional block 50, delay circuits are provided for all of the locations that may cause malfunction due to hold, between the latch 53 and the latch 54, between the latch 55 and the latch 56, etc. 51, 52, ... are inserted. In this case, the number of gate stages constituting the delay circuits 51 and 52 is preferably as small as possible in order to reduce the circuit scale. For example, when an inverter is used for the logic gates constituting the delay circuit, the number of stages is two or at most four. The delay time control circuit 58 generates control signals VDDH, VDDL, VSSH, VSSL, and CNTL necessary for delay time control of the delay circuits 51 and 52. An example of this generation method will be described below. Depending on the configuration of the delay circuit used in the delay circuits 51 and 52, there may be a case where all of the control signals VDDH, VDDL, VSSH, VSSL, and CNTL necessary for delay time control are not required. A case where all control signals are required will be described.

  A series of processes prepared in advance are executed for the entire chip / function block 50, and the result determination circuit 57 performs a coincidence comparison between the execution result and the expected value. It is desirable that this series of processes activate most of the circuits of the entire chip / functional block 50, but it is difficult in practice. If it is activated, it will not be a big problem. If a processor is used, it can be easily realized by a method similar to BIST (Built in Self Test). This is realized by controlling the delay time control circuit 58 incrementally as follows based on the determination result in the result determination circuit 57.

  An example of the delay time optimization method of the delay circuits 51 and 52 by the result determination circuit 57 and the delay time control circuit 58 will be described. As the initial value of the control signal output from the delay time control circuit 58, a value that maximizes the delay time of the delay circuits 51 and 52 is used. For example, VDDH, VDDL, VSSH, and VSSL are the maximum potential differences that satisfy VDDH ≧ VDDL and VSSH ≧ VSSL, and CNTL is the maximum value of the number of logic gates for which the delay value is to be increased. When the reset signal REST for the delay time control circuit 58 is input, the control signals VDDH, VDDL, VSSH, VSSL, CNTL are set to this value. After the reset signal REST is released, when the test mode setting signal TMOD for the whole chip / functional block 50 is input, the BIST operation starts. The operation speed at this time is not a maximum speed but a sufficiently low speed. Since high speed operation may cause malfunction due to insufficient setup time, it is desirable that the speed be 10% or less of the maximum speed.

  In the result determination circuit 57, the end of the BIST operation is detected by the output signal End of the whole chip / functional block 50, and then the output signal Result is compared with the expected value, and a result signal GO / ND indicating coincidence / mismatch is output. After the reset signal RES is input, the delay time of the delay circuits 51 and 52 is set to the maximum value, so that malfunction due to hold does not occur. Therefore, when the result signal GO / ND indicates a mismatch, another cause other than the malfunction due to the hold can be considered. In the case of malfunction due to insufficient setup, there is a possibility that it can be solved by further reducing the operation speed. Here, the description will be continued assuming that no malfunction other than the hold will occur.

  After a match is confirmed by the result determination circuit 57 in the BIST operation after the reset signal REST is released, the delay time control circuit 58 resets the control signal CNTL to a value obtained by decrementing the number of gates for which the delay value is to be increased. Thereafter, the test mode setting signal TMOD for the whole chip / functional block 50 is re-input, the BIST operation is started, the end signal is detected by the result determination circuit 57 → the coincidence comparison between the Result signal and the expected value → the GO / NG signal A series of operations of output to the delay time control circuit 58 is executed. When the GO / NG signal indicates a match, the delay time control circuit 58 resets the control signal CNTL to a value obtained by decrementing the number of gates for which the delay value is to be increased. When the number of gates for which the delay value is to be increased becomes the minimum value (“0”), the minimum that can control the potential difference between VDDH and VDDL and VSSH and VSSL with respect to the control signals VDDH, VDDL, VSSH, and VSSL Decrease one step at a time. When setting is possible only for either one of VDDH and VDDL or VSSH and VSSL, control is performed only for the settable group. When setting is possible for both VDDH and VDDL, and VSSH and VSSL, there are various setting methods such as fixing one of them and changing the other, but a predetermined setting method. Accordingly, the potential difference between VDDH and VDDL and between VSSH and VSSL is decreased incrementally.

The above operation is repeated until a mismatch occurs in the result signal GO / ND of the result determination circuit 57. The delay time control circuit 58 includes two sets of registers, an output setting register and an existing state storage register, as registers for storing the states of the control signals VDDH, VDDL, VSSH, VSSL, and CNTL. The output setting register is a register for setting the control signal output of the delay time control circuit 58, and the existing state storage register is a register for storing the previous state of the control signal output on the assumption that the above series of operations are repeated. . Immediately after the reset signal REST is input, the two sets of registers are set to the same value. When a mismatch occurs in the result signal GO / ND of the result determination circuit 57, the delay time control circuit 58 resets the value of the output setting register to the value of the existing state storage register and ends the series of operations.
As described above, by controlling the delay circuits 51 and 52 with the control signals VDDH, VDDL, VSSH, VSSL, and CNTL set in the output setting register of the delay time control circuit 58, the minimum necessary delay that can avoid malfunction due to hold. It becomes possible to give the delay circuits 51 and 52 time.

  In the above description, a case where a set of control signals VDDH, VDDL, VSSH, VSSL, CNTL is output and controlled by the delay time control circuit 58 to the entire chip / functional block 50 has been described. A configuration in which the functional block 50 is divided into a plurality of sub-blocks and a plurality of sets of control signals VDDH, VDDL, VSSH, VSSL, and CNTL are output and controlled for each of the divided sub-blocks is also conceivable. This is an effective method for optimizing the delay time of the delay circuit in units of sub-blocks. However, even in the configuration of the eighth embodiment shown in FIG. 12 used for the description, the same effect can be obtained by adopting a configuration in which the range of the entire chip / functional block 50 is subdivided into sub-blocks and a plurality of blocks are provided in the chip. Is obtained.

Embodiment 9 FIG.
FIG. 13 is a circuit diagram showing a phase adjustment circuit using a delay circuit according to the ninth embodiment of the present invention. In the figure, the phase adjustment circuit 60 includes an input signal Ain and a reference signal Bin inputted from an input block 61. Are output to the output block 62 as the output signal Aout and the output signal Bout. In the phase adjustment circuit 60, the delay circuit 63 corresponds to any one of the delay circuits shown in the first to seventh embodiments, and delays and outputs the input signal (first digital signal) Ain. Is. The reference circuit 64 delays and outputs a reference signal (second digital signal) Bin. The phase comparison circuit 65 performs a phase comparison between the output signal Aout from the delay circuit 63 and the output signal Bout from the reference circuit 64. The delay time control circuit 66 matches the phase comparison result by the phase comparison circuit 65. Thus, the delay time by the delay circuit 63 is controlled.

Next, the operation will be described.
In the ninth embodiment, the delay circuit shown in the first to seventh embodiments is applied to the phase adjustment circuit.
In FIG. 13, a delay circuit 63 delays an input signal Ain by a desired delay time and outputs it as an output signal Aout, and uses any one of the delay circuits of the first to seventh embodiments. The type and the number of stages of logic gates constituting the delay circuit 63 are determined within an adjustable phase range. If the phase range that needs to be adjusted is large, a logic gate having a larger delay time per logic gate is used, and the number of stages naturally increases. However, it goes without saying that it is necessary to keep the minimum number of stages to avoid the problem of an increase in circuit scale.
The reference circuit 64 delays the reference signal Bin for phase adjustment by an appropriate delay time for phase adjustment and outputs it as an output signal Bout. When the phase shift between the input signal Ain and the reference signal Bin is known in advance, the input signal Ain is always better than the reference signal Bin for the purpose of delaying this phase shift in advance. If it is advanced or the phase relationship is unknown in advance, it is not necessary to insert a delay. In this case, the reference signal Bin is passed through and output as the output signal Bout.

  The phase comparison circuit 65 detects the phase relationship between the output signals Aout and Bout and generates an output signal UP / DN for delay time control to the delay time control circuit 66. Hereinafter, an example in which the rising edges have the same phase will be described. The other Bout and Aout are sampled at the rising edges of the output signals Aout and Bout, respectively. As a result, if (Aout, Bout) = (↑, 0) and (Aout, Bout) = (1, ↑), the rising edge of the output signal Aout is advanced, so that the output signal Aout is delayed. “DN” is output. If (Aout, Bout) = (↑, 1) and (Aout, Bout) = (0, ↑), the rising edge of the output signal Aout is delayed. UP ”is output. The output timing of the output signal UP / DN is output in synchronization with the synchronization signal SYNC. In order to make the phase of the edge the same at the falling edge, it can be realized by the same method as described above only by sampling the other Bout and Aout at the falling of each of Aout and Bout.

  The delay time control circuit 66 generates control signals VDDH, VDDL, VSSH, VSSL, CNTL for the delay circuit 63 based on the output signal UP / DN of the phase comparison circuit 65. Depending on the configuration of the delay circuit used in the delay circuit 63, there are cases where not all the control signals are required. In the following description, an example of the operation when all the control signals are required will be described. When the reset signal REST for the delay time control circuit 66 is input, the control signals VDDH, VDDL, VSSH, VSSL, and CNTL are set to the following initial values. VDDH, VDDL, VSSH, and VSSL are maximum potential differences that satisfy VDDH ≧ VDDL and VSSH ≧ VSSL, and CNTL is an intermediate value between the maximum value and the minimum value of the number of logic gates for which the delay value is to be increased. After the reset signal REST is released, the output signal UP / DN of the phase comparison circuit 65 is detected in synchronization with the synchronization signal SYNC, and in the case of “UP”, the CNTL is reset to one smaller value and the “DN” In this case, CNTL is reset to one larger value. The delay time control circuit 66 has an existing UP / DN register that stores the previous state of the output signal UP / DN of the phase comparison circuit 65. The comparison between the existing UP / DN register and the output signal UP / DN is performed every time in synchronization with the synchronization signal SYNC, and the operation of controlling the control signal CNTL is repeated until the comparison result is different.

  When “DN” continues and CNTL reaches the maximum value of the number of logic gates for which the delay value is to be increased, it is impossible to increase the delay value any more, so “OV” for the output flag OV / UN. "Is output and the process ends. When “UP” continues and CNTL reaches the minimum value of the number of logic gates whose delay value is to be increased, the control signals VDDH, VDDL, VSSH, and VSSL are controlled as follows. Since VDDH ≧ VDDL and VSSH ≧ VSSL, the potential difference between VDDH and VDDL and between VSSH and VSSL is reduced with the minimum potential that can control the potential difference between VDDH and VDDL and VSSH and VSSL as a unit. The process is performed in synchronization with SYNC until the comparison result between the existing UP / DN register and the output signal UP / DN is different. Still, when “UP” continues and VDDH = VDDL and VSSH = VSSL, the next is set to VDDH <VDDL and VSSH <VSSL, and the delay value is further reduced by forward bias. Furthermore, when “UP” continues and the maximum potential difference of the forward bias is reached, it is impossible to reduce the delay value any more, so “UN” is output to the output flag OV / UN and processed. Exit.

  When the comparison result between the existing UP / DN register and the output signal UP / DN is different, the control signals VDDH, VDDL, VSSH, and VSSL are controlled according to the following. Since VDDH ≧ VDDL and VSSH ≧ VSSL, the potential difference between VDDH and VDDL and between VSSH and VSSL is reduced with the minimum potential that can control the potential difference between VDDH and VDDL and VSSH and VSSL as a unit. The process is performed in synchronization with SYNC until the comparison result between the existing UP / DN register and the output signal UP / DN becomes the same. If “UP” continues, the minimum potential that can control the potential difference in the direction of VDDH <VDDL is reset in units. If “DN”, the minimum potential that can control the potential difference in the direction of VDDH> VDDL is set. Reset in units. The operation of controlling the control signals VDDH, VDDL, VSSH, and VSSL is repeated until the comparison result between the existing UP / DN register and the output signal UP / DN is different.

  In the control of the control signals VDDH, VDDL, VSSH, and VSSL, when setting is possible only for one of VDDH and VDDL or VSSH and VSSL, the control is performed only for the settable. When setting is possible for both VDDH and VDDL, and VSSH and VSSL, there are various setting methods such as fixing one of them and changing the other, but a predetermined setting method. Accordingly, the minimum potential that can control the potential difference between VDDH and VDDL and between VSSH and VSSL is controlled as a unit.

In the above description, as the initial values of the control signals VDDH, VDDL, VSSH, and VSSL after the reset signal REST is input to the delay time control circuit 66, VDDH, VDDL, VSSH, and VSSL are the maximum potential differences that satisfy VDDH ≧ VDDL and VSSH ≧ VSSL. CNTL described the case where the delay value is set to an intermediate value between the maximum value and the minimum value of the number of logic gates to be increased. As this initial value, VDDH, VDDL, VSSH, and VSSL can be set to VDDH = VDDL and VSSH = VSSL, or can be set to a maximum potential difference that satisfies VDDH <VDDL and VSSH <VSSL. In either case, by first determining the number of gate stages by CNTL and then determining the potential difference by VDDH, VDDL, VSSH, and VSSL, it becomes possible to perform fine phase alignment after rough phase alignment. .
As described above, it is possible to realize a phase adjustment circuit with a small circuit configuration and fine resolution.

Embodiment 10 FIG.
FIG. 14 is a circuit diagram showing a DLL (Delay Locked Loop) circuit using a delay circuit according to the tenth embodiment of the present invention. In the figure, the phase adjustment circuit 60 is equivalent to FIG. The circuit 63 inputs the clock signal CLKout to be phase-adjusted by the functional block 70 as the input signal Ain, and outputs the clock signal CLKin of the functional block 70 as the delayed output signal Aout. The reference circuit 64 inputs the reference clock signal CLKbase for adjusting the phase as the reference signal Bin, and outputs it with a delay. The phase comparison circuit 65 compares the phase of the input signal Ain input to the delay circuit 63 and the reference signal Bin input to the reference circuit 64.
The functional block 70 includes a clock driver 71, clock tree drivers 72 to 74, and a latch 75. The functional block 70 receives a clock signal CLKin, outputs a clock signal CLKout that has passed through the clock tree driver 74 before the latch 75, and outputs to the delay circuit 63. Input.

Next, the operation will be described.
In the tenth embodiment, in order to match the phase of the clock signal CLKout of the functional block 70 with the phase of the reference clock signal CLKbase, the phase comparison circuit 65 is moved to the input signal side in the phase adjustment circuit shown in the ninth embodiment. Applied.
In FIG. 14, the output signal Aout of the delay circuit 63 of the phase adjustment circuit 60 is input to the clock signal CLKin for the functional block 70, and the clock signal CLKout that is a target for phase adjustment of the functional block 70 is output. The clock signal CLKout may be directly output from the clock signal CLKin, but after the clock signal CLKin is driven by the clock driver 71, the signal before being supplied to the latch 75 at the end through the clock tree driver 74 used for clock distribution. Is generally output as the clock signal CLKout. The input signal Ain of the phase adjustment circuit 60 is inputted with the clock signal CLKout of the functional block 70 to be subjected to clock phase adjustment, and the reference signal Bin is inputted with the reference clock signal CLKbase for adjusting the phase.
With the above configuration, based on the operation principle of the phase adjustment circuit 60 described in the ninth embodiment, it is possible to easily match the phase of the clock signal CLKout in the functional block 70 with the phase of the reference clock signal CLKbase.

Embodiment 11 FIG.
FIG. 15 is a circuit diagram showing a semiconductor integrated circuit using a delay circuit according to the eleventh embodiment of the present invention. In FIG. Each of the functional blocks divided into a plurality of blocks is provided with a DLL circuit.
The phase adjustment circuit 60a including the reference circuit 64a, and the functional block 70a including the clock driver 71a, the clock tree drivers 72a to 74a, and the latch 75a are equivalent to the DLL circuit shown in FIG. Phase adjustment circuit 60b including a reference circuit 64b, a clock driver 71b, clock tree drivers 72b to 74b, a functional block 70b including a latch 75b, a phase adjustment circuit 60c including a reference circuit 64c, a clock driver 71c, a clock A functional block 70c including the tree drivers 72c to 74c and the latch 75c is equivalent to the DLL circuit shown in FIG. These DLL circuits are used for clock skew adjustment between the functional blocks 70a to 70c divided into a plurality of parts.

Next, the operation will be described.
In the eleventh embodiment, the DLL circuit shown in the tenth embodiment is applied to the clock skew adjustment between the functional blocks 70a to 70c divided into a plurality of parts.
In the entire chip / system 80 shown in FIG. 15, the range that requires the supply of the reference clock signal CLKbase is divided into a plurality of functional blocks 70a, 70b, 70c,. The clock skew adjustment in the functional blocks 70a to 70c is performed using a technique such as a clock tree and a clock mesh in each functional block. The skew adjustment between the functional blocks 70a to 70c is performed by the phase adjustment circuits 60a to 60c provided in the respective functional blocks 70a to 70c, and the reference clock signal CLKbase distributed to the respective functional blocks 70a to 70c and the inside of each functional block. This can be realized by adjusting the phase of the distributed clock signal CLKout.

  The output signal Aout of each of the phase adjustment circuits 60a to 60c is input to the clock signal CLKin for each of the functional blocks 70a to 70c, and the clock signal that is the phase adjustment target of the functional blocks 70a to 70c is output as CLKout. Although CLKin may be directly output as CLKout, it is general that CLKin is distributed in each of the functional blocks 70a to 70c and a signal before being supplied to the respective latches 75a to 75c is output as CLKout. . Each of the input signals Ain of the phase adjustment circuits 60a to 60c is distributed to the clock signal CLKout of each of the functional blocks 70a to 70c to be subjected to clock phase adjustment, and the input signal Bin is distributed to the entire chip / system 80. The reference clock signal CLKbase is input.

In the distribution of the reference clock signal CLKbase, devices such as equal-length wiring distribution, clock tree distribution, and H-tree structure distribution are used so that there is no difference in the delay time for reaching the clock signal CLKin of each of the functional blocks 70a to 70c. is required. However, when the delay time difference reaching each CLKin of each functional block 70a to 70c is known in advance, or when it is desired to intentionally add a delay difference to a specific functional block, the phase adjustment circuit 70a The reference circuits 64a to 64c provided in the respective .about.70c can be easily dealt with by giving a desired delay.
As described above, even in the large-scale block of the whole chip / the whole system 80 where clock skew adjustment is difficult, only by adding the phase adjustment circuits 60a-60c having a small circuit configuration to each of the divided functional blocks 70a-70c, Clock skew adjustment can be easily realized.

Embodiment 12 FIG.
FIG. 16 is a circuit diagram showing a PLL (Phase Locked Loop) circuit using a delay circuit according to the twelfth embodiment of the present invention. In the figure, a phase adjustment circuit 60 is equivalent to FIG. The / N frequency dividing circuit 90 divides the clock signal CLKxn output from the delay circuit 63 by 1 / N (N is an arbitrary natural number) and inputs it to the delay circuit 63. The reference circuit 64 inputs the reference clock signal CLKbase for adjusting the phase as the reference signal Bin, and outputs it with a delay.

Next, the operation will be described.
In the twelfth embodiment, the phase adjustment circuit shown in the tenth embodiment is applied to obtain a clock obtained by multiplying the reference clock.
In FIG. 16, when the output signal Aout of the delay circuit 63 of the phase adjustment circuit 60 is input to the 1 / N frequency dividing circuit 90, a clock signal whose frequency is divided by 1 / N is output. Therefore, a clock signal obtained by dividing the period of the output signal Aout by 1 / N is input to the input signal Ain of the phase adjustment circuit 60, and the reference clock signal CLKbase is input to the input signal Bin. . As a result, the phase of the reference clock signal CLKbase and the 1 / N frequency divided clock of the input signal Ain is adjusted, and a clock obtained by multiplying the reference clock signal CLKbase by N is output to the output signal Aout, that is, the clock signal CLKxn.
With the above configuration, a clock obtained by multiplying the reference clock signal CLKbase by N can be easily obtained based on the operation principle of the phase adjustment circuit 60 described in the ninth embodiment.

Embodiment 13 FIG.
FIG. 17 is a circuit diagram showing a PLL circuit using a delay circuit according to the thirteenth embodiment of the present invention. In the figure, phase adjustment circuit 60 and functional block 70 are equivalent to those in FIG. The N frequency dividing circuit 90 divides the clock signal CLKout passed through the clock tree driver 74 before the latch 75 of the functional block 70 by 1 / N and inputs it to the delay circuit 63.

Next, the operation will be described.
The thirteenth embodiment is shown in the tenth embodiment in order to obtain a clock obtained by matching the phase of the clock signal CLKout of the functional block 70 with the phase of the reference clock signal CLKbase and further multiplying the reference clock signal CLKbase by N. The DLL circuit is applied.
In FIG. 17, the output signal Aout of the delay circuit 63 of the phase adjustment circuit 60 is input to the clock signal CLKin for the functional block 70, and the clock signal to be phase adjusted by the functional block 70 is output as CLKout. CLKout may be directly output from CLKin. However, after CLKin is driven by the clock driver 71, a signal before being supplied to the terminal latch 75 via the clock tree driver 74 used for clock distribution is output as CLKout. It is common. The input signal Ain of the phase adjustment circuit 60 is inputted with a clock obtained by dividing the output signal CLKout of the functional block 70 to be subjected to the multiplication clock phase adjustment by the 1 / N frequency divider 90 so that the clock cycle is 1 / N. A reference clock signal CLKbase for adjusting the phase is input to the input signal Bin. As a result, the phase adjustment between the reference clock signal CLKbase and the 1 / N frequency divided clock of CLKout of the functional block 70 is performed. That is, since the clock signal CLKout used for phase adjustment at this time is a clock obtained by multiplying the reference clock signal CLKbase by N, the N-multiplied clock having a phase matching with the reference clock signal CLKbase is supplied to the functional block 70. Will be supplied.
With the above configuration, based on the operation principle of the phase adjustment circuit 60 described in the ninth embodiment, the phase of the reference clock signal CLKbase is matched with that of the specific function block 70, and the reference clock signal CLKbase is multiplied by N. A clock can be easily supplied.

1 is a circuit diagram showing a delay circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the selector of the delay circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the selector of the delay circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the selector of the delay circuit by Embodiment 3 of this invention. It is a circuit diagram which shows the selector of the delay circuit by Embodiment 3 of this invention. It is a circuit diagram which shows the selector of the delay circuit by Embodiment 4 of this invention. It is a circuit diagram which shows the selector of the delay circuit by Embodiment 4 of this invention. It is a circuit diagram which shows the delay circuit by Embodiment 5 of this invention. It is a table | surface figure which shows the relationship between the selection signal with respect to a priority encoder, and the selection signal with respect to a switch. It is a circuit diagram which shows the delay circuit by Embodiment 6 of this invention. It is a circuit diagram which shows the delay circuit by Embodiment 7 of this invention. It is a circuit diagram which shows the semiconductor integrated circuit using the delay circuit by Embodiment 8 of this invention. It is a circuit diagram which shows the phase adjustment circuit using the delay circuit by Embodiment 9 of this invention. It is a circuit diagram which shows the DLL circuit using the delay circuit by Embodiment 10 of this invention. It is a circuit diagram which shows the semiconductor integrated circuit using the delay circuit by Embodiment 11 of this invention. It is a circuit diagram which shows the PLL circuit using the delay circuit by Embodiment 12 of this invention. It is a circuit diagram which shows the PLL circuit using the delay circuit by Embodiment 13 of this invention.

Explanation of symbols

  1-n inverter (logic gate), 1a-na, 1n P-ch transistor, 1b-nb, 1m N-ch transistor, 1c-nc switch (first switch group), 1d-nd switch (second switch) Group), 1e P-ch transistor (first P-ch transistor), 1f, 1k P-ch transistor (second P-ch transistor), 1g, 1j inverter, 1h N-ch transistor (first N-channel transistor) -Ch transistor), 1i, 1l N-ch transistor (second N-ch transistor), 11-18 inverter, 21-28, 31-38 switch, 30 priority encoder (first priority encoder), 40 priority encoder (Second priority encoder), 50 chips / machine Block, 51, 52, 63 delay circuit, 53-56, 75, 75a-75c latch, 57 result judgment circuit, 58, 66 delay time control circuit, 60, 60a-60c phase adjustment circuit, 61 input block, 62 output block 64, 64a to 64c reference circuit, 65 phase comparison circuit, 70, 70a to 70c functional block, 71, 71a to 71c clock driver, 72 to 74, 72a to 72c, 73a to 73c, 74a to 74c clock tree driver, 80 Whole chip / whole system, 90 1 / N divider circuit.

Claims (18)

A logic gate composed of a P-ch transistor and an N-ch transistor;
A series circuit formed by connecting the logic gates in a plurality of stages, and delaying an input digital signal by passing the logic gates in the plurality of stages;
A first potential supply circuit for supplying a first potential to the substrate electrode of each P-ch transistor;
A second potential supply circuit for supplying a second potential;
A first switch group connected to the source electrode of each P-ch transistor and selecting the first potential or the second potential as a potential supplied to the source electrode;
The delay characterized in that at least one of the first potential supplied from the first potential supply circuit and the second potential supplied from the second potential supply circuit is adjustable. circuit. A logic gate composed of a P-ch transistor and an N-ch transistor;
A series circuit formed by connecting the logic gates in a plurality of stages, and delaying an input digital signal by passing the logic gates in the plurality of stages;
A third potential supply circuit for supplying a third potential to the substrate electrode of each N-ch transistor;
A fourth potential supply circuit for supplying a fourth potential;
A second switch group connected to the source electrode of each N-ch transistor and selecting the third potential or the fourth potential as a potential supplied to the source electrode;
The delay characterized in that at least one of the third potential supplied from the third potential supply circuit and the fourth potential supplied from the fourth potential supply circuit is adjustable. circuit. A logic gate composed of a P-ch transistor and an N-ch transistor;
A series circuit formed by connecting the logic gates in a plurality of stages, and delaying an input digital signal by passing the logic gates in the plurality of stages;
A first potential supply circuit for supplying a first potential to the substrate electrode of each P-ch transistor;
A second potential supply circuit for supplying a second potential;
A first switch group connected to the source electrode of each of the P-ch transistors and selecting the first potential or the second potential as a potential supplied to the source electrode;
A third potential supply circuit for supplying a third potential to the substrate electrode of each N-ch transistor;
A fourth potential supply circuit for supplying a fourth potential;
A second switch group connected to the source electrode of each N-ch transistor and selecting the third potential or the fourth potential as a potential supplied to the source electrode;
At least one of the first potential supplied from the first potential supply circuit and the second potential supplied from the second potential supply circuit is adjustable, and the third potential is adjusted. A delay circuit, wherein at least one of a third potential supplied from a potential supply circuit and a fourth potential supplied from the fourth potential supply circuit is adjustable. The first switch group
A first P-ch transistor connected to the first potential supply circuit and operating in response to a selection signal;
4. The selector comprising a transfer gate having a second P-ch transistor connected to a second potential supply circuit and operating in response to a selection signal. Delay circuit. The second group of switches
A first N-ch transistor connected to the third potential supply circuit and operating in response to a selection signal;
4. The selector comprising a transfer gate having a second N-ch transistor connected to a fourth potential supply circuit and operating in response to a selection signal. Delay circuit.   The substrate electrode of the second P-ch transistor is connected to the first potential supply circuit, or the substrate electrode of the first P-ch transistor is connected to the second potential supply circuit. The delay circuit according to claim 4.   The substrate electrode of the second N-ch transistor is connected to the third potential supply circuit, or the substrate electrode of the first N-ch transistor is connected to the fourth potential supply circuit. The delay circuit according to claim 5. The first switch group
A selector composed of a transfer gate having a P-ch transistor and an N-ch transistor operating in response to a selection signal;
When a P-ch transistor is connected to the first potential supply circuit, an N-ch transistor is connected to the second potential supply circuit, and an N-ch transistor is connected to the first potential supply circuit. 4. The delay circuit according to claim 1, wherein a P-ch transistor is connected to the second potential supply circuit. The second group of switches
A selector composed of a transfer gate having a P-ch transistor and an N-ch transistor operating in response to a selection signal;
When an N-ch transistor is connected to the third potential supply circuit, a P-ch transistor is connected to the fourth potential supply circuit, and a P-ch transistor is connected to the third potential supply circuit 4. The delay circuit according to claim 2, wherein an N-ch transistor is connected to the fourth potential supply circuit.   A first priority encoder that encodes a first control signal input corresponding to the delay time, generates a first selection signal for operating the first switch group, and supplies the first selection signal to the first switch group; The delay circuit according to claim 1, further comprising a delay circuit according to claim 1, wherein the delay circuit is provided.   A second priority encoder that encodes a second control signal input corresponding to the delay time, generates a second selection signal for operating the second switch group, and supplies the second selection signal to the second switch group; The delay circuit according to any one of claims 2, 3, 5, 7, and 9, wherein the delay circuit is provided. A first priority encoder that encodes an input first control signal corresponding to the delay time, generates a first selection signal for operating the first switch group, and supplies the first selection signal to the first switch group; ,
A second priority encoder that encodes a second control signal input corresponding to the delay time, generates a second selection signal for operating the second switch group, and supplies the second selection signal to the second switch group; 4. The delay circuit according to claim 3, further comprising a delay circuit. The delay circuit according to any one of claims 1 to 12, wherein the delay circuit is inserted in a place where there is a risk of malfunction due to hold in the entire chip or the functional block.
A result determination circuit for determining a coincidence comparison between an execution result and an expected value when a predetermined process is executed for the entire chip or the functional block;
A semiconductor integrated circuit comprising: a delay time control circuit for controlling a delay time by the delay circuit so that the determination by the result determination circuit does not cause a malfunction due to hold and the delay time by the delay circuit is minimized. The delay circuit according to any one of claims 1 to 12, wherein the first digital signal input is output after being delayed;
A reference circuit for delaying and outputting an input second digital signal;
A phase comparison circuit for performing phase comparison between the first digital signal output from the delay circuit and the second digital signal output from the reference circuit;
A phase adjustment circuit comprising: a delay time control circuit that controls a delay time by the delay circuit so that phase comparison results by the phase comparison circuit match. The delay circuit according to any one of claims 1 to 12, wherein a clock signal to be phase-adjusted for a functional block is input, delayed and output as a clock signal for the functional block;
A reference circuit for inputting a reference clock signal for adjusting the phase and outputting the delayed signal, and
A phase comparison circuit for performing phase comparison between a clock signal input to the delay circuit and a reference clock signal input to the reference circuit;
A DLL circuit comprising: a delay time control circuit that controls a delay time by the delay circuit so that phase comparison results by the phase comparison circuit match.   The DLL circuit according to claim 15 is provided in each of the plurality of divided functional blocks in the entire chip or the entire system, and the DLL circuits are used for clock skew adjustment between the divided functional blocks. A semiconductor integrated circuit. The delay circuit according to any one of claims 1 to 12, wherein an input clock signal is delayed and output;
A 1 / N frequency dividing circuit that divides the clock signal output from the delay circuit by 1 / N (N is an arbitrary natural number) and inputs the frequency divided to the delay circuit;
A reference circuit that delays and outputs an input reference clock signal;
A phase comparison circuit for performing phase comparison between a clock signal input to the delay circuit and a reference clock signal input to the reference circuit;
A PLL circuit comprising: a delay time control circuit for controlling a delay time by the delay circuit so that phase comparison results by the phase comparison circuit match. A 1 / N frequency dividing circuit that inputs a clock signal to be subjected to phase adjustment of the functional block and divides the frequency by 1 / N (N is an arbitrary natural number)
The delay circuit according to any one of claims 1 to 12, wherein a clock signal divided by 1 / N by the 1 / N divider circuit is delayed and output as a clock signal of the functional block;
A reference circuit for inputting a reference clock signal for adjusting the phase and outputting the delayed signal, and
A phase comparison circuit for performing phase comparison between a clock signal input to the delay circuit and a reference clock signal input to the reference circuit;
A PLL circuit comprising: a delay time control circuit for controlling a delay time by the delay circuit so that phase comparison results by the phase comparison circuit match.

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