JP2006032630A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having TFT with different characteristics suitable for a TFT for the pixels of a display device and a high speed operation TFT for a driving circuit. <P>SOLUTION: This semiconductor device is provided with a first poly-crystal silicon layer 24b poly-crystallized by excimer laser irradiation, a second poly-crystal silicon layer 24c poly-crystallized by CW laser irradiation arranged at the upper part of an insulating substrate 21 with an amorphous silicon layer as departure materials, a first gate insulating film of lamination including first and second insulating layers 25 and 27 formed on the first island-shaped poly-crystallized silicon layer 24b, a second gate insulating film formed at the upper part of at least a portion of the second island-shaped poly-crystallized silicon layer 24c and formed including either the first or second insulating layer 25 and 27, and first and second gate electrodes 28 and 26 formed on the gate insulating film. The first and second channel regions are provided with different impurity doping concentrations. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a thin film transistor and a manufacturing method thereof, and more particularly to a semiconductor device using a polycrystalline silicon thin film and a manufacturing method thereof.

  In recent years, liquid crystal display devices and organic EL display devices have been used as flat panel displays. When an active matrix including a switching (active) element such as a thin film transistor (TFT) is used for each display pixel, the function of the display device can be enhanced. Such an active matrix substrate is widely used for PCs (personal computers), mobile phones and the like.

  When a thin film transistor (TFT) is formed on a glass substrate, an amorphous silicon layer was initially used due to the limitation of the heat resistant temperature of the glass substrate. In recent years, high-performance polycrystalline silicon with significantly improved mobility compared to amorphous silicon transistors by polycrystallizing an amorphous silicon layer or by depositing a polycrystalline silicon layer from the beginning A transistor is obtained. When a polycrystalline silicon layer is used, a driver circuit can be mounted on the same substrate. With such a configuration, development is progressing with the aim of further improving performance and reducing power consumption.

  A technique is used in which an amorphous silicon layer is scanned and polycrystallized with a linear excimer laser beam. Crystallization of a large area amorphous silicon layer can be performed efficiently. However, the grain size of the obtained polycrystalline silicon is small.

  In order to further improve the performance of TFT, a new crystallization technique has also been proposed. It is said that a larger crystal grain size can be obtained by using a continuous wave (CW) laser and causing lateral growth. The CW laser has a spot shape, and is crystallized after processing the semiconductor layer into an island shape.

  The driving circuit of the liquid crystal display device includes a display controller and a shift register, which are preferably operated at high speed. A TFT that requires high-speed operation preferably has a short channel length and does not have an LDD structure. For this reason, it is desirable that the power supply voltage of the circuit is small. In general, in order to lower the power supply voltage, it is necessary to lower the threshold value of the TFT, and the gate insulating film needs to be thinned.

  The driving circuit of the liquid crystal display device also includes an output buffer, a level shifter, and an analog switch that are desirably high withstand voltage. The TFTs in these circuits require a higher breakdown voltage than high-speed operation. Pixel TFTs also require a higher breakdown voltage than high-speed operation. The high breakdown voltage TFT needs to withstand a desired high voltage, and a conventional TFT structure having a gate insulating film thickness and LDD is desirable.

  It is difficult to satisfy the requirements of both a high-speed operation (low breakdown voltage) TFT and a high breakdown voltage TFT with the same TFT structure. Therefore, a technique for forming two types of TFTs on the same substrate has been proposed. A thick gate insulating film is formed on the high breakdown voltage TFT, and a thin gate insulating film is formed on the high speed operation (low breakdown voltage) TFT.

  Japanese Patent Laid-Open No. 2003-45892 forms an island-shaped semiconductor layer, then forms a first gate insulating layer suitable for a low breakdown voltage TFT, forms a gate electrode on the low breakdown voltage transistor, In the pixel transistor, it is proposed that a second gate insulating layer is further stacked on the first gate insulating layer, and a gate electrode is formed thereon. The first gate insulating layer of the low breakdown voltage transistor has a thickness of 30 nm, for example, and the gate insulating layer of the high breakdown voltage transistor and the pixel transistor, which is a stack of the first and second gate insulating films, has a thickness of 130 nm, for example.

  In JP 2003-86505 A, an amorphous semiconductor layer is patterned into an island shape, and then a continuous wave (CW) laser beam is irradiated from the back surface of the transparent substrate using a semiconductor (LD) excited solid laser (DPSS laser). Have proposed a technology for polycrystallization. According to this crystallization method, it is described that large crystal grains can be realized.

  In the TFT manufacturing process, the impurity is activated by laser annealing using an excimer laser or thermal annealing. When excimer laser annealing is used, low resistance aluminum or aluminum alloy can also be used as the gate wiring. Thermal annealing is more desirable in order to obtain high reliability. In particular, when the high-speed operation circuit is constituted by a dedicated TFT or when crystallization is performed by CW laser light, thermal annealing is desired for the activation of impurities. When performing thermal annealing, it is inappropriate to use aluminum or an aluminum alloy as the gate wiring, and a refractory metal is used.

  Japanese Patent Application Laid-Open No. 11-281997 states that TFTs for driving circuits need low thresholds and high mobility, and TFTs for pixels need high thresholds and low mobility. In order to satisfy these requirements, non-doped amorphous A part of the silicon layer is etched and thinned, and a B-doped amorphous silicon layer is laminated thereon and crystallized. The pixel TFT is a polycrystalline film having a small average grain size and a small mobility. It is proposed that the TFT for a drive circuit formed of a silicon layer is formed of a polycrystalline silicon layer having a high B concentration and a thin film having a large average particle size and a large mobility.

JP 2003-45892 A JP 2003-86505 A JP-A-11-281997

An object of the present invention is to provide a semiconductor device having TFTs with different characteristics suitable for pixel TFTs and high-speed operation TFTs for driving circuits, and a method for manufacturing the same.
Another object of the present invention is to provide a semiconductor device having a high breakdown voltage TFT and a low breakdown voltage high-speed operation TFT and having improved characteristics and a method for manufacturing the same.

According to one aspect of the present invention,
An insulating substrate;
A first island-shaped polycrystalline silicon layer disposed above the insulating substrate and made polycrystalline by irradiation with an excimer laser using an amorphous silicon layer as a starting material;
A second island-like polycrystalline silicon layer disposed above the insulating substrate and made polycrystalline by irradiation with CW laser using the amorphous silicon layer as a starting material;
A first gate insulating film formed on the first island-like polycrystalline silicon layer and formed of a stack including the first and second insulating layers;
A second gate formed on the second island-like polycrystalline silicon layer and including only one of the first and second insulating layers and having a lower breakdown voltage than the first gate insulating film An insulating film;
A first gate electrode formed on the first gate insulating film and defining a first channel region below;
A second gate electrode formed on the second gate insulating film and defining a second channel region below;
There is provided a semiconductor device in which the first channel region and the second channel region have different impurity doping concentrations for aligning a threshold value.

According to another aspect of the invention,
(A) depositing an amorphous silicon layer above the insulating substrate;
(B) polycrystallizing the first region of the amorphous silicon layer with an excimer laser to form a first polycrystalline silicon layer;
(C) polycrystallizing the second region of the amorphous silicon layer with a CW laser to form a second polycrystalline silicon layer;
(D) forming a first gate insulating film including a stack of a first insulating layer and a second insulating layer on the first polycrystalline silicon layer, and forming a first gate electrode thereon; Defining a first channel region below the first channel region;
(E) forming a second gate insulating film including only one of the first and second insulating layers on the second polycrystalline silicon layer, and forming a second gate electrode thereon; Forming and defining a second channel region thereunder;
(F) a step of selectively doping the first region or the second region with an impurity for controlling a threshold;
A first thin film transistor is formed using the first polycrystalline silicon layer, the first gate insulating film, and the first gate electrode, and the second polycrystalline silicon layer and the second gate insulating layer There is provided a method for manufacturing a semiconductor device in which a second thin film transistor is formed using a second gate electrode.

  A polycrystalline semiconductor film with a large grain size and a polycrystalline semiconductor film with a small grain size can be obtained from the same amorphous semiconductor thin film, and low-voltage high-speed operation TFTs and high-voltage TFTs are provided using gate insulating films with different film thicknesses can do. The threshold value can be made uniform by performing selective doping.

  Among TFTs of liquid crystal display devices, there are TFTs that desirably operate at high speed, and TFTs that desirably have high breakdown voltage and low leakage current, such as pixel TFTs. Polycrystallization using a CW laser is suitable for polycrystallizing a selected region, and is suitable for producing a polycrystal TFT having a large grain size, high mobility, and high off-leakage current. Polycrystallization with an excimer laser is suitable for polycrystallizing the entire surface, and is suitable for producing a polycrystalline TFT having a small particle size, low mobility, and low off-leakage current. Therefore, it is conceivable that the high-speed operation unit creates a TFT with a silicon layer polycrystallized with a CW laser, and the high withstand voltage unit produces a TFT with a polycrystallized silicon layer with an excimer laser. Hereinafter, the experiment and the results conducted by the inventors will be described.

  As shown in FIG. 1A, on a glass substrate 11, a silicon nitride (SiN) layer 12 having a thickness of 50 nm, a silicon oxide (SiO) layer 13 having a thickness of 200 nm, and a thickness 50 doped with boron (B). A ~ 60 nm amorphous silicon layer 14 was deposited by thermal chemical vapor deposition (CVD). The doping amount of B adjusts the threshold value of the obtained TFT. A region where a TFT polycrystallized with a CW laser is formed is AR2, and a region where a TFT polycrystallized only with an excimer laser is formed is AR1.

  As shown in FIG. 1B, after the amorphous silicon layer 14 was dehydrogenated by thermal annealing, the entire surface of the amorphous silicon layer 14 was polycrystallized by an excimer laser EL. Although it is not necessary to irradiate the area AR2 with the excimer laser, the area AR2 is also polycrystallized because it is easier to polycrystallize the entire surface due to the properties of the device.

  As shown in FIG. 1C, the silicon layer 14 in the region AR2 was patterned into an island shape having an area showing a heat storage effect suitable for polycrystallization by a CW laser, and polycrystallized by irradiating the CW laser CL. The silicon layer in the region AR2 is changed to a polycrystalline silicon layer 14a having a large grain size by lateral crystallization.

  As shown in FIG. 1D, the polycrystalline silicon layer is patterned into a shape suitable for forming a TFT, and is polycrystallized by an excimer laser. The island silicon layer 14c is polycrystallized by a CW laser. It was processed into.

  As shown in FIG. 1E, an SiON layer 60 having a thickness of 60 nm is deposited on the entire surface of the substrate so as to cover the island-like silicon layers 14b and 14c by CVD, and an AlNd alloy layer 16 having a thickness of 300 nm is deposited thereon. Deposition was performed by physical vapor deposition (PVD), and then the AlNd layer 16 was patterned into a gate electrode shape.

As shown in FIG. 1F, the SiO layer 15 was etched using the AlNd gate electrode 16 as a mask. The underlying SiO layer 13 is also etched to some extent. Phosphorus (P) was ion-doped using phosphine (PH ₃ ) as a source gas and the gate electrode 16 as a mask. In addition, since mass spectrometry is not performed in ion doping, H is also doped at the same time. Channel regions 14b and 14c that are not doped with P are left under the gate electrode 16, and regions S / D doped with P are formed on both sides of the gate electrode.

As shown in FIG. 1G, after removing hydrogen by heat treatment at 350 ° C. for 2 hours, the doped impurities were activated by excimer laser EL irradiation at 250 mJ / cm ² . The doped P is activated and becomes an n-type source / drain region S / D. A TFT using the silicon layer 14b polycrystallized by the excimer laser and a TFT using the silicon layer 14c polycrystallized by the CW laser are formed.

  As shown in FIG. 1H, an SiN layer 19 having a thickness of 300 nm was formed by CVD on the entire surface of the substrate so as to cover the TFT, thereby forming an interlayer insulating film. The contact hole was etched using photolithography.

  As shown in FIG. 1I, a contact hole was buried, a Ti layer 20 having a thickness of 500 nm was formed by PVD, and patterned into an electrode shape. In this manner, a TFT substrate having two types of n-channel thin film transistors T1 and T2 was produced.

  FIG. 1J shows the result of measuring the drain current Id versus gate voltage Vg characteristics of the fabricated thin film transistors T1 and T2. The characteristic of the thin film transistor T1 polycrystallized by the excimer laser is r1, and the characteristic of the thin film transistor T2 polycrystallized by the CW laser after the excimer laser irradiation is r2. Compared to the threshold value Vth1 of the excimer laser irradiation TFT, the drain current of the CW laser irradiation TFT increased, and the threshold value Vth2 shifted to the 1.2V plus side. Vth2-Vth1 = 1.2V. The polycrystalline silicon layer polycrystallized by the CW laser has a large grain size compared to other crystal silicon having a small grain size that is polycrystallized by an excimer laser, and B that is not activated by being trapped by a grain boundary or the like is reduced. It is considered that the threshold value shifts to the positive side because the activation rate of the is increased. This phenomenon will occur even if the impurity species are changed.

  When the threshold value of the CW laser irradiation TFT suitable for high-speed operation approaches 0V, the threshold value of the excimer laser irradiation TFT shifts to the negative side, and the drain current flows even at a gate voltage of 0V. When such a TFT is used for a pixel TFT, the off-leakage current is high and the voltage holding characteristic is deteriorated. Other high breakdown voltage TFTs also increase the off-leakage current and increase the current consumption.

  It has been found that when a high-speed TFT having a large grain size and a high-voltage TFT having a small grain size are produced from different single crystallized layers from a single amorphous silicon layer, a difference in threshold occurs, and a suitable circuit operation cannot be expected. In order to align the threshold values of the high-speed operation n-channel TFT and the high-breakdown-voltage n-channel TFT, it is necessary to selectively perform channel doping in one of the regions.

  2A to 4N are cross-sectional views showing the main steps of a method of manufacturing a thin film transistor semiconductor device according to an embodiment of the present invention and the structure of the obtained semiconductor device. A case C1 in which the entire drive circuit is formed from a silicon layer polycrystallized by CW laser irradiation and a case C2 in which only the high-speed operation part of the drive circuit is formed from a polycrystallized silicon layer by CW laser irradiation will be described. In addition to the case where the impurity activation is performed by the excimer laser, a case where the impurity activation is performed by thermal annealing will also be described. Case 1 is suitable when priority is given to high-speed operation over the entire drive circuit, and Case 2 is suitable when priority is given to reducing leakage current in the high-voltage portion of the drive circuit.

As shown in FIG. 2A, a silicon nitride (SiN) layer 22 having a thickness of 50 nm, a silicon oxide (SiO) layer 23 having a thickness of 200 nm, and boron (B) are formed on a transparent insulating substrate 21 such as a glass substrate. A doped amorphous silicon layer 24 having a thickness of 50 to 60 nm is deposited by thermal chemical vapor deposition (CVD). The doping amount of B doped into the silicon layer 24 is an amount that appropriately controls the threshold value of the CW laser irradiation TFT.
A region for forming a high breakdown voltage n-channel TFT for a pixel is PIX-Vh-n, a region for forming a high breakdown voltage n-channel TFT for a drive circuit is DR-Vh-n, and a region for forming a high breakdown voltage p-channel TFT for a drive circuit is formed. DR-Vh-p, a region for forming a high speed operation (low withstand voltage) n-channel TFT for a drive circuit is DR-Vl-n, and a region for forming a high speed operation for drive circuit (low withstand voltage) p-channel TFT is DR-Vl- Indicated by p. PIX represents a pixel, Vh represents a high breakdown voltage, Vl represents a low breakdown voltage, n represents an n channel, and p represents a p channel.

FIG. 2B1 shows the case C1, in which the driving circuit portion is covered with a resist pattern PR1, and the n-channel high breakdown voltage TFT region PIX-Vh-n for pixels is ion-doped with p-type impurities, and the n-channel TFT of the excimer irradiation portion n-channel TFT. The threshold and the threshold of the CW laser irradiation unit n-channel TFT are made equal. For example, B having a doping amount of 1 × 10 ¹² cm ⁻² suitable for shifting the threshold value by 1.0 to 1.5 V plus is trapped with an acceleration voltage of 5 kV.

  FIG. 2B2 shows the case 2 in which the high-speed operation portion of the drive circuit is covered with the resist pattern PR2, and the high-voltage n-channel TFT region PIX-Vh-n for the pixel and the high-voltage region DR-Vh-n of the drive circuit, DR-Vh-p is ion-doped with, for example, the above-mentioned doping amount B suitable for making the threshold of the excimer laser irradiation unit equal to the threshold of the CW laser irradiation unit.

As shown in FIG. 2C, after the amorphous silicon layer is dehydrogenated by thermal annealing at 500 ° C. in an annealing furnace, the entire surface of the substrate is irradiated with an excimer laser EL1 of 300 mJ / cm ² , and the entire surface of the amorphous silicon layer 24 is irradiated. Is polycrystallized.

  As shown in FIG. 2D1, in the case 1, the silicon layer of the drive circuit unit is patterned into an island shape having an area showing a heat storage effect suitable for polycrystallization by a CW laser, and the island-shaped region is scanned with the CW laser CL1. Polycrystallization is performed by irradiation at a speed of 20 cm / sec and an output of 8.0 kW. The silicon layer of the drive circuit portion is changed to a polycrystalline silicon layer 24a having a large grain size by lateral crystallization.

  As shown in FIG. 2D2, in the case 2, only the silicon layer of the high-speed operation portion of the drive circuit is patterned into an island shape having an area showing a heat storage effect suitable for polycrystallization by a CW laser, and the CW is formed in the island region. Crystallization is performed by irradiating with a laser CL2. The silicon layer of the high-speed operation part is changed to a polycrystalline silicon layer 24a having a large grain size by lateral crystallization.

  As shown in FIG. 3E, the polycrystalline silicon layer is patterned into a shape suitable for forming a TFT, and is polycrystallized by an excimer laser. The island-like silicon layer 24c is polycrystallized by a CW laser. To process.

  As shown in FIG. 3F, a first SiON layer 25 having a thickness of 30 nm is deposited by CVD on the entire surface of the substrate so as to cover the island-like silicon layers 24b and 24c, and a first AlNd alloy having a thickness of 300 nm is formed thereon. The layer 26 is deposited by physical vapor deposition (PVD) such as sputtering, and then the AlNd layer 26 of the high speed operation portion is patterned into a gate electrode shape. The AlNd layer 26 in other regions is removed.

  As shown in FIG. 3G, a second SiO layer 27 having a thickness of 80 nm is deposited on the entire surface of the substrate by CVD, and a second AlNd alloy layer 28 having a thickness of 300 nm is deposited thereon by physical vapor deposition (PVD) such as sputtering. ). Thereafter, the second AlNd layer 28 of the high voltage TFT portion is patterned into a gate electrode shape. The second AlNd layer 28 in other regions is removed.

As shown in FIG. 3H, a resist mask PR3 covering the LDD portions on both sides of the gate electrode 28 of the high breakdown voltage portion is formed, and the second SiO layer 27 and the first SiO layer 25 are collectively etched.
As shown in FIG. 3I, the gate insulating film having an overhanging portion that defines the LDD region is patterned in the high breakdown voltage portion. In the high speed operation part, there is no overhanging part for forming the LDD, and the side wall 27s of the second SiO layer remains on the side wall of the gate electrode 26.

As shown in FIG. 3J, a resist pattern PR4 covering the p-channel TFT portion is formed, and phosphine (PH ₃ ) is used, and phosphorus (P) is ion-doped using the resist pattern PR4 and the gate electrode of the n-channel TFT as a mask. To do. Channel regions 24b and 24c that are not doped with P are left under the gate electrodes 26 and 28, and regions S / D doped with P at a high concentration are formed on both outer sides of the gate insulating film. In the high withstand voltage portion, a high concentration irregularity is doped outside the gate insulating film, and an LDD region doped with a low concentration impurity is formed under the gate insulating film protruding from the gate electrode. In the high-speed operation unit, an offset region is formed under the sidewall-like second SiO layer 27s. The LDD region is effective for reducing leakage current. For example, ion doping is performed by doping a contact portion with a high-concentration impurity at a low voltage suitable for doping a high-concentration impurity, and then penetrating through the gate insulating film that protrudes above the silicon. A high voltage, low concentration impurity that can be doped with impurities is doped.

  As shown in FIG. 3K, a resist pattern PR5 covering the n-channel TFT portion is formed, and B is ion-doped using the resist pattern PR5 and the gate electrode of the p-channel TFT as a mask. A channel region where B is not doped is left under the gate electrodes 26 and 28, and a region S / D in which B is highly doped is formed on both outer sides of the gate insulating film. In the high withstand voltage portion, a high concentration irregularity is doped outside the gate insulating film, and an LDD region doped with a low concentration impurity is formed under the gate insulating film protruding from the gate electrode. In the high-speed operation unit, an offset region is formed under the side wall 27s of the second SiO layer.

As shown in FIG. 4L1, after removing hydrogen by heat treatment at 350 ° C. for 2 hours, the doped impurities are activated by an excimer laser EL2 of 250 mJ / cm ² . The doped impurities are activated to form source / drain regions S / D and LDD portions.

  As shown in FIG. 4L2, activation can be performed by thermal annealing Th instead of activation by excimer laser. In this case, the gate electrodes 26 and 28 are made of a refractory metal such as Mo instead of the AlNd alloy.

In this manner, a TFT using the silicon layer 14b polycrystallized by the excimer laser and a TFT using the silicon layer 14c polycrystallized by the CW laser are formed.
As shown in FIG. 4M, an SiN layer 29 having a thickness of 300 nm is formed on the entire surface of the substrate by CVD so as to cover the TFT, thereby forming an interlayer insulating film. The contact hole is etched using photolithography.

  As shown in FIG. 4N, a contact hole is filled, and a Ti layer 30 having a thickness of 500 nm is formed by PVD and patterned into an electrode shape. In this manner, a TFT substrate having five types of thin film transistors is formed.

  As shown in FIG. 4O, a SiN layer 31 is deposited to form an interlayer insulating film, and the contact holes are etched. A pixel electrode 32 is formed by depositing and patterning an indium-tin oxide film (ITO) which is a transparent electrode. An organic resin is applied on the surface to form the protective film 33. In this way, the TFT substrate of the liquid crystal display device is formed.

  In the above embodiment, the excimer laser polycrystallized region is selectively doped with p-type impurities. The threshold may be adjusted by selectively doping the CW laser polycrystallized region with n-type impurities.

  As shown in FIG. 5A, similarly to the process of FIG. 2A, a silicon nitride (SiN) layer 22 having a thickness of 50 nm and a silicon oxide (SiO) layer 23 having a thickness of 200 nm are formed on a transparent insulating substrate 21 such as a glass substrate. The amorphous silicon layer 24 doped with boron (B) and having a thickness of 50 to 60 nm is laminated by thermal chemical vapor deposition (CVD). The doping amount of B doped into the silicon layer 24 is an amount that appropriately controls the threshold value of the excimer laser irradiation TFT.

FIG. 5B1 shows the case C1, in which the pixel TFT region is covered with a resist pattern PR1a, n-type impurity P is ion-doped in the drive circuit unit, and the threshold value of the CW laser irradiation unit TFT and the threshold value of the excimer laser irradiation TFT are equal. To. For example, P suitable for shifting the threshold value to the negative side of 1.0 to 1.5 V is ion-doped by doping with a dose amount of 5 × 10 ¹¹ cm ⁻² and an acceleration voltage of 10 kV.

  FIG. 5B2 shows the case 2 where the pixel TFT portion and the high breakdown voltage portion of the drive circuit are covered with a resist pattern PR2a, and the CW laser irradiation portion is applied to the drive circuit high-speed operation portions DR-Vl-n and DR-Vl-p. Is ion-doped, for example, with the above-mentioned doping amount suitable for making the threshold value equal to the threshold value of the excimer laser irradiation unit. Thereafter, the steps shown in FIG. 2C and thereafter are performed to complete a TFT substrate for a liquid crystal display device.

In the above embodiment, one resist mask is used for selective channel doping. It is also possible to perform selective channel doping without using a resist mask.
FIGS. 6A to 6G show another embodiment in which only the high-speed operation portion of the drive circuit is formed of a silicon layer polycrystallized by a CW laser. 6A is the same as FIG. 2A. On a transparent insulating substrate 21 such as a glass substrate, a silicon nitride (SiN) layer 22 having a thickness of 50 nm, a silicon oxide (SiO) layer 23 having a thickness of 200 nm, and boron are formed. The amorphous silicon layer 24 having a thickness of 50 to 60 nm doped with (B) is laminated by thermal chemical vapor deposition (CVD). The doping amount of B doped into the silicon layer 24 is an amount that appropriately controls the threshold value of the CW laser irradiation TFT.

FIG. 6B shows the same process as FIG. 2C, and the amorphous silicon layer 24 not selectively doped is thermally annealed at 500 ° C. in an annealing furnace to dehydrogenate the amorphous silicon layer, and then the substrate. The entire surface is irradiated with an excimer laser EL1 of 300 mJ / cm ² to polycrystallize the entire surface of the amorphous silicon layer 24.

  FIG. 6C is the same process as FIG. 2D2, and only the silicon layer of the high-speed operation part of the drive circuit is patterned into an island shape with an area showing a heat storage effect suitable for crystallization by a CW laser, and a CW laser is formed in the island region. Polycrystallization is performed by irradiation with CL2. The silicon layer of the high-speed operation part is changed to a polycrystalline silicon layer 24a having a large grain size by lateral crystallization.

  FIG. 6D is the same process as FIG. 3E, in which the polycrystalline silicon layer is patterned into a shape suitable for creating a TFT, and is polycrystallized by an excimer laser and polycrystallized by a CW laser. The island-shaped silicon layer 24c is processed.

  FIG. 6E shows a process similar to FIG. 3F. A first SiO layer 25 having a thickness of 30 nm is deposited by CVD on the entire surface of the substrate so as to cover the island-like silicon layers 24b and 24c, and a 300 nm thickness is formed thereon. The first AlNd alloy layer 26 is deposited by physical vapor deposition (PVD) such as sputtering, and then the AlNd layer 26 in the high speed operation part is patterned into a gate electrode shape. The AlNd layer 26 in other regions is removed.

  As shown in FIG. 6F, the high-voltage n-channel TFT region PIX-Vh-n for the pixel and the high-voltage regions DR-Vh-n, DR of the drive circuit are used using the gate electrode 26 of the high-speed operation unit of the drive circuit as a mask. -Vh-p is ion-doped through the first silicon oxide layer 25 with a doping amount of B suitable for making the threshold of the excimer laser irradiation unit equal to the threshold of the CW laser irradiation unit. Since the channel region of the high-speed operation part of the drive circuit is covered with the gate electrode 26, it is not doped.

  FIG. 6G shows a process similar to FIG. 3G, in which a second SiO layer 27 having a thickness of 80 nm is deposited on the entire surface of the substrate by CVD, and a second AlNd alloy layer 28 having a thickness of 300 nm is deposited thereon. Deposit by physical vapor deposition (PVD). Thereafter, the second AlNd layer 28 of the high voltage TFT portion is patterned into a gate electrode shape. The second AlNd layer 28 in other regions is removed. In this way, a configuration similar to that of FIG. 3G is obtained. Thereafter, the steps shown in FIG. 6A to 6G, the impurity activation may be performed by excimer laser or thermal annealing, similar to the embodiment of FIGS. 2A to 4O.

7A to 7D show an embodiment in which selective channel doping is performed using a gate insulating film. 7A-7D show the same steps as FIGS. 6A-6D.
As shown in FIG. 7E, a first silicon oxide layer 25 is deposited on the surface of the substrate so as to cover the island-like polycrystalline silicon region by, for example, CVD with a thickness of 30 nm. A gate electrode and a resist pattern PR6 corresponding to the LDD portions on both sides of the gate electrode are formed thereon, and using the resist pattern PR6 as a mask, the first silicon oxide layer 25 is etched to have a gate insulating portion having an LDD portion overhang portion. A film is formed. Thereafter, the resist pattern PR6 is removed.

As shown in FIG. 7F, the exposed polycrystalline silicon layer penetrates, and in a portion where the gate insulating film is formed on the exposed portion, the polycrystalline silicon layer penetrates the gate insulating film and then stops at the polycrystalline silicon layer below the gate insulating film. Then, p-type impurity doping is performed so that the threshold value of the excimer laser irradiation unit is equal to the threshold value of the CW laser irradiation unit. For example, 1 × 10 ¹² cm ⁻² of B is ion-doped with an acceleration voltage of 20 kV in an amount suitable for shifting the threshold value to the positive side of 1.0 to 1.5 V. The range of B under this condition is said to be 66 nm in Si and 62 nm in silicon oxide. The silicon layer with a thickness of 50 nm penetrates, and when there is a silicon layer with a thickness of 50 nm under the silicon oxide layer with a thickness of 30 nm, the silicon oxide layer penetrates but remains in the silicon layer. Therefore, in the high breakdown voltage portion of the pixel TFT and the driving circuit, B is doped in the channel region. The active layer on which the first silicon oxide layer 25 does not exist is not doped with B.

As another method, the CW laser irradiation unit may be ion-doped with an n-type impurity that makes the threshold value of the CW laser irradiation unit equal to the threshold value of the excimer laser irradiation unit. For example, an amount suitable for shifting the threshold value to the negative side of 1.0 to 1.5 V is ion-doped with 5 × 10 ¹¹ cm ⁻² of P at an acceleration voltage of 10 kV. Under this condition, P ions do not penetrate the silicon oxide layer having a thickness of 30 nm, and are doped only on the surface of the exposed silicon layer. Since the silicon oxide layer is present on the channel region (and LDD region) of the high breakdown voltage portion, P is not doped, and the silicon layer of the high speed operation portion is exposed, so that channel doping is performed. In this case, the B doping amount of the amorphous silicon layer is set to a value suitable for threshold control of the excimer laser irradiation unit.

  As shown in FIG. 7G, a gate electrode 28 is formed by depositing a second silicon oxide layer 27 on the entire surface of the substrate, depositing an AlNd alloy layer, and patterning the AlNd layer. Thereafter, the steps shown in FIG. 3H and subsequent steps are performed to complete a TFT substrate for a liquid crystal display device.

  FIG. 8 shows a configuration example of the active matrix substrate. A display area DA for displaying and a peripheral circuit area PH for forming a peripheral circuit are defined on an insulating transparent substrate SUB such as a glass substrate. In the display area DA, a plurality of scanning gate lines (bus lines) GL extend in the row (horizontal) direction, and a plurality of image data lines (bus lines) DL for supplying image data extend in the column (vertical) direction. Extend.

  A thin film transistor TFT is connected to each intersection of the scanning gate line GL and the image data line DL, and an output terminal of the thin film transistor is connected to a pixel electrode PX formed of a transparent electrode such as ITO. Further, an auxiliary capacitor SC is connected to each pixel electrode PX. The other electrode of the auxiliary capacitor SC is connected to an auxiliary capacitor line (bus line) SCL having a constant potential. In the configuration shown in the figure, the auxiliary capacitance line SCL extends in the row direction, but may be configured to extend in the column direction.

  In the peripheral circuit region PH, a gate driver GD for generating a scanning signal group to be supplied to the scanning gate wiring, a data driver DD for supplying image data to be supplied to the image data wiring, and a control signal CS from the outside A display controller DC for controlling the gate driver GD and the data driver DD is formed. The gate driver GD includes a shift register SR1, a level shifter LS1, an output buffer OB, and the like. The data driver DD includes a shift register SR2, a level shifter LS2, an analog switch AS, and the like. Further, reference voltages VL and VH and an image signal ID are supplied from the outside.

  In an active matrix substrate in which peripheral circuits are integrated, the display controller DC and the shift registers SR1 and SR2 are required to perform a relatively high speed operation, and are formed by the above-described high speed operation TFT. The level shifters LS1, LS2, the output buffer OB, and the analog switch AS are required to have a high breakdown voltage that operates at a relatively high voltage.

  A switching thin film transistor (TFT) used in the display area is required to have a relatively high breakdown voltage. The high breakdown voltage TFT for driving circuit, that is, the pixel TFT, is formed by the high breakdown voltage TFT described above. Even if the TFT of the display area DA is formed by only an n-channel TFT, it is preferable that the peripheral circuit PH is configured by a CMOS circuit. Therefore, in addition to the n-channel TFT, a p-channel TFT is also produced. In the case of a circuit for a display device using polycrystalline silicon, a MOS capacitor is generally used as the auxiliary capacitor.

  FIG. 9A shows a configuration example of a liquid crystal display device. The active matrix substrate 201 has a display area DA and a peripheral circuit area PH, and a scanning gate line GL, an auxiliary capacitance bus line SCL, a data line DL, and a pixel structure are formed in the display area DA. A gate control circuit GD and a data control circuit DD are formed in the peripheral circuit region PH. On the counter substrate 202, a color filter 203 corresponding to the pixel region and a common electrode 204 common to all the pixels are formed. A liquid crystal layer 205 is sandwiched between the color filter substrate 202 and the active matrix substrate 201.

  FIG. 9B shows a configuration example of the organic EL panel. The active matrix substrate 201 is formed with a scanning gate wiring, a data wiring, a thin film TFT, and the like on a glass substrate as in the above embodiments. In each pixel region, the TFT source is connected to an anode 211 made of, for example, ITO. On the anode 211, a hole transport layer 212, a light emitting layer 213, an electron transport layer 214, and a cathode 215 formed of aluminum or the like are laminated to form an organic EL element structure. The light emitted from the organic EL element is directed downward and emitted from the glass substrate of the active matrix substrate 201 to the outside. The upper part of the organic EL element is covered with a sealing material 220.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, the exemplified materials and thicknesses are examples and can be variously changed according to the design. Instead of the glass substrate, a transparent insulating substrate such as a quartz substrate may be used. As the gate electrode layer, a metal layer that satisfies the conditions of conductivity and heat resistance can be used. As p-type impurities and n-type impurities, B.I. In addition to P, other impurities such as Sb and As can also be used. The gate insulating film may be formed of an insulating layer other than a silicon oxide layer. For example, a silicon oxynitride layer, a silicon nitride layer, an organic insulating layer, or the like may be used. It will be apparent to those skilled in the art that other various modifications, improvements, and combinations can be made. The features of the present invention will be described below.

(Appendix 1) (1)
An insulating substrate;
A first island-shaped polycrystalline silicon layer disposed above the insulating substrate and made polycrystalline by irradiation with an excimer laser using an amorphous silicon layer as a starting material;
A second island-like polycrystalline silicon layer disposed above the insulating substrate and made polycrystalline by irradiation with CW laser using the amorphous silicon layer as a starting material;
A first gate insulating film formed on the first island-like polycrystalline silicon layer and formed of a stack including the first and second insulating layers;
Formed on at least a part of the second island-like polycrystalline silicon layer, including any one of the first and second insulating layers, and having a lower breakdown voltage than the first gate insulating film A second gate insulating film;
A first gate electrode formed on the first gate insulating film and defining a first channel region below;
A second gate electrode formed on the second gate insulating film and defining a second channel region below;
A semiconductor device in which the first channel region and the second channel region have different impurity doping concentrations for aligning a threshold value.

(Appendix 2) (2)
The insulating substrate is a glass substrate, the amorphous silicon layer is a layer doped with a p-type impurity, and the second island-shaped polycrystalline silicon layer is larger than the first island-shaped polycrystalline silicon layer. The first island-shaped polycrystalline silicon layer, the first gate insulating film, and the first gate electrode constitute a first n-channel thin film transistor, and the second island-shaped polycrystalline silicon is formed of polycrystalline silicon having a diameter. The semiconductor device according to appendix 1, wherein the crystalline silicon layer, the second gate insulating film, and the second gate electrode constitute a second n-channel thin film transistor.

(Appendix 3)
The semiconductor device according to claim 2, wherein the first channel region is further selectively doped with a p-type impurity, or the second channel region is further selectively doped with an n-type impurity.

(Appendix 4) (3)
An insulating substrate;
A first island-shaped polycrystalline silicon layer disposed above the display region of the insulating substrate, having an amorphous silicon layer as a starting material, and polycrystallized by excimer laser irradiation;
A second island-like polycrystalline silicon layer disposed above the peripheral portion of the insulating substrate, the amorphous silicon layer as a starting material, and polycrystallized by CW laser irradiation;
A first gate insulating film formed on the first island-like polycrystalline silicon layer and formed of a stack including the first and second insulating layers;
Formed on at least a part of the second island-like polycrystalline silicon layer, including any one of the first and second insulating layers, and having a lower breakdown voltage than the first gate insulating film A second gate insulating film;
A first gate electrode formed on the first gate insulating film and defining a first channel region below;
A second gate electrode formed on the second gate insulating film and defining a second channel region below;
A pixel electrode electrically connected to the first polycrystalline silicon layer;
The first channel region and the second channel region have different impurity doping concentrations for aligning thresholds; and
A color filter substrate disposed opposite to the TFT substrate;
A liquid crystal layer sandwiched between the TFT substrate and the color filter substrate;
A liquid crystal display device.

(Appendix 5) (4)
(A) depositing an amorphous silicon layer above the insulating substrate;
(B) polycrystallizing the first region of the amorphous silicon layer with an excimer laser to form a first polycrystalline silicon layer;
(C) polycrystallizing the second region of the amorphous silicon layer with a CW laser to form a second polycrystalline silicon layer;
(D) forming a first gate insulating film including a stack of a first insulating layer and a second insulating layer on the first polycrystalline silicon layer, and forming a first gate electrode thereon; Defining a first channel region below the first channel region;
(E) A second gate insulating film including only one of the first and second insulating layers is formed on the second polycrystalline silicon layer, and a second gate electrode is formed thereon. Forming and defining a second channel region thereunder;
(F) a step of selectively doping the first region or the second region with an impurity for controlling a threshold;
A first thin film transistor is formed using the first polycrystalline silicon layer, the first gate insulating film, and the first gate electrode, and the second polycrystalline silicon layer and the second gate insulating layer A method for manufacturing a semiconductor device, in which a second thin film transistor is formed using a second gate electrode.

(Appendix 6)
6. The method of manufacturing a semiconductor device according to appendix 5, wherein the amorphous silicon layer is a layer doped with a p-type impurity, and the first and second thin film transistors are n-channel thin film transistors.

(Appendix 7) (5)
The steps (d) and (e)
(De1) depositing the first insulating layer over the first and second polycrystalline silicon layers;
(De2) forming a second gate electrode on the first insulating layer on the second polycrystalline silicon layer;
(De3) depositing a second insulating layer on the first insulating layer so as to cover the second gate electrode;
(De4) forming a first gate electrode on the second insulating layer above the first polycrystalline silicon layer;
(De5) etching and removing unnecessary portions of the second insulating layer and the first insulating layer;
The manufacturing method of the semiconductor device of Claim 5 including this.

(Appendix 8)
The manufacturing method of the semiconductor device according to appendix 7, wherein in the step (f), after the step (de2), the first and second polycrystalline silicon layers are doped with a p-type impurity using the second gate electrode as a mask. Method.

(Appendix 9) (6)
The steps (d) and (e)
(De1) depositing a first insulating layer over the first and second polycrystalline silicon layers;
(De2) patterning the first insulating layer and leaving the first gate insulating film only on the first polycrystalline silicon layer;
(De3) selectively doping impurities into the first channel region or the second channel region using the first gate insulating film;
(Fg4) forming a first gate electrode and a second gate electrode on the second insulating layer in the first and second regions;
(Fg5) etching and removing unnecessary portions of the second insulating layer;
The manufacturing method of the semiconductor device of Claim 5 including this.

(Appendix 10)
In the step (de3), the single layer of the first and second polycrystalline silicon layers penetrates, and the stack of the first gate insulating film and the first polycrystalline silicon layer does not penetrate the p layer at an acceleration energy. Item 9. The method for manufacturing a semiconductor device according to appendix 8, wherein the first channel layer is doped with a p-type impurity.

(Appendix 11)
The manufacturing method of the semiconductor device according to appendix 8, wherein in the step (de3), an n-type impurity is doped with an acceleration voltage that can be blocked by the first gate insulating film, and the second polycrystalline silicon layer is doped with the n-type impurity. Method.

It is sectional drawing and the graph which show the sample preparation process of the experiment which the present inventors conducted, and the characteristic of obtained TFT. It is sectional drawing which shows the manufacturing method of the semiconductor device by a 1st Example. It is sectional drawing which shows the manufacturing method of the semiconductor device by a 1st Example. It is sectional drawing which shows the manufacturing method of the semiconductor device by a 1st Example. It is sectional drawing which shows the manufacturing method of the semiconductor device by a 2nd Example. It is sectional drawing which shows the manufacturing method of the semiconductor device by a 3rd Example. It is sectional drawing which shows the manufacturing method of the semiconductor device by a 4th Example. It is a top view of the TFT substrate for liquid crystal display devices containing the semiconductor device by an Example. It is the perspective view and sectional drawing which show the structural example of a display apparatus.

Explanation of symbols

11, 21 Glass substrate (transparent insulating substrate)
12, 22 Silicon nitride layer 13, 23 Silicon oxide layer 14, 24 Silicon layer 15, 25 Silicon oxide layer 16, 26 Gate electrode layer 19, 29 Interlayer insulating film 20, 30 Electrode

Claims (6)

An insulating substrate;
A first island-shaped polycrystalline silicon layer disposed above the insulating substrate and made polycrystalline by irradiation with an excimer laser using an amorphous silicon layer as a starting material;
A second island-like polycrystalline silicon layer disposed above the insulating substrate and made polycrystalline by irradiation with a CW laser, using the amorphous silicon layer as a starting material;
A first gate insulating film formed on the first island-like polycrystalline silicon layer and formed of a stack including the first and second insulating layers;
Formed on at least a part of the second island-like polycrystalline silicon layer, including any one of the first and second insulating layers, and having a lower breakdown voltage than the first gate insulating film A second gate insulating film;
A first gate electrode formed on the first gate insulating film and defining a first channel region below;
A second gate electrode formed on the second gate insulating film and defining a second channel region below;
A semiconductor device in which the first channel region and the second channel region have different impurity doping concentrations for aligning a threshold value.   The insulating substrate is a glass substrate, the amorphous silicon layer is a layer doped with a p-type impurity, and the second island-shaped polycrystalline silicon layer is larger than the first island-shaped polycrystalline silicon layer. The first island-shaped polycrystalline silicon layer, the first gate insulating film, and the first gate electrode constitute a first n-channel thin film transistor, and the second island-shaped polycrystalline silicon is formed of polycrystalline silicon having a diameter. 2. The semiconductor device according to claim 1, wherein the crystalline silicon layer, the second gate insulating film, and the second gate electrode constitute a second n-channel thin film transistor. An insulating substrate;
A first island-shaped polycrystalline silicon layer disposed above the display region of the insulating substrate, having an amorphous silicon layer as a starting material, and polycrystallized by excimer laser irradiation;
A second island-like polycrystalline silicon layer disposed above the peripheral portion of the insulating substrate, the amorphous silicon layer as a starting material, and polycrystallized by CW laser irradiation;
A first gate insulating film formed on the first island-like polycrystalline silicon layer and formed of a stack including the first and second insulating layers;
Formed on at least a part of the second island-like polycrystalline silicon layer, including any one of the first and second insulating layers, and having a lower breakdown voltage than the first gate insulating film A second gate insulating film;
A first gate electrode formed on the first gate insulating film and defining a first channel region below;
A second gate electrode formed on the second gate insulating film and defining a second channel region below;
A pixel electrode electrically connected to the first polycrystalline silicon layer;
The first channel region and the second channel region have different impurity doping concentrations for aligning thresholds; and
A color filter substrate disposed opposite to the TFT substrate;
A liquid crystal layer sandwiched between the TFT substrate and the color filter substrate;
A liquid crystal display device. (A) depositing an amorphous silicon layer above the insulating substrate;
(B) polycrystallizing the first region of the amorphous silicon layer with an excimer laser to form a first polycrystalline silicon layer;
(C) polycrystallizing the second region of the amorphous silicon layer with a CW laser to form a second polycrystalline silicon layer;
(D) forming a first gate insulating film including a stack of a first insulating layer and a second insulating layer on the first polycrystalline silicon layer, and forming a first gate electrode thereon; Defining a first channel region below the first channel region;
(E) forming a second gate insulating film including one of the first and second insulating layers on at least a part of the second polycrystalline silicon layer; Forming a gate electrode and defining a second channel region below the gate electrode;
(F) a step of selectively doping the first region or the second region with an impurity for controlling a threshold;
A first thin film transistor is formed using the first polycrystalline silicon layer, the first gate insulating film, and the first gate electrode, and the second polycrystalline silicon layer and the second gate insulating layer A method for manufacturing a semiconductor device, in which a second thin film transistor is formed using a second gate electrode. The steps (d) and (e)
(De1) depositing the first insulating layer over the first and second polycrystalline silicon layers;
(De2) forming a second gate electrode on the first insulating layer on the second polycrystalline silicon layer;
(De3) depositing a second insulating layer on the first insulating layer so as to cover the second gate electrode;
(De4) forming a first gate electrode on the second insulating layer above the first polycrystalline silicon layer;
(De5) etching and removing unnecessary portions of the second insulating layer and the first insulating layer;
The manufacturing method of the semiconductor device of Claim 4 containing this. The steps (d) and (e)
(De1) depositing a first insulating layer over the first and second polycrystalline silicon layers;
(De2) patterning the first insulating layer and leaving the first gate insulating film only on the first polycrystalline silicon layer;
(De3) selectively doping impurities into the first channel region or the second channel region using the first gate insulating film;
(Fg4) forming a first gate electrode and a second gate electrode on the second insulating layer in the first and second regions;
(Fg5) etching and removing unnecessary portions of the second insulating layer;
The manufacturing method of the semiconductor device of Claim 4 containing this.

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