JP2006032381A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent deterioration in transistor performance by preventing an interface state from being generated due to the nitriding of an oxide film and a silicon interface of a sidewall. <P>SOLUTION: A semiconductor device includes a gate electrode 104 formed on a substrate 101, an oxide film 105 serving as a first sidewall and a nitride film 106 serving as a second sidewall formed on the sidewall of the gate electrode 104, and a low concentration impurity diffusion region 107 and a high concentration impurity diffusion region 109 formed in the region of the substrate 101 located on the side of the gate electrode 104. A nitrogen concentration on the interface is 1×10<SP>20</SP>cm<SP>-3</SP>or less between the oxide film 105 as the first sidewall and the low concentration impurity diffusion region 107. Thus, the quantity of the interface state generated at the interface is reduced between the region 107 and the oxide film 105 as the first sidewall, thereby suppressing the formation of a depletion layer in the low concentration impurity diffusion region caused by the interface state and preventing deterioration in transistor performance. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a side wall is formed on a side wall of a gate electrode and a method for manufacturing the same.

  Recently, when forming contact members to the source / drain regions of MOS transistors, a self-aligned contact structure (SAC structure) has begun to be used in response to the higher density of elements. In this method, the sidewall used for forming the LDD (Lightly Doped Drain) structure is also used as an etching stopper when the contact is formed by self-alignment.

  In order to use the sidewall as an etching stopper, a silicon nitride film is generally used for the sidewall.

  8 (a) to 8 (d) are cross-sectional views of essential steps showing a method of manufacturing a MOS transistor having a silicon nitride film as a sidewall in order to form a conventional general self-aligned contact structure (patent) Reference 1).

  As transistor miniaturization progresses recently, a so-called LDD structure is used as a transistor structure, and as a manufacturing method thereof, a side wall is formed on the side surface of the gate electrode. Generally, high concentration source / drain regions are formed by ion implantation using a mask.

  First, in the step shown in FIG. 8A, a gate insulating film thermal oxide film 402, a gate electrode polysilicon film 403, and a silicon nitride film 404 are sequentially formed on a semiconductor substrate 401, and then a gate patterning resist. A film 405 is formed.

  Next, in the step shown in FIG. 8B, using the resist film 405 as an etching mask, the silicon nitride film 404, the polysilicon film 403, and the thermal oxide film 402 are sequentially etched to form the on-gate protective layer 404a and the gate electrode. After forming 403a and the gate insulating film 402a, impurities (phosphorus or arsenic in an n-channel MOS transistor, boron in a p-channel MOS transistor) are ion-implanted into the semiconductor substrate 401 using the gate electrode 403a and the like as a mask. Then, low concentration source / drain regions 406 are formed.

  Thereafter, a silicon oxide film 407 and a silicon nitride film 408 are deposited on the substrate 401 in the step shown in FIG.

  Next, in the step shown in FIG. 8C, anisotropic dry etching is performed on the silicon oxide film 407 and the silicon nitride film 408 to form an oxide film side wall 407a on the side wall of the gate electrode 403a, and nitride. A film sidewall 408a is formed.

Next, in the step shown in FIG. 8D, impurities (phosphorus or arsenic in the n-channel MOS transistor, p-channel MOS transistor in the n-channel MOS transistor) using the gate electrode 403a, the oxide film sidewall 407a and the nitride film sidewall 408a as a mask. Boron) ions are implanted to form high concentration source / drain regions 409, whereby an LDD structure MOS transistor is completed.
JP 2000-106436 A

However, the conventional configuration has the following problems as miniaturization progresses. That is, when the silicon nitride film 408 is formed on the silicon oxide film 407 in the step shown in FIG. 8B, the material for forming the silicon nitride film 408 at the interface between the silicon oxide film 407 and the silicon substrate 401. NH ₃ (ammonia), which is one of the gases, diffuses in the silicon oxide film 407, and a nitride 410 (FIG. 9) is formed at the interface between the low concentration source / drain region 406 and the silicon oxide film 407.

  FIG. 9 is a diagram schematically showing a state in which the nitride 410 is formed at the interface between the low concentration source / drain region 406 and the oxide film side wall 407a in the step shown in FIG.

  Further, the nitride 410 generates an interface state 411 at the interface between the low concentration source / drain region 406 and the oxide film side wall 407 a, and the interface state 411 forms a depletion layer 413 in the low concentration source / drain region 406. To do. The depletion layer 413 has a problem that the width in the depth direction of the low concentration source / drain region 406 is reduced, thereby increasing the parasitic resistance contributing to the source / drain of the transistor and degrading the performance of the transistor. .

  Accordingly, the object of the present invention is to solve the above-mentioned problems, and in an LDD structure transistor having a nitride film as a sidewall, generation of interface states due to nitridation of the oxide film / silicon interface of the sidewall is suppressed. It is to prevent deterioration of the performance of the transistor, and to provide a semiconductor device in which the nitrogen concentration at the interface between the sidewall and the substrate is controlled to such an extent that the performance of the transistor is not deteriorated, and a manufacturing method thereof. .

In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a gate electrode formed on a substrate, and an oxide film which is a first sidewall formed on a side wall of the gate electrode. A nitride film as a second sidewall; a low-concentration impurity diffusion region and a high-concentration impurity diffusion region formed in the region of the substrate located on the side of the gate electrode; The nitrogen concentration at the interface between the oxide film as a wall and the low-concentration impurity diffusion region is 1 × 10 ²⁰ cm ⁻³ or less.

  The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the conductive film constituting the gate electrode is made of one or more elements selected from the group consisting of Si, Ge, and C. It is formed with.

4. The method of manufacturing a semiconductor device according to claim 3, wherein a step of forming a gate insulating film on the substrate, a step of forming a gate electrode film on the gate insulating film, and etching at least a part of the gate electrode film. Forming a gate electrode; forming a low-concentration impurity region in a region of the substrate located laterally of the gate electrode; and forming the low-concentration impurity region on the substrate on which the low-concentration impurity region is formed. A nitride film is formed on the oxide film at a temperature such that an oxide film is formed and a nitrogen concentration at the interface between the oxide film and the low concentration impurity region is 1 × 10 ²⁰ cm ⁻³ or less. Performing anisotropic etching on the nitride film and the oxide film, and forming a first sidewall made of the oxide film on the sidewall of the gate electrode and a second film made of the nitride film. A high concentration impurity region having a concentration higher than that of the low concentration impurity region in a region of the substrate located on a side of the first sidewall and the second sidewall. Forming the step.

  According to a fourth aspect of the present invention, in the semiconductor device manufacturing method, the temperature of the substrate in the step of forming the nitride film is 600 ° C. or lower.

6. The method of manufacturing a semiconductor device according to claim 5, wherein a step of forming a gate insulating film on a substrate, a step of forming a gate electrode film on the gate insulating film, and etching at least a part of the gate electrode film. Forming a gate electrode; forming a low-concentration impurity region in a region of the substrate located laterally of the gate electrode; and forming the low-concentration impurity region on the substrate on which the low-concentration impurity region is formed. A step of forming an oxide film, a step of forming a diffusion preventive film for preventing diffusion of a gas containing nitrogen as a constituent element on the oxide film, and a step of forming on the diffusion preventive film By forming a nitride film and reacting the diffusion preventive film with a gas containing nitrogen as a constituent element for forming the nitride film, the concentration of nitrogen at the interface between the oxide film and the low-concentration impurity region is increased. And controlling to 1 × 10 ²⁰ cm ^-3 or less, with respect to the nitride film and the oxide film, by performing anisotropic etching on the sidewalls of the gate electrode, the first consisting of the oxide film A step of forming a sidewall and a second sidewall made of the nitride film, and a region of the substrate located on a side of the first sidewall and the second sidewall; Forming a high concentration impurity region having a higher concentration than the concentration impurity region.

The method for manufacturing a semiconductor device according to claim 6 is the method for manufacturing a semiconductor device according to claim 5, wherein the gas containing nitrogen as a constituent element is NH ₃ .

  The method of manufacturing a semiconductor device according to claim 7 is the method of manufacturing a semiconductor device according to claim 3, 4, 5 or 6, wherein a gate protective film is formed on the gate electrode film in the step of forming the gate electrode. And a step of patterning the gate protective film and etching the gate electrode film using the patterned gate insulating film as a mask.

  The method for manufacturing a semiconductor device according to claim 8 is the method for manufacturing a semiconductor device according to claim 3, 4, 5 or 6, wherein the gate electrode film is one or more selected from the group consisting of Si, Ge and C. It is made of a material composed of these elements.

According to the semiconductor device of the first aspect of the present invention, since the nitrogen concentration at the interface between the oxide film as the first sidewall and the low-concentration impurity diffusion region is 1 × 10 ²⁰ cm ⁻³ or less, the second Even when a nitride film is used as the sidewall, the nitrogen concentration at the interface between the low-concentration impurity diffusion region and the oxide film as the first sidewall is 1 × 10 4 when the nitride film is formed on the oxide film. By forming the nitride film at a temperature of ²⁰ cm ⁻³ or less, the amount of interface states generated at the interface between the low-concentration impurity diffusion region and the oxide film as the first sidewall is reduced, and the interface state is reduced. By suppressing the formation of a depletion layer in the low-concentration impurity diffusion region due to, it is possible to prevent deterioration in the performance of the transistors constituting the semiconductor device.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the conductive film constituting the gate electrode is formed of a material composed of one or more elements selected from the group consisting of Si, Ge, and C. It is desirable. Thereby, the electrical resistance of the gate electrode can be lowered.

According to the semiconductor device manufacturing method of the present invention, the step of forming the oxide film on the substrate on which the low concentration impurity region is formed and the nitrogen concentration at the interface between the oxide film and the low concentration impurity region are set to 1. A step of forming a nitride film on the oxide film at a temperature of × 10 ²⁰ cm ⁻³ or less, and anisotropic etching is performed on the nitride film and the oxide film, thereby forming a sidewall of the gate electrode. And the step of forming the first sidewall made of the oxide film and the second sidewall made of the nitride film, the nitride film is oxidized even when the nitride film is used for the second sidewall. When forming on the film, the nitride film is formed at such a temperature that the nitrogen concentration at the interface between the low-concentration impurity diffusion region and the oxide film as the first sidewall becomes 1 × 10 ²⁰ cm ⁻³ or less. Depending on the low concentration The generation amount of the interface state at the interface between the oxide diffusion region and the oxide diffusion region is reduced, the formation of a depletion layer in the low concentration impurity diffusion region due to the interface state is suppressed, and the transistor performance is deteriorated. It is possible to manufacture a prevented semiconductor device.

  According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, it is desirable that the temperature of the substrate in the step of forming the nitride film is 600 ° C. or lower. Thereby, the nitrogen concentration at the interface between the low-concentration impurity diffusion region and the oxide film as the first sidewall can be reliably reduced.

According to the method of manufacturing a semiconductor device according to claim 5 of the present invention, the step of forming the oxide film on the substrate on which the low concentration impurity region is formed, and the nitrogen to the oxide film on the oxide film as a constituent element Forming a diffusion preventive film for preventing diffusion of gas to be formed, forming a nitride film on the diffusion preventive film, and a gas containing nitrogen as a constituent element for forming the diffusion preventive film and the nitride film And the step of controlling the nitrogen concentration at the interface between the oxide film and the low-concentration impurity region to 1 × 10 ²⁰ cm ⁻³ or less, and anisotropic etching is performed on the nitride film and the oxide film. As a result, a step of forming a first sidewall made of an oxide film and a second sidewall made of a nitride film on the side wall of the gate electrode is included. Therefore, a nitride film is used for the second sidewall. In some cases, By reacting the gas containing nitrogen as a constituent element to form the diffusion prevention film and the nitride film, the gas containing nitrogen as a constituent element diffuses in the oxide film, and the low-concentration impurity diffusion region and the first side are diffused. Reaching the interface of the oxide film as the wall can be prevented, and by setting the nitrogen concentration at the interface to 1 × 10 ²⁰ cm ⁻³ or less, the low concentration impurity diffusion region and the oxide film as the first sidewall can be prevented. It is possible to manufacture a semiconductor device in which the generation amount of interface states at the interface is reduced, the formation of a depletion layer in the low-concentration impurity diffusion region due to the interface states is suppressed, and deterioration of transistor performance is prevented.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, NH ₃ can be used as a gas containing nitrogen as a constituent element.

  7. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming a gate protective film on the gate electrode film in the step of forming the gate electrode, And etching the gate electrode film using the patterned gate insulating film as a mask. With such a configuration, when the gate electrode is formed by patterning, the gate protective film functions as a hard mask, and it is possible to prevent the upper portion of the gate electrode from being etched.

  According to claim 8, in the method of manufacturing a semiconductor device according to claim 3, 4, 5 or 6, the gate electrode film is made of a material composed of one or more elements selected from the group of Si, Ge, and C. It is desirable to form. Thereby, the electrical resistance of the gate electrode can be lowered.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.

  FIG. 1A is a cross-sectional structure of a main part of an N-channel transistor constituting the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a side wall in FIG. FIG. 5 is an enlarged view of a source / drain portion. Note that the P-channel transistor also has the same structure except that the conductivity type of the impurity doped in each part of the MIS transistor is different.

  1A and 1B, 101 is a silicon substrate, 102 is an element isolation region made of a silicon oxide film for electrically isolating each element, 103 is a gate insulating film made of a silicon oxide film, and 104 is an N-type. A gate electrode made of polysilicon (P-type in the case of a P-channel transistor), 105 a first sidewall made of a silicon oxide film, 106 a second sidewall made of a silicon nitride film, and 107 a low-concentration impurity The region is an N-type (P-type in the case of a P-channel transistor) low-concentration source / drain region, 108 is a P-type (N-type in the case of a P-channel transistor) pocket region, and 109 is a high-concentration impurity region. An N-type (P-type in the case of a P-channel transistor) high concentration source / drain region 110 is a low concentration source / drain region 1 7 is a nitride formed at the interface between the oxide film side wall 105 and 111 is a depletion formed by the interface state of the nitride 110 formed at the interface between the low concentration source / drain region 107 and the first side wall 105. The layer 112 is a diffusion resistance of the low concentration source / drain region 107, and 113 is a cobalt silicide having a low resistance formed on the surface of the high concentration source / drain region 109 and the gate electrode 104.

  As described above, this semiconductor device includes the gate electrode 104 formed on the silicon substrate 101, the oxide film 105 that is the first sidewall formed on the sidewall of the gate electrode 104, and the nitride that is the second sidewall. A film 106 and a low-concentration impurity diffusion region 107 and a high-concentration impurity diffusion region 109 formed in a region of the substrate 101 located on the side of the gate electrode 104 are provided.

The silicon substrate 101 has a well concentration suitable for transistor operation and a surface concentration that controls a threshold voltage. The nitrogen concentration in the nitride 110 made of Si _x N _y O _z formed at the interface between the low concentration source / drain region 107 and the oxide film side wall 105 is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ^−3. By being controlled as described below, generation of interface states due to the nitride 110 is suppressed, and the spread of the depletion layer 111 in the low concentration source / drain region 107 immediately below the first sidewall 105 can be suppressed. Therefore, it is possible to suppress an increase in resistance of the diffused resistor 112 in the low concentration source / drain region 107 and to prevent performance deterioration of the MIS transistor.

  In the present embodiment, the second sidewall 106 has been described as being L-shaped, but it goes without saying that the same effect can be obtained even with a ¼ elliptical sidewall. Further, although cobalt silicide is used as the silicide 113, it goes without saying that the same effect can be obtained even if other silicide films such as titanium silicide and nickel silicide are used.

  A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. More specifically, in the semiconductor device manufacturing method according to the second embodiment of the present invention, in the semiconductor device according to the first embodiment of the present invention, the second sidewall 106 is formed into a quarter oval shape. A manufacturing method for manufacturing a semiconductor device.

  2A and 2B, FIGS. 3A and 3B, and FIG. 4 illustrate a process of manufacturing an N-channel transistor that constitutes the semiconductor device according to the second embodiment of the present invention. It is principal part process sectional drawing. Also in the P-channel transistor, only the conductivity type of the impurity doped in each part of the MIS transistor is different, and basically the same process as that shown in FIGS. 2 to 4 is performed.

  First, after forming the element isolation region 202 on the silicon substrate 201 in the step shown in FIG. 2A, the following steps are performed to form a MIS transistor in the active region surrounded by the element isolation region. Do.

  First, a thermal oxidation process is performed to form a silicon oxide film having a film thickness of about 3 nm on the main surface of the silicon substrate 201, and then a nitriding process is performed to form a gate insulating film 203 made of a silicon oxynitride film (having a film thickness of about 3 nm). Then, a gate electrode film 204 made of polysilicon and a gate protective film 205 (thickness of 30 nm or less) made of a silicon oxide film are formed on the silicon oxynitride film 203. At this time, although not shown, the same process as the process shown in FIG.

  That is, after the gate electrode film 204 and the gate protective film 205 are deposited, the gate insulating film 203, the gate electrode film 204, and the gate protective film 205 are patterned by performing photolithography and dry etching to obtain the structure shown in FIG. As shown, a gate insulating film 203a, a gate electrode 204a, and a gate protective film 205a are formed.

  Note that the gate electrode 204a is doped with an N-type impurity (a P-type impurity for a P-channel MIS transistor). The gate protective film 205a is used as a hard mask for patterning the gate electrode 204a and has a thickness of 30 nm or less. Note that the gate protective film 205a is not necessarily formed.

Thereafter, using the gate electrode 204a and the gate protective film 205a as a mask, phosphorus ions (P ⁺ ) are tilted into the region of the substrate located on the side of the gate electrode 204a with an inclination angle of 0 to 40 degrees and an implantation energy of 10 to 10. Implantation is performed under the conditions of 30 keV and a dose: about 5 × 10 ¹³ cm ⁻² to form a low concentration source / drain region 206 which is a low concentration impurity diffusion region. An extension region may be formed instead of the low concentration source / drain region 206. In this case, arsenic ions (As) are implanted with an implantation energy of 10 to 20 keV and a dose of 5 × 10 ¹³ cm ^−2. Inject under the conditions of Boron ions (or boron fluoride ions) are implanted under the conditions of tilt angle: 20 to 50 degrees, implantation energy: 10 to 50 keV, and dose: 1 to 5 × 10 ¹³ cm ⁻² , for punch-through stoppers. The pocket implantation region 207 is formed. Note that the pocket implantation region 207 is not necessarily formed.

  Thereafter, in order to activate the impurities doped in each of the regions 206 and 207, RTA (Rapid Thermal Annealing) processing is performed under the conditions of processing temperature: 900 to 1000 ° C. and processing time: 10 to 60 seconds.

  Through the above steps, the structure shown in FIG. 2B is formed.

  Next, in the step shown in FIG. 3A, a thin non-doped oxide film 208 (for example, an NSG film or an HTO film (high temperature oxide film)) having a thickness of 10 to 20 nm and a thickness of 10 to 10 are formed on the entire surface of the substrate 201. A 100 nm silicon nitride film 209 is sequentially deposited.

The silicon nitride film 209 is formed by forming the nitride film 209 on the oxide film 208 at a temperature such that the nitrogen concentration at the interface between the oxide film 208 and the low-concentration impurity region 206 is 1 × 10 ²⁰ cm ⁻³ or less. Form. In this case, BT-BAS (Bis-Tertially-Butyl-Amino-Silane) or HCD (Hexa-Chloro-Dislane), which can form a silicon nitride film at a film forming temperature of 600 ° C. or lower, is used. The time (pre-purge time) for flowing NH ₃ gas as a nitride material before film formation is set to 1 minute or less. When the silicon nitride film 209 is formed, NH ₃ diffuses in the oxide film 208, and a nitride 210 is formed at the interface between the low concentration source / drain region 206 formed in the silicon substrate 201 and the silicon oxide film 208. .

  Next, in the step shown in FIG. 3B, anisotropic etching is performed to form a first sidewall 208a made of a silicon oxide film and a second sidewall made of a silicon nitride film on the sidewall of the gate electrode 204a. 209a. By this processing, the gate protective film 205a is further etched, and the film thickness is 10 nm or less.

Then, using the gate electrode 204a and the side walls 208a and 209a as a mask, arsenic ions are implanted under the conditions of an inclination angle of 7 degrees, an implantation energy of 30 to 50 keV, and a dose amount of 3 to 5 × 10 ¹³ cm ^−2. Thus, a high concentration source / drain region 211 which is a high concentration impurity diffusion region having a higher concentration than the low concentration impurity region is formed.

  Thereafter, in order to activate the impurities doped in the high concentration source / drain regions 211, RTA treatment is performed under the conditions of treatment temperature: 900 to 1090 ° C. and treatment time: 60 seconds or less.

  Although not shown, a material film (BPSG, PSG, etc.) that can be selectively removed is formed on the silicon nitride film 208 that forms the second sidewall 208a, and the sidewalls 207a, 208a, BPSG are formed. After the third sidewall is formed by the above, the L sidewall may be formed by selectively removing the third sidewall by dilute hydrofluoric acid or HF vapor phase etching.

  Thereafter, although not shown, an oxide film for forming a portion where no silicide is formed is formed on the entire surface, and patterning with photolithography and oxide film etching with dilute hydrofluoric acid or buffered hydrofluoric acid are performed (silicide region). Is removed), the on-gate protective film 205a is removed.

  Next, in the step shown in FIG. 4, cobalt (film thickness is 8 to 12 nm) and cap film titanium nitride (film thickness is 10 to 30 nm) are formed on the entire surface of the silicon substrate 201 by PVD (Physical Vapor Deposition). In the RTA process under conditions of a processing temperature of 400 to 500 ° C. and a processing time of 30 to 120 seconds, silicide is formed by reacting the surface of the silicon substrate 201 with cobalt and the polysilicon surface of the gate electrode 204a with cobalt, The silicide 212 is formed by selectively removing cobalt and titanium nitride that have not reacted with silicon with an oxide water mixed solution or ammonia / peroxide mixed solution. Thereafter, in order to reduce the resistance of the silicide 212, an RTA process is performed under conditions of a processing temperature: 700 to 850 ° C. and a processing time of 15 to 60 seconds.

According to the manufacturing method of the present embodiment, in the step shown in FIG. 3A, the formation temperature of the silicon nitride film 209 is 600 ° C. or less, and the NH ₃ gas pre-purge time before film formation is 1 minute or less. Therefore, NH ₃ diffusing in the oxide film 208 can be suppressed, and the nitrogen concentration in the nitride 210 formed at the interface between the low concentration source / drain region 206 formed in the silicon substrate 201 and the oxide film 208 is reduced. Is controlled to 1 × 10 ²⁰ cm ⁻³ or less. As a result, the generation of the interface state due to the nitride 210 is suppressed, and the spread of the depletion layer in the low concentration source / drain region 206 due to the interface state is suppressed. As a result, the low concentration source / drain region 206 is suppressed. The resistance increase of the MIS transistor can be prevented, and the performance degradation of the MIS transistor can be prevented.

  A semiconductor device manufacturing method according to the third embodiment of the present invention will be described with reference to FIGS. Specifically, in the method of manufacturing the semiconductor device according to the third embodiment of the present invention, the second sidewall 106 is formed into a quarter oval shape in the semiconductor device according to the first embodiment of the present invention. A manufacturing method for manufacturing a semiconductor device.

  FIGS. 5A and 5B, FIGS. 6A and 6B, and FIGS. 7A and 7B show N-channel transistors constituting the semiconductor device according to the third embodiment of the present invention. It is principal part process sectional drawing explaining the process of manufacturing. In the P-channel transistor, only the conductivity type of the impurity doped in each part of the MIS transistor is different, and basically the same process as the process shown in FIGS.

  First, in the step shown in FIG. 5A, after forming the element isolation region 302 on the silicon substrate 301, the following steps are performed to form a MIS transistor in the active region surrounded by the element isolation region. Do.

  First, a thermal oxidation process is performed to form a silicon oxide film having a thickness of about 3 nm on the main surface of the silicon substrate 301, and then nitriding is performed to form a gate insulating film 303 made of a silicon oxynitride film (having a thickness of about 3 nm). ). Then, a gate electrode film 304 made of polysilicon and a gate protective film 305 (thickness of 30 nm or less) made of silicon oxide are formed on the gate insulating film 303. At this time, although not shown, the same process as the process shown in FIG.

  That is, after depositing the gate electrode film 304 and the gate protective film 305, the gate insulating film 303, the gate electrode film 304, and the gate protective film 305 are patterned by performing photolithography and dry etching to obtain the structure shown in FIG. As shown, a gate insulating film 303a, a gate electrode 304a, and a gate protective film 305a are formed.

  Note that the gate electrode 304a is doped with an N-type impurity (a P-type impurity for a P-channel MIS transistor). The gate protective film 305a is used as a hard mask for patterning the gate electrode 304a and has a thickness of 30 nm or less. Note that the gate protective film 305a is not necessarily formed.

Then, using the gate electrode 304a and the gate protective film 305a as a mask, phosphorus ions (P ⁺ ) are inclined into the region of the substrate located on the side of the gate electrode 304a at an inclination angle of 0 to 40 degrees and an implantation energy of 10 to 10. Implantation is performed under the conditions of 30 keV and a dose amount of about 5 × 10 ¹³ cm ⁻² to form low concentration source / drain regions 306 which are low concentration impurity diffusion regions. An extension region may be formed instead of the low concentration source / drain region 306. In this case, arsenic ions (As) are implanted under conditions of an implantation energy of 10 to 20 keV and a dose of 5 × 10 ¹³ cm ⁻² . Inject with. Boron ions (or boron fluoride ions) are implanted under the conditions of tilt angle: 20 to 50 degrees, implantation energy: 10 to 50 keV, and dose: 1 to 5 × 10 ¹³ cm ⁻² , for punch-through stoppers. The pocket implantation region 307 is formed. Note that the pocket implantation region 307 is not necessarily formed.

  Thereafter, in order to activate the impurities doped in the regions 306 and 307, RTA treatment is performed under the conditions of treatment temperature: 900 to 1000 ° C. and treatment time: 10 to 60 seconds.

  Next, in the step shown in FIG. 6A, a thin non-doped oxide film 308 (eg, NSG film or HTO film) having a thickness of 10 to 20 nm and silicon having a thickness of 1 to 10 atomic layers are formed on the entire surface of the substrate 301. A diffusion prevention film 320 formed in (1) is deposited.

Thereafter, in the step shown in FIG. 6B, a silicon nitride film 309 having a thickness of 10 to 100 nm is deposited. When the silicon nitride film 309 is formed, the diffusion prevention film 320 reacts with the NH ₃ during a time (pre-purge time) in which NH ₃ gas as a nitride material flows before the film formation, so that the diffusion prevention film 320 becomes an insulator. The nitrogen concentration at the interface between the oxide film 308 and the low concentration impurity region 306 is controlled to 1 × 10 ²⁰ cm ⁻³ or less. Some NH ₃ diffuses in the oxide film 308, and a nitride 310 is formed at the interface between the low concentration source / drain region 306 and the oxide film 308 formed in the silicon substrate 301.

  7A, anisotropic etching is performed to form a first sidewall 308a made of a silicon oxide film and a second sidewall made of a silicon nitride film on the sidewall of the gate electrode 304a. 309a. By this processing, the on-gate protective film 305a is further etched, and the film thickness is 10 nm or less.

Then, using the gate electrode 304a and the side walls 308a and 309a as a mask, arsenic ions are implanted under the conditions of an inclination angle of 7 degrees, an implantation energy of 30 to 50 keV, and a dose amount of 3 to 5 × 10 ¹³ cm ^−2. Thus, a high concentration source / drain region 311 which is a high concentration impurity diffusion region is formed.

  Thereafter, in order to activate the impurities doped in the high concentration source / drain regions 311, RTA treatment is performed under the conditions of treatment temperature: 900 to 1090 ° C. and treatment time: 60 seconds or less.

  Although not shown, a material film (such as BPSG or PSG) that can be selectively removed is formed on the nitride film 308 that forms the second sidewall 308a, and each sidewall 307a, 308a, BPSG, or the like is formed. After the third sidewall is formed by the above, the L-type sidewall may be formed by selectively removing the third sidewall by vapor phase etching of dilute hydrofluoric acid or HF.

  Thereafter, although not shown, an oxide film for forming a portion where no silicide is formed is formed on the entire surface, and patterning with photolithography and oxide film etching with dilute hydrofluoric acid or buffered hydrofluoric acid are performed (silicide region). Is removed), the on-gate protective film 305a is removed.

  Next, in the step shown in FIG. 7B, cobalt (film thickness is 8 to 12 nm) and cap film titanium nitride (film thickness is 10 to 30 nm) are formed on the entire surface of the silicon substrate 301 by the PVD method. Silica is formed by reacting the surface of the silicon substrate 301 with cobalt and the polysilicon surface of the gate electrode 304a and cobalt by RTA treatment under the conditions of temperature: 400 to 550 ° C. and treatment time: 30 to 120 seconds, and hydrochloric acid / peroxide water. The silicide 312 is formed by selectively removing cobalt and titanium nitride that have not reacted with silicon with a mixed solution or ammonia / peroxide mixed solution. Thereafter, in order to reduce the resistance of the silicide 312, an RTA process is performed under conditions of a processing temperature: 700 to 850 ° C. and a processing time of 15 to 60 seconds.

According to the manufacturing method of the present embodiment, the diffusion prevention film 320 formed in the process shown in FIG. 6A is subjected to NH ₃ pre-purge just before the formation of the silicon nitride film 309 in the process shown in FIG. In the meantime, by reacting with NH ₃ , the diffusion prevention film 320 becomes a silicon nitride layer 320a which is an insulator, so that the amount of NH ₃ diffusing through the silicon oxide film 308 can be significantly reduced, and the silicon substrate 301 The nitrogen concentration in the nitride 310 formed at the interface between the low-concentration source / drain region 306 and the oxide film 308 formed therein is controlled to 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. Has been. As a result, the generation of the interface state due to the nitride 310 is suppressed, and the spread of the depletion layer in the low concentration source / drain region 306 due to the interface state is suppressed. As a result, the low concentration source / drain region 306 is suppressed. The resistance increase of the MIS transistor can be prevented, and the performance degradation of the MIS transistor can be prevented.

In the present embodiment, silicon is used as the constituent material of the diffusion preventing film 320, but the same effect can be obtained even with other semiconductor materials such as germanium that reacts with NH ₃ to become an insulator.
In this embodiment, NH ₃ is used as a nitride material for forming the silicon nitride film 309, but N ₂ O may be used as another nitride material.

  In the first to third embodiments, the silicon oxide film is used as the gate insulating film 103 and the silicon oxynitride film is used as the gate insulating films 203 and 303. However, the present invention is not limited to this. A silicon oxynitride film 103 may be used, a silicon oxide film may be used as the gate insulating films 203 and 303, and another insulating film made of a high dielectric material may be used.

  In the first to third embodiments, polysilicon is used as the material of the gate electrode films 104, 204, and 304. However, the present invention is not limited to this, and one type selected from the group of Si, Ge, and C is used. A material composed of the above elements may be used.

In the semiconductor device and the manufacturing method thereof according to the present invention, the nitrogen concentration at the interface between the low-concentration impurity diffusion region and the oxide film when the nitride film is formed on the oxide film even when the nitride film is used as the sidewall. By forming a nitride film at a temperature such that is less than 1 × 10 ²⁰ cm ^{−3, the} amount of interface states generated at the interface between the low-concentration impurity diffusion region and the oxide film is reduced, and the low concentration due to the interface states A semiconductor in which the formation of a depletion layer in an impurity diffusion region is suppressed and a semiconductor device in which deterioration of transistor performance is prevented can be manufactured, and a side wall is formed on a side wall of a gate electrode This method is useful for a method of manufacturing a device and a semiconductor device.

(A) And (b) is principal part sectional drawing of the semiconductor device concerning the 1st Embodiment of this invention. (A) And (b) is principal part process sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. (A) And (b) is principal part process sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. It is principal part process sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. (A) And (b) is principal part process sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning the 3rd Embodiment of this invention. (A) And (b) is principal part process sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning the 3rd Embodiment of this invention. (A) And (b) is principal part process sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning the 3rd Embodiment of this invention. (A)-(d) is principal part process sectional drawing which shows each process of the manufacturing method of the conventional semiconductor device. It is principal part sectional drawing for demonstrating the subject in the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Silicon substrate 102 Element isolation region 103 Gate insulating film 104 Gate electrode 105 1st side wall 106 2nd side wall 107 Low concentration source / drain region 108 Pocket region 109 High concentration source / drain region 110 Nitride 111 Depletion layer 112 Diffusion resistance 113 Silicide 201 Silicon substrate 202 Element isolation region 203 Gate insulating film 204 Gate electrode 204a Gate electrode 205 Gate protective film 205a Gate protective film 206 Low concentration source / drain region 207 Pocket implantation region 208 Oxide film 208a First sidewall 209 Silicon nitride film 209a Second sidewall 210 Nitride 211 High concentration source / drain region 212 Silicide 301 Silicon substrate 302 Element isolation region 3 3 Gate insulating film 304 Gate electrode 304a Gate electrode 305 Gate protective film 305a Gate protective film 306 Low concentration source / drain region 307 Pocket implantation region 308 Oxide film 308a First sidewall 309 Silicon nitride film 309a Second sidewall 310 Nitride 311 High concentration source / drain region 312 Silicide 320 Diffusion prevention film 320a Silicon nitride layer

Claims (8)

A gate electrode formed on the substrate;
An oxide film as a first sidewall and a nitride film as a second sidewall formed on the sidewall of the gate electrode;
A low-concentration impurity diffusion region and a high-concentration impurity diffusion region formed in the region of the substrate located on the side of the gate electrode;
A semiconductor device, wherein a nitrogen concentration at an interface between the oxide film as the first sidewall and the low-concentration impurity diffusion region is 1 × 10 ²⁰ cm ⁻³ or less.   2. The semiconductor device according to claim 1, wherein the conductive film constituting the gate electrode is formed of a material composed of one or more elements selected from the group consisting of Si, Ge, and C. 3. Forming a gate insulating film on the substrate;
Forming a gate electrode film on the gate insulating film;
Forming a gate electrode by etching at least a portion of the gate electrode film;
Forming a low-concentration impurity region in the region of the substrate located on the side of the gate electrode;
Forming an oxide film on the substrate on which the low-concentration impurity region is formed;
Forming a nitride film on the oxide film at a temperature such that the nitrogen concentration at the interface between the oxide film and the low-concentration impurity region is 1 × 10 ²⁰ cm ⁻³ or less;
By performing anisotropic etching on the nitride film and the oxide film, a first sidewall made of the oxide film and a second sidewall made of the nitride film are formed on the sidewall of the gate electrode. Forming a step;
Forming a high-concentration impurity region having a concentration higher than that of the low-concentration impurity region in a region of the substrate located on the side of the first sidewall and the second sidewall. Manufacturing method.   The method for manufacturing a semiconductor device according to claim 3, wherein the temperature of the substrate in the step of forming the nitride film is 600 ° C. or less. Forming a gate insulating film on the substrate;
Forming a gate electrode film on the gate insulating film;
Forming a gate electrode by etching at least a portion of the gate electrode film;
Forming a low-concentration impurity region in the region of the substrate located on the side of the gate electrode;
Forming an oxide film on the substrate on which the low-concentration impurity region is formed;
Forming a diffusion prevention film for preventing diffusion of a gas containing nitrogen as a constituent element on the oxide film on the oxide film;
A nitride film is formed on the diffusion barrier film, and the oxide film and the low-concentration impurity are reacted by reacting the diffusion barrier film with a gas containing nitrogen as a constituent element for forming the nitride film. Controlling the nitrogen concentration at the interface with the region to 1 × 10 ²⁰ cm ⁻³ or less;
By performing anisotropic etching on the nitride film and the oxide film, a first sidewall made of the oxide film and a second sidewall made of the nitride film are formed on the sidewall of the gate electrode. Forming a step;
Forming a high-concentration impurity region having a concentration higher than that of the low-concentration impurity region in a region of the substrate located on the side of the first sidewall and the second sidewall. Manufacturing method. The method for manufacturing a semiconductor device according to claim 5, wherein the gas containing nitrogen as a constituent element is NH ₃ . A step of forming a gate protective film on the gate electrode film during the step of forming the gate electrode;
7. The method of manufacturing a semiconductor device according to claim 3, further comprising: patterning the gate protective film, and etching the gate electrode film using the patterned gate insulating film as a mask.   7. The method for manufacturing a semiconductor device according to claim 3, wherein the gate electrode film is formed of a material composed of one or more elements selected from the group consisting of Si, Ge, and C.

Images