JP2006023974A - Remainder calculation processor and remainder calculation processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a remainder calculation processor and a remainder calculation processing method capable of performing remainder calculation by a multiplication method, and reducing the processing quantity of remainder calculation for an input value whose range is limited. <P>SOLUTION: When an integer whose range is limited is defined as a dividend and the integer of a fixed value is defined as a divisor, a dividend (103) is multiplied (104) by an invert (100) of a fixed point display divisor, and a decimal part is extracted from the multiplication result of the invert (106), and the extraction result of the decimal part is multiplied (108) by a divisor (107), and an integral part is extracted (110) as a division calculation result from a multiplication result (109). In this case, an error to be generated due to the cutoff of non-display digits is guaranteed by adding 1 to the least significant digit of the valid display digits of the invert (100) of the divisor (102) to perform the above arithmetic processing. Also, the number of digits of the fixed point display decimal part is defined as the precisely guaranteed minimum number of digits, and when the decimal point is extracted (106), the decimal part is extracted by mask processing with the precisely guaranteed minimum number of bits. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a residue calculation processing device and a residue calculation processing method, and more particularly to a residue calculation processing device and a residue calculation processing method for performing a residue calculation process at a higher speed by a processor such as a DSP (Digital Signal Processor).

  In a processor such as a DSP of a baseband signal processing unit of W-CDMA (Wideband Code Division Multiple Access), a remainder calculation is performed in order to calculate a count value of a radio frame or a time slot serving as a reference timer in the apparatus. Conventionally, a remainder operation in a processor or simulator such as a DSP is performed using a library dedicated to the processor or simulator.

The remainder calculation using the library uses the subtraction method and the AND method in parallel. When the dividend X and the divisor Y are used, the remainder calculation by the subtraction method repeatedly performs the process of subtracting the divisor Y from the dividend X as follows.
X−Y = X ₁
X ₁ −Y = X _{2
X 2} -Y = X ₃
...
_Xn- Y = _{Xn + 1}

Here, the operation result X _{n + 1} when the subtraction is repeatedly performed is
X _{n + 1} <Y
Then, X _{n + 1} is output as a remainder. That is, the subtraction by the divisor Y is repeatedly performed, and when the subtraction result becomes smaller than the divisor Y, the subtraction result is output as a remainder.

The AND method is a method used only when the divisor Y is a multiplier of 2. The AND method is a method of calculating the remainder by masking the dividend X with (divisor Y-1). For example, the remainder by the AND method when 10 is a dividend and 2 which is the square of 2 is calculated as follows.
10% 4 = 10 & (4-1) = 2

  Here, “10% 4” represents the remainder when 10 is the dividend and 4 is the divisor, and “10 & (4-1) = 2” is “10 (1010 in binary notation)” and “(4- 1) (0011 in binary notation) and logical product (AND) operation processing (that is, mask processing) between bits of each digit, and as a result, “2 (0010 in binary notation)” is obtained. Represents.

  Further, the remainder calculation is performed when the quotient of the dividend x (integer) by the divisor a (integer) is b (integer) and the remainder is c (integer), and the remainder c is obtained by multiplying the dividend x by the reciprocal of the divisor a. Can be calculated as an integer part obtained by taking out the decimal part {c · (1 / a)} and multiplying it by the divisor a. This remainder calculation method is called a multiplication method.

The multiplication method is also explained by a modification of the following mathematical formula. When the quotient of the dividend x (integer) by the divisor a (integer) is b (integer) and the remainder is c (integer), the following equation is established.
x = a · b + c
When the right side of the above formula is wrapped with a,
x = a · {b + c · (1 / a)}
And when further deformed,
x / a = b + c · (1 / a)
It becomes.

here,
a> c
Because
c · (1 / a) <1
It is. That is, {c · (1 / a)} is a decimal part of the calculation result when the dividend x is multiplied by the reciprocal of the divisor a.

As a prior art document related to the present invention, an arithmetic processing apparatus that performs a remainder operation by a multiplication method is described in Patent Document 1 below.
JP-A-8-202534

  The conventional remainder calculation method is an arithmetic method in which a highly accurate output value is obtained as a remainder value over the range of all input values (divisor and dividend). In the subtraction method, the divisor is divided until divisor> dividend. As the difference between the dividend and the divisor is larger, the number of loops for the subtraction and determination process increases. Therefore, there is a problem that the processing amount becomes very large.

  Conventionally, the multiplication method has not been adopted because the reciprocal of the divisor becomes a decimal, and the subsequent operation becomes a floating-point operation, resulting in a large amount of processing for separating the decimal part and the integer part. This is because there was a problem. An object of the present invention is to reduce a processing amount of remainder calculation for an input value having a limited range by using a multiplication method.

  The remainder calculation processing device of the present invention is (1) a remainder calculation processing device for calculating a remainder when a range-limited integer is used as a dividend and a fixed-value integer is used as a divisor. A reciprocal multiplication means for multiplying the reciprocal number, a fractional part extraction means for extracting a fractional part of the multiplication result of the fixed-point display by the reciprocal multiplication means, and a result obtained by multiplying the extraction result of the fixed-point display by the decimal part extraction means by the divisor A divisor multiplication unit for performing the operation, and an integer part extraction unit for extracting an integer part as a remainder calculation result from the multiplication result of the fixed-point display by the divisor multiplication unit.

(2) The reciprocal multiplication means is characterized in that the dividend is multiplied by a value obtained by adding 1 to the least significant digit of the effective display digit of the reciprocal of the divisor of the fixed-point display.
(3) The decimal part extraction means includes means for extracting the decimal part of the multiplication result of the reciprocal multiplication means by a logical product operation with a logical code having a predetermined number of bits, and the integer part extraction means includes: The storage position of the multiplication result of the fixed-point display by the divisor multiplication means is shifted by the number of decimal digits of the fixed-point display, and only the integer part is left in the storage unit and extracted.

  The remainder calculation processing method of the present invention is (4) a remainder calculation processing method for calculating a remainder when a range-limited integer is a dividend and a fixed-value integer is a divisor, and is fixed to the dividend. Multiply the reciprocal of the divisor of the decimal point display, extract the decimal part of the multiplication result of the fixed point display by the reciprocal multiplication, multiply the extraction result of the fixed point display by the decimal part extraction by the divisor, and fix by the divisor multiplication In the remainder calculation processing method that extracts the integer part from the multiplication result of the decimal point display as the remainder calculation result, in order to determine the optimal decimal point position as the fixed decimal point display of the reciprocal of the divisor, the decimal point display is sequentially increased to increase the decimal point display. A step of setting the number of digits; whether the remainder calculation result by the remainder calculation process is good or bad; and the minimum number of digits for which the remainder calculation result is good is the decimal point of the fixed-point display And has a determining and 示桁 number.

  (5) When extracting the fractional part of the multiplication result of the fixed-point display by the reciprocal multiplication, the decimal point is sequentially increased in order to determine the number of digits of the fractional part to be extracted. A step of setting the number of extracted digits; and a step of determining whether the remainder calculation result by the remainder calculation process is good or not, and determining a minimum number of digits for which the remainder calculation result is good as the number of digits of the fractional part to be extracted. I have it.

  According to the present invention, when the remainder is calculated by the multiplication method, the reciprocal of the divisor is displayed in a fixed-point display, so that all subsequent arithmetic processing is handled in a fixed-point display, and the processing load is burdened on a processor such as a DSP. A small number of instructions (shift operation, mask) can be used, and the amount of processing can be reduced. Further, unlike the conventional subtraction method, there is no difference in processing amount depending on the value of the divisor and the dividend.

  In addition, the multiplication method according to the present invention adds 1 to the least significant digit of the reciprocal of the reciprocal of the divisor of the fixed-point display, thereby causing a remainder operation error due to the truncation of the fractional part less than the effective number of the subsequent operation results. Can be corrected. Further, when extracting the decimal part of the multiplication result in the fixed-point display, the multiplication part of the decimal part and the divisor is obtained by extracting the decimal part with a small bit width by logical product operation with a logical code having a predetermined number of bits. (Bit width used for multiplication) can be reduced. The bit width of the fractional part to be extracted is calculated in advance as a limit bit width that can guarantee accuracy.

  FIG. 1 shows a flow of the remainder calculation of the multiplication method by the fixed point display (Q format) of the present invention. Input processing includes input processing of the reciprocal (1 / Y) of the divisor Y of the fixed-point display (Q format) in the processing unit 100, input processing of the dividend X in the processing unit 103, and divisor Y in the processing unit 107. Input processing.

  Both the divisor Y and the dividend X are integers, the divisor Y is a fixed value, and the dividend X is an arbitrary value within a limited range. The decimal point position of the fixed-point display (Q format) when expressing the reciprocal of the divisor Y is determined in advance by a program. In FIG. 1, the fixed point position is indicated by a symbol “Δ”.

  Here, as a specific example, the calculation of the remainder in the Q6 format (fixed decimal point display where the decimal point position is the sixth digit bit position (bit # 6)) will be described. First, as the dividend X and the divisor Y, in order to correct the error of the final remainder calculation result, the least significant bit of the effective display digit is “1” and the other bits are “0”, that is, “1”. And added to the reciprocal of the divisor Y in the fixed-point display (Q format).

That is, as shown in FIG. 1, the reciprocal (1 / Y) of the divisor input in the processing unit 100, the least significant bit stored by the processing unit 101 is “1”, and the other bits are “0”. Are added by the processing unit 102. When a Q6 format of a fixed-point representation in the embodiment shown in FIG. 1, by multiplying the 2 ⁶ to the reciprocal of the divisor Y type a number of moving the position of the decimal point position 6 in the processing unit 100, the The numerical value “1” of the processing unit 101 is added to the numerical value. This is expressed by the following formula.
{(1 / Y) · 2 ⁶ } +1

Next, the addition result (the reciprocal of the divisor Y + 1) of the previous processing unit 102 is multiplied by the dividend X. That is, in FIG. 1, the processing unit 104 multiplies the output data of the processing unit 102 and the dividend X input by the processing unit 103. This is expressed by the following formula.
[{(1 / Y) · 2 ⁶ } +1] · X
Since (reciprocal number of divisor Y + 1) is fixed point display (Q format), multiplication with dividend X in processing unit 104 is integer multiplication.

Next, the decimal part in the fixed-point display (Q format) is extracted from the result of the integer multiplication. In FIG. 1, the result of integer multiplication in the processing unit 104 described above is stored in the processing unit 105, and the processing unit 105 extracts a fractional part with a hatched portion. In the process of extracting the fractional part, when extracting all the digits after the decimal point position, the output data of the processing unit 105 is masked with a bit string of “0... 111111 (2)” = “0... 3f (16)”. If there is no problem in accuracy in practice, only the first digit after the decimal point is extracted and masked with a bit string of '0 ... 100,000 (2)' = '0 ... 20 (16)' You can also This is expressed by the following formula.
[[{(1 / Y) · 2 ⁶ } +1] · X] &'0 ... 20 (16)'

  Note that (2) such as '0 ... 111111 (2)' means binary display, and (16) such as '0 ... 3f (16)' means hexadecimal display. Yes. Further, in FIG. 1, a fractional part is extracted by masking the integer multiplication result stored in the processing unit 105, and the extracted decimal part is stored in the processing unit 106 shown in FIG.

Next, the extracted decimal part is multiplied by a divisor Y (integer multiplication). In FIG. 1, the decimal part of the processing unit 106 and the divisor Y input to the processing unit 107 are input to the processing unit 108 and multiplied. This is expressed by the following formula.
[[[{(1 / Y) · 2 ⁶ } +1] · X] &'0 ... 20 (16)'] · Y

  In the above-described calculation of extracting the fractional part in the processing units 105 and 106 in FIG. 1, by performing masking by limiting the number of extracted bits, the number of effective bits of the extracted fractional part is reduced, and the decimal part is reduced. The circuit scale of the processing unit 108 that multiplies the divisor Y with the divisor Y can be reduced.

  FIG. 4 shows details of the calculation for extracting the decimal part in the processing units 105 and 106. In the figure, a bit string used for mask processing when a fractional part is extracted from stored data of the processing unit 401 is shown in a table 404. The bit string used for the mask processing is not fixed to only “1111... 11 (2)” for extracting all the digits after the decimal point. If the precision of the remainder result is maintained, the bit string is shown in the table 404. A bit string of “1” up to any digit is used, the bit string is set in the processing unit 402, mask processing is performed using the bit string, and a decimal part of only a necessary digit is extracted to the processing unit 403. In FIG. 4, processing units 401 and 403 correspond to the processing units 105 and 106 in FIG. 1, respectively.

Finally, the operation result is shifted by the decimal point position in the fixed-point display (Q format) to extract the integer part, and this result is the remainder value to be obtained. In FIG. 1, the multiplication result of the processing unit 108 is stored in the processing unit 109, and the data stored in the processing unit 109 is shifted to the right by 6 bits (because this is an example of the Q6 format), and only the integer part is processed. Take out to 110. The calculation result extracted by the processing unit 110 shown in FIG. This is expressed by the following formula.
[[[[{(1 / Y) · 2 ⁶ } +1] · X] &'0 ... 20 (16)'] · Y] >> 6
Here, “>> 6” represents shifting data to the right by 6 bits.

  Next, error correction of the remainder calculation by the multiplication method will be described. The error of the remainder calculation by the multiplication method is caused by truncation of the decimal part of the digit smaller than the decimal part that can be displayed (stored in a register or the like) in storing the reciprocal of the divisor Y in the fixed-point display (Q format), Further, when the data of the processing unit 109 shown in FIG. 1 is shifted to the right and the integer part is extracted, an error occurs due to the fractional part of the data stored in the processing unit 109 being truncated.

Qn format of remainder operation in (X% Y), the true value of the remainder _{R tru,} the value of the remainder calculated by multiplying method When _{R Cal, R Cal} becomes as the following equation.
R _Cal = [[[[[{(1 / Y) · 2 ⁿ } +1] · X] & (2 ⁿ −1)] · Y] >> n

Reciprocal P0 = (1 / Y) · 2 n of Qn format divisor input to the processing unit 100, since the non-display portion is truncated, between the true value _{P tru} of the reciprocal of the divisor Y, Qn format An error of less than “1” is generated below the least significant digit of the display part. Δp is the error
0 <Δp <1
And
P _true -1 <P0 <P _true
(See FIG. 2A).

A value obtained by adding a numerical value in which the least significant digit of the Qn format is set to “1” to the reciprocal number P0 = (1 / Y) · 2 ⁿ of the Qn format P1 = (1 / Y) · 2 ⁿ +1 is a divisor Y large next than the true value P _tru of inverse and the error between the true value P _tru of the reciprocal of the divisor Y is a error in the least significant digit of the numeric '1' less than the visible portion of the Qn format. This error is (1−Δp),
0 <1-Δp <1
P _true <P1 <P _true +1
(See FIG. 2A).

Next, the dividend X is multiplied by the aforementioned value P1. If the value is P2,
P2 = [{(1 / Y) · 2 ⁿ } +1] · X
The values of X and n are limited so that the error (1-Δp) · X at this time falls within the following range.
0 <(1-Δp) · X <2 ⁿ (see FIG. 2B)
The dividend X is limited so as to satisfy the above formula, or the number of digits n of the decimal part of the fixed point is determined according to the required size of the dividend X.

Next, the decimal part is extracted from the calculation result of P2. Let this fractional part be P3. P3 is as follows.
P3 = [[{(1 / Y) · 2 ⁿ } +1] · X] & (2 ⁿ −1) (see FIG. 2C)
The error at this time is also
0 <(1-Δp) · X <2 ⁿ
It becomes.

Next, the operation result P3 is multiplied by the divisor Y. The multiplication result is P4.
P4 = [[[[{(1 / Y) · 2 ⁿ } +1] · X] & (2 ⁿ −1)] · Y
The error (1-Δp) · X · Y is limited to the following range.
0 <(1-Δp) · X · Y <2 ⁿ
That is, the divisor Y is limited so as to satisfy the above equation (see FIG. 2D).

Finally, the operation result P4 is shifted n bits to the right to extract the integer part, and the integer part is output as the remainder R _Cal . Here, shifting the calculation result P4 to the right by n bits is equivalent to a process of dividing the P4 by ²ⁿ and truncating the decimal part. If the calculation result when P4 is divided by ²ⁿ is P5, the calculation result P5 is as follows.
P5 = [[[[[{(1 / Y) · 2 ⁿ } +1] · X] & (2 ⁿ −1)] · Y] / 2 ⁿ

The error at this time is expressed as follows.
0 <{(1-Δp) · X · Y} / 2 ⁿ <1 (see FIG. 2 (e))
As described above, since the error of the calculation result P5 is less than 1, the remainder calculation result R _Cal obtained by rounding down the decimal part becomes equal to the exact remainder value R _true .

  Next, calculation of the Q format will be described. In order to calculate the remainder by the multiplication method described above, first, the decimal point position in the fixed point display (Q format) of the reciprocal of the divisor Y must be determined. Further, in the remainder calculation by the multiplication method, the dividend X and (reciprocal number of the divisor Y + 1) are multiplied, and the bit limit (mask value) when extracting the fractional part from the multiplication result must also be determined.

  Regarding a program for determining a fixed-point display (Q format) and a mask value, a process for determining a Q format and a mask value with an initial value in Q6 format (when LSB is bit # 0, bit # 6 is the decimal point position) This will be described below. FIG. 3 shows a flowchart thereof.

  First, the minimum value (Min) and maximum value (Max) of the dividend X, the divisor Y (fixed value), and the minimum value (Min; 6 in this example) of the Q format are input (step 300). Next, the input minimum value (Min; 6) of the Q format is set as the initial value of the Q format (step 301). In the following processing, the calculation is repeated while gradually increasing the Q format value, and the Q format and the mask value are determined.

  Next, a mask value for determining the decimal place extraction digit is set. The initial value is a value in which only the most significant digit (leftmost bit) after the decimal point is ‘1’, that is, ‘100000 (2)’ (step 302). Using the previously set Q format value (6) and the fractional part extraction mask value set in step 303, in step 303, in order from the minimum value (Min) to the maximum value (Max) of the dividend X. For the dividend X set while being incremented to, calculate the remainder by the divisor Y set in step 300, and whether the calculation result matches the result of the remainder by the conventional arithmetic method (for example, subtraction method) It is determined in step 304 whether or not.

  In the determination of step 304, if there is even one dividend X that does not match, the remainder calculation / determination processing step is exited without completing the calculation for the entire range of the dividend X, and the mask value for fractional part extraction is set. Is all '1' (step 305), if not all '1', the process returns to step 302 and the bit of '1' is incremented by the lower one digit as the mask value for extracting the fractional part and again. Then, the calculation / determination of the remainder from step 303 is resumed.

  As the mask value, as shown in the table 404 in FIG. 4, the remainder is calculated while sequentially increasing the number of digits having a value of “1”, and the value at the time when the precision of the remainder is guaranteed is used. Become. The processing of steps 302 to 304 is repeated, and all the bits of the mask are set to “1”, and the mask value becomes “11... 111 (2)”. When the remainder by the multiplication method does not match, it is determined whether or not the Q format has reached the maximum (step 307). If the Q format has not yet reached the maximum, the process returns to step 301 to set the decimal point position of the Q format. Shift to the left by 1 bit and set again. In step 302, the mask value is set again in accordance with the Q format, and the calculation and determination of the remainder in steps 303 and 304 are repeated.

  FIG. 5 shows how the Q format is set. In the figure, the lower one shows a larger Q format value (larger display part after the decimal point). As shown in FIG. 5, the Q format is set by gradually increasing the display part after the decimal point to check whether the precision of the remainder is guaranteed, and when the accuracy is confirmed, the Q format is confirmed. Will be adopted.

  In the above-described embodiment, since the Q6 format is used, if the accuracy is not guaranteed with this Q6 format, the Q format is set to one larger as the Q format at step 301 in FIG. Is reset to '1000000 (2)', and the remainder calculation / determination is started again.

  Steps 301 to 304 are repeated. If any of the determination conditions does not match the result of the conventional arithmetic method and the result of the remainder of the multiplication method according to the present invention and the Q format reaches the maximum value, "Is output (step 308). If it is confirmed in step 304 that the remainder results match and the setting value of dividend X has reached the maximum value (Max) in step 306, the remainder calculation / determination process in step 304 is terminated. Then, the Q format and the mask value at the time when the remainder results are confirmed to match are output as the Q format and mask decision values to be used (step 309).

A list of the meaning contents of the symbols in the above mathematical formula is shown below.
x + y: addition xy: subtraction x · y: multiplication x / y: division x% y: remainder x & y: logical product x >> y: shift operation ^xy : x to the power of y xxxxxxxx (2): binary number display xxxxxxxx (16): Hexadecimal display

It is a figure which shows the flow of the remainder calculation of the multiplication method by the fixed point display of this invention. It is a figure which shows the error which arises in the remainder calculation by a multiplication method. It is a figure which shows the flow which determines the value of Q format and a mask. It is a figure which shows the detail of the arithmetic processing which extracts the decimal part in this invention. It is a figure which shows the aspect of the setting of Q format in this invention.

Explanation of symbols

100 Input value of reciprocal of divisor Y in fixed-point display (Q format) 101 Addition value “1” for error correction of remainder calculation in fixed-point display (Q format)
102 Addition of 100 and 101 103 Input value of dividend X 104 Multiplication of 102 and 103 105 Multiplication result of 104 106 Result of extraction of decimal part from 105 107 Input value of divisor Y 108 Multiplication of 106 and 107 109 Multiplication result 110 The result of extracting the integer part of 109

Claims (5)

In a remainder calculation processing device that calculates a remainder when a range-limited integer is a dividend and a fixed integer is a divisor,
Reciprocal multiplication means for multiplying the dividend by the reciprocal of the divisor of the fixed-point display, decimal part extraction means for extracting the fraction part of the multiplication result of the fixed-point display by the reciprocal multiplication means, and fixed-point display by the decimal part extraction means And a divisor multiplication unit that multiplies the extraction result by the divisor, and an integer part extraction unit that extracts an integer part from the multiplication result of the fixed-point display by the divisor multiplication unit as a remainder calculation result. Processing equipment.   2. The remainder calculation processing apparatus according to claim 1, wherein the reciprocal multiplication means multiplies the dividend by a value obtained by adding 1 to the least significant digit of the effective display digit of the reciprocal of the divisor of the fixed-point display. The fraction part extraction means comprises means for extracting the fraction part of the multiplication result of the reciprocal multiplication means by a logical product operation with a logical code having a predetermined number of bits,
The integer part extraction means shifts the storage position of the multiplication result of the fixed-point display by the divisor multiplication means by the number of decimal digits of the fixed-point display and takes out only the integer part in the storage part. The remainder calculation processing apparatus according to claim 1. A residue calculation processing method for calculating a remainder when a range-limited integer is a dividend and a fixed-value integer is a divisor,
Multiplying the dividend by the reciprocal of the divisor of the fixed-point display, extracting the fractional part of the multiplication result of the fixed-point display by the reciprocal multiplication, multiplying the extraction result of the fixed-point display by the decimal part extraction by the divisor, In a residue calculation processing method for extracting an integer part as a remainder calculation result from a multiplication result of a fixed point display by divisor multiplication,
In order to determine the optimal decimal point position as the fixed-point display of the reciprocal of the divisor, the step of setting the decimal point display digits while sequentially increasing the decimal point display digits, and the quality of the residue calculation result by the residue calculation process is determined And determining the minimum number of digits for which the remainder calculation result is good as the number of decimal digits displayed in the fixed-point display. A residue calculation processing method for calculating a remainder when a range-limited integer is a dividend and a fixed-value integer is a divisor,
Multiplying the dividend by the reciprocal of the divisor of the fixed-point display, extracting the fractional part of the multiplication result of the fixed-point display by the reciprocal multiplication, multiplying the extraction result of the fixed-point display by the decimal part extraction by the divisor, In a residue calculation processing method for extracting an integer part as a remainder calculation result from a multiplication result of a fixed point display by divisor multiplication,
When extracting the decimal part of the multiplication result of the fixed-point display by the reciprocal multiplication, in order to determine the number of digits of the fraction part to be extracted, the number of decimal points extracted is set while sequentially increasing the number of digits of the fraction part to be extracted. And determining whether the remainder calculation result by the remainder calculation process is good or not and determining the minimum number of digits for which the remainder calculation result is good as the number of digits of the fractional part to be extracted. Remainder calculation processing method.

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