JP2006023402A - Display apparatus and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus which can compensate uneven luminance caused by the variation of the threshold voltage in a driving transistor without increasing a driving period, and to provide a driving method thereof. <P>SOLUTION: A pixel circuit Aij is provided corresponding to a combination of a gate line Gi and a source line Sj, and includes: an organic EL element EL1 driven by a current from a power line Vp; a switching transistor 13 which is controlled by a scan signal from the gate line Gi to activate and which outputs the data from the source line Sj when activated; a driving transistor 13 which controls the current supply from the power line Vp to the organic EL element EL1 in accordance with the data; a switching transistor 12 for blanking; and a switching transistor 14 which short-circuits a gate terminal and a source terminal or a drain terminal of the driving transistor 13 so as to compensate variations in the threshold voltage in the driving transistor 13 in a period of blanking. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device using a current driving element such as an organic EL (Electro Luminescence) display or FED (Field Emission Display), and a driving method thereof.

  In recent years, research and development of current-driven light-emitting elements such as organic EL displays and FEDs have been actively conducted. In particular, the organic EL display is a display that can emit light with low voltage and low power consumption, and thus has attracted attention as a display used in portable devices such as mobile phones and PDAs (Personal Digital Assistants).

  As a pixel circuit configuration for this organic EL display, the circuit configuration shown in Patent Document 1 (Japanese Patent Publication No. 2002-514320) is shown in FIG.

  As shown in FIG. 25, the pixel circuit 300 of Patent Document 1 includes four P-type TFTs (Thin Film Transistors) 360, 365, 370, 375, two capacitors 350, 355, and an OLED (organic light-emitting diode; organic EL). 380. A TFT 365, a TFT 375, and an OLED 380 are connected in series between the power supply line 390 (potential + VDD) and the common cathode (GND line). A capacitor Cc 350 and a switching TFT 360 are connected in series between the gate terminal of the driving TFT 365 and the data line 310. Further, a switching TFT 370 is connected between the gate terminal and the drain terminal of the driving TFT 365, and a capacitor Cs 355 is connected between the gate terminal and the source terminal of the driving TFT 365. A select line 320, an auto zero line 330, and an illumination line 340 are coupled to the gate terminals of the TFT 360, TFT 370, and TFT 375, respectively.

  In the pixel circuit 300, the auto-zero line 330 and the illumination line 340 are low during the first period, the switching TFT 370 and the driving TFT 375 are turned on, and the drain terminal potential and the gate terminal potential of the driving TFT 365 are equal. At this time, a current flows from the driving TFT 365 toward the OLED 380, and the gate potential of the driving TFT 365 becomes such a potential that the driving TFT 365 is turned on.

  At this time, the reference voltage is input to the data line 310, the select line 320 is set to Low, and the other terminal (terminal on the TFT 360 side) of the capacitor Cc350 is set to the reference voltage.

  Next, in a second period, the illumination line 340 is set to High, and the TFT 375 is turned off.

  As a result, the gate potential of the driving TFT 365 gradually increases, and when the gate potential becomes a value (+ VDD−Vth) corresponding to the threshold voltage (−Vth) of the driving TFT 365, that is, the gate of the driving TFT 365. -When the source-to-source voltage becomes equal to the threshold voltage of the driving TFT 365, the driving TFT 365 is turned off.

  Next, in a third period, the potential of the auto zero line 330 is set to High, and the switching TFT 370 is turned off. As a result, the difference between the gate potential and the reference potential is stored in the capacitor Cc350.

  That is, the gate potential of the driving TFT 365 becomes a value (+ VDD−Vth) corresponding to the threshold voltage (−Vth) of the driving TFT 365 when the potential of the data line 310 is the reference potential. When the potential of the data line 310 changes from the reference potential, the potential corresponding to the change is applied to the gate terminal of the driving TFT 365 regardless of the threshold potential of the driving TFT 365.

  Therefore, a voltage corresponding to a desired gate potential is applied to the data line 310 from the reference potential, and the select line 320 is set to a high state (a state where the potential is high). At this time, the gate terminal potential of the driving TFT 365 is maintained at a potential corresponding to the difference between the desired gate potential and the threshold voltage (desired gate potential−threshold potential). This ends the pixel selection period.

  As described above, when the pixel circuit shown in FIG. 25 is used, a variation in threshold potential of the driving TFT 365 is compensated, and a potential (desired gate potential−threshold potential) is compensated for the variation in threshold potential at the gate terminal of the driving TFT 365. Can be applied).

  On the other hand, FIG. 26 shows the driving timing of the driving method disclosed in Patent Document 2 (Japanese Patent Publication No. 9-511589) as a method for time-division gradation display of ferroelectric liquid crystal. FIG. 27 shows a row waveform (a waveform of a voltage applied to the row electrode) and a column waveform (a waveform of a voltage applied to the column electrode) for realizing the drive timing shown in FIG.

  In FIG. 26, the horizontal axis is time, and the vertical axis is row number. The symbol “S” in FIG. 26 indicates that in the row waveform of the row number corresponding to the symbol (shown in FIG. 27), the time corresponding to the symbol is the voltage (strobe pulse) Vs (exactly voltage 0 and the voltage Vs) are applied, and this indicates a selection period (corresponding to the strobe portion in Patent Document 2, also referred to as writing time). The symbol “b” indicates that in the row waveform (shown in FIG. 27) of the row number corresponding to the symbol, the time corresponding to the symbol is applied with voltage (erase pulse) −Vb and the row is blocked. This indicates that the blanking period is to be ranked (erased).

  In each pixel, data is written in the writing period, which is the beginning of the display period, and display corresponding to the data is performed. Thereafter, the display is continued until blanking. For example, the pixel of row number 1 is selected at time 1 and data (this data is B2) is written and blanked at time 15. The pixel of row number 1 is selected again at time 22 and data (this data is referred to as B1) is written and blanked at time 29.

  That is, the data B2 written in the first writing period (time 1) is displayed for 14 unit times from time 1 to time 14. Data B1 written in the next writing period (time 22) is displayed over 7 unit times (selection period) from time 22 to time 28. Therefore, by using asynchronous blanking, it is possible to perform time-division gradation display in which the weight of data B2: the weight of data B1 is 2: 1.

  The data B2 and B1 are supplied to the data line (column electrode) as the column waveform shown in FIG. Therefore, the data B2 is generated at an odd time, the data B1 is generated at an even time, and the timing of applying the data B1 and B2 to a row of a certain row number (for example, 1) is delayed by 2 unit times, respectively. It is assumed that data B1 and B2 are applied to the next row number (for example, 2).

  In this way, the timings of writing the data B2 and the data B1 to a plurality of pixels sharing one data line can be prevented from overlapping each other (in this specification, time division gray scale driving is performed at such timings. This is referred to as “time-multiplexed gradation driving”).

  As described above, when the driving method shown in FIG. 26 is used, it is possible to realize time-multiplexed gradation driving by using asynchronous blanking.

  Further, Patent Document 3 discloses an organic EL element provided corresponding to a combination of a plurality of scanning lines and at least one data line, and a current selection among the plurality of scanning lines discretely selected. Driving means for supplying instruction data indicating display in a display period until instruction data is next supplied to the organic EL element corresponding to the scanning line being set via the data line corresponding to the organic EL element; A display device is disclosed. Further, in Patent Document 3, for the pixel circuit constituting the display device, in addition to the organic EL element, each TFT is selected by a data line to which each instruction data is output, and each instruction through the selected TFT. It is disclosed that a capacitor to which data is applied and a driving TFT that sets a current that flows from a power supply line to an organic EL element by changing a source-drain resistance depending on the potential of the capacitor are disclosed (Patent Document 3). (See FIG. 2).

Further, Patent Document 4 discloses a matrix type display device having a memory property capable of gradation display with the number of gradations R (R is an integer of 2 or more) and m number of scanning electrodes. Scanning is performed n (n is an integer of 2 or more) times within a frame period, and the time ratio of the first, second,..., Nth display period is X: RX:...: Rn-1 X (X is a positive integer) ), A driving method of a matrix type display device that performs time-division display is disclosed.
Japanese translation of PCT publication No. 2002-514320 (International publication date: October 29, 1998) No. 9-511589 (International publication date: October 19, 1995) Japanese Patent Laying-Open No. 2004-4501 (Publication date: January 8, 2004) JP-A-9-127906 (Publication date: May 16, 1997) “4.0-in. TFT-OLED Displays and a Novel Digital Driving Method”, SID'00 Digest, pp.924-927, Semiconductor Energy Laboratory (released in 2000) “Continuous Grain Silicon Technology and Its Applications for Active Matrix Display”, AM-LCD 2000, pp.25-28, Semiconductor Energy Laboratory (released in 2000) “Polymer Light-Emitting Diodes for use in Flat panel Display”, AM-LCD 2001, pp.211-214, Semiconductor Energy Laboratory (released in 2001)

  However, in the pixel circuit of Patent Document 1 shown in FIG. 25, a period for compensating for variation in threshold potential of the driving TFT 365 is required at the beginning of each selection period. During the compensation period, it is necessary to apply a reference potential to the data line 310, and the data line 310 is occupied. Therefore, a desired voltage corresponding to display data cannot be supplied to the data line 310.

  In the case of a display device that does not compensate for variation in threshold voltage, the selection period includes only a period during which a desired voltage corresponding to display data is supplied to the data line 310. However, in the pixel circuit of Patent Document 1 shown in FIG. 25, as described above, the threshold voltage variation compensation is performed at the beginning of each selection period, separately from the period during which a desired voltage corresponding to display data is supplied to the data line 310. It is necessary to provide a period for performing For this reason, in the pixel circuit having the configuration shown in FIG. 25, the period during which the data line 310 is occupied (that is, the selection period) becomes longer by the period during which the threshold voltage variation compensation is performed. As a result, the number of selection periods that can exist in one frame period is reduced, and there is a problem in that many select lines cannot be driven by one drive circuit.

  Further, in the display device of Patent Document 3, since it is necessary to provide a blanking signal as one of the instruction data, the number of instruction data usable for display is reduced, and the instruction data having the maximum weight among the instruction data is reduced. There is a problem that the weight becomes large and it is difficult to suppress the generation of the moving image false contour.

  In the driving methods of Patent Document 2 and Patent Document 4, a blanking period is always provided immediately before the instruction data is written. For this reason, there exists a subject that the sum total of a blanking period becomes long (namely, the ratio of a non-light-emission period becomes high).

  SUMMARY OF THE INVENTION Accordingly, a first object of the present invention is to provide a display device and a driving method thereof that can compensate for luminance unevenness caused by variations in threshold voltages of driving transistors without lengthening the selection period. .

  Further, in the display device disclosed in Patent Document 3, blanking is performed by supplying a blanking signal to the source wiring. Therefore, it is necessary to provide the blanking signal as one of the instruction data. As a result, one of the instruction data always has a weight of “0” and cannot be used for display, so the number of instruction data that can be used for display is reduced. Therefore, it is necessary to increase the weight of instruction data usable for display accordingly. For this reason, the weight of the heaviest instruction data is increased, which causes a problem that the moving image false contour is easily noticeable. Patent Document 1 does not disclose or suggest any blanking.

  Accordingly, a second object of the present invention is to provide a display device that can perform blanking without supplying a blanking signal to the source wiring, and as a result, can suppress the occurrence of moving image false contours low. It is in.

  Further, in the time-multiplexed gradation driving methods of Patent Document 2 and Patent Document 4, a blanking period is required for each selection period. For this reason, the proportion of the blanking period existing in one frame period is large, and the proportion of the display period (the state in which the electro-optic element is controlled according to the display data) is small accordingly. Therefore, there is a problem that high average luminance cannot be obtained or the life of the electro-optic element is shortened.

  Patent Document 1 does not disclose or suggest any blanking period.

  Accordingly, a third object of the present invention is to provide a display device capable of increasing the ratio of the display period existing in one frame period and, as a result, extending the life of the electro-optic element and improving the luminance. It is to provide a driving method.

  1) In order to solve the above problems, a display device according to the present invention includes a plurality of gate lines to which scanning signals are supplied, at least one source line to which data for display is supplied, An electro-optical element that is provided corresponding to a combination of a gate wiring and the at least one source wiring and is driven by a current supplied from a power source, and conduction is controlled by a scanning signal supplied to the gate wiring. A first switch transistor that sometimes outputs data from the source wiring, and a power supply and the electro-optic element interposed between the first power supply and the electro-optic element to supply current to the electro-optic element. Driving transistor controlled in accordance with data output from the driving transistor and blanking for blanking the display of the electro-optic element And a control wiring provided in parallel with the gate wiring for controlling the blanking means, and for compensating for variations in threshold voltage of the driving transistor during the blanking period during which the blanking is performed. And a second switching transistor for short-circuiting the gate terminal and the source terminal or drain terminal of the driving transistor.

  According to the above configuration, the second switching transistor is turned on during the blanking period in which the blanking is performed, and the gate terminal and the source terminal or the drain terminal of the driving transistor are short-circuited. The potential difference (gate-source potential or gate-drain potential) between the gate terminal and the source terminal or drain terminal of the driving transistor can be made equal to the threshold voltage of the driving transistor. As a result, when a driving current flows through the electro-optic element, the potential difference between the gate terminal and the source terminal or drain terminal of the driving transistor corresponds to the data supplied to the source wiring without depending on the threshold potential. The potential is changed from the threshold potential by the determined potential. Therefore, the current flowing through the driving transistor has a current value corresponding to the data supplied to the source wiring regardless of the threshold potential. As a result, luminance unevenness due to variation in threshold potential of the driving transistor is compensated, and display without uneven luminance can be performed.

  In the above configuration, the compensation of the variation in the threshold potential of the driving transistor is not performed at the beginning of each selection period as in the pixel circuit shown in FIG. 25 of Patent Document 1, but in a non-display period outside the selection period. Perform during a blanking period. For this reason, it is not necessary to provide a period for performing threshold voltage variation compensation in each selection period, and the entire selection period can be used as a display period. Therefore, the selection period can be shortened compared to the configuration of Patent Document 1. As a result, driving transistors corresponding to more gate wirings can be driven by one scanning signal supply means (gate driver). Therefore, for example, a display device having a larger size can be driven by one scanning signal supply unit.

  As described above, according to the above configuration, the first object can be achieved.

  Further, according to the above configuration, blanking can be performed by controlling the blanking means by the control wiring, so that a blanking signal for erasing the electro-optical element is not supplied from the driving circuit to the source wiring. It is also possible to realize a configuration for performing blanking. In such a configuration, since all instruction data can be used for display, the weight of the instruction data having the largest weight among the instruction data can be reduced. As a result, the generation of a moving image false contour can be suppressed. Therefore, according to the above configuration, the second object can be achieved in addition to the first object.

  Note that in this specification, the “selection period” refers to a period in which a source wiring is occupied to change a display state of a specific electro-optical element, or a period in which a gate wiring supplies an on-voltage. .

  2) In the display device according to the present invention, the blanking means is inserted between the driving transistor and the electro-optical element, and is controlled by the control wiring to flow from the driving transistor to the electro-optical element. It is preferable that the third switching transistor is configured to stop.

  According to the above configuration, blanking (stopping the current flowing from the driving transistor to the electro-optic element) can be performed by controlling the third switching transistor by the control wiring. Unlike the means for performing blanking (means for supplying a blanking signal to the source wiring), without supplying a signal (blanking signal) for setting the electro-optic element to the erased state from the driving circuit to the source wiring, Blanking can be performed. As a result, it is possible to effectively use the instruction data, and it is possible to reduce the weight of the instruction data having the largest weight among the instruction data. As a result, the generation of a moving image false contour can be suppressed. Therefore, according to the above configuration, the second object can be achieved in addition to the first object.

  3) The display device according to the present invention preferably maintains a potential difference between the gate terminal and the source terminal or drain terminal of the driving transistor in the display device including the third switching transistor and the control wiring. And a third switching transistor that is in an ON state during a period in which the second switching transistor is in an ON state in order to compensate for variations in threshold voltage of the driving transistor. From the driving transistor to the OFF state, and the current flowing from the driving transistor to the electro-optical element is stopped.

  According to the above configuration, when the second switching transistor is turned on, the gate terminal of the driving transistor is short-circuited with the source terminal or the drain terminal. Next, in this state, when the third switching transistor shifts from the ON state to the OFF state and the current flowing from the driving transistor to the electro-optical element stops, the gate terminal and the source terminal or drain terminal of the driving transistor (The potential between the gate and the source or the potential between the gate and the drain) gradually changes, and the driving transistor shifts from the ON state to the OFF state. Thereby, the potential difference (gate-source potential or gate-drain potential) between the gate terminal and the source terminal or drain terminal of the driving transistor becomes equal to the threshold potential. Thereafter, even if the second switching transistor is turned off, the potential difference equal to the threshold voltage of the driving transistor is held by the potential difference holding means. As a result, when a drive current flows through the electro-optic element, the potential difference (gate-source potential or gate-drain potential) between the gate terminal and the source terminal or drain terminal of the driving transistor depends on the threshold potential. Instead, the potential is changed from the threshold potential by the potential corresponding to the data supplied to the source wiring. Therefore, the current flowing through the driving transistor has a current value corresponding to the data supplied to the source wiring regardless of the threshold potential. As a result, luminance unevenness due to variation in threshold potential of the driving transistor is compensated, and display without uneven luminance can be performed.

  4) The display device according to the present invention is preferably a display device comprising the potential difference holding means, wherein the potential difference holding means has one end connected to the gate terminal of the driving transistor, and the source terminal or drain terminal of the driving transistor. A second capacitor having one end connected to the gate terminal of the driving transistor and a second capacitor having the other end connected to the first switching transistor. A fourth switch transistor is further provided for connecting the other end of the second capacitor to a predetermined potential wiring during a period in which the switch transistor is in an ON state.

  According to the above configuration, when the first switch transistor is in the OFF state, the fourth switch transistor is turned on, and a predetermined potential is applied from the predetermined potential wiring to the other end of the second capacitor. The second switching transistor can be turned on to short-circuit between the gate terminal and the drain terminal (or source terminal) of the driving transistor. At this time, since the third switching transistor is in the ON state, the gate potential of the driving transistor becomes the ON potential.

  Thereafter, by turning off the third switching transistor, the gate-source potential (or gate-drain potential) of the driving transistor gradually changes, and the driving transistor changes from the ON state to the OFF state. .

  Then, the second switching transistor is turned off and the fourth switching transistor is also turned off, so that the gate of the driving transistor can be obtained when the potential of the other end of the second capacitor is the predetermined potential. The source potential (or gate-drain potential) can be set equal to the threshold potential. The potential set at this time is held by the first capacitor and the second capacitor.

  After that, when the first switch transistor is turned on and a desired potential (potential according to the display data) is applied from the source wiring to the other end of the second capacitor with reference to the predetermined potential, driving is performed. The output current of the driving transistor can be set to a current value corresponding to the display data regardless of the threshold potential of the driving transistor.

  As described above, according to the above configuration, it is possible to compensate for variations in the threshold value of the driving transistor by applying a predetermined potential to the second capacitor during the blanking period which is a non-display period outside the selection period.

  The display device according to the present invention is preferably a display device comprising the potential difference holding means, wherein the potential difference holding means has one end connected to the gate terminal of the driving transistor and the other of the source terminal or drain terminal of the driving transistor. A second capacitor having one end connected to the gate terminal of the driving transistor and having the other end connected to the first switch transistor; and the second switch transistor. And a fifth switch transistor for connecting the other end of the second capacitor to the gate terminal of the driving transistor during a period in which the second capacitor is ON.

  According to the above configuration, when the first switching transistor is in the OFF state, the fifth switching transistor is turned on, and the other end of the second capacitor is connected to the gate terminal of the driving transistor. The second switching transistor can be turned on to short-circuit between the gate terminal and the drain terminal (or source terminal) of the driving transistor. At this time, since the third switching transistor is in the ON state, the gate potential of the driving transistor is in the ON state, and the potential at both ends of the second capacitor becomes a predetermined potential (for example, a power supply potential). The potential across the second capacitor is held even after the fifth switching transistor is turned off.

  Thereafter, by turning off the third switching transistor, the gate-source potential (or gate-drain potential) of the driving transistor gradually changes, and the driving transistor changes from the ON state to the OFF state. .

  Thereafter, the second switch transistor and the fifth switch transistor are turned off. Thus, if a predetermined potential (for example, a power supply potential) supplied to the other end of the second capacitor during the period is supplied to the other end of the second capacitor, the gate potential of the driving transistor becomes the threshold potential. Can be set. The potential set at this time is held by the first capacitor even after the fifth switching transistor is turned off.

  After that, when the first switch transistor is turned on and a desired potential (potential according to the display data) is applied from the source wiring to the other end of the second capacitor with reference to the predetermined potential, driving is performed. The output current of the driving transistor can be set to a current value corresponding to the display data regardless of the threshold potential of the driving transistor. .

  As described above, according to the above configuration, it is possible to compensate for variations in the threshold value of the driving transistor by applying a predetermined potential to the second capacitor during the blanking period which is a non-display period outside the selection period.

  The display device according to the present invention is preferably a display device comprising the potential difference holding means, wherein the potential difference holding means has one end connected to the gate terminal of the driving transistor and the other of the source terminal or drain terminal of the driving transistor. A first capacitor having an end connected thereto, further including a second capacitor having one end connected to the gate terminal of the driving transistor and the other end connected to the first switch transistor; The switch transistor sets the charge of the second capacitor by connecting the other end of the second capacitor to the source wiring during a period in which the third switch transistor is OFF. It is the composition which is.

  According to the above configuration, when the first switching transistor is in the OFF state, the second switching transistor is turned on, so that the gate terminal and the drain terminal (or the source terminal) of the driving transistor are connected. It is possible to short-circuit between them. At this time, since the third switching transistor is in the ON state, the gate potential of the driving transistor is in the ON state.

  Thereafter, by turning off the third switching transistor, the gate-source potential (or gate-drain potential) of the driving transistor gradually changes, and the driving transistor changes from the ON state to the OFF state. .

  Also, the charge of the second capacitor is set by turning on the first switch transistor and connecting the other end of the second capacitor to the source wiring and simultaneously turning on the second switch transistor. it can. Thereafter, the first switching transistor is turned off, so that the second capacitor holds the potential difference at the time point.

  Thereafter, the second switch transistor is turned off. Thus, if a predetermined potential (for example, a power supply potential) supplied to the other end of the second capacitor during the period is supplied to the other end of the second capacitor, the gate potential of the driving transistor becomes the threshold potential. Can be set. The potential set at this time is held by the first capacitor.

  After that, when the first switch transistor is turned on and a desired potential (potential according to the display data) is applied from the source wiring to the other end of the second capacitor with reference to the predetermined potential, driving is performed. The output current of the driving transistor can be set to a current value corresponding to the display data regardless of the threshold potential of the driving transistor.

  As described above, according to the above configuration, it is possible to compensate for variations in the threshold value of the driving transistor by applying a predetermined potential to the second capacitor during the blanking period which is a non-display period outside the selection period.

  Furthermore, according to the above configuration, the fourth switching transistor is not necessary, and the number of transistors per pixel circuit can be reduced. As a result, high aperture ratio and high definition can be achieved.

  In the display device according to the present invention, it is preferable that instruction data for instructing the output state of each driving transistor sharing the source wiring to the source wiring is the driving transistor 1 sharing the source wiring. Further, there is provided instruction data supply means for supplying A (A is an integer of 2 or more) at a time, and the first switch transistor includes the instruction data output to the source wiring according to the scan signal. The instruction data corresponding to the driving transistor is selected and supplied to the driving transistor, thereby setting the display state of the electro-optic element A times in one frame period.

  According to the above configuration, it is possible to provide a display device that can perform gradation display by time-multiplexed gradation driving. Even if there is a difference between one frame period and the total length of the driving period corresponding to each instruction data, blanking is performed by controlling the control wiring provided in parallel with the gate wiring. The time multiplex gradation drive can be realized by filling the difference by the blanking period. Therefore, restrictions on the number of gate wirings, the configuration of the electro-optic element, and the like are removed, and the degree of freedom in designing the display device can be ensured.

  The display device according to the present invention is preferably configured to include the above instruction data supply means, wherein the blanking period is set after a specific instruction data display period.

  According to the above configuration, the ratio of the blanking period to one frame period is smaller than that of the time-multiplexed grayscale driving methods of Patent Document 2 and Patent Document 4 that require a plurality of blanking periods in one frame period. That is, the ratio of the display period to one frame period can be increased. As a result, when the luminance in one frame is the same as that of the conventional time-multiplexed gradation driving method, the luminance of the display period in one frame can be set relatively low by the amount of the display period, and the electro-optic The lifetime of the element can be extended. Further, if the luminance in the display period in one frame is made the same as that in the conventional time-multiplexed gradation driving method, the luminance in the entire one frame can be made relatively high. Therefore, according to the above configuration, the third object can be achieved in addition to the first object.

In the display device according to the present invention, in order to solve the above-described problem, the instruction data supply means includes the instruction data having the same number corresponding to a plurality of different gate wirings among the instruction data at a constant cycle. To supply
When the weights of the A pieces of instruction data are W1 to Wa (W1 to Wa are integers of 1 or more), the weights W1 to Wa _-1 are
MOD (W1, A) ≠ 0
MOD (W1 + W2, A) ≠ 0
MOD (W1 + W2, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ 0
MOD (W1 + W2 + W3, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ MOD (W1 + W2, A)
...
MOD (W1 +... + W _a-1 , A) ≠ MOD (W1 +... + W _a-2 , A)
(However, MOD (x, y) indicates the remainder when x is divided by y)
And the weight Wa is
Wa = (number of gradations to be displayed) − (W1 +... + W _a−1 ) −1
When the number of gate wirings is n, the time Wb for stopping the current flowing from the driving transistor to the electro-optical element is
Wb = n × A− (W1 +... + Wa) × m
(M is an integer greater than or equal to 1 and not a multiple of A)
It is characterized by being set to be.

According to the above configuration, when the number of instruction data is A (A is an integer of 2 or more) and the weight of each instruction data B1 to Ba is W1 to Wa (W1 to Wa is an integer of 1 or more),
MOD (W1, A) ≠ 0
MOD (W1 + W2, A) ≠ 0
MOD (W1 + W2, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ 0
MOD (W1 + W2 + W3, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ MOD (W1 + W2, A)
...
MOD (W1 +... + W _a-1 , A) ≠ MOD (W1 +... + W _a-2 , A)
The weights W1 to Wa _-1 of the instruction data B1 to Ba are determined so that ## EQU2 ## where MOD (x, y) indicates the remainder obtained by dividing x by y.

Wa is Wa = (the number of gradations to be displayed) − (W1 +... + W _a−1 ) −1.
Decide. At this time, when the number of gate wirings is n, the time Wb for stopping the current flowing from the driving transistor to the electro-optical element is:
Wb = n × A− (W1 +... + Wa) × m
(M is an integer greater than or equal to 1 and not an integer multiple of A).

Then, the timing for giving the instruction data B1 to Ba of the pixels corresponding to the first gate wiring to the source wiring Gi is set to time 0 to t1, W1 × m × t1 to (W1 × m + 1) × t1,. W1 +... + W _a-1 ) × m × t1 to ((W1 +... + W _a-1 ) × m + 1) × t1.

Then, the timing for supplying the instruction data B1 to Ba of the pixel corresponding to the next gate wiring Gi _{+ 1} is delayed by time A × t1 from the above timing.

  Thus, it is possible to drive the instruction data supplied to a plurality of driving transistors sharing one source wiring so that the timings do not overlap each other (that is, time-multiplexed gradation driving is possible).

  Further, the second switching transistor is controlled over time (W1 +... + Wa) × m × t1 to n × A × t1, and the current flowing from the driving transistor to the electro-optical element is stopped.

As a result,
(Number of gate wirings n) × (Number of instruction data A)
And the number of display gradations (W1 +... + Wa + 1) × m
Thus, a display device with a reduced blanking period ratio can be realized in which the length of the blanking period in one frame period is Wb × t1.

  Thus, compared with the time-multiplexed grayscale driving methods of Patent Document 2 and Patent Document 4 that require a plurality of blanking periods in one frame period, the ratio of the blanking period in one frame period is small. The ratio of the display period in one frame period can be increased. As a result, when the luminance in one frame is the same as that of the conventional time-multiplexed gradation driving method, the luminance of the display period in one frame can be set relatively low by the amount of the display period, and the electro-optic The lifetime of the element can be extended. Further, if the luminance in the display period in one frame is made the same as that in the conventional time-multiplexed gradation driving method, the luminance in the entire one frame can be made relatively high. Therefore, according to the above configuration, the third object can be achieved.

  In order to solve the above problems, a driving method according to the present invention includes a plurality of gate wirings to which scanning signals are supplied, at least one source wiring to which data for display is supplied, and the plurality of gate wirings. And the at least one source wiring, and the conduction is controlled by the electro-optic element driven by the current supplied from the power source and the scanning signal supplied to the gate wiring. A first switch transistor that outputs data from a source wiring, and is interposed between the power source and the electro-optical element, and supplies current from the power source to the electro-optical element. A driving transistor controlled according to data output from the gate, and a gate terminal and a source terminal or a drain terminal of the driving transistor And a second switching transistor disposed between the first switching transistor and the second switching transistor in a period in which the second switching transistor is in the ON state after the second switching transistor is in the ON state. The variation of the threshold voltage of the driving transistor is compensated by performing blanking for erasing the display of the electro-optical element.

  According to the above method, when the second switching transistor is turned on, the gate terminal of the driving transistor is short-circuited with the source terminal or the drain terminal. Next, blanking for erasing the display of the electro-optic element is performed during a period in which the second switching transistor is in an ON state, whereby a potential difference ((a) between the gate terminal and the source terminal or the drain terminal of the driving transistor). The gate-source potential or the gate-drain potential) can be made equal to the threshold potential to compensate for variations in the threshold voltage of the driving transistor. As a result, luminance unevenness due to variation in threshold potential of the driving transistor is compensated, and display without uneven luminance can be performed.

  In the above method, since the variation in the threshold potential of the driving transistor is compensated for in the blanking period, which is the non-display period, the entire selection period can be used as the display period, and the selection period can be shortened. As a result, driving transistors corresponding to more gate wirings can be driven by one scanning signal supply means (gate driver).

  As described above, according to the above method, the first object can be achieved.

  In order to solve the above problems, a driving method according to the present invention includes a plurality of gate wirings to which scanning signals are supplied, at least one source wiring to which data for display is supplied, and the plurality of gate wirings. And the at least one source wiring, and the conduction is controlled by the electro-optic element driven by the current supplied from the power source and the scanning signal supplied to the gate wiring. A first switch transistor that outputs data from a source wiring, and is interposed between the power source and the electro-optical element, and supplies current from the power source to the electro-optical element. And a driving transistor that controls the data according to data output from the display device, the driving method comprising: A data (A is an integer of 2 or more) is supplied to each of the driving transistors sharing the source wiring, and instruction data for indicating the output state of each driving transistor sharing the source wiring is supplied to the gate wiring. By supplying a scanning signal to the first switching transistor, the first switching transistor is caused to select instruction data corresponding to the driving transistor from the instruction data output to the source wiring and is supplied to the driving transistor. Thereby, the display state of the electro-optic element is set A times in one frame period, and after the display period of specific instruction data among the instruction data, it is blocked by the control wiring provided in parallel with the gate wiring. Blanking is performed by controlling the ranking means to erase the display of the electro-optic element.

  According to the above configuration, blanking can be performed by controlling the blanking means by the control wiring, so that the blanking signal for erasing the electro-optical element is not supplied from the driving circuit to the source wiring. It is also possible to realize a configuration for performing the above. In such a configuration, since all instruction data can be used for display, the weight of the instruction data having the largest weight among the instruction data can be reduced. As a result, the generation of a moving image false contour can be suppressed. Therefore, according to the above method, the second object can be achieved.

  According to the above method, the ratio of the display period to one frame period can be increased. As a result, when the luminance in one frame is the same as that of the conventional time-multiplexed gradation driving method, the luminance of the display period in one frame can be set relatively low by the amount of the display period, and the electro-optic The lifetime of the element can be extended. Further, if the luminance in the display period in one frame is made the same as that in the conventional time-multiplexed gradation driving method, the luminance in the entire one frame can be made relatively high. Therefore, according to the above method, the third object can be achieved.

  As described above, according to the present invention, it is possible to provide a display device and a driving method thereof that can compensate for luminance unevenness due to variations in threshold voltages of driving transistors without increasing the selection period. .

  Further, according to the present invention, it is possible to realize a configuration in which blanking is performed without supplying a blanking signal to the source wiring. In such a configuration, all of the instruction data can be used for display, and the weight is the highest. It is possible to provide a display device capable of reducing the weight of heavy instruction data and suppressing the generation of a moving image false contour.

  In addition, according to the present invention, there is provided a display device and a driving method capable of increasing the ratio of the display period existing in one frame period and, as a result, extending the life of the electro-optic element and improving the luminance. Can be provided.

  Embodiments of the present invention will be described below as Embodiments 1 to 4 based on FIGS.

  The driving transistor and the switching transistor (switching element) used in the present invention can be composed of a low-temperature polysilicon TFT, a CG (Continuous Grain) silicon TFT, or the like. In the following first to fourth embodiments, a CG silicon TFT is used as a driving transistor or a switching transistor.

  Here, the configuration of the CG silicon TFT is disclosed in Non-Patent Document 1, for example. A manufacturing process of the CG silicon TFT is disclosed in Non-Patent Document 2, for example. That is, since the structure of CG silicon TFT and its manufacturing process are both known, detailed description thereof is omitted here.

  The configuration of the organic EL element, which is an electro-optical element used in the present embodiment, is also publicly known and disclosed in Non-Patent Document 3, for example, and detailed description thereof is omitted here.

[Embodiment 1]
A display device according to an embodiment of the present invention will be described below with reference to FIGS.

  As shown in FIG. 2, the display device 1 according to this embodiment includes a plurality of pixel circuits Aij (i = 1, 2,..., N; j = 1, 2,..., M; m arranged in a matrix. And n are integers of 2 or more), a plurality of gate wirings Gi connected to the pixel circuit Aij, a plurality of control wirings Ri provided in parallel with the gate wiring Gi and connected to the pixel circuit Aij, and A plurality of source lines Sj arranged so as to intersect the gate line Gi and the control line Ri and connected to the pixel circuit Aij, gate driver circuits 3a and 3b for driving the gate line Gi, and the source line Sj are driven. It has a source driver circuit (instruction data supply means) 2 and a control circuit (not shown). In this case, the display element portion of the display device 1 is formed by the pixel circuit Aij, and a drive circuit for driving the display element portion (display device) is configured by the gate driver circuits 3a and 3b, the source driver circuit 2, and the control circuit. ing.

  Each pixel circuit Aij is arranged corresponding to a region where the source line Sj and the gate line Gi intersect. The pixel circuit Aij is formed on a substrate such as a glass substrate or a silicon substrate (not shown).

  The source driver circuit 2 and the gate driver circuits 3a and 3b use CG silicon TFTs on the same substrate as the substrate on which the pixel circuit Aij is formed in order to reduce the size of the entire display device 1 and reduce the manufacturing cost. , Preferably all or part of it is formed. However, although the above effect cannot be obtained, part or all of the source driver circuit 2 and the gate driver circuits 3a and 3b are formed as an IC (integrated circuit) on a substrate different from the substrate on which the pixel circuit Aij is formed. However, it may be externally connected to the pixel circuit Aij. For example, COG (Chip On Grass) in which an IC is directly bonded to a glass substrate may be used. Further, an IC can be arranged on a flexible substrate and bonded to an input / output terminal on the substrate on which the pixel circuit Aij is formed.

  The source driver circuit 2 includes an m-bit shift register 4 composed of m cascaded registers (not shown), an m-bit register 5, an m-bit latch circuit 6, and one source line Sj. It is composed of m analog switch circuits 7 provided one by one.

  The source driver circuit 2 receives a start pulse SP from the control circuit to the head register of the m-bit shift register 4. The start pulse SP is transferred in the shift register 4 in accordance with the clock clk supplied from the control circuit, and at the same time, is output as a timing pulse SSP from each output stage of the shift register 4 to the register 5. The m-bit register 5 is composed of m flip-flops corresponding to the source line Sj. The register 5 holds 1-bit digital image data Dx input from the control circuit in each of the m flip-flops according to the corresponding timing pulse SSP sent from the shift register 4. The register 5 transfers the total m-bit digital image data Dx to the latch circuit 6 at a timing synchronized with the latch pulse LP. The latch circuit 6 outputs the digital image data Dx to the analog switch circuit 7. The analog switch circuit 7 selects a potential corresponding to the digital image data Dx and outputs it to the source line Sj as instruction data for display. The analog switch circuit 7 is a potential (ON potential) that turns on a transistor 11 (see FIG. 1) to be described later in the pixel circuit Aij in accordance with whether the digital image data Dx is “High” or “Low”. , And a potential (OFF potential) for turning off the transistor 11 (non-conducting state) is selected and output to the source line Sj as instruction data. This instruction data is data for instructing an output state of each pixel circuit Aij sharing the source line Sj (an output state of a driving transistor 11 or 16 described later). As will be described later, time-division gradation display is performed. In the method, A (A is an integer of 2 or more) is prepared for each pixel circuit Aij.

  Further, the gate driver circuit 3a has an unstable output during the period when the address Add and the control signal OE (address Add are updated) input from the control circuit. During this period, the selection voltage is not unnecessarily output to the gate line Gi. Signal) is decoded by a decoder circuit (not shown) built in the gate driver circuit 3a. The gate driver circuit 3a outputs a scanning signal Gi necessary for the gate wiring Gi to the gate wiring Gi corresponding to the decoded address signal Add.

  In the gate driver circuit 3b, the input control signal YI (start pulse for controlling the control wirings Ri, Pi, etc.) is generated in the shift register circuit built in the gate driver circuit 3b according to the clock yck supplied from the control circuit. And is output from the shift register circuit to the control wiring Ri as a control signal Ri necessary for the control wiring Ri at a corresponding timing. The gate driver circuit 3b outputs a control potential Pi at a predetermined level to the control wiring Pi as will be described later.

  The control circuit outputs the start pulse SP, the clock clk, the latch pulse LP, and the digital image data Dx to the source driver circuit 2. The control circuit outputs the address signal Add and the control signal OE to the gate driver circuit 3a, and outputs the clock yck and the control signal YI to the gate driver circuit 3b.

  The configuration of the pixel circuit Aij of this embodiment will be described based on the circuit diagram of FIG.

  As shown in FIG. 1, the pixel circuit Aij is arranged in a peripheral region at a position where the source wiring Sj and the gate wiring Gi intersect, and is a driving transistor 11 that is a p-type TFT and a switch that is an n-type TFT. A switching transistor (first switching transistor) 13, a switching transistor (third switching transistor) 12, which is a p-type TFT, and an organic EL element (electro-optical element) EL1.

  Specifically, a power supply wiring Vp (predetermined potential wiring) to which a predetermined power supply voltage Vp is applied from a DC power supply (not shown) and a predetermined common potential (for example, a ground potential) having a predetermined potential difference with respect to the power supply voltage Vp. Between the applied common wiring Vcom, the driving transistor 11, the switching transistor 12, and the organic EL element EL1 are connected in series in this order.

  The organic EL element EL1 as an electro-optical element is disposed in the vicinity of the intersection of the source line Sj and the gate line Gi. Although not shown, the organic EL element EL1 includes a transparent electrode made of ITO (indium tin oxide) or the like as its anode, and a common electrode (Ca / Al alloy or the like) connected to the common wiring Vcom as its cathode. The organic EL element EL1 is driven by a current supplied through a driving transistor 11 from a power source (not shown).

  The drive transistor 11 has a source terminal connected to the power supply line Vp and a drain terminal connected to the source terminal of the switch transistor 12. The driving transistor 11 is interposed between the DC power supply and the organic EL element EL1, and the organic EL element EL1 is supplied from the DC power supply in accordance with instruction data (a binary potential of ON potential or OFF potential) supplied to the gate terminal thereof. It controls the supply of current to the. More specifically, when the ON potential is supplied to the gate terminal of the driving transistor 11, the driving transistor 11 is turned on and supplies the current from the DC power source to the organic EL element EL1. On the other hand, when the OFF potential is supplied to the gate terminal of the driving transistor 11, the driving transistor 11 is turned off and stops supplying current from the DC power source to the organic EL element EL1. As will be described later, the instruction data is output from the switching transistor 13 and held in the capacitor C2, and is supplied from the capacitor C2 to the gate terminal of the driving transistor 11.

  The switching transistor 12 inserted between the driving transistor 11 and the organic EL element EL1 is controlled so as to be in an OFF state (non-conducting state) for a certain period by a control signal Ri supplied from the control wiring Ri, As a result, the current flowing from the driving transistor 11 to the organic EL element EL1 is stopped only during the above period. Thereby, the operation (blanking) of erasing the display of the organic EL element EL1 (that is, bringing the organic EL element EL1 into a non-light emitting state) is performed during the above period. Further, the switching transistor 12 shifts from an ON state to an OFF state during a period in which a switching transistor 14 described later is in an ON state in order to compensate for variations in threshold voltage of the driving transistor 11. .

  In this case, the blanking means is configured by the switching transistor 12 and the control wiring Ri. As blanking means, instead of these, there is means for giving a signal (blanking signal) for setting the organic EL element EL1 in an erased state to the pixel circuit Aij for a certain period, for example, blanking means in Patent Document 3. .

  Further, a switching transistor (threshold voltage compensation means, second switching transistor) 14 which is an n-type TFT is disposed between the gate terminal and the drain terminal (output terminal) of the driving transistor 11. In other words, the switching transistor 14 is interposed on the wiring connecting the gate terminal and the drain terminal of the driving transistor 11.

  The switching transistor 14 has a blanking period (blanking period), that is, a period in which the current flowing from the driving transistor 11 to the organic EL element EL1 is stopped (a period in which the switching transistor 12 is in the OFF state). ) Is turned ON. As a result, the gate terminal and the drain terminal of the driving transistor 11 are short-circuited during the blanking period, and as a result, variations in the threshold voltage of the driving transistor 11 are compensated. The principle of compensating for variations in threshold voltage will be described later. On the other hand, during the period in which the switching transistor 12 is in the ON state, the transistor 14 is in the OFF state except for a predetermined time immediately before the blanking period. The switching transistor 14 has a gate terminal connected to the control wiring Pi, and is controlled by a control potential Pi supplied to the control wiring Pi. Although not shown, the control wiring Pi is connected to the gate driver circuit 3b shown in FIG. Note that the threshold voltage compensation means is capable of conducting the gate terminal and the output terminal (source terminal or drain terminal) of the driving transistor outside the driving transistor during the blanking period. It is not limited to the switching transistor 14.

  Further, a capacitor (first capacitor) C1 and a capacitor (second capacitor) C2 are connected to the gate terminal of the driving transistor 11. These capacitors C1 and C2 have a function as potential difference holding means for holding a potential difference between the gate terminal and the source terminal of the driving transistor 11.

  One terminal of the capacitor C1 is connected to the gate terminal of the driving transistor 11, and the other terminal is connected to the source terminal of the driving transistor 11, that is, the power supply wiring Vp.

  One terminal of the capacitor C <b> 2 is connected to the gate terminal of the driving transistor 11, and the other terminal is connected to the drain terminal of the switching transistor 13. The capacitor C2 holds instruction data output from the drain terminal of the switching transistor 13 and supplies it to the gate terminal of the driving transistor 11.

  The source terminal of the switch transistor 13 is connected to the source line Sj. The gate terminal of the switching transistor 13 is connected to the gate wiring Gi. The conduction of the switch transistor 13 is controlled by the scanning signal Gi supplied to the gate wiring Gi. The switching transistor 13 outputs instruction data from the source line Sj to the capacitor C2 and holds it in the capacitor C2 when conducting. Thereby, the instruction data for instructing the display state of the organic EL element EL1 (the output state of the driving transistor 11) can be written in the pixel circuit Aij. In the pixel circuit according to the present embodiment, the time division gradation display is realized by writing the instruction data a plurality of times in one frame period. When time division gradation display is not performed, the instruction data may be written only once in one frame period. Further, the switching transistor 13 selects instruction data corresponding to the driving transistor 11 from the instruction data output to the source line Sj in accordance with the scanning signal Gi and supplies it to the driving transistor 11. .

  The other terminal of the capacitor C2 (the terminal connected to the drain terminal of the switch transistor 13) is also connected to the drain terminal of the switch transistor (fourth switch transistor) 15 which is an n-type TFT. Yes. The source terminal of the switching transistor 15 is connected to the power supply wiring Vp. The switching transistor 15 has its gate terminal connected to the control wiring Pi, and is controlled by the control potential Pi supplied to the control wiring Pi. The switch transistor 15 is for applying a predetermined potential (power supply voltage Vp) to the other terminal of the capacitor C2. The switch transistor 15 connects the other terminal of the capacitor C2 (the terminal connected to the drain terminal of the switch transistor 13) to the power supply wiring (predetermined potential wiring) Vp while the switch transistor 14 is in the ON state. To connect to.

The drive timing of the pixel circuit Aij is shown in FIG. The three waveforms shown in the upper part of FIG. 3 are, in order from the top, 1) a scanning signal G2 supplied to the pixel circuit A2j via the gate wiring G2, and 2) supplied to the pixel circuit A2j via the control wiring P2. Control potential P2, 3) Each waveform of the control signal R2 supplied to the pixel circuit A2j via the control wiring R2. 3 indicates the type of instruction data supplied to the source wiring Sj by a bit number (described later). The three waveforms shown in the lower part of FIG. 3 are, in order from the top, 4) a scanning signal G3 supplied to the pixel circuit A3j via the gate wiring G2, and 5) supplied to the pixel circuit A3j via the control wiring P3. Control potential P3, 6) Each waveform of the control signal R3 supplied to the pixel circuit A3j via the control wiring R3. In this case, the instruction data includes eight types of instruction data B1 to B8 (B is omitted in FIG. 3) as in driving condition examples 1 and 2 described later. FIG. 3 shows a case where a time-multiplex gradation driving method described later is adopted. A period between broken lines in FIG. 3 corresponds to one unit period. In addition, the time axis indicated by the horizontal axis in FIG. 3 indicates t1 as a unit. This t1 corresponds to half of the length of the occupation period described later. (Note that the length of the selection period and the occupation period is the same)
Pixel A2j enters the blanking period from time 13t1. At time 13t1, the potential of the control wiring P2 (control potential P2) is set to High (GH), and the switching transistors 15 and 14 are turned on. When the switch transistor 15 is turned on, the power supply side terminal of the capacitor C1 (the terminal connected to the power supply wiring Vp) and the other terminal of the capacitor C2 (the one connected to the switch transistor 13). Terminal) is supplied with a power supply voltage Vp having a predetermined potential from the power supply wiring Vp. Further, when the switching transistor 14 is turned on, the gate terminal and the drain terminal of the driving transistor 11 are short-circuited. At this time, since the potential of the control wiring R2 (the potential of the control signal R2) is Low (GL), the switching transistor 12 is in the ON state. Therefore, the drain potential of the driving transistor 11 is lowered, and the gate potential of the driving transistor 11 becomes the ON potential.

Thereafter, at time 14t1, the potential of the control wiring R2 (the potential of the control signal R2) is set to High (GH), and the switching transistor 12 is turned off (at this time, the switching transistors 15 and 14 remain in the ON state). is there). As a result, the drain potential of the driving transistor 11 rises, and the gate-source potential of the driving transistor 11 changes from the ON state to the OFF state and reaches the threshold potential Vth. Therefore, the gate potential Vg of the driving transistor 11 is equal to the difference between the power supply voltage Vp and the threshold potential Vth of the driving transistor 11, that is,
Vg = Vp-Vth
It becomes. Therefore, the potential difference between both ends of the capacitors C1 and C2 becomes equal to the gate-source potential of the driving transistor 11, that is, the threshold potential Vth.

  At time 15t1, the potential of the control wiring P2 becomes Low (GL), and the switching transistors 15 and 14 are turned off. As a result, the potential difference Vp−Vg, that is, a charge corresponding to the threshold potential Vth is held at both ends of the capacitors C1 and C2, that is, a potential difference equal to the threshold potential Vth is held (the charge corresponding to the threshold potential Vth is held). Retained).

  Thereafter, the blanking period ends at time 16t1. At time 16t1, the potential of the control wiring R2 is set to Low (GL), and the switching transistor 12 is turned on. Further, the potential of the gate wiring G2 is set to High (GH), and the switching transistor 13 is turned on. As a result, the other terminal of the capacitor C2 (the terminal connected to the switching transistor 13) is short-circuited with the source line Sj.

  At this time, since the instruction data (instruction data B1 corresponding to bit number 7 described later) is supplied to the source wiring Sj, the other terminal of the capacitor C2 (the terminal connected to the switching transistor 13). The potential is a potential (VH or VL) corresponding to the instruction data (instruction data B1 corresponding to bit number 7 described later). For this reason, the gate potential of the driving transistor 11 changes corresponding to the instruction data (instruction data B1 corresponding to bit number 7 described later).

  At this time, since the potential difference equal to the threshold voltage Vth of the driving transistor 11 is held at both ends of the capacitors C1 and C2, the gate potential of the driving transistor 11 does not depend on the threshold potential Vth, and the instruction data Is a potential changed from the threshold potential (power supply potential Vp−Vth) by a potential corresponding to. That is, the gate-source potential of the driving transistor 11 becomes a potential changed from the threshold potential Vth by a potential corresponding to the instruction data without depending on the threshold potential Vth. Thereby, the current Id flowing through the driving transistor 11 becomes a current value corresponding to the instruction data regardless of the threshold potential Vth. Therefore, the variation in the current flowing from the driving transistor 11 to the organic EL element EL1 due to the variation in the threshold voltage Vth of the driving transistor 11 is compensated. At this time, if the switching transistor 12 is in the ON state, the current Id flows from the driving transistor 11 to the organic EL element EL1. Therefore, the luminance of the organic EL element EL1 is a luminance in which variation due to variation in the threshold potential Vth of the driving transistor 11 is compensated. That is, the organic EL element EL1 is in a display state corresponding to the instruction data without depending on the threshold potential Vth of the driving transistor 11. As a result, display without unevenness in luminance can be performed.

  After time 17t1, the potential of the gate wiring G2 is set to Low (GL) and the switching transistor 13 is turned off, so that the other terminal of the capacitor C2 (the terminal connected to the switching transistor 13) is connected. The potential applied between time 16t1 and time 17t1 (potential corresponding to the instruction data) is held.

  As a result, the current Id flowing through the driving transistor 11 has a current value corresponding to the instruction data (instruction data B1 corresponding to bit number 7 described later) regardless of the threshold potential Vth. At this time, since the switching transistor 12 is in the ON state, the current Id flows from the driving transistor 11 to the organic EL element EL1. As a result, a display with no unevenness of brightness corresponding to the instruction data is maintained.

  Note that, after time 17t1, the instruction data sent to the source wiring Sj is changed to instruction data corresponding to the other gate wiring, but the switching transistor 13 corresponding to the gate wiring G2 is in the OFF state, so The transistor 11 and the like are not affected by the change of the instruction data.

  In the above configuration, the charge for compensating the variation in the threshold potential Vth of the driving transistor 11 is accumulated in the capacitors (C1 and C2) because the switching transistor 14 is ON (period from time 13t1 to time 15t1). ) Only once per frame period. However, the charge for compensating for the variation in the threshold potential Vth of the driving transistor 11 is retained even when the transistor 14 is turned off and a voltage is applied to the capacitor from the source line Sj. Therefore, if this charge is updated once in one frame period, the variation in the threshold potential Vth of the driving transistor 11 can be compensated as long as the transistor 14 is OFF no matter how many times the instruction data is given in one frame period. .

  FIG. 4 shows the result of simulating the current Id flowing through the driving transistor 11 and the gate potential Vg and drain potential Vd of the driving transistor 11 during the blanking period.

  In FIG. 4, the current (Id) and potential (Vg, Vd) marked with (1) and (2) are the results of simulation using the conditions (1) and (2) shown in the following table, respectively.

  Condition (1) was that the mobility of the driving transistor 11 was the best and the threshold potential Vth was the best. Condition (2) was that the mobility of the driving transistor 11 was worst and the threshold potential Vth was worst. In this simulation, the power supply voltage Vp = 13V. Further, the control potential P2 was set to 16 V (corresponding to VH in FIG. 3) during the period from 2628 to 2752 μs (corresponding to the period from time 13t1 to time 15t1 in FIG. 3). Further, the potential of the control signal R2 was set to 16V (corresponding to VH in FIG. 3) during a period of 2632 to 2756 μs (corresponding to the time 14t1 to the time 16t1 in FIG. 3).

  As can be seen from FIG. 4, the current Id flowing through the driving transistor 11 is substantially zero during the blanking period (time 2628 to 2752 μs). In addition, the gate potential Vg of the driving transistor 11 has a value corresponding to the threshold potential Vth.

  Therefore, after the blanking period, the gate wiring Gi is set to High (GH), and a desired voltage (instruction data potential) is input from the source wiring Sj to the other terminal of the capacitor C2 through the switching transistor 13.

  At this time, the potential Sj (potential of instruction data) of the source wiring Sj is changed, and the result of simulating the current Id flowing through the driving transistor 11 under each of the above conditions (1) and (2) is shown in FIG. In this simulation, the potential of the gate line G2 (the potential of the scanning signal G2) is changed immediately after the potential Sj of the source line Sj is changed in steps of 1V from 11V to 4V and the potential Sj of the source line Sj is changed. The voltage was changed from 0V to 16V.

  As can be seen from FIG. 5, the current Id flowing through the driving transistor 11 increases as the potential Sj of the source line Sj is lowered from the power supply potential Vp (13 V).

  Further, the current Id flowing through the driving transistor 11 also changes depending on the condition (1) and the condition (2). Therefore, if the driving transistor 11 under the condition (1) and the driving transistor 11 under the condition (2) are mixed in one display device 1, the current Id also varies. The variation in the current Id depends on the variation in mobility of the driving transistor 11.

  Therefore, the result of simulating the current Id flowing through the driving transistor 11 under the condition (3) shown in the following table matches the result of simulation under the condition (1). Further, the result of simulating the current Id flowing through the driving transistor 11 under the condition (4) shown in the following table coincides with the result of simulation under the condition (2).

  The difference in mobility between the driving transistors 11 is relatively small between the driving transistors 11 of the adjacent pixel circuits, and is relatively large between the driving transistors 11 of the pixel circuits that are separated from each other.

  Note that currents Id (1) and Id (2) flowing through the driving transistor 11 illustrated in FIG. 5 correspond to the best value and the worst value in the display device 1.

  Since the mobility is not different between the driving transistors 11 in the adjacent pixel circuits as between the conditions (1) and (2), the driving transistors 11 shown in FIG. 5 flow between the adjacent pixel circuits. As the difference between the current Id (1) and the current Id (2), the current Id flowing through the driving transistor 11 (current flowing through the organic EL element EL1) is not different. Therefore, the difference in luminance between adjacent pixels due to the difference in current Id is not so noticeable.

  Therefore, the current Id flowing through the driving transistor 11, that is, the current flowing through the organic EL element EL1, is determined by the potential of the source line Sj corresponding to the instruction data Bx, regardless of the threshold potential Vth.

  Therefore, the current flowing through the organic EL element EL1 can be controlled by the potential of the source line Sj corresponding to the instruction data Bx, regardless of the threshold potential Vth of the corresponding driving transistor 11. Therefore, even if the threshold potential Vth of the driving transistor 11 varies among the pixel circuits Aij, the luminance of the organic EL element EL1 can be made uniform throughout the display device 1.

  Further, if the potential supplied to the source wiring Sj is a binary value of High (VH) and Low (VL), a circuit for determining the voltage supplied to the source wiring Sj can be constituted by the analog switch circuit 7.

  As described above, the display device 1 according to the present embodiment can compensate for variations in the threshold potential Vth of the driving transistor 11 during the blanking period outside the driving period corresponding to the instruction data B1 to Ba. Therefore, it is not necessary to provide a period for compensating for variations in threshold voltage in each driving period corresponding to the instruction data B1 to Ba, and the entire driving period can be used as a display period. Therefore, the selection period can be shortened compared to the configuration of Patent Document 1. As a result, driving transistors corresponding to more gate wirings can be driven by one gate driver circuit 3a. Therefore, for example, a display device having a larger size can be driven by one scanning signal supply unit.

  Further, in the display device 1 according to the present embodiment, since the blanking operation can be performed by controlling the switching transistor 12 by the control wiring Ri, the blanking means described in Patent Document 3 (blanking). Unlike the means for supplying the ranking signal to the source wiring, blanking can be performed without supplying the blanking signal from the source driver circuit 2 to the source wiring Sj. As a result, since all the instruction data transferred from the control circuit to the source driver circuit 2 can be used for display, the weight of the instruction data having the largest weight among the instruction data can be reduced. As a result, the generation of a moving image false contour can be suppressed.

  Next, as a driving method of the display device 1 described above, a time-multiplex grayscale driving method capable of increasing the ratio of the display period existing in one frame period will be described.

  This driving method is an improvement over the conventional time-multiplexed gradation driving method for the purpose of realizing a time-multiplexed gradation driving method capable of increasing the proportion of display periods existing in one frame period.

In this driving method, A pieces of instruction data (A is an integer of 2 or more) are generated from image data signals of p bit gradation, that is, 2 ^p gradation, and each gate wiring is generated based on these A pieces of instruction data. Setting of the display state of the organic EL element EL1 on Gi, that is, writing of instruction data to the pixel circuit Aij on each gate line Gi is performed A times in one frame period. The display state of the organic EL element EL1 is set to one of an ON state and an OFF state. The set display state is maintained until the next setting or blanking is performed. Then, among the A periods (drive periods) maintained after the display state of the organic EL element EL1 is set, the p-bit gradation (depending on which period the organic EL element EL1 is set to the ON state) p is an integer of 2 or more).

  For this purpose, the analog switch circuit 7 (FIG. 2) supplies the instruction data to the source line Sj, one of the n pixel circuits Aij sharing the source line Sj (the driving transistor shown in FIG. 1). 11 (one of 11) is supplied by A (A is an integer of 2 or more), that is, a total of n × A.

  In this driving method, one frame period is equally divided into n. In the present specification, a period obtained by dividing one frame period into n equal parts is referred to as a “unit period”. Further, the period during which the display state of the organic EL element EL1 is set based on the same instruction data is set so that the gate lines Gi do not coincide with each other. For example, on the first gate line G1, if the period during which the display state of the organic EL element EL1 is set based on certain instruction data is part of the first unit period, the second gate line G2 Above, the period during which the display state of the organic EL element EL1 is set based on the instruction data is set to be a part of the unit period other than the first. The timing at which the display state of the organic EL element EL1 is set is set so as to be shifted by, for example, one unit period (by a selection period A) between adjacent gate wirings Gi.

  Further, each of n unit periods constituting one frame period is equally divided into A. In the present specification, a period obtained by equally dividing the n unit periods into A is referred to as an “occupation period”. In the 0th to (A-1) th occupation period, the setting of the display state of the organic EL element EL1 based on one instruction data corresponding to each is set on any one of the gate wirings Gi. That is, all of the 0th to (A-1) th occupation periods correspond to one of the instruction data. Here, the length of the occupation period in which the display state of the organic EL element EL1 is set is equal to the length of the selection period. This occupation period may be referred to as a “writing period”.

In proportion to the length of the display period corresponding to the instruction data, the magnitude (weight) of the influence of the display period on the average gradation (corresponding to the gradation felt by human eyes) in one frame period Becomes larger. The length of the display period corresponding to the instruction data is set in units of the length corresponding to one selection period. In this specification, a value representing the length of the display period corresponding to the instruction data in units of the length of one selection period is referred to as “bit length of instruction data”. Further, in this specification, the value representing the length of the display period corresponding to the instruction data in an integer ratio, that is, the value representing the length of the display period corresponding to the instruction data in the unit of the length of the shortest display period. Is referred to as “instruction data weight”. The weights of the A pieces of instruction data can be expressed in 2 ^p ways by a combination of the numbers.

  Further, in this driving method, within one frame period, there is a period (blanking period) in which the display of the organic EL element EL1 is erased (blanking) in addition to the A period (display period). A plurality of blanking periods may be provided within one frame period. However, in this driving method, only one blanking period exists within one frame period in order to increase the total sum of the display periods. The length of the blanking period (the time for stopping the current flowing from the driving transistor 11 to the organic EL element EL1) is equal to the difference between the total of the A display periods and one frame period. Note that the blanking period does not affect the average gradation in one frame period, so the weight is 0.

  Next, a method for setting the weight of the instruction data and the length of the blanking period in this driving method will be described in more detail. Here, among the A display periods, the instruction data corresponding to the first display period is the instruction data B1, the instruction data corresponding to the next display period is the instruction data B2, and further the instruction corresponding to the next display period. The data is designated as instruction data B3,..., And the instruction data corresponding to the Ath display period is designated as instruction data Ba. In this case, the blanking period is provided after the Ath display period.

In this driving method, when the weights of the A instruction data B1 to Ba are W1 to Wa (W1 to Wa are integers of 1 or more), the weights W1 to Wa _-1 of the instruction data B1 to Ba _{-1 are shown.} The
MOD (W1, A) ≠ 0
MOD (W1 + W2, A) ≠ 0
MOD (W1 + W2, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ 0
MOD (W1 + W2 + W3, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ MOD (W1 + W2, A)
...
MOD (W1 +... + W _a-1 , A) ≠ MOD (W1 +... + W _a-2 , A)
... (1)
(However, MOD (x, y) indicates the remainder obtained by dividing x by y, that is, the number of the occupation period).

That is, the weight _{W1~W a-1, MOD (W1} + W2, A), MOD (W1 + W2, A), MOD (W1 + W2 + W3, A), ···, MOD (W1 + ··· + W a-1, A), MOD (W1 +... + W _a-2 , A) is set so as not to be equal to each other and not equal to 0. Thereby, the writing period corresponding to the A pieces of instruction data B1 to Ba (occupation period of the first selection period included in the display period corresponding to each of the instruction data B1 to Ba) should not overlap each other. Can do. As a result, a time-multiplexed gradation driving method can be realized.

The weight W1~W _a-1 of each instruction data B1~B _a-1 is either actually any configuration, using a computer, the instruction data B1~B _a-1 weight W1～W _{a- It} can be understood by changing ₁ and examining whether the condition of the simultaneous equation (1) is satisfied.

Further, the weight Wa of the instruction data Ba is set to the gradation number G (= 2 ^p ) to be displayed.
W1 + W2 + ... + W _a-1 + Wa = G-1 (2)
Set to be. That is, the weight Wa of the instruction data Ba is
Wa = G− (W1 +... + W _a-1 ) −1
Set to be. Note that the weights W1 to Wa can represent all the numbers 0 to G-1 by their combination (the sum of 0 to A weights among them).

If the bit length of the instruction data B1 to Ba (the value of the length of the display period corresponding to the instruction data B1 to Ba expressed in units of the length of one selection period) is represented by L1 to La, L1 to L1 La is the weight W1-Wa,
L1 = k × W1
L2 = k × W2
...
La = k × Wa
(K is an integer greater than or equal to 1 and not a multiple of A)
Is set to satisfy the relationship.

At this time, the length Wb of the blanking period expressed in units of the selection period is equal to the number n of the gate wirings Gi.
Wb = n × A− (W1 +... + Wa) × k (3)
(K is an integer greater than or equal to 1 and not a multiple of A)
That is,
Wb = n * A- (G-1) * k
Set to be.

  The number of instruction data (the number of instruction data supplied to one pixel circuit Aij in one frame period) A and the weights of instruction data B1 to Ba so as to satisfy the simultaneous equations (1) and (2) W1 to Wa are set. Then, the length Wb of the blanking period can be shortened to, for example, the length corresponding to the minimum one of the weights W1 to Wa of the instruction data B1 to Ba. Therefore, the ratio of the blanking period to one frame period is smaller than that of the time-multiplexed gradation driving methods of Patent Document 2 and Patent Document 4 that require a plurality of blanking periods in one frame period, that is, 1 The ratio of the display period to the frame period can be increased. As a result, when the luminance of one frame is made the same as that of the conventional time-multiplexed gradation driving method, the luminance of the light emitting period in one frame can be set relatively low by the amount of the display period, and the organic EL The lifetime of the element EL1 can be extended. Further, if the luminance in the light emission period in one frame is made the same as that in the conventional time-multiplexed gradation driving method, the luminance in the whole frame can be made relatively high.

At this time, in order to suppress the occurrence of the moving image false contour, the number A of the instruction data is set to be one or more larger than the bit number p of the display gradation number G, that is, the following formula A> 1 + log ₂ G
In order to further suppress the occurrence of the moving image false contour, the following formula A ≧ 2 + log ₂ G
You may set so that it may satisfy | fill.

  Note that the driving method of the present invention is not limited to the pixel circuit Ai shown in FIG. 1 as long as it is a display device that can generate a blanking period by a control wiring without depending on the instruction data of the source wiring Sj. When the above driving method is applied to pixel circuits other than the pixel circuit Aij shown in FIG. 1, as a method for erasing (blanking) the display of the organic EL element EL1, a signal for setting the organic EL element EL1 in an erased state. A method of giving (blanking signal) to the organic EL element EL1 only for a certain period (for example, changing the voltage of the common electrode Vcom) may be used.

The integer k is a condition that the right side of the expression (3) is positive, that is,
k <n × A / (G−1) (4)
It is an integer that satisfies the following condition and does not become a multiple of A (however, a value that satisfies the simultaneous equation (1)). Further, when there are a plurality of integers satisfying inequality (4) and not a multiple of A, in order to minimize the length Wb of the blanking period, the maximum number is set to k. It is preferable.

In the above driving method, assuming that the length of the selection period is t1, timings (periods) for giving the instruction data B1 to Ba to the pixel circuit corresponding to the gate wiring Gi are time 0 to t1 and time W1 × k × t1 respectively. (W1 × k + 1) × t1,..., Time (W1 +... + W _a-1 ) × k × t1 to ((W1 +... + W _a-1 ) × k + 1) × t1. Further, as described above, the timing (period) for supplying the instruction data B1 to Ba of the pixel corresponding to the next gate wiring Gi _{+ 1} is set to a time corresponding to one unit period (in this case, the time A). X) (same as t1). Accordingly, it is possible to realize a driving method of supplying the instruction data B1 to Ba to all the pixel circuits sharing one source line Sj at a timing that does not overlap each other. That is, time-multiplexed gradation driving can be realized.

  In the above driving method, by providing a blanking period at least once in one frame period, the length of one frame period (in this case, equal to (number of gate lines n) × (number of instruction data A)), display period The difference Wb from the total sum (W1 +... + Wa) × k of the (gradation display period) length can be filled. In order to provide this blanking period, for example, the pixel circuit Aij is used, and the switching transistor 12 is turned off over time (W1 +... + Wa) × k × t1 to n × A × t1. The current flowing from the driving transistor 11 to the organic EL element EL1 may be stopped.

  Further, in the above driving method, since the blanking period provided in one frame period is set to one time, a plurality of blanking periods are performed in one frame period disclosed in Patent Document 2 (Japanese Patent Publication No. 9-511589). Therefore, the non-display period can be shortened as compared with the time-multiplexed gradation driving method.

  As described above, the number of instruction data A and the simultaneous data (1) and (2) are satisfied and the blanking period length Wb is minimized (or a relatively small value). By setting the weights W1 to Wa of the instruction data B1 to Ba, the blanking period length Wb occupying one frame period is set to, for example, the minimum unit time or less, and the ratio of the blanking period that is a non-display period is reduced. A display device can be realized.

  As a result, in the case where the display device as a whole has a luminance comparable to that of the conventional display device, the luminance of the light emission period within one frame can be set relatively low by the amount that the non-display period is reduced. Thereby, the lifetime of the organic EL element EL1 can be extended.

  Hereinafter, specific examples of the driving method will be described as driving condition examples 1 to 4.

(Driving condition example 1)
In this driving condition example, it is assumed that the screen size of the display device 1 is QVGA (320 × 240 pixels), and the QVGA is scanned in the longitudinal direction. Then, the number n of gate wirings Gi (denoted as “number of lines” in the drawing) is 320. Further, the display device 1 includes three pixel circuits corresponding to three colors for each pixel, and the display gradation number G of each color is 64 gradations (the bit number p of the display gradation number G is 6 bits). Shall. Further, in this example, in order to suppress the occurrence of the moving image false contour, the number A of instruction data (denoted as “data number” in the drawing) is a value that is two larger than the bit number p of the display gradation number G, that is, Eight. In this example, a memory for storing instruction data (A instruction data) for one unit period provided in the control circuit is an 8-bit memory.

Under this condition, using a computer, the weights W1 to W _a-1 of the instruction data B1 to B _a-1 are changed to check whether the simultaneous equations (1) are satisfied, and the simultaneous equations (1 ) Satisfying the weights W1 to W _a-1 . Further, the weight of the instruction data Ba is determined so as to satisfy the formula (2).

  An example of conditions obtained as a result of such weight determination (program) is shown in FIG.

  FIG. 6 shows the bit number, weight, display period length, and bit length (= display period length + blanking period length) for the instruction data B1 to B8.

  Bit numbers are assigned to the instruction data B1 to B8 as 1, 2,... As a result, instruction data B1 is bit number 7, instruction data B2 is bit 8, instruction data B3 is bit number 1, instruction data B4 is bit number 3, instruction data B5 is bit number 4, instruction data B6 is bit number 2, Instruction data B7 corresponds to bit number 5, and instruction data B8 corresponds to bit number 6. Each bit number corresponds to the number of each bit in the 8-digit bit string (how many bits are counted from the least significant bit side). In this case, the weights of the instruction data (bits) of bit numbers 1 to 8 are 1, 2, 4,. In this case, the bit numbers corresponding to the instruction data B1 to B8 are 7, 8, 1, 3, 4, 2, 5, 6, and are not arranged in order from the bit number 1. Thus, it is easier to satisfy the simultaneous equation (1) if they are not arranged in order from bit number 1. A blanking period is provided after the display period of the last bit number 6. In FIG. 6, the bit weight corresponding to the display period in which the blanking period is finally provided is indicated with “+ B”. The length of the blanking period (abbreviated as “B length” in the drawing) is obtained by equation (3).

In this case, as a result of performing the weight determination (program) as described above, the weights of the instruction data (bits) B1 to B7 of the respective bit numbers are 12, 13, 1, 4, 7, 2, 12. Is set to
In this example, the value of the left side in the simultaneous equation (1) is
MOD (W1, A) = MOD (12, 8) = 4
MOD (W1 + W2, A) = MOD (25, 8) = 1
MOD (W1 + W2 + W3, A) = MOD (26,8) = 2
MOD (W1 + W2 + W3 + W4, A) = MOD (30,8) = 6
MOD (W1 + W2 + W3 + W4 + W5, A) = MOD (37,8) = 5
MOD (W1 + W2 + W3 + W4 + W5 + W6, A) = MOD (39,8) = 7
MOD (W1 + W2 + W3 + W4 + W5 + W6 + W7, A) = MOD (51,8) = 3
It becomes. Therefore, the simultaneous equation (1) is satisfied.

The sum of the weights W1 to W8 of the instruction data B1 to B8 (bits of bit numbers 1 to 8) is set to be 63. Therefore, the weight of the last instruction data B8 (bit of bit number 6) satisfies the equation (2), that is,
W1 + W2 + ... + W8 = 63
It is set to become.

The integer k is the number of gate lines n (= 320), the number of instruction data A (= 8), and the number of gradations G (= 64) to be displayed.
k <n × A / (G−1) (4)
Satisfy, that is,
k <320 × 8/63
It is an integer that satisfies the above and is not a multiple of A (= 8). Further, k is an integer that satisfies this inequality, and is preferably a maximum number that is not a multiple of A in order to minimize the length Wb of the blanking period. However, when k is a prime factor of A, the simultaneous equation (1) may not be satisfied. If k is a multiple of A ± 1, it satisfies the simultaneous equation (1) and can be used without any problem. In this case, the maximum number that satisfies the inequality (4) and does not become a multiple of A (= 8) is 39, which satisfies the simultaneous equation (1). Therefore, in this case, k = 39.

The blanking period length Wb can be calculated from the equation (3). That is, if k = 39, from the above equation (3),
Wb = 320 × 8−63 × 39 = 103
It becomes.

  Further, in FIG. 6, the scanning condition satisfying the simultaneous equation (1) is a condition that “the writing periods corresponding to the respective instruction data B1 to B8 do not overlap each other” (in order to realize the time-multiplex gradation driving method). (Requirement requirement) is schematically shown.

  Here, the vertical axis indicates the instruction data number, and the horizontal axis indicates the bit number, the bit weight, the length of the bit display period, and the occupation period number. In FIG. 6, black circles indicate which occupation period numbers correspond to the respective instruction data B1 to B8 or blanking periods.

When the occupation period numbers of the instruction data B1 to Ba are N1 to Na, these are:
N1 = 0
N2 = MOD (W1, A)
N3 = MOD (W1 + W2, A)
...
Na = MOD (W1 +... + W _a-1 , A)
It can ask for. The result is shown in FIG.

It can be seen from FIG. 6 that the occupation periods of the instruction data B1 to B8 (bit number 7 to bit number 6) do not overlap each other. In addition, the value representing the total length of one frame period in units of the selection period (denoted as “total” in the drawing) is
One frame period = 320 × 8 selection period = 2560 selection period. By using the above driving method, a value representing the length of the display period in one frame period (the total length of A driving periods included in one frame period) with the selection period as a unit (in the drawing, simply “ Display period ”)
Display period = 39 × 63 selection period = 2457 selection period. The remaining 103 selection periods are the blanking period length Wb.

At this time, the ratio of blanking period to one frame period is ratio of blanking period = 103/2560 = about 4%
It becomes. Therefore, it can be seen that if the above driving method is used, the ratio of the blanking period to one frame period can be made sufficiently small.

(Driving condition example 2)
This drive condition example is the same as the drive condition example 1 except that the number n of gate wirings is changed to n = 8 so that the drive timing is easy to illustrate in the drive condition example 1. Also in this example, the memory for storing instruction data (A instruction data) for one unit period provided in the control circuit is an 8-bit memory.

  In this driving condition example, the number of instruction data A and the number of display gradations G are the same as in driving condition example 1, and therefore the weight of each instruction data is set to the same weight as in driving condition example 1.

On the other hand, in this case, the integer k is the inequality (4), that is,
k <8 × 8/63
It is an integer that satisfies the above and is not a multiple of A (= 8). Therefore, in this case, k is set to k = 1 unlike the driving condition example 1.

  FIG. 7 shows the scanning conditions in this example in the same manner as in FIG.

In this case, the value representing the total length of one frame period in units of the selection period is
One frame period = 8 × 8 selection period = 64 selection periods. A value in which the length of the display period in one frame period is expressed with the selection period as a unit is display period = 1 × 63 selection period = 63 selection period. At this time, the ratio of the blanking period to one frame period is the ratio of the blanking period = (64−63) /63=1.6%.
It becomes.

  In the above driving method, the length of the blanking period is only one selection period per one frame period. Therefore, blanking is dramatically performed as compared with the driving method disclosed in Patent Document 2 (Japanese Patent Publication No. 9-511589). Period ratio decreases.

  FIG. 8 and FIG. 9 show how the scanning conditions shown in FIG. FIG. 8 shows a part of the frame period (selection periods 1 to 40), and FIG. 9 shows the remaining part of the frame period.

  8 and 9, the horizontal axis represents time. Each row shows, from the top, the number of the selection period, the number of the unit period, the number of the occupation period, and the driving timing of the gate wirings G1 to G8. A period indicated by a double arrow below is a drive period corresponding to each instruction data in the gate line G1, and a number shown above the double arrow is a bit length of the period. The selection period number indicates the number of the selection period within one frame period. The unit period number indicates the number of the unit period in one frame period. The column indicating the drive timing of the gate lines G1 to G8 indicates which bit number instruction data of the pixel Aij corresponding to which gate line Gi is supplied to the source line Sj. That is, in the column indicating the drive timing of the gate wirings G1 to G8, the positions of the writing period (first selection period included in the display period) corresponding to each instruction data are indicated by the bit numbers 1 to 8. “B” does not indicate the time for transferring blanking data to the source line Sj, but indicates a period for performing blanking using the control line Ri.

  Next, a method for determining the drive timing shown in FIGS. 8 and 9 will be described.

  First, the timing for sending each instruction data B1 to B8 corresponding to the gate wiring G1 to the source wiring Sj (timing for writing each instruction data B1 to B8 to the pixel circuit A1j corresponding to the gate wiring G1) is the scanning condition of FIG. Determine based on. That is, first, since the bit number of the instruction data B1 is 7 under the scanning condition of FIG. 7, the instruction data (instruction data of the bit number 7 is selected during the selection period 1 for the pixel circuit A1j corresponding to the gate wiring G1. Decide to send B1). Next, under the scanning conditions of FIG. 7, the bit numbers of the instruction data B2 to B8 are 8, 1, 3, 4, 2, 5, 6, and the bit length (the length of the drive period) of the instruction data B1 to B7 is 12, 13, 1, 4, 7, 2, 12. Therefore, a period during which the instruction data B2 to B8 of the bit numbers 8, 1, 3, 4, 2, 5, 6 corresponding to the gate wiring G1 is sent to the source wiring Sj (for the pixel circuit A1j corresponding to the gate wiring G1) Corresponding to the writing period in which the instruction data B2 to B8 are written) is the selection period 13, the selection period 26, the selection period 27, the selection period 31, the selection period 38, the selection period 40, and the selection period 52, respectively. I understand. Since the bit length of the instruction data B8 is 12 and the bit length of the blanking period is 1, the selection period 64 is set to the blanking period. At this time, display periods (bit display periods) for performing display corresponding to the instruction data B1 to B8 of the respective bit numbers in the pixel circuit Aij corresponding to the gate wiring G1 are respectively the selection periods 1 to 12, the selection periods 13 to 25, The selection period 26, the selection periods 27 to 30, the selection periods 31 to 37, the selection periods 38 to 39, the selection periods 40 to 51, and the selection periods 52 to 63 are provided.

  Here, a display period (bit display period) in which display corresponding to the instruction data B1 to B8 of each bit number is performed in the pixel circuit Aij corresponding to the next gate line G2 is a display period of each bit number of the gate line G1. One unit period (8 selection periods) is added. Then, in the selection period in which each instruction data B1 to B8 corresponding to the gate wiring G2 is sent to the source wiring Sj, 8 is added to the number of the selection period in which each instruction data B1 to B8 corresponding to the gate wiring G1 is sent to the source wiring Sj. It is required by that. Note that the display period of each bit number of the gate wiring G3 and the like instead of the gate wiring G2 may be one unit period added to the display period of each bit number of the gate wiring G1.

  Hereinafter, similarly, the selection period for sending the instruction data B1 to B8 corresponding to the gate wirings G3 to G8 to the source wiring Sj is determined, and by combining them, the timing of each instruction data to be output to the source wiring Sj is determined. Is decided.

  As a result, the timing for sending the instruction data B1 to B8 corresponding to the gate lines G1 to G8 shown in FIGS. 8 and 9 to the source line Sj can be determined.

  As can be seen from the drive timings shown in FIGS. 8 and 9, the timings of sending the instruction data B1 to B8 corresponding to the gate lines G1 to G8 to the source line Sj do not overlap each other. Therefore, at this timing, if the instruction data B1 to B8 of each bit number corresponding to each pixel circuit A1j to A8j sharing the source wiring Sj is supplied to the source wiring Sj shared by the pixel circuits A1j to A8j, It can be seen that each pixel circuit Aij can display time-division gradation display while continuously supplying instruction data.

(Driving condition example 3)
In this driving condition example, the number n of gate wirings Gi (denoted as “number of lines” in the drawing) is 480. Further, the display device 1 includes three pixel circuits corresponding to three colors for each pixel, and the display gradation number G of each color is 256 gradations (the bit number p of the display gradation number G is 8 bits). Shall. Further, in this example, in order to suppress the occurrence of the moving image false contour, the number A of instruction data (denoted as “data number” in the drawing) is a value that is two larger than the bit number p of the display gradation number G, that is, 10 is assumed. In this example, a memory for storing instruction data (A instruction data) for one unit period provided in the control circuit is a 10-bit memory.

Under these conditions, the weights W1 to W9 of the instruction data B1 to B9 are determined so as to satisfy the simultaneous equation (1). Further, the weight W10 of the instruction data B10 is determined so as to satisfy the formula (2). The integer k is the inequality (4) above, ie
k <480 × 10/256
It is an integer that satisfies the above and is not a multiple of A (= 10). The integer k is preferably the maximum number that satisfies this condition. Therefore, in this case, k is preferably set to 18 in order to minimize the length Wb of the blanking period. However, in this case, it was found that k does not go well at 18, so it is further reduced by one and set to 17.

Then, the blanking time length Wb is satisfied so as to satisfy the formula (3).
Wb = 480 × 10− (256-1) × 17 = 465
And Then, the bit length of the instruction data B10 is a value obtained by adding the weight W10 and the blanking period length Wb.

The scanning conditions obtained as a result of the above settings are shown in FIG. 10 in the same manner as in FIG.
Under the scanning conditions of FIG. 10, 256 gradation display can be realized by turning ON / OFF each instruction data B1 to B10 independently.

(Driving condition example 4)
In the case of driving condition example 3, as described above, a 10-bit storage area is secured as a storage area for storing instruction data, or 10-bit data is stored from 8-bit data stored in an 8-bit memory. It is necessary to create instruction data. In the former, it is necessary to secure a large number of storage areas, and in the latter, it is necessary to increase the memory access frequency. Therefore, when it is required not to secure a large storage area or increase the memory access frequency, there is a driving method for independently turning ON / OFF the instruction data of each bit as in driving condition example 3. It may not be usable.

  In such a case, it is effective to use the following driving method. That is, the instruction data B1 of bit number 9, the instruction data B10 of bit number 10, the instruction data B2 of bit number 8, and the instruction data B9 of bit number 7 are simultaneously turned ON / OFF. The memory for storing the instruction data has an 8-bit configuration, the instruction data B3 to B8 of the bit numbers 1 to 6 are the lower 6 bits, the instruction data B1 of the bit number 9 that also serves as the instruction data B10 of the bit number 10 and the bit number The instruction data B2 of bit number 8 also serving as the instruction data B9 of 7 is stored in the memory as the upper 2 bits. Then, the upper 2 bits of data are read from the memory twice in one unit period.

  In this case, unlike the driving condition example 3, the weights W1 to W10 of the respective instruction data B1 to B10 are set to 0 to 255 depending on a combination of eight numbers of W1, W2, W3, W4, W5, W6, W7 + W8, and W9 + W10. Be able to represent numbers.

  In FIG. 11, under such conditions, the number n of gate wirings Gi (denoted as “number of lines” in the drawing) is set to 480, the number A of instruction data is set to 10, and 256 gradations are displayed ( The results of obtaining the scanning conditions for G = 256) are shown in the same manner as in FIG. In this case, k is set to 17.

  Under this driving condition, it is only necessary to secure a storage area for 8 bits as a storage area for storing instruction data, so there is no need to secure a large number of storage areas or increase the memory access frequency. Here, the upper 2 bits of the data stored in the memory also serve as a plurality of instruction data. However, the upper 1 bit or the upper 3 bits or more of the data stored in the memory also serve as a plurality of instruction data. You may do it.

  As described above, when the above driving method is used, it is possible to realize a time-multiplex gradation driving method in which the proportion of blanking periods existing in one frame period is reduced.

  Further, when the above driving method is used for the pixel circuit Aij driven at the driving timing shown in FIG. 3, the pixel circuit A2j always switches the switching transistor 13 during the blanking period from the time 13t1 to the time 16t1. Is kept in the OFF state. Therefore, the pixel circuit A2j in the blanking period is not connected to the source line Sj and does not occupy the source line Sj. For this reason, when the pixel circuit A2j is in the blanking period, instruction data is supplied to the other pixel circuit Aij (for example, the pixel circuit A3j) sharing the source line Sj with the pixel circuit A2j via the source line Sj. It becomes possible. Therefore, it is possible to continuously supply the instruction data to any one of the pixel circuits Aij sharing the source line Sj through the source line Sj. As a result, the number of selection periods in one frame period is the same as that in a configuration in which there is a period in which the supply of instruction data via the source wiring Sj is stopped (for example, a configuration in a third embodiment described later). In this case, the number A of instruction data can be increased. As a result, the bit weight of the instruction data that maximizes the bit weight can be reduced and the occurrence of the moving image false contour can be suppressed, so that the display quality can be improved.

  Note that the display device 1 including the pixel circuit shown in FIG. 1 according to this embodiment has a driving method other than the driving method described above, for example, a driving method disclosed in Patent Document 2 (Japanese Patent Publication No. 9-511589), or a patent. You may drive by the drive method etc. of the literature 3 (Unexamined-Japanese-Patent No. 2004-4501).

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The display device of the present embodiment has the same configuration as that of the display device 1 except that the configuration of the pixel circuit Aij in the display device 1 of the first embodiment shown in FIG. 2 is changed. Since portions other than the pixel circuit Aij are the same as those of the display device 1, detailed description thereof is omitted.

  The pixel circuit Aij included in the display device of this embodiment is the pixel circuit Aij illustrated in FIG.

  As shown in FIG. 12, the pixel circuit Aij is arranged near the position where the source line Sj and the gate line Gi intersect, and is a driving transistor 16 that is an n-type TFT and a switch transistor that is an n-type TFT. A transistor (first switch transistor) 13, a switch transistor (third switch transistor) 17 that is an n-type TFT, and an organic EL element EL 1 (electro-optical element) are provided.

  Specifically, a power supply wiring Vp (predetermined potential wiring) to which a predetermined power supply voltage Vp is applied from a DC power supply (not shown) and a predetermined common potential (for example, a ground potential) having a predetermined potential difference with respect to the power supply voltage Vp. Between the given common wiring Vcom, the driving transistor 16, the switching transistor 17, and the organic EL element EL1 are connected in series in this order.

  The drive transistor 16 has a drain terminal connected to the power supply line Vp and a source terminal connected to the drain terminal of the switch transistor 17. The driving transistor 16 is interposed between the DC power source and the organic EL element EL1, and controls the supply of current from the DC power source to the organic EL element EL1 according to instruction data supplied to the gate terminal thereof. . More specifically, when the ON potential is supplied to the gate terminal of the driving transistor 16, the driving transistor 16 is turned on and supplies the current from the DC power source to the organic EL element EL1. On the other hand, when the OFF potential is supplied to the gate terminal of the driving transistor 16, the driving transistor 16 is turned off and stops supplying current from the DC power source to the organic EL element EL1.

  The switching transistor 17 is controlled to be in an OFF state (non-conducting state) for a certain period by a control signal Ri supplied from the control wiring Ri, and as a result, a current flowing from the driving transistor 16 to the organic EL element EL1 is supplied. It stops only for the above period. In this case, the switching transistor 17 and the control wiring Ri constitute a current interruption means. Further, the switching transistor 17 shifts from an ON state to an OFF state during a period in which a switching transistor 19 described later is in an ON state in order to compensate for variations in threshold voltage of the driving transistor 16. .

  In this case, the switching transistor 17 and the control wiring Ri constitute blanking means. Instead of these, as a blanking means, a means for giving a signal (blanking signal) for setting the organic EL element EL1 in an erased state to the pixel circuit Aij for a certain period, for example, a means for performing blanking in Patent Document 3 is used. May be.

  A switching transistor 19 (threshold voltage compensation means, second switching transistor) is arranged between the gate terminal and the drain terminal (terminal on the power supply wiring Vp side) of the driving transistor 16. In other words, the switching transistor 19 is interposed on the wiring connecting the gate terminal and the drain terminal of the driving transistor 16.

  The switching transistor 19 has a blanking period (blanking period), that is, a period in which a current flowing from the driving transistor 16 to the organic EL element EL1 is stopped (a period in which the switching transistor 17 is in an OFF state). ) Is turned ON. As a result, the gate terminal and the drain terminal of the driving transistor 16 are short-circuited during the blanking period, and as a result, variations in the threshold voltage of the driving transistor 16 are compensated. The principle of compensating for variations in threshold voltage will be described later. On the other hand, the transistor 19 is in an OFF state during a period in which the switching transistor 17 is in an ON state except for a predetermined time immediately before the blanking period. The switching transistor 19 has a gate terminal connected to the control wiring Pi, and is controlled by a control potential Pi supplied to the control wiring Pi.

  In addition, a capacitor (first capacitor) C 3 and a capacitor (second capacitor) C 4 are connected to the gate terminal of the driving transistor 16.

  One terminal of the capacitor C <b> 3 is connected to the gate terminal of the driving transistor 16, and the other terminal is connected to the source terminal of the driving transistor 16. The capacitor C3 functions as a potential difference holding unit for holding a potential difference between the gate terminal and the source terminal of the driving transistor 16.

  The capacitor C4 has one terminal connected to the gate terminal of the driving transistor 16, and the other terminal connected to the drain terminal of the switching transistor 13. The capacitor C4 holds the instruction data output from the drain terminal of the switching transistor 13 and supplies it to the gate terminal of the driving transistor 16.

  The source terminal of the switch transistor 13 is connected to the source line Sj. The gate terminal of the switching transistor 13 is connected to the gate wiring Gi. The switch transistor 13 is controlled in conduction by the scanning signal Gi supplied to the gate wiring Gi, and when it is conductive, the instruction data from the source wiring Sj is output to the capacitor C4 and is held in the capacitor C4.

  The other terminal of the capacitor C4 (the terminal connected to the drain terminal of the switch transistor 13) is also connected to the drain terminal of the switch transistor (fifth switch transistor) 20. The source terminal of the switching transistor 20 is connected to the gate terminal of the driving transistor 16. The switching transistor 20 has its gate terminal connected to the control wiring Pi, and is controlled by the control potential Pi supplied to the control wiring Pi. The switching transistor 20 uses the other terminal of the capacitor C4 (the terminal connected to the drain terminal of the switching transistor 13) as the gate terminal of the driving transistor 16 while the switching transistor 19 is in the ON state. This is for connecting and applying a predetermined potential (power supply voltage Vp) to the other terminal of the capacitor C4.

  In the pixel circuit Aij of the present embodiment, since all the transistors are composed of n-type TFTs, the pixel circuit Aij can be formed not only with a polysilicon substrate but also with an amorphous silicon substrate. On the other hand, in the pixel circuit Aij according to the first embodiment, p-type TFTs are used for some of the transistors, so that it is generally necessary to make them using a polysilicon substrate instead of an amorphous silicon substrate. This is because, in general, a p-type TFT is not formed from an amorphous silicon substrate.

  The drive timing of the pixel circuit Aij is shown in FIG. 13 in the same manner as in FIG. The three waveforms shown in the upper part of FIG. 13 correspond to the pixel circuit A2j, and are the waveforms of 1) the scanning signal G2, 2) the control potential P2, and 3) the control signal R2 in order from the top. Further, Sj shown in the center of FIG. 13 indicates the type of instruction data supplied to the source wiring Sj by a bit number. The three waveforms shown in the lower part of FIG. 13 correspond to the pixel circuit A3j, and are the waveforms of 4) scanning signal G3, 5) control potential P3, 6) control signal R3 in order from the top. In this case, the instruction data includes eight types of instruction data B1 to B8 (B is omitted in FIG. 13). FIG. 13 shows a case where the time-multiplex gradation driving method described in the first embodiment is adopted. Further, the time axis indicated by the horizontal axis in FIG. 13 indicates t1 corresponding to half the length of the occupation period as a unit.

  Pixel A2j enters the blanking period from time 13t1. At time 13t1, the potential of the control wiring P2 is set to High (GH), and the switching transistors 20 and 19 are turned on. When the switching transistor 20 is turned on, the other terminal of the capacitor C4 (the terminal connected to the switching transistor 13) is connected to the gate terminal of the driving transistor 16. Further, when the switching transistor 19 is turned on, the gate terminal and the drain terminal of the driving transistor 16 are short-circuited. At this time, since the potential of the control wiring R2 is High (GH), the switching transistor 17 is turned on. Accordingly, the potential of the source terminal of the driving transistor 16 is lowered, and the gate potential of the driving transistor 16 becomes the ON potential. A power supply voltage Vp having a predetermined potential is applied to both ends of the capacitor C2 from the power supply wiring Vp.

Thereafter, at time 14t1, the potential of the control wiring R2 is set to Low (GL), and the switching transistor 17 is turned off (at this time, the switching transistors 20 and 19 remain in the ON state). As a result, the potential of the source terminal of the driving transistor 16 rises, the gate-source potential of the driving transistor 16 changes from the ON state to the OFF state, and reaches the threshold potential Vth. Therefore, the source potential Vs of the driving transistor 16 is equal to the difference between the power supply voltage Vp and the threshold potential Vth of the driving transistor 16, that is,
Vs = Vp−Vth
It becomes. Therefore, the potential difference between both ends of the capacitor C3 is equal to the gate-source potential of the driving transistor 16, that is, the threshold potential Vth.

  At time 15t1, the potential of the control wiring P2 is set to Low (GL), and the switching transistors 20 and 19 are turned off. As a result, the potential difference Vp−Vs, that is, a potential difference equal to the threshold potential Vth is held at both ends of the capacitor C3 (charge corresponding to the threshold potential Vth is held), while both ends of the capacitor C4 are held at the power supply potential Vp. Is done.

  Thereafter, the blanking period ends at time 16t1. At time 16t1, the potential of the control wiring R2 is set to High (GH), and the switching transistor 17 is turned on. Further, the potential of the gate wiring G2 is set to High (GH), and the switching transistor 13 is turned on. As a result, the other terminal of the capacitor C4 (the terminal connected to the switching transistor 13) is short-circuited with the source line Sj.

  At this time, since the instruction data (instruction data B1 corresponding to bit number 7) is supplied to the source wiring Sj, the potential of the other terminal of the capacitor C4 (the terminal connected to the switching transistor 13) is The potential (VH or VL) corresponds to the instruction data (instruction data B1 corresponding to bit number 7). For this reason, the gate potential of the driving transistor 16 changes corresponding to the instruction data (instruction data B1 corresponding to bit number 7).

  At this time, since the potential difference equal to the threshold voltage Vth of the driving transistor 16 is held across the capacitor C3, the gate potential of the driving transistor 16 corresponds to the instruction data without depending on the threshold potential Vth. The potential is changed from the predetermined potential (power supply potential Vp) by the determined potential. That is, the gate-source potential of the driving transistor 16 becomes a potential changed from the threshold potential Vth by a potential corresponding to the instruction data without depending on the threshold potential Vth. As a result, like the pixel circuit Aij shown in FIG. 1, the organic EL element EL1 is in a display state corresponding to the instruction data without depending on the threshold potential Vth of the driving transistor 16. As a result, luminance unevenness due to variation in the threshold potential Vth of the driving transistor 16 is compensated, and display without luminance unevenness can be performed.

  After time 17t1, the potential of the gate wiring G2 is set to Low (GL) and the switching transistor 13 is turned off, so that the other terminal of the capacitor C4 (the terminal connected to the switching transistor 13) is connected. The potential applied between time 16t1 and time 17t1 (potential corresponding to the instruction data) is held.

  Thus, the current Id flowing through the driving transistor 16 has a current value corresponding to the instruction data B1 (instruction data B1 corresponding to bit number 7) regardless of the threshold potential Vth. At this time, since the switching transistor 17 is in the ON state, the current Id flows from the driving transistor 11 to the organic EL element EL1. As a result, a display with no unevenness of brightness corresponding to the instruction data is maintained.

  Note that, after time 17t1, the instruction data sent to the source wiring Sj is changed to instruction data corresponding to the other gate wiring, but the switching transistor 13 corresponding to the gate wiring G2 is in the OFF state, so The transistor 11 and the like are not affected by the change of the instruction data.

  As described above, in the display device according to the present embodiment, similarly to the display device 1 according to the first embodiment, the threshold potential of the driving transistor 16 during the blanking period outside the selection period corresponding to the instruction data B1 to Ba. Variations in Vth can be compensated. Therefore, similarly to the display device 1 according to the first embodiment, the selection period can be shortened.

  Further, in the display device according to the present embodiment, as in the display device 1 according to the first embodiment, the blanking operation can be performed by controlling the switching transistor 17 by the control wiring Ri. Since all can be used for display, the weight of the instruction data having the largest weight can be reduced. As a result, the generation of a moving image false contour can be suppressed.

  Also in the display device according to this embodiment, the driving method described in Embodiment 1 can be used. For example, the scanning conditions shown in FIG. 7 can be used in this embodiment as well as in the first embodiment. Since the above driving method is the same as that of the first embodiment, the description thereof is omitted.

[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the first or second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The display device of the present embodiment has the same configuration as that of the display device 1 except that the configuration of the pixel circuit Aij in the display device 1 of the first embodiment shown in FIG. 2 is changed. Since portions other than the pixel circuit Aij are the same as those of the display device 1, detailed description thereof is omitted.

  The pixel circuit Aij used in the present embodiment is the pixel circuit Aij shown in FIG. The pixel circuit Aij of the present embodiment has a configuration in which the switching transistor 20 is removed from the pixel circuit Aij of the second embodiment shown in FIG. 12, and the other points are the same as the pixel circuit Aij of the second embodiment. Therefore, the description regarding each component of the pixel circuit Aij is omitted here. However, in the pixel circuit Aij used in the present embodiment, the switching transistor 13 is connected to the other terminal of the capacitor C4 (a terminal on the switching transistor 13 side) during the period when the switching transistor 17 is OFF (blanking period). Is connected to the source line Sj to set the charge of the capacitor C4.

  FIG. 15 shows the drive timing of the pixel circuit Aij in the same manner as in FIG. The three waveforms shown in the upper part of FIG. 15 correspond to the pixel circuit A2j, and are waveforms of 1) the scanning signal G2, 2) the control potential P2, and 3) the control signal R2, in order from the top. Further, Sj shown in the center of FIG. 15 indicates the type of instruction data supplied to the source wiring Sj by a bit number. The three waveforms shown in the lower part of FIG. 15 correspond to the pixel circuit A3j, and are waveforms of 4) scanning signal G3, 5) control potential P3, 6) control signal R3 in order from the top. In this case, the instruction data includes seven types of instruction data B1 to B7 (B is omitted in FIG. 15). In a unit period including a blanking period, a blanking signal is supplied to the source line Sj as instruction data. FIG. 15 shows a case where the time-multiplex gradation driving method described in FIG. 17 is adopted. In addition, the time axis indicated by the horizontal axis in FIG. 15 indicates t1 corresponding to half the length of the occupation period as a unit.

  Pixel A2j enters the blanking period from time 13t1. At time 13t1, the potential of the control wiring P2 is set to High (GH), and the switching transistor 19 is turned on. As a result, the gate terminal and the drain terminal of the driving transistor 16 are short-circuited. At this time, since the potential of the control wiring R2 is High (GH), the switching transistor 17 is turned on. Accordingly, the potential of the source terminal of the driving transistor 16 is lowered, and the gate potential of the driving transistor 16 becomes the ON potential.

  After that, at time 14t1, the potential of the control wiring R2 is set to Low (GL), and the switching transistor 17 is turned off (at this time, the switching transistor 19 remains on). At time 14t1, the potential of the gate line Gi is set to High (GH), the switching transistor 13 is turned on, and the other terminal of the capacitor C4 is short-circuited to the source line Sj. At this time, the blanking potential (for example, the potential of the power supply wiring Vp) given as the instruction data B8 is supplied to the source wiring Sj. Note that the potential of the gate wiring Gi is set to High (GH) only in the first part in the period from the time 14t1 to the time 15t1.

As a result, the potential of the source terminal of the driving transistor 16 rises, the gate-source potential of the driving transistor 16 changes from the ON state to the OFF state, and reaches the threshold potential Vth. Therefore, the source potential Vs of the driving transistor 16 is equal to the difference between the power supply voltage Vp and the threshold potential Vth of the driving transistor 16, that is,
Vs = Vp−Vth
It becomes. Therefore, the potential difference between both ends of the capacitor C3 is equal to the gate-source potential of the driving transistor 16, that is, the threshold potential Vth.

  At this time, the potential difference between both ends of the capacitor C4 is determined to be a predetermined potential difference (for example, 0 when the blanking potential is the potential of the power supply wiring Vp).

  At time 15t1, the gate wiring Gi is set to Low (GL), and the switching transistor 13 is turned off. Thereby, the potential difference Vp−Vs, that is, a potential difference equal to the threshold potential Vth is held at both ends of the capacitor C3 (charge corresponding to the threshold potential Vth is held), while both ends of the capacitor C4 are held at time t1. (For example, 0 when the blanking potential is the potential of the power supply wiring Vp) is held.

  Thereafter, the blanking period ends at time 16t1. At time 16t1, the potential of the control wiring R2 is set to High (GH), and the switching transistor 17 is turned on. Further, the potential of the gate wiring G2 is set to High (GH), and the switching transistor 13 is turned on. At this time, since the instruction data is supplied to the source wiring Sj, the potential of the other terminal of the capacitor C4 (the terminal connected to the switching transistor 13) is a potential (VH or V) corresponding to the instruction data. VL). For this reason, the gate potential of the driving transistor 16 changes corresponding to the instruction data.

  At this time, since the potential difference equal to the threshold voltage Vth of the driving transistor 16 is held across the capacitor C3, the gate potential of the driving transistor 16 corresponds to the instruction data without depending on the threshold potential Vth. The potential is changed from the predetermined potential (power supply potential Vp) by the determined potential. That is, the gate-source potential of the driving transistor 16 becomes a potential changed from the threshold potential Vth by a potential corresponding to the instruction data without depending on the threshold potential Vth. As a result, like the pixel circuit Aij shown in FIG. 12, the organic EL element EL1 does not depend on the threshold potential Vth of the driving transistor 16, and enters a display state corresponding to the instruction data. As a result, luminance unevenness due to variation in the threshold potential Vth of the driving transistor 16 is compensated, and display without luminance unevenness can be performed.

  After time 17t1, the potential of the gate wiring G2 is set to Low (GL) and the switching transistor 13 is turned off, so that the other terminal of the capacitor C4 (the terminal connected to the switching transistor 13) is connected. The potential applied between time 16t1 and time 17t1 (potential corresponding to the instruction data) is held.

  Thus, the current Id flowing through the driving transistor 16 has a current value corresponding to the instruction data B1 (instruction data B1 corresponding to bit number 7) regardless of the threshold potential Vth. At this time, since the switching transistor 12 is in the ON state, the current Id flows from the driving transistor 11 to the organic EL element EL1. As a result, a display with no unevenness of brightness corresponding to the instruction data is maintained.

  Note that, after time 17t1, the instruction data sent to the source wiring Sj is changed to instruction data corresponding to the other gate wiring, but the switching transistor 13 corresponding to the gate wiring G2 is in the OFF state, so The transistor 11 and the like are not affected by the change of the instruction data.

  In the drive timing shown in FIG. 15, the blanking period is about one selection period. However, in an actual display device, a potential change for compensating the threshold voltage Vth of the driving transistor 16 (thresholds at both ends of the capacitor C3). The operation of holding the charge corresponding to the potential Vth may take several selection times.

  However, the time required for the initialization operation for setting the potential at both ends of the capacitor C4 is only a moment (about time t1). For this reason, even if several selection times are required to compensate the threshold voltage of the driving transistor 16 in an actual display device, the selection period for the blanking operation can be one selection period.

  FIG. 16 shows a result of simulation of the current Id flowing through the driving transistor 16 and the gate potential Vg and the source potential Vs of the driving transistor 16 during the blanking period.

  In FIG. 16, the current (Id) and potential (Vg, Vd) marked with (1) and (2) are the results of simulation using the conditions (1) and (2) shown in the first embodiment, respectively. is there. In this simulation, the period of 2624 to 2688 μs (corresponding to the period from time 13t1 to time 15t1 in FIG. 15) and the control potential P2 were set to 14V (corresponding to VH in FIG. 15). Further, the potential of the control signal R2 was set to −2V (corresponding to VL in FIG. 15) during the period 2628 to 2692 μs (corresponding to the time 14t1 to time 16t1 in FIG. 15). Further, the period of 2628 to 2632 μs (corresponding to the first part in the period from time 14t1 to time 15t1 in FIG. 15), and the potential of the scanning signal G2 was set to 14V (corresponding to VH in FIG. 15).

  As can be seen from FIG. 16, the gate-source potential Vgs (= Vg−Vs) of the driving transistor 16 changes corresponding to the threshold potential Vth of the driving transistor 16.

  In addition, the period during which the gate wiring Gi is High (GH) is only 2628 to 2632 μs, but the threshold compensation period can be continued up to 2688 μs thereafter.

  As described above, when the pixel circuit Aij of FIG. 14 is used, it is necessary to connect the other terminal of the capacitor C4 to the source line Sj for a moment, but most of the threshold compensation period of the driving transistor 16 can be a blanking period.

  As described above, in the display device according to the present embodiment, similarly to the display device according to the second embodiment, the threshold potential Vth of the driving transistor 16 during the blanking period outside the selection period corresponding to the instruction data B1 to Ba. Can be compensated for. Therefore, similarly to the display device according to Embodiment 2, the selection period can be shortened.

  Further, in the display device according to the present embodiment, the number of transistors per pixel circuit can be reduced by the amount obtained by removing the switching transistor 20 as compared with the second embodiment. As a result, it is possible to increase the aperture ratio and improve the pixel density (high definition).

  In the pixel circuit Aij shown in FIG. 14, the capacitor C4 is directly connected to the gate terminal of the driving transistor 16. However, as shown in FIG. 22, the capacitor C5 (second capacitor) may be connected to the gate terminal of the driving transistor 16 through the switching transistor 13 (first switching transistor).

  Therefore, a time-multiplex gradation driving method capable of increasing the ratio of the display period existing in one frame period will be described as a driving method of the display device 1 described above.

  The driving method of this embodiment is basically the same as the driving method described in detail in the first embodiment. In other words, in the driving method of the present embodiment, the length of the display period corresponding to the instruction data is set with a period obtained by equally dividing the n unit periods constituting one frame period by A. Also in this embodiment, all of the 1st to Ath selection periods correspond to one of the instruction data. However, the A-th instruction data is always blanking data indicating “0”.

Also in the driving method of this embodiment, the weights W1 to W _a-1 of the instruction data are set so as to satisfy the simultaneous equations (1) and (2).

The length Wb of the blanking period expressed in units of the selection period is also the above formula (3).
Sought by.

  The integer k is also an integer that satisfies the inequality (4) and is a number that does not become a multiple of A (however, a value that satisfies the simultaneous expression (1)). In addition, when there are a plurality of numbers that do not become multiples of A, in order to minimize the length Wb of the blanking period, it is preferable to set the maximum number among these numbers to k.

  Hereinafter, specific examples of the driving method will be described as driving condition examples 5 and 6.

(Driving condition example 5)
In this driving condition example, the number n of gate wirings Gi (denoted as “number of lines” in the drawing) is eight. Further, the display device 1 includes three pixel circuits corresponding to three colors for each pixel, and the display gradation number G of each color is 64 gradations (the bit number p of the display gradation number G is 6 bits). Shall. In this example, the number A of instruction data (denoted as “data number” in the drawing) is 2 larger than the bit number p of the display gradation number G so that the length Wb of the blanking period is reduced. Value, ie, 8. Since one of them is blanking data that is always “0”, a memory for storing instruction data (A instruction data) for one unit period provided in the control circuit is provided. Bit memory.

Then
n × A = 8 × 8 = 64
It becomes.

The integer k is
k <n × A / (G−1) (4)
It is an integer that satisfies the above and is a number that does not become a multiple of A (however, a value that satisfies the simultaneous equation (1)). Therefore, k = 1 and the bit length of the weight 1 bit (instruction data) is 1.

  Then, the weights W1 to W7 (W1 to W7 are integers of 1 or more) of the instruction data B1 to B7 are determined so as to satisfy the simultaneous equation (1). The instruction data B8 is blanking data that is always “0”, and its weight is zero.

  An example of scanning conditions obtained as a result of such weight determination is shown in FIG. 17 in the same manner as in FIG.

  Bit numbers are assigned to the instruction data B1 to B7 as 1, 2,... As a result, instruction data B1 is bit number 5, instruction data B2 is bit number 4, instruction data B3 is bit number 3, instruction data B4 is bit number 2, instruction data B5 is bit number 1, and instruction data B6 is bit number 6. The instruction data B7 is bit number 7. The instruction data B8 is a bit number B which is blanking data. In this case, the weights of the instruction data (bits) of bit numbers 1 to 7 are set to 14, 7, 4, 2, 1, 14, 21 respectively. The weight of the instruction data B8 is 0.

  When the number of gate wirings is n = 320, k = 39 may be used as shown in the driving condition example 2 of the first embodiment. In this example of driving conditions, k = 1 and the number of gate wirings n = 8 in order to make it easy to indicate the driving timing.

  FIG. 18 and FIG. 19 show how the scanning conditions shown in FIG. 17 are driven in the same manner as in FIGS. FIG. 18 shows a part of the frame period (selection periods 1 to 40), and FIG. 19 shows the remaining part of the frame period. 18 and 19, unlike FIGS. 8 and 9 shown in the first embodiment, there is instruction data B8 having a weight of zero. In FIG. 18 and FIG. 19, this instruction data B8 is represented as 8.

  Next, a method for determining the drive timing shown in FIGS. 18 and 19 will be described.

  First, the timing for sending each instruction data B1 to B8 corresponding to the gate wiring G1 to the source wiring Sj (timing for writing each instruction data B1 to B8 to the pixel circuit A1j corresponding to the gate wiring G1) is the scanning condition of FIG. Determine based on. That is, first, under the scanning condition of FIG. 17, the bit number of the instruction data B1 is 5, so that the instruction data (instruction data of bit number 5) is selected in the selection period 1 for the pixel circuit A1j corresponding to the gate wiring G1. Decide to send B1). Next, under the scanning conditions of FIG. 17, the bit numbers of the instruction data B2 to B8 are 4, 3, 2, 1, 6, 7, and 8, and the bit length (the length of the drive period) of the instruction data B1 to B7 is 7, 4, 2, 1, 14, 21. Therefore, a period during which the instruction data B2 to B8 of the bit numbers 4, 3, 2, 1, 6, 7, and 8 corresponding to the gate wiring G1 is sent to the source wiring Sj (for the pixel circuit A1j corresponding to the gate wiring G1) Corresponding to the writing period in which the instruction data B2 to B8 are written) is the selection period 15, the selection period 22, the selection period 26, the selection period 28, the selection period 29, the selection period 43, and the selection period 64, respectively. I understand. At this time, a display period (bit display period) in which display corresponding to the instruction data B1 to B7 of each bit number is performed in the pixel circuit Aij corresponding to the gate wiring G1 is a selection period 1 to 14, a selection period 15 to 21, respectively. The selection periods 22 to 25, the selection periods 26 to 27, the selection period 28, the selection periods 29 to 42, and the selection periods 43 to 63 are provided.

  Here, a display period (bit display period) in which display corresponding to the instruction data B1 to B8 of each bit number is performed in the pixel circuit Aij corresponding to the next gate line G2 is a display period of each bit number of the gate line G1. One unit period (8 selection periods) is added. Then, in the selection period in which each instruction data B1 to B8 corresponding to the gate wiring G2 is sent to the source wiring Sj, 8 is added to the number of the selection period in which each instruction data B1 to B8 corresponding to the gate wiring G1 is sent to the source wiring Sj. Is required. Note that the display period of each bit number of the gate wiring G3 and the like instead of the gate wiring G2 may be one unit period added to the display period of each bit number of the gate wiring G1.

  Hereinafter, similarly, the selection period for sending the instruction data B1 to B8 corresponding to the gate wirings G3 to G8 to the source wiring Sj is determined, and by combining them, the instruction data to be output to the source wiring Sj and the block data are output. The timing of the ranking signal is determined.

  As a result, the timing for sending the instruction data B1 to B8 corresponding to the gate lines G1 to G8 shown in FIGS. 18 and 19 to the source line Sj can be determined.

  As can be seen from the drive timings shown in FIGS. 18 and 19, the timings of sending the instruction data B1 to B8 corresponding to the gate wirings G1 to G8 to the source wiring Sj do not overlap each other. Therefore, at this timing, if the instruction data B1 to B8 of each bit number corresponding to each pixel circuit A1j to A8j sharing the source wiring Sj is supplied to the source wiring Sj shared by the pixel circuits A1j to A8j, It can be seen that each pixel circuit Aij can display time-division gradation display while continuously supplying instruction data.

  FIG. 20 shows which of the instruction data of each bit number 5 to 8 is in the ON state and which is in the OFF state in each gradation. In FIG. 20, the instruction data that is turned on in each gradation is indicated by white circles. In FIG. 20, the “gradation number” represents the number of gradations from the lowest.

  In the instruction data, if the ON state is represented by “1” and the OFF state is represented by “0”, the instruction data B1 corresponding to the bit numbers 5, 4, 3, 2, 1, 6, 7 is understood from FIG. The states of .about.B7 are (0, 1, 0, 0, 1, 0, 0) at the 9th gradation (8/63 gradation) and (0, 0) at the 16th gradation (15/63 gradation). , 0, 0, 1, 1, 0), 23rd gradation (22/63 gradation), (0, 1, 0, 0, 1, 1, 0), 30th gradation (29/63 gradation) ) At (1, 0, 0, 0, 1, 1, 0), 37th gradation (36/63 gradation), (1, 1, 0, 0, 1, 1, 0), 44th gradation (1,1,0,0,1,0,1) at (43/63 gradation), (1,0,0,0,1,1,1) at the 51st gradation (50/63 gradation) ), (1, 1, 0, 0, 1, 1, 1) at the 58th gradation. In FIG. 20, only some of the gradations are shown, but all other gradations can be displayed in the same manner.

(Driving condition example 6)
Examples of weights W1 to W7 (W1 to W7 are integers of 1 or more) and instruction data B8 of other instruction data B1 to B7 determined so as to satisfy the simultaneous equation (1) under the same conditions as the driving condition example 5 Is shown in the scanning conditions of FIG.

  Bit numbers are assigned to the instruction data B1 to B7 as 1, 2,... As a result, instruction data B1 is bit number 7, instruction data B2 is bit number 6, instruction data B3 is bit number 1, instruction data B4 is bit number 2, instruction data B5 is bit number 4, instruction data B6 is bit number 3. The instruction data B7 is bit number 5. The weights of the instruction data (bits) B1 to B7 of the bit numbers 1 to 7 are set to be 18, 17, 1, 1, 2, 7, 4, and 14, respectively. The weight of the instruction data B8 is 0.

  Thus, there are various conditions that satisfy the simultaneous equation (1). The driving condition example 6 also seems appropriate from the number of display gradations, the number of instruction data, the number of gate wirings, and the like.

[Embodiment 4]
The following will describe still another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in any of Embodiments 1 to 3 are given the same reference numerals, and explanation thereof is omitted.

  The means for generating the blanking period by stopping the current flowing from the driving transistor to the electro-optical element according to the present invention is not only applicable to a display device that compensates the threshold voltage of the driving transistor during the blanking period. The present invention is generally applicable to display devices that perform blanking.

  As a display device according to still another embodiment of the present invention, means for generating a blanking period by stopping a current flowing from the driving transistor according to the present invention to the electro-optic element is provided in the blanking period. An example of a display device that does not include means for compensating the threshold voltage will be described.

  The display device of the present embodiment has the same configuration as that of the display device 1 except that the configuration of the pixel circuit Aij in the display device 1 of the first embodiment shown in FIG. 2 is changed. Since portions other than the pixel circuit Aij are the same as those of the display device 1, detailed description thereof is omitted.

  A pixel circuit Aij included in the display device of this embodiment is the pixel circuit Aij shown in FIG. As shown in FIG. 23, this pixel circuit Aij has the switching transistors 14 and 15 and the capacitor C2 removed from the pixel circuit Aij of the first embodiment shown in FIG. 1, and the drain terminal of the switching transistor 13 is directly connected to the capacitor. This is connected to one end of C1 and the gate terminal of the driving transistor 11.

  In the pixel circuit Aij, in a region where the source wiring Sj and the gate wiring Gi intersect, a driving transistor 11 (driving transistor), a switching transistor 13 (first switching transistor), and a switching transistor 12 (third transistor) A switching transistor), and an organic EL element EL1 (electro-optical element).

  Specifically, the driving transistor 11, the switching transistor 12, and the organic EL element EL1 are connected in series between the power supply wiring Vp (predetermined potential wiring) and the common wiring Vcom.

  Further, a capacitor C1 is disposed between the source and gate terminals of the driving transistor 11. A switching transistor 13 (first switching transistor) is disposed between the gate terminal of the driving transistor 11 and the source wiring Sj.

  The drive timing of the pixel circuit Aij is shown in FIG.

  The driving timing of the pixel circuit Aij is shown in FIG. 24 in the same manner as in FIG. The three waveforms shown in the upper part of FIG. 24 correspond to the pixel circuit A2j, and are the waveforms of 1) the scanning signal G2 and 2) the control wiring R2 in order from the top. Further, Sj shown in the center of FIG. 24 indicates the type of instruction data supplied to the source wiring Sj by a bit number. The two waveforms shown in the lower part of FIG. 24 correspond to the pixel circuit A3j, and are the waveforms of 3) the scanning signal G3 and 4) the control signal R3 in order from the top. In this case, the instruction data includes eight types of instruction data B1 to B8 (B is omitted in FIG. 24), as in FIG. FIG. 24 shows a case where the time-multiplex gradation driving method described in the first embodiment is adopted. Further, the time axis indicated by the horizontal axis in FIG. 24 indicates t1 corresponding to half the length of the occupation period as a unit.

  Pixel A2j enters the blanking period from time 14t1. At time 14t1, the control wiring R2 is set to High (GH), and the switching transistor 12 (p-type TFT) is turned off. As a result, the current flowing from the driving transistor 11 to the organic EL element EL1 is stopped. Therefore, in this case, a blanking period starting at time 14t1 is provided.

  The drive timing of FIG. 24 corresponds to the scanning condition of FIG. 7, so the blanking period is one selection period. At time 16t1, the control wiring R2 is set to Low (GL), and the switching transistor 12 is turned on. As a result, this blanking period ends.

  As described above, in the display device according to the present embodiment, the blanking operation can be performed by controlling the switch transistor 12 by the control wiring Ri, as in the display device according to the first embodiment. The data transfer frequency from the circuit to the source driver circuit 2 can be kept low. As a result, low power consumption can be achieved.

  Further, by using this pixel circuit Aij to drive at the drive timings shown in FIGS. 8 and 9, a display device having a large ratio of display periods existing in one frame period can be realized.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can also be expressed as follows.

[1] Corresponding to a combination of a plurality of gate wirings and at least one source wiring, the electro-optical element, the driving transistor (11), the first switching transistor (13), and the third switching transistor (12 ) Arranged,
Instruction data B1 to Ba corresponding to different driving transistors are supplied to the source wiring for every A (A is an integer of 2 or more), and the first switching transistor (13) controlled by the gate wiring. The instruction data B1 to Ba corresponding to each gate wiring is selected from the instruction data B1 to Ba output to the source wiring, the instruction data B1 to Ba is supplied to the driving transistor, and the output state of the driving transistor is selected. Is set A times in one frame period, and the third switching transistor (12) is controlled by a control wiring provided in parallel with the gate wiring, so that a current flowing from the driving transistor to the electro-optic element is controlled. A display device characterized by stopping.

  According to the above configuration, the operation (blanking) for stopping the current flowing from the driving transistor to the electro-optical element is performed by means for performing blanking (means for transferring blanking data to the panel) described in Patent Document 3. Unlike), it can be realized without transferring blanking data to the panel. As a result, since all the instruction data can be used for display, the weight of the instruction data having the highest weight can be reduced. As a result, the occurrence of a moving image false contour can be suppressed.

  [2] In the display device according to [1], a second switch transistor (14) is disposed between a gate terminal and a source terminal (or a drain terminal) of the driving transistor, and the electro-optic is connected to the driving transistor. The display device (FIGS. 1, 12, and 12) is characterized in that the second switching transistor is turned on during the period when the current flowing to the element is stopped to compensate for variations in threshold voltage of the driving transistor. 14 and FIG. 20).

  According to the display device, in the blanking period, the second switching transistor is turned on to set the gate potential of the driving transistor to the ON potential, and then the current flowing from the driving transistor to the electro-optic element is changed. The gate potential of the driving transistor can be changed from the ON potential to the OFF potential.

  As a result, the threshold compensation of the driving transistor can be performed during the blanking period, and a display device capable of compensating the threshold voltage of the driving transistor can be realized. That is, in this display device, the threshold voltage of the driving transistor can be compensated for during a non-display period (blanking period) outside the selection period, and it is not necessary to perform threshold compensation during the selection period.

  As a result, the selection period can be shortened and driving transistors corresponding to more data wirings can be controlled as compared with the pixel circuit configuration shown in the prior art (Patent Document 1: Japanese Translation of PCT International Publication No. 2002-514320).

  [3] In the display device of [2], a first capacitor (C1) and a second capacitor (C2) are connected to a gate terminal of the driving transistor (11), and the second capacitor (C2). Are connected to the first switching transistor (13) and the fourth switching transistor (15), and the other terminal of the second capacitor (C2) is connected to the fourth switching transistor (15). To the predetermined potential wiring, and during the period when the second switch transistor (14) is in the ON state, the current flowing from the drive transistor (11) to the electro-optical element is stopped, and the drive transistor (11 ) Is compensated for variations in threshold voltage (corresponding to FIG. 1).

  According to the configuration, in the blanking period, the fourth switching transistor (15) is turned on, a predetermined potential (power supply voltage Vp) is applied to the other terminal of the second capacitor (C2), and the second The switching transistor (14) is turned on so that the gate and drain of the driving transistor (11) can be short-circuited.

  At this time, since the third switching transistor (12) is in the ON state, the gate potential of the driving transistor (11) becomes the ON potential.

  Thereafter, by turning off the third switching transistor (12), the gate-source potential of the driving transistor (11) gradually changes, and the driving transistor (11) changes from the ON state to the OFF state. Become.

  Then, by turning off the second switch transistor (14) and turning off the fourth switch transistor (15), when the other terminal of the second capacitor (C2) is at the predetermined potential, The gate-source potential of the driving transistor (11) can be set to a threshold potential.

  After that, if the first switching transistor (13) is turned on and a desired potential is applied to the other terminal of the second capacitor (C2), the driving transistor (11) is independent of the threshold potential of the driving transistor (11). 11) The output current can be set.

  As described above, according to the pixel circuit configuration, it is possible to compensate the threshold value of the driving transistor by applying a predetermined potential to the second capacitor during the blanking period which is a non-display period outside the selection period. Thus, by applying a potential based on the predetermined potential from the source wiring during the selection period, the output current can be set regardless of the threshold potential of the driving transistor.

  [4] In the display device of [2], a first capacitor (C3) and a second capacitor (C4) are connected to a gate terminal of the driving transistor (16), and the second capacitor (C4). Are connected to the first switching transistor (13) and the fifth switching transistor (20), and the other terminal of the second capacitor (C4) is connected to the fifth switching transistor (20). Is connected to the gate terminal of the driving transistor (16), and the current flowing from the driving transistor (16) to the electro-optical element is stopped while the second switching transistor (19) is in the ON state. A display device (corresponding to FIG. 12), which compensates for variations in the threshold voltage of the driving transistor (16).

  According to the above configuration, in the blanking period, the fifth switching transistor (20) is turned on, and the other terminal of the second capacitor (C4) is connected to the gate terminal of the driving transistor (16). The second switch transistor (19) is turned on to short-circuit the gate-drain potential of the drive transistor (16).

  At this time, since the third switching transistor (17) is in the ON state, the gate potential of the driving transistor (16) is in the ON state.

  Thereafter, the potential at both ends of the second capacitor (C4) is maintained by turning off the fifth switching transistor (20).

  Thereafter, by turning off the third switching transistor (17), the gate-source potential of the driving transistor (16) gradually changes, and the driving transistor (16) changes from the ON state to the OFF state. Become.

  Thereafter, the second switch transistor (19) is turned off.

  Thus, if the potential (for example, the power supply potential) supplied to the other terminal of the second capacitor (C4) in the above period is supplied to the other terminal of the second capacitor (C4), the driving transistor (11) The gate potential can be set to be the threshold potential.

  After that, if the first switching transistor (13) is turned on and a desired potential is applied to the other terminal of the second capacitor (C4), the output current is reduced regardless of the threshold potential of the driving transistor (16). Can be set.

  As described above, according to the pixel circuit configuration, it is possible to compensate the threshold value of the driving transistor by applying a predetermined potential to the second capacitor during the blanking period which is a non-display period outside the driving period. Thus, by applying a potential based on the predetermined potential from the source wiring during the driving period, the output current can be set regardless of the threshold potential of the driving transistor.

  [5] In the display device of [2], the first capacitor (C3) and the second capacitor (C4) are connected to the gate terminal of the driving transistor (16), and the second capacitor (C4). The other terminal of the second capacitor (C4) is connected to the source line through the first switch transistor (13), and the second switch transistor (13) is connected to the other terminal. The switching transistor (19) is turned on, the charge of the second capacitor (C4) is set, and during the period in which the other terminal of the second capacitor (C4) is open, the driving transistor ( 16), the current flowing from the electro-optical element to the electro-optic element is stopped, and the variation in threshold voltage of the driving transistor (16) is compensated (FIG. 14). Correspondence).

  According to the above configuration, the first switching transistor (13) is turned on, the other terminal of the second capacitor (C4) is connected to the source line Sj, and the second switching transistor (19) is turned on. By setting the state, the charge of the second capacitor (C4) can be set.

  Thereafter, the first switching transistor (13) is turned off to hold the potential difference at the above time in the second capacitor (C4).

  If the third switching transistor (17) is turned on, the gate potential of the driving transistor (11) is turned on.

  Thereafter, by turning off the third switching transistor (17), the gate-source potential of the driving transistor (16) gradually changes, and the driving transistor (16) changes from the ON state to the OFF state. Become.

  After that, if the first switching transistor (13) is turned on and a desired potential is applied to the other terminal of the second capacitor (C4), the output current is reduced regardless of the threshold potential of the driving transistor (16). Can be set.

  As described above, according to the pixel circuit configuration, it is possible to compensate the threshold value of the driving transistor by applying a predetermined potential to the second capacitor during the blanking period which is a non-display period outside the selection period. Thus, by applying a potential based on the predetermined potential from the source wiring during the selection period, the output current can be set regardless of the threshold potential of the driving transistor.

  Furthermore, if the pixel circuit configuration is used, the fourth switching transistor is not necessary, and the number of transistors per pixel circuit can be reduced. As a result, high aperture ratio and high definition can be achieved.

[6] A driving method of a display device in which an electro-optic element and a driving transistor are arranged corresponding to a combination of n (n is an integer of 2 or more) gate wirings and at least one source wiring,
Instruction data B1 to Ba corresponding to different driving transistors are supplied to the source wiring for every A (A is an integer of 2 or more), and the instruction data B1 to Ba output to the source wiring is supplied by the gate wiring. The instruction data B1 to Ba corresponding to the driving transistor is selected, the instruction data B1 to Ba is supplied to the driving transistor, and the output state of the driving transistor is set A times in one frame period. When the weights of the instruction data B1 to Ba are W1 to Wa, a period Wb in which the current flowing from the driving transistor to the electro-optical element is stopped by a control wiring provided in parallel with the gate wiring is Wb = n × A − (W1 +... + Wa) × k
(K is an integer greater than or equal to 1 and not an integer multiple of A).

  According to the above method, the instruction data B1 to Ba can be supplied to all the pixels sharing one source wiring at a timing that does not overlap each other.

  Further, according to the above method, by providing the period (blanking period) Wb for stopping the current flowing from the driving transistor to the electro-optic element, one frame period n × A and the gradation display period (W1 +... The difference of + Wa) × k can be filled.

  In the above method, a blanking period can be provided a plurality of times in one frame period. However, by providing a blanking period once in one frame period, the time-multiplex gradation driving method shown in the prior art (Patent Document) 2: The non-display period can be made shorter than the driving method disclosed in JP-A-9-511589.

  As a result, the luminance of the light emission period within one frame can be set relatively low (as the non-display period is shortened), so that the life of the electro-optic element can be extended.

  INDUSTRIAL APPLICABILITY The present invention can be used for a display device using a current-driven electro-optical element such as an organic EL display or FED and a driving method thereof, and thereby, without increasing the driving period, the threshold value of the driving transistor. Benefits such as the ability to compensate for uneven brightness due to voltage variations are obtained.

4 is a circuit diagram illustrating a pixel circuit configuration in the display device according to Embodiment 1. FIG. It is a circuit diagram which shows the structure of the display apparatus which concerns on Embodiment 1-4. It is a wave form diagram which shows the operation timing of the said pixel circuit and a drive circuit. 5 is a graph showing a result of simulating changes in a gate potential Vg, a drain potential Vd, and a source-drain current Id of a driving transistor in the pixel circuit. It is a graph which shows the simulation result of the electric current value which flows through an organic EL element in the said pixel circuit. It is a figure which shows the scanning conditions which show the order and weight of each instruction | indication data which are the Example of the drive method of this invention. It is a figure which shows the scanning conditions when the scanning conditions of FIG. 6 are made to respond | correspond to the number of 8 gate wiring. It is a wave form diagram which shows the operation timing on the said scanning conditions. It is a wave form diagram which shows the operation timing on the said scanning conditions. It is a figure which shows the example of the scanning conditions which show the order and weight of each instruction | indication data which are the examples of the drive method of this invention shown in Embodiment 1. FIG. It is a figure which shows another example of the scanning conditions which show the order and weight of each instruction | indication data which are the examples of the drive method of this invention shown in Embodiment. FIG. 6 is a circuit diagram illustrating a pixel circuit configuration in a display device according to a second embodiment. It is a wave form diagram which shows the operation timing of the said pixel circuit and a drive circuit. 6 is a circuit diagram illustrating a pixel circuit configuration in a display device according to Embodiment 3. FIG. It is a wave form diagram which shows the operation timing of the said pixel circuit and a drive circuit. 6 is a graph showing a result of simulating changes in a gate potential Vg, a source potential Vs, and a source-drain current Id of a driving transistor in the pixel circuit. It is a figure which shows the scanning condition which shows the order and weight of each instruction | indication data which are the Examples of the drive method of this invention used in Embodiment 3. FIG. It is a wave form diagram which shows the operation timing on the said scanning conditions. It is a wave form diagram which shows the operation timing on the said scanning conditions. FIG. 18 is a diagram showing at which gradation each bit is turned on under the scanning condition of FIG. 17. FIG. 10 is a diagram showing another scanning condition shown in the third embodiment. 12 is a circuit diagram illustrating another pixel circuit configuration in a display device according to Embodiment 3. FIG. FIG. 6 is a circuit diagram illustrating a pixel circuit configuration in a display device according to a fourth embodiment. It is a wave form diagram which shows the operation timing of the said pixel circuit and a drive circuit. It is a circuit diagram which shows the structural example of the pixel circuit in the conventional display apparatus. It is a drive timing diagram which shows the example of a timing of the drive method in the conventional display apparatus. FIG. 27 is a voltage timing diagram showing an actual voltage waveform of the drive timing shown in FIG. 26.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Source driver circuit 3a Gate driver circuit 3b Gate driver circuit 4 Shift register circuit 5 Register 6 Latch circuit 7 Analog switch circuit (instruction data supply means)
11 driving transistor 12 switching transistor (blanking means, third switching transistor)
13 Switch transistor (first switch transistor)
14 Switch transistor (second switch transistor)
15 Switch transistor (fourth switch transistor)
16 driving transistor 17 switching transistor (blanking means, third switching transistor)
19 Switch transistor (second switch transistor)
20 switch transistor (fifth switch transistor)
C1 capacitor (potential difference holding means, first capacitor)
C2 capacitor (potential difference holding means, second capacitor)
C3 capacitor (potential difference holding means, first capacitor)
C4 capacitor (second capacitor)
EL1 Organic EL element (electro-optic element)
Aij pixel circuit Sj source wiring Gi gate wiring Ri control wiring (blanking means)
Pi control wiring Vp power supply wiring (predetermined potential wiring)

Claims (11)

A plurality of gate wirings to which scanning signals are supplied;
At least one source line to which data for display is supplied;
An electro-optic element provided corresponding to a combination of the plurality of gate wirings and the at least one source wiring and driven by a current supplied from a power source;
Conduction is controlled by a scanning signal supplied to the gate wiring, and a first switch transistor that outputs data from the source wiring when conducting,
A driving transistor that is interposed between the power source and the electro-optic element, and controls the supply of current from the power source to the electro-optic element according to data output from the first switch transistor;
Blanking means for performing blanking to erase the display of the electro-optic element;
A control wiring provided in parallel with the gate wiring and controlling the blanking means;
For the second switch for short-circuiting the gate terminal and the source terminal or the drain terminal of the driving transistor in order to compensate for variations in threshold voltage of the driving transistor during the blanking period in which the blanking is performed A display device comprising a transistor. The blanking means is
And a third switch transistor which is inserted between the driving transistor and the electro-optical element and is controlled by the control wiring to stop a current flowing from the driving transistor to the electro-optical element. The display device according to claim 1. A potential difference holding means for holding a potential difference between the gate terminal and the source terminal or drain terminal of the driving transistor;
The third switching transistor shifts from the ON state to the OFF state during the period in which the second switching transistor is in the ON state in order to compensate for the variation in the threshold voltage of the driving transistor. 3. A display device according to claim 2, wherein a current flowing from the transistor to the electro-optic element is stopped. The potential difference holding means is
A first capacitor having one end connected to the gate terminal of the driving transistor and the other end connected to the source terminal or drain terminal of the driving transistor;
A second capacitor having one end connected to the gate terminal of the driving transistor and the other end connected to the first switching transistor;
4. A fourth switch transistor for connecting the other end of the second capacitor to a predetermined potential wiring during a period in which the second switch transistor is in an ON state. Item 4. The display device according to Item 3. The potential difference holding means is
A first capacitor having one end connected to the gate terminal of the driving transistor and the other end connected to the source terminal or drain terminal of the driving transistor;
A second capacitor having one end connected to the gate terminal of the driving transistor and the other end connected to the first switching transistor;
A fifth switching transistor for connecting the other end of the second capacitor to the gate terminal of the driving transistor during a period in which the second switching transistor is in an ON state; The display device according to claim 3. The potential difference holding means is
A first capacitor having one end connected to the gate terminal of the driving transistor and the other end connected to the source terminal or drain terminal of the driving transistor;
A second capacitor having one end connected to the gate terminal of the driving transistor and the other end connected to the first switching transistor;
The first switch transistor sets the charge of the second capacitor by connecting the other end of the second capacitor to a source line during a period in which the third switch transistor is OFF. The display device according to claim 3, wherein the display device is configured as described above. Instruction data for instructing the output state of each driving transistor sharing the source wiring with respect to the source wiring is A for each driving transistor sharing the source wiring (A is an integer of 2 or more). ) Further comprising instruction data supply means for supplying
The first switch transistor selects instruction data corresponding to the driving transistor from instruction data output to the source wiring in accordance with the scanning signal, and supplies the instruction data to the driving transistor. 7. A display device according to claim 1, wherein the display state of the optical element is set A times in one frame period.   8. The display device according to claim 7, wherein the blanking period is set after a display period of specific instruction data. The instruction data supply means supplies the instruction data of the same number corresponding to a plurality of different gate wirings among the instruction data to the source wiring at a constant cycle,
When the weights of the A pieces of instruction data are W1 to Wa (W1 to Wa are integers of 1 or more), the weights W1 to Wa _-1 are
MOD (W1, A) ≠ 0
MOD (W1 + W2, A) ≠ 0
MOD (W1 + W2, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ 0
MOD (W1 + W2 + W3, A) ≠ MOD (W1, A)
MOD (W1 + W2 + W3, A) ≠ MOD (W1 + W2, A)
...
MOD (W1 +... + W _a-1 , A) ≠ MOD (W1 +... + W _a-2 , A)
(However, MOD (x, y) indicates the remainder when x is divided by y)
And the weight Wa is
Wa = (number of gradations to be displayed) − (W1 +... + W _a−1 ) −1
When the number of gate wirings is n, the time Wb for stopping the current flowing from the driving transistor to the electro-optical element is
Wb = n × A− (W1 +... + Wa) × m
(M is an integer greater than or equal to 1 and not a multiple of A)
The display device according to claim 8, wherein the display device is set to be A plurality of gate wirings to which scanning signals are supplied;
At least one source line to which data for display is supplied;
An electro-optic element provided corresponding to a combination of the plurality of gate wirings and the at least one source wiring and driven by a current supplied from a power source;
Conduction is controlled by a scanning signal supplied to the gate wiring, and a first switch transistor that outputs data from the source wiring when conducting,
A driving transistor that is interposed between the power source and the electro-optic element, and controls the supply of current from the power source to the electro-optic element according to data output from the first switch transistor;
A driving method of a display device comprising: a second switching transistor disposed between a gate terminal and a source terminal or a drain terminal of the driving transistor,
After the second switch transistor is turned on, blanking for erasing the display of the electro-optic element is performed during a period in which the second switch transistor is in the on state. A driving method characterized by compensating for variations in the above. A plurality of gate wirings to which scanning signals are supplied;
At least one source line to which data for display is supplied;
An electro-optic element provided corresponding to a combination of the plurality of gate wirings and the at least one source wiring and driven by a current supplied from a power source;
Conduction is controlled by a scanning signal supplied to the gate wiring, and a first switch transistor that outputs data from the source wiring when conducting,
A driving transistor that is interposed between the power source and the electro-optic element and controls the supply of current from the power source to the electro-optic element in accordance with data output from the first switch transistor; A driving method of a display device,
Instruction data for instructing the output state of each driving transistor sharing the source wiring with respect to the source wiring is A for each driving transistor sharing the source wiring (A is an integer of 2 or more). )
By supplying a scanning signal to the gate wiring, the first switching transistor is caused to select instruction data corresponding to the driving transistor from the instruction data output to the source wiring. To the transistor, thereby setting the display state of the electro-optic element A times in one frame period;
Blanking is performed to erase the display of the electro-optic element by controlling blanking means by a control wiring provided in parallel with the gate wiring after a display period of specific instruction data among the instruction data. Driving method.

Images