JP2006015700A - Image formation device and controlling method for this device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the power consumption of an image formation device lowered while suppressing the cost increase for production to a minimum. <P>SOLUTION: When information indicating a specific mode is received from a video controller 27 through a video-interface communication circuit 101, CLKEN control circuit 102 is controlled so that a CPU 106 may stop a clock GCLK 109 to another circuit 110. If information representing another mode is received with the state that the clock to the video-interface communication circuit 101 is kept as it is, the controlling is performed so that the clock stop may be canceled. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to energy saving control in an image forming apparatus such as a printer or a copier that has an interface with an external device such as a computer and forms an image on recording paper based on image information input from the external device through the interface. Is.

  Conventionally, this type of image forming apparatus has a plurality of operation states as follows.

  The first is a printing state, in which recording paper is conveyed and the printing operation is performed.

  The second is a standby state in which printing can be performed immediately. For example, in the case of an electrophotographic printer, in the case of thermal fixing using a halogen heater, temperature control is performed so that the fixing temperature during printing or a slightly lower temperature is maintained during standby. Some printers that use an ink jet printer or an on-demand fixing device do not have this standby state.

  The third is a sleep state, which is a state provided for energy saving. In this state, the power consumption is further reduced compared to the standby mode. In this sleep state, for example, the power consumption for the actuator is stopped, or the power supply for various sensors is stopped to achieve low power consumption.

  Incidentally, some printers include an image processing unit that generates an image signal based on image information from an external device and an image forming unit that forms an image based on the image signal. State control is performed by the image forming means. Further, the transition to the sleep state and the instruction to return from the sleep state are made from the image processing unit to the image forming unit based on information from the external device.

  When such an image forming apparatus is used in a normal office or the like, the state in which no image is formed is often longer than the state in which the image is formed, and the power consumption is required to be lower in the sleep state. It has been. For this reason, a configuration has been proposed in which not only the unnecessary power supply is stopped, but also the clock of the CPU of the image forming unit is stopped in the sleep state, thereby reducing the power consumption (for example, see Patent Document 1).

Also, as a method of activating the CPU clock again when returning from the sleep state, a method is disclosed in which the activation signal line output from the image processing means and input to the image forming means is used. Specifically, the recovery from the sleep state is realized by connecting the activation signal line to the non-maskable interrupt port of the CPU or to the reset port.
JP 07-336486 A

  However, the method described in Patent Document 1 has a drawback in that the number of signal lines between the image processing unit and the image forming unit increases, the number of pins of the connector and cable increases, and the cost increases.

  An object of the present invention is to minimize the increase in production cost and to reduce the power consumption of an image forming apparatus.

  The present invention is an image forming apparatus comprising: an image processing unit that generates an image signal based on image information from an external device; and an image forming unit that forms an image based on the generated image signal. The forming unit includes a clock control unit that controls a clock supplied to a circuit of the image forming unit, and a communication unit that communicates information with the image processing unit, and the clock control unit includes the communication unit When information indicating a specific mode is received from the image processing unit via the means, control is performed such that the clock to the communication means is maintained and the clock to other circuits is stopped.

  The present invention also provides an image forming apparatus control method comprising: an image processing unit that generates an image signal based on image information from an external device; and an image forming unit that forms an image based on the generated image signal. A clock control step for controlling a clock supplied to a circuit of the image forming unit, and a communication step for communicating information with the image processing unit, wherein the clock control step includes the communication step. When the information indicating the specific mode is received from the image processing unit, control is performed such that communication in the communication process is maintained and clocks to other circuits are stopped.

  According to the present invention, it is possible to minimize an increase in production cost and to reduce power consumption of the image forming apparatus.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings. In this embodiment, a laser beam printer that forms an image by an electrophotographic method will be described as an example of the image forming apparatus. However, the present invention is not limited to this, and can be applied to a copying machine and a facsimile apparatus.

  In the first embodiment, a case will be described in which a clock supplied to a circuit other than video interface communication is stopped in a control IC of an engine controller in a laser beam printer to achieve low power consumption.

  FIG. 1 is a cross-sectional view illustrating a schematic configuration of the laser beam printer according to the first embodiment. As shown in FIG. 1, a printer main body (hereinafter referred to as a main body) 1 includes a cassette 2 that stores recording paper S, and is provided with rollers 5 that feed and transport the recording paper S from the cassette 2. An image developing unit 8 that forms a toner image on the recording paper S based on the laser beam from the laser scanner unit 7 is provided downstream of the paper feed roller 5. Further, a fixing device 9 for thermally fixing a toner image formed on the recording paper S is provided downstream of the image developing unit 8, and the recording paper S on which recording has been completed is provided downstream of the fixing device 9. A paper discharge tray 12 is provided.

  The engine controller 26 controls the electrophotographic process by the laser scanner unit 7, the image developing unit 8, and the fixing unit 9, and controls the conveyance of the recording paper in the main body 1.

  The video controller 27 is connected to an external device 31 such as a computer through a general-purpose interface (USB, 10BASE-T, etc.). The video controller 27 develops image information sent through the general-purpose interface 30 into bit data, and the bit Data is sent to the engine controller 26 as a video signal. Further, the image information sent through the general-purpose interface 30 may be bit data or compressed data obtained by compressing bit data after being subjected to image processing by the external device 31 in advance.

  The video interface 28 functions as a communication means between the video controller 27 and the engine controller 26.

  FIG. 2 is a diagram illustrating a configuration of the video interface 28 according to the first embodiment. In FIG. 2, SCMDCK, SCMD, SSTSCK, and SSTS are signal lines for serial communication between the video controller 27 and the engine controller 26. Note that the video controller 27 and the engine controller 26 perform full-duplex serial communication.

  First, SCMDCK is a synchronous clock for serial communication, and is sent from the video controller 27 to the engine controller 26. The next SCMD is a data signal from the video controller 27 of serial communication to the engine controller 26, and is transmitted in synchronization with the SCMDCK. Here, the data is command data indicating an instruction from the video controller 27 to the engine controller 26.

  Next, SSTSCK is a synchronous clock for serial communication, and is sent from the engine controller 26 to the video controller 27. The next SSTS is a data signal from the engine controller 26 of the serial communication to the video controller 27, and is transmitted in synchronization with SSTSCK. Here, the data is status data indicating the internal state of the engine unit. The command data and status data described above are both 16-bit data.

  Next, VSYNC is a vertical synchronization signal that synchronizes the image output sent from the engine controller 26 to the video controller 27 in the vertical direction (paper transport direction). HSYNC is a horizontal synchronization signal that synchronizes the image output sent from the engine controller 26 to the video controller 27 in the horizontal direction (beam scanning direction).

  Finally, VDO is an image signal in which the video controller 27 sends a dot image serially to the engine controller 26 in synchronization with the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC.

  Here, an image forming process based on serial communication between the video controller 27 having the above-described configuration and the engine controller 26 will be described.

  First, when power is turned on to the main body 1 and initialization of the video controller 27 is completed and serial communication is possible, the video controller 27 is serially connected to the engine controller 26 with SCMDCK and SCMD (hereinafter, command communication line). Data indicating that communication is possible is transmitted.

  On the other hand, upon receiving command data from the video controller 27, the engine controller 26 transmits the current internal state of the engine to the video controller 27 using SSTSCK and SSTS (hereinafter, status signal line).

  Here, when the above-described stator data is transmitted from the engine controller 26 within a certain time, the video controller 27 determines that the engine unit is in an operable state, and the status data is transmitted within the certain time. If not, the engine controller 26 determines that serial communication is not possible, and transmits command data again after a predetermined time.

  The video controller 27 requests the engine controller 26 for a status as to whether or not the engine unit can be printed on the command communication line at regular intervals, and in response to this request, whether or not the engine controller 26 can print on the status communication line Returns the status.

  After that, when printing is possible, the video controller 27 is ready to accept a print request from an external device 31 such as a computer. When the print request is received, the image information is developed into a dot image. When the development process is completed, the video controller transmits a print start command to the engine controller 26 via the 27 command communication line.

  On the other hand, when receiving the print start command, the engine controller 26 feeds and transports the recording paper S by the roller 5. When the leading end position of the recording paper S reaches a specific position, the engine controller 26 sets the vertical synchronization signal VSYNC to TRUE. Thus, when the video controller 27 confirms TRUE of the vertical synchronization signal VSYNC, the video controller 27 starts outputting the image signal VDO after a predetermined time.

  During printing, the engine controller 26 sends a horizontal synchronization signal HSYNC to the video controller 27 at a predetermined timing synchronized with the laser beam scanning, and modulates the laser beam emitted from the laser scanner 7 based on the image signal VDO. The image developing unit 8 forms a latent image with a density corresponding to the intensity of the laser beam, and the latent image is transferred to the recording paper S. After the recording paper S passes through the image developing unit 8, the image is fixed by the fixing device 9 and loaded on the paper discharge tray 12.

  Normally, the printer main body 1 is in a standby state or a sleep state except for an abnormal state such as the occurrence of a failure other than the print state. In other words, the standby state is a state in which if there is a print request, it can immediately shift to the print state. Specifically, the temperature of the fixing device 9 is controlled to a temperature lower than the temperature during the printing operation. However, in the case of on-demand fixing, temperature control during standby of the fixing device 9 is not necessary.

  On the other hand, the sleep state is a state in which power consumption is reduced as compared with the above-described standby state. In the sleep state, low power consumption is achieved by stopping the power source used for driving the actuator and the power source used for laser driving or sensors. In addition, the backlight of the display unit of the control panel is also turned off.

  In the first embodiment, the transition from the standby state to the sleep state is performed based on a specific command sent from the video controller 27 to the engine controller 26 through the video interface 28.

  Next, the configuration and operation of the engine controller 26 that changes the state of the engine unit based on commands sent from the video controller 27 will be described.

  FIG. 3 is a diagram illustrating a configuration of the engine controller 26 according to the first embodiment. As shown in FIG. 3, the engine controller 26 includes an ASIC 113 that is a control IC, a CPU 106, and an oscillator 105. The ASIC 113 and the CPU 106 are connected via a CPU bus 112, and the oscillator 105 supplies a clock to the ASIC 113 and the CPU 106.

  The ASIC 113 includes a video interface communication circuit 101 that controls serial communication with the video controller 27, a CPU interface circuit 104 that controls communication with the CPU 106, and a gated clock circuit that generates a gated clock GCLK 109 to be supplied to other circuits 110. 103, a CLKEN control circuit 102 that controls enable / disable of the gated clock circuit 103, and other circuits 110.

  The other circuit 110 is a circuit that controls the laser scanner 7, the image developing unit 8, the fixing device 9, and the like shown in FIG. 1.

  The above-described CPU interface circuit 104 is connected to the CPU 106 via the CPU bus 112, and reads / writes registers in the ASIC 113 based on communication from the CPU 106. It is assumed that the registers exist in the video interface communication circuit 101, the CLKEN control circuit 102, and other circuits 110, respectively. The CPU interface circuit 104 and these registers are connected by an internal bus 111 of the ASIC 113.

  The clock CLK 107 output from the oscillator 105 is supplied to the video interface communication circuit 101, CLKEN control circuit 102, gated clock circuit 103, CPU interface circuit 104, and CPU 106 of the ASIC 113. The gated clock GCLK 109 generated by the gated clock circuit 103 is supplied as a clock for the other circuit 110.

  Here, the control of the gated clock GCLK 109 generated by the gated clock circuit 103 and supplied to the other circuit 110 will be described.

  First, when the CPU 106 writes “1” to the CLKEN register in the CLKEN control circuit 102 via the CPU bus 112, the CPU interface circuit 104, and the internal bus 111, the gated clock control signal CLKEN 108 becomes “1”. Here, it is assumed that the value of the CLKEN register always matches the value of the gated clock control signal CLKEN108.

  Next, when CLKEN 108 becomes “1”, the gate of the latch 113 in the gated clock circuit 103 opens at the timing when the CLK 107 becomes Low, and the AND gate 114 in the gated clock circuit 103 becomes transparent to the CLK 107, and the CLK 107 A GCLK 109 synchronized with the above is generated. On the other hand, when “0” is written to the CLKEN register by the CPU 106, the AND gate 114 in the gated clock circuit 103 is closed at the timing when the CLK 107 becomes Low, and the GCLK 109 is stopped at “0”.

  Since CLKEN 108 that matches the register value operates in synchronism with CLK 107, no glitch appears on GCLK 109.

  Since the clock CLK 107 is always output from the oscillator 105, the video interface communication circuit 101, the CLKEN control circuit 102, and the CPU interface circuit 104 are always operating.

  On the other hand, in the other circuit 110 operating at GCLK 109, the clock supply is stopped by writing “0” from the CPU 106 to the CLKEN register in the CLKEN control circuit 102, and the laser scanner of the engine unit controlled by the other circuit 110. 7. The operations of the image developing unit 8 and the fixing device 9 can be stopped.

  FIG. 4 is a diagram illustrating a configuration of the video interface communication circuit 101 according to the first embodiment. As shown in FIG. 4, the video interface communication circuit 101 is mainly composed of a communication circuit 135 and a register 130. The register 130 can be read and written from the CPU 106 via the CPU bus 112, the CPU interface circuit 104, and the internal bus 111. Then, the communication circuit 135 controls serial communication with the video controller 27 according to the setting of the register 130.

  The register 130 includes a reception data register 131, a reception flag register 132, and the like. The reception data register 131 stores data received from the video controller 27. The reception flag register 132 stores “1” when data is received from the video controller 27. That is, the CPU 106 polls the reception flag register 132, reads the data stored in the reception data register 131 when it becomes “1”, and then sets the reception flag register 132 to “0”.

  Next, processing for changing the state of the engine unit from the standby state to the sleep state will be described.

  First, when the engine controller 26 receives a command to shift to the sleep state from the video controller 27 via the video interface 28, the CPU 106 of the engine controller 26 receives the video interface via the CPU bus 112, the CPU interface circuit 104, and the internal bus 111. By reading a command stored in the reception data register 131 in the communication circuit 101 and stopping the power supply of the fixing device 9, the power supply for driving the actuator, the power supply for the laser drive and the sensor based on the command, the power consumption Reduce. Further, if the power supply has a mode for increasing the power supply efficiency at the time of low power consumption such as a low power consumption mode, the mode is shifted to that mode.

  Next, the CPU 106 writes “0” to the CLKEN register in the CLKEN control circuit 102 via the CPU bus 112, the CPU interface circuit 104, and the internal bus 111. Here, CLKEN 108 becomes “0”, and the gated clock GCLK 109 stops at “0”. As a result, the clock supply to the flip-flops in the other circuits 110 is interrupted, so that the power consumption by the flip-flops is almost “0”. Further, since the signal of the clock buffer driving GCLK 109 does not change, the power consumption of the clock buffer is also reduced.

  Next, the operation of the engine controller 26 that has transitioned to the sleep state will be described.

  During sleep, the CPU 106 polls the reception flag register 132 at regular intervals. If the reception flag register 132 is “0”, the CPU 106 maintains the sleep state as it is. If the reception flag register 132 is “1”, the data stored in the reception data register 131 is read. If a command that needs to be changed from the sleep state to the standby state or the print state is received, the sleep state is changed to the required state by an operation described later. If the data (command) is a command that can be maintained in the sleep state, the sleep state is maintained as it is.

  However, depending on the command, the status is returned to the video controller 27 as necessary. In addition, after the data in the reception data register 131 is read, “0” is written in the reception flag register 132.

  Next, an operation for shifting from the sleep state to the standby state or the print state will be described.

  As described above, when it is necessary to shift from the sleep state to the standby state or the print state, the CPU 106 writes “1” in the register CLKEN in the CLKEN control circuit 102. As a result, CLKEN 108 becomes “1”, the gate in the gated clock circuit 103 opens, and the clock GCLK 109 becomes a clock synchronized with the clock CLK 107. As a result, the clock is supplied to the flip-flops in the other circuit 110, and the laser scanner 7, the image developing unit 8, the fixing device 9 and the like controlled by the other circuit 110 are put into operation.

  Next, a transition is made to the standby state or the print state by starting up various power sources that were stopped when the sleep state was entered, or performing other necessary operations.

  In the first embodiment described above, an image forming apparatus using an electrophotographic process such as a laser beam printer has been described. However, even in other printers such as an ink jet printer, an image processing portion and an image are recorded on paper or the like. The present invention can be applied to any image forming apparatus that is divided into portions that are connected to each other by communication.

  Further, the clock supply to the watchdog timer for detecting the CPU runaway or the like during sleep may be configured not to stop. The watchdog timer constantly counts up, and the CPU periodically monitors the operation of the CPU by clearing the watchdog timer. If the watchdog timer is not cleared for a certain time or more, it is detected that the CPU is running out of control, and a signal for resetting the CPU is activated for a certain period to reset the CPU.

  As described above, since the watchdog timer monitors the runaway of the CPU, it may be better to operate it even during sleep depending on the system configuration. In that case, the clock dock timer circuit may be configured to continue to supply a clock even during sleep as described above. Not only the watchdog timer but also a circuit that needs to operate even during sleep may be configured to continue supplying a clock even during sleep.

  According to the first embodiment, in the sleep state, it is possible to cut off the clock supply except for necessary circuits such as the video interface communication circuit 101 and the CPU 106 in the ASIC 113. Further, the clock of the ASIC 113 can be operated in accordance with a command transmitted from the video controller 27. Thereby, power consumption during sleep can be reduced, and low power consumption can be realized.

  Further, it is not necessary to provide a dedicated signal line for the sleep state between the video controller 27 and the engine controller 26, and this can be realized without an increase in cost due to a connector or a cable.

  Next, Embodiment 2 according to the present invention will be described in detail with reference to the drawings. In the second embodiment, the video interface communication circuit and the CPU are built in one IC, the supply of clocks to other than the video interface communication circuit and the CPU core is stopped, and the clock frequency of the CPU core is switched to a low frequency. Is.

  The configurations of the image forming apparatus and the video interface in the second embodiment are the same as those in the first embodiment described with reference to FIGS. 1 and 2, and the description thereof is omitted.

  Here, the configuration and operation of the engine controller 26 that changes the state of the engine unit based on a command sent from the video controller 27 will be described.

  FIG. 5 is a diagram illustrating a configuration of the engine controller 26 according to the second embodiment. In FIG. 5, the same elements as those in FIG.

  First, the difference from the configuration shown in FIG. 3 is that a CPU core 206 is built in the ASIC 113 instead of the CPU 106. As a result, since the internal bus 111 is completed inside the ASIC 113, the pins for the CPU bus 112 become unnecessary, the number of pins of the ASIC 113 can be reduced, the package can be reduced, and the cost of the ASIC can be reduced. Can be planned.

  Another difference in configuration is that the clock of the CPU core 206 is supplied by the PLL 221. The PLL 221 can control the clock frequency by the control signal 220 output from the CPU core 206. Depending on the state of the control signal 220, the frequency of the clock 222 output from the PLL 221 is smaller than the normal frequency and the normal frequency. A low frequency which is a frequency can be selected.

  Next, the operation of the engine controller 26 will be described.

  The control of the gated clock GCLK 109 of the second embodiment is performed by the CPU core 206 as in the first embodiment.

  In the print state or standby state, the CPU core 206 performs control so that the normal frequency clock 222 is output from the PLL 221 via the control signal 220.

  Next, processing for changing the state of the engine unit from the standby state to the sleep state will be described.

  First, when the engine controller 26 receives a command to shift to the sleep state from the video controller 27 via the video interface 28, the CPU core 206 of the engine controller 26 receives the received data in the video interface communication circuit 101 via the internal bus 111. The command stored in the register 131 is read, and the power consumption of the fixing device 9, the power source for driving the actuator, the power source for the laser beam and the sensor, etc. are stopped based on the command, thereby reducing the power consumption. Further, if the power supply has a mode for increasing the power supply efficiency at the time of low power consumption such as a low power consumption mode, the mode is shifted to that mode.

  Next, the CPU core 206 writes “0” to the CLKEN register in the CLKEN control circuit 102 via the internal bus 111. Here, CLKEN 108 becomes “0”, and the gated clock GCLK 109 stops at “0”. As a result, the clock supply to the flip-flops in the other circuits 110 is interrupted, so that the power consumption by the flip-flops is almost “0”. Further, since the signal of the clock buffer driving GCLK 109 does not change, the power consumption of the clock buffer is also reduced.

  In order to reduce the power of the CPU core 206, the CPU core 206 switches the frequency of the output clock 222 of the PLL 221 to a low frequency via the control signal 220.

  Next, the operation of the engine controller 26 that has transitioned to the sleep state will be described.

  During sleep, the CPU core 206 polls the reception flag register 132 at regular intervals. If the reception flag register 132 is “0”, the CPU core 206 maintains the sleep state as it is. If the reception flag register 132 is “1”, the data stored in the reception data register 131 is read. If a command that needs to be changed from the sleep state to the standby state or the print state is received, the sleep state is changed to the required state by an operation described later. If the data (command) is a command that can be maintained in the sleep state, the sleep state is maintained as it is.

  However, depending on the command, the status is returned to the video controller 27 as necessary. In addition, after the data in the reception data register 131 is read, “0” is written in the reception flag register 132.

  Next, an operation for shifting from the sleep state to the standby state or the print state will be described.

  As described above, when it is necessary to shift from the sleep state to the standby state or the print state, the CPU core 206 switches the frequency of the clock 222 output from the PLL 221 to the normal frequency via the control signal 220.

  Further, the CPU core 206 writes “1” to the register CLKEN in the CLKEN control circuit 102. As a result, CLKEN 108 becomes “1”, the gate in the gated clock circuit 103 opens, and the clock GCLK 109 becomes the same clock as the clock CLK 107. As a result, the clock is supplied to the flip-flops in the other circuit 110, and the laser scanner 7, the image developing unit 8, the fixing device 9 and the like controlled by the other circuit 110 are put into operation.

  Next, a transition is made to the standby state or the print state by starting up various power sources that were stopped when the sleep state was entered, or performing other necessary operations.

  In the above-described second embodiment, the CPU core 206 is configured to be incorporated into the ASIC 113. However, as in the first embodiment, the CPU can be arranged in an IC different from the ASIC including the video interface communication circuit 101. is there.

  In the second embodiment, the configuration in which the power consumption is reduced by reducing the clock frequency of the CPU core 206 has been described. However, the CPU operation may be changed to an intermittent operation for low power consumption without changing the frequency. Similar effects can be obtained.

  According to the second embodiment, in the sleep state, it is possible to cut off the clock supply except for necessary circuits such as the video interface communication circuit 101 in the ASIC 113. Further, the clock of the ASIC 113 can be operated in accordance with a command transmitted from the video controller 27. Furthermore, since the operating frequency of the CPU core 206 can be reduced, the power consumption can be further reduced. Thereby, power consumption during sleep can be reduced, and low power consumption can be realized.

  Further, it is not necessary to provide a dedicated signal line for the sleep state between the video controller 27 and the engine controller 26, and this can be realized without an increase in cost due to a connector or a cable.

  Further, since the CPU core 206 is built in the ASIC 113, pins for the CPU bus are not necessary, and the IC package can be made smaller and the cost can be reduced.

  Next, Embodiment 3 according to the present invention will be described in detail with reference to the drawings. In the third embodiment, the CPU core clock is also stopped during sleep.

  The configurations of the image forming apparatus and the video interface in the third embodiment are the same as those in the first embodiment described with reference to FIGS. 1 and 2, and the description thereof is omitted.

  Here, the configuration and operation of the engine controller 26 that changes the state of the engine unit based on a command sent from the video controller 27 will be described.

  FIG. 6 is a diagram illustrating a configuration of the engine controller 26 according to the third embodiment. In FIG. 6, the same elements as those in FIGS. 3 and 5 are given the same reference numerals.

  The difference from FIG. 5 is that the clock of the CPU core 206 is the gated clock 109 and that the video interface communication circuit 101 can directly control the CLKEN 108 that controls the output of the gated clock 109.

  Since the CPU core 206 uses the GCLK 109 as a clock, when the CPU core 206 stops the GCLK 109 via the internal bus 111 and the CLKEN control circuit 102, the CPU core 206 itself also stops.

  Also, the reception flag register 132 (FIG. 4) of the video interface communication circuit 101 and the control signal 250 output from the video interface communication circuit 101 are always the same value. When the video interface communication circuit 101 receives data from the video controller 27, the reception flag register 132 becomes “1”, and as a result, the control signal 250 also becomes “1”. When the control signal 250 becomes “1”, the CLKEN 108 becomes “1” and the GCLK 109 is output regardless of the value of the control signal 251 output from the CLKEN control circuit 102.

  Next, the operation of the engine controller 26 will be described.

  The CPU core 206 controls the gated clock GCLK 109 in the third embodiment in the same manner as in the first and second embodiments.

  Next, processing for changing the state of the engine unit from the standby state to the sleep state will be described.

  First, when the engine controller 26 receives a command to shift to the sleep state from the video controller 27 via the video interface 28, the CPU core 206 of the engine controller 26 receives the received data in the video interface communication circuit 101 via the internal bus 111. The command stored in the register 131 is read, and the power consumption of the fixing device 9, the power source for driving the actuator, the power source for the laser beam and the sensor, etc. are stopped based on the command, thereby reducing the power consumption. Also, if the power supply has a mode for increasing the power supply efficiency at the time of low power consumption such as the low power consumption mode, the mode is shifted to that mode.

  Next, the CPU core 206 clears the reception flag register 132 in the video interface communication circuit 101 to “0” via the internal bus 111, and similarly writes “0” to the CLKEN register in the CLKEN control circuit 102. . At the same time, the CPU core 206 waits for a certain time. Note that the predetermined time is longer than the time required to write “0” to the CLKEN register.

  Since both the control signals 250 and 251 become “0”, the CLKEN 108 also becomes “0”, and the gated clock GCLK 109 stops at “0”. As a result, the clock supply to all the circuits in the ASIC 113 except for the video interface communication circuit 101 is cut off, so that the power consumption by the flip-flop becomes almost “0”. The clock stops while the CPU core 206 is waiting. Further, since the signal of the clock buffer driving GCLK 109 does not change, the power consumption of the clock buffer is also reduced. Then, since the clock supply to the CPU core 206 is also cut off, the CPU core is also stopped.

  Next, the operation in the sleep state and the operation for shifting to the standby state or the print state will be described.

  The video interface circuit 101 is operating even during sleep, and can receive data from the video controller 27. Since the clocks of other circuits (including the CPU core 206) are stopped, no operation is performed.

  When the video interface circuit 101 receives data from the video controller 27, the reception flag register 132 becomes “1”, and as a result, the control signal 250 and the CLKEN 108 become “1”. Since GCLK 109 operates, a clock is supplied to the circuit including the CPU core 206, and all circuits start operating. Here, the CPU core 206 starts executing the program from the wait state, and can execute the sequence after a predetermined time.

  As a result, the CPU core 206 looks at the reception flag register 132, and when it is confirmed that it is “1”, reads the data stored in the reception data register 131. Then, “0” is written in the reception flag register 132. Thereafter, an appropriate operation according to the received data is performed.

  For example, by starting various power sources that are stopped when the sleep state is changed, or by performing other necessary operations, the state is changed to the standby state or the print state.

  When the received data does not need to be returned to the standby state or the print state, after necessary processing, the control signal 251 is set to “0” by controlling the register in the CLKEN control circuit 102 again. The clock GCLK109 is stopped and the sleep state is continued.

  In the third embodiment, the case where the CPU core 206 is in the same IC as the video interface communication circuit 101 has been described. However, even when the CPU and the video interface communication circuit 101 are in different ICs, the CPU low power consumption mode ( The clock of the CPU is stopped at the time of sleep by connecting the clock stop) and the return pin (interrupt pin) of the low power consumption mode to the control signal output from the video interface communication circuit 101, and output from the video interface communication circuit 101. It is also possible to cancel the CPU clock stop by a control signal.

  According to the third embodiment, in the sleep state, it is possible to cut off the clock supply except for necessary circuits such as the video interface communication circuit in the ASIC, and the power consumption during the sleep can be reduced.

  During sleep, it is possible to display that the display unit of the operation panel (for example, a liquid crystal panel) is in sleep and detect that a button on the operation panel has been pressed. In that case, the clock may be configured to continue to be supplied not only to the video interface communication circuit 101 but also to a control circuit of the liquid crystal panel and a circuit that detects that a button has been pressed.

  Further, the clock supply to the CPU may be restored by pressing the button.

  As in this example, the clock may be continuously supplied to necessary circuits even during sleep.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  Another object of the present invention is to supply a recording medium in which a program code of software realizing the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores it in the recording medium. Needless to say, this can also be achieved by reading and executing the programmed program code.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

1 is a cross-sectional view illustrating a schematic configuration of a laser beam printer in Embodiment 1. FIG. FIG. 3 is a diagram illustrating a configuration of a video interface in the first embodiment. FIG. 2 is a diagram illustrating a configuration of an engine controller 26 according to the first embodiment. 1 is a diagram illustrating a configuration of a video interface communication circuit 101 in Embodiment 1. FIG. FIG. 6 is a diagram illustrating a configuration of an engine controller 26 according to a second embodiment. FIG. 6 is a diagram illustrating a configuration of an engine controller 26 according to a third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 2 Cassette 5 Paper feed roller 7 Laser scanner 8 Image developing part 9 Fixing device 12 Paper discharge tray 26 Engine controller 27 Video controller 28 Video interface 30 General-purpose interface 31 External device 101 Video interface communication circuit 102 CLKEN control circuit 103 Gated Clock circuit 104 CPU interface circuit 105 Oscillator 106 CPU
131 Reception Data Register 132 Reception Flag Register 135 Communication Circuit 206 CPU Core 221 PLL

Claims (14)

An image forming apparatus having an image processing unit that generates an image signal based on image information from an external device, and an image forming unit that forms an image based on the generated image signal,
A clock control means for controlling a clock supplied to the circuit of the image forming section in the image forming section;
Communication means for communicating information with the image processing unit,
When receiving information indicating a specific mode from the image processing unit via the communication unit, the clock control unit performs control so as to maintain a clock to the communication unit and stop clocks to other circuits. An image forming apparatus.   The image forming apparatus according to claim 1, wherein a clock to a CPU that controls the image forming unit is not stopped in the specific mode.   The image forming apparatus according to claim 1, wherein in the specific mode, a frequency of a clock to the CPU that controls the image forming unit is switched to a low frequency.   The image forming apparatus according to claim 1, wherein a clock to a CPU that controls the image forming unit is stopped in the specific mode.   2. The image forming apparatus according to claim 1, wherein when the information that needs to shift to another mode is received from the image processing unit via the communication unit, the clock stop to the other circuit is canceled. .   The image forming apparatus according to claim 3, wherein when the information that needs to shift to another mode is received from the image processing unit via the communication unit, the frequency of the clock is switched to a normal frequency.   The image forming apparatus according to claim 4, wherein when the information that needs to shift to another mode is received from the image processing unit via the communication unit, the clock stop to the CPU is canceled.   The image forming apparatus according to claim 1, wherein in the specific mode, a clock to a CPU that controls the image forming unit is intermittently operated.   9. The image forming apparatus according to claim 8, wherein when the information necessary to shift to another mode is received from the image processing unit via the communication unit, the intermittent operation of the clock to the CPU is canceled. .   The image forming apparatus according to claim 1, wherein in the specific mode, the display unit of the image forming apparatus displays that the apparatus is in the specific mode.   The image forming apparatus according to claim 1, wherein the specific mode is a low power consumption mode. An image forming apparatus control method comprising: an image processing unit that generates an image signal based on image information from an external device; and an image forming unit that forms an image based on the generated image signal.
A clock control step for controlling a clock supplied to the circuit of the image forming unit;
A communication step of communicating information with the image processing unit,
When the clock control step receives information indicating a specific mode from the image processing unit in the communication step, the clock control step maintains the communication in the communication step and controls to stop the clock to other circuits. A control method for an image forming apparatus.   A program for causing a computer to execute the control method of the image forming apparatus according to claim 12.   A computer-readable recording medium on which the program according to claim 13 is recorded.

Images