JP2006013846A - Code sequence conversion method and apparatus therefor, code sequence conversion table generating apparatus, and turbo code coder and decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a code sequence conversion method capable of realizing a high degree of randomizing, an apparatus therefor, a conversion sequence conversion table generating apparatus, and turbo coding coder and decoder. <P>SOLUTION: Using a virtual bit sequence äU<SB>n</SB>} generates a real number label äY<SB>n</SB>} attached to each configuration bit of the sequence at random, each real number label and arrangement positional information of each bit attached with each real number label are sequentially arranged in pairs in a row direction in a matrix form, an in-row sorting is carried out, wherein each arrangement positional information is rearranged in the magnitude sequence of numerals of each real number label in each row, and thereafter block sorting is carried out, wherein each arrangement positional information is rearranged according to a prescribed block sequence conversion rule in the unit of rows, and each arrangement positional information is sequentially read in a columnar direction to create a code sequence conversion table. Then an information bit sequence is rearranged by using the code sequence conversion table. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a code order conversion method and apparatus for performing code order conversion processing of an information bit sequence, a code order conversion table creation apparatus, and a turbo code encoder and decoder. It can be used for systems and other information processing equipment with turbo codes.

  Conventionally, processing for changing the order of codewords has been performed in order to increase error tolerance of a coded sequence. As a device for performing such processing, an interleaver (code order conversion device) is used. ing. Further, as a device paired with the interleaver, a deinterleaver (decoding sequence restoration device) for returning to the original order on the decoding side is used.

  In an environment where these interleavers and deinterleavers (hereinafter sometimes referred to as deinterleavers) are most often used, a turbo code is interposed. The turbo code was proposed by Berrou et al. In 1993 as a coding method capable of realizing performance close to the Shannon limit. At present, it is adopted as an error correction code in a data communication unit of W-CDMA, which is a third generation mobile phone system. In FIG. 1 described later, the configuration of an encoder and a decoder for turbo code including an interleaver and a deinterleaver is shown as a configuration example of the present invention. Since it is the same as the conventional one except for the configuration of the contents of the interleaver, details will be described later.

  In this turbo code, a randomizing operation is required so that input sequences to two partial encoders (hereinafter, referred to as element encoders) built in the encoder side become uncorrelated with each other. is there. Such a randomizing operation is also necessary for two partial decoders on the decoder side (hereinafter also referred to as element decoders). This degree of decorrelation is significantly related to the performance of the turbo code, and several types of interleavers have been proposed so far.

  Among these, a prime interleaver (prime interleaver) that performs code order conversion processing using a prime number (prime field) is a standard technology of IMT-2000 (see Patent Literature 1 and Non-Patent Literature 1). Prior to that, several types of interleavers have been proposed, although the performance is inferior to that of prime interleavers (see Non-Patent Document 2, for example).

  As a technique related to the present invention, there is a technique for generating a pseudo stochastic process (see Non-Patent Documents 3 and 4).

JP 2000-353965 A (paragraphs [0015] to [0019], FIG. 5, summary) Hiroto Suda, Akira Shibuya, Hideki Imai, “Interleaver for Turbo Codes Using Elementary Fields”, IEICE Transactions, IEICE, November 2002, Vol. J85-A, no. 11, p. 1168-1181 B. B. Vucetic, J.A. J. Yuan, “Turbo Codes”, Kluwer Academic Publishers, 2000 Y. Y. Linde, R.M. M.M. Gray (RM.Gray), “A fake process approach to data compression”, IEEE Transactions on Communications, 1978, Vol. . COM-26, No. 6, p. 840-847 Y.Matsuyama, R.M. M.M. Gray (R.M..Gray), “Universal tree encoding for speech”, IEEE Transactions on Information Theory, 1981, Vol. IT-27, p. 31-40

  However, if the prime interleaver described in Patent Document 1 and Non-Patent Document 1 described above is to be realized by a hardware circuit, a multiplier and a remainder calculator are indispensable, but an interleaver that does not need them as much as possible. It is convenient if the processing time can be shortened, the chip size can be reduced, and the calorific value can be reduced by developing the above and simplifying the processing contents. Further, it is desired to further improve the degree of decorrelation of the input sequence with respect to the two partial encoders on the encoder side or the two partial decoders on the decoder side, thereby improving the performance of the interleaver.

  Furthermore, not only the interleaver for turbo codes, but if the degree of randomization by the code order conversion device can be increased, it is possible to improve the performance of various information processing devices.

  The techniques described in Non-Patent Document 3 and Non-Patent Document 4 described above are merely aimed at generating a pseudo-probabilistic process, and the method and apparatus mechanism relating to code order conversion and restoration as in the present invention. Does not provide.

  An object of the present invention is to provide a code order conversion method and apparatus capable of realizing a high degree of randomization, a code order conversion table creation apparatus, and a turbo code encoder and decoder.

  The present invention intends to achieve the above object by attaching a real number label to each bit constituting a bit sequence and realizing a code order conversion process using the magnitude relation of the real number label.

  Specifically, the code order conversion method of the present invention generates or prepares a virtual bit sequence as a substitute for the information bit sequence prior to the code order conversion processing of the information bit sequence, and a plurality of code bits that constitute the virtual bit sequence. Using the value of at least one of the bits, a real number label attached to each bit constituting this virtual bit sequence is randomly generated, and each generated real number label and each of these real number labels are attached. In addition, each array position information together with each real number label is arranged in a matrix format according to the array order before the code order conversion process of each bit in a state paired with the array position information in the virtual bit sequence before the code order conversion process of each bit. In-line sorting that arranges each array position information arranged in a matrix format in order according to the order of the numerical value of each real number label in each line. After performing the block sorting that rearranges each array position information after in-row sorting arranged in a matrix format in units of rows according to a predetermined block order conversion rule, and after each block sorting arranged in a matrix format By sequentially reading the array position information in the column direction, a code order conversion table that predetermines the correspondence between the constituent bits of the bit sequence before the code order conversion process and the bit sequence after the code order conversion process is generated and encoded. When performing the code order conversion process of the information bit sequence stored in the order conversion table storage unit, the code sequence conversion table stored in the code order conversion table storage unit is used to configure each information bit sequence. The bit is rearranged.

  Here, the “information bit sequence” is, for example, a signal such as a sound (including sound), an image (including a still image and a moving image), and the like. The same applies to the following inventions.

  In addition, “to generate or prepare a virtual bit sequence as a substitute for an information bit sequence” is that a virtual bit sequence may be newly generated or a bit that already exists when the code order conversion table is created in advance. This means that the sequence may be used as a virtual bit sequence. The “virtual bit sequence” may coincide with the information bit sequence accidentally or intentionally. The same applies to the following inventions.

  Furthermore, “using the value of at least one bit among a plurality of bits constituting the virtual bit sequence” means that the number of bits used to generate one real number label may be one bit. However, from the viewpoint that a randomized real number label can be easily generated, it is preferable to use a value of a plurality of bits. In addition, when generating a real number label using a plurality of bit values, the plurality of bits may be a plurality of consecutive bits in the virtual bit sequence, or may be a plurality of bits extracted intermittently. It is good, but when generating a real number label with a hardware circuit, it is possible to use a shift register to facilitate processing and simplify the device configuration. preferable. The same applies to the following inventions.

  The “arrangement position information” is information indicating the position of each constituent bit in the bit sequence, that is, the order. For example, “1” for the first constituent bit, and for the second constituent bit. Is information such as “2”, and the third component bit is “3”. The same applies to the following inventions.

  Further, “in accordance with the order of the numerical values of the respective real number labels” means that the labels may be arranged in order from the largest to the smallest. The same applies to the following inventions.

  In such a code order conversion method of the present invention (hereinafter, the corresponding device invention is also referred to as “invention of code order conversion table in advance”), prior to performing the code order conversion processing of the information bit sequence, As pre-processing, a code order conversion table is created in advance using a real number label, and a code order conversion table already prepared and prepared is used when performing code order conversion processing of an information bit sequence.

  At this time, since the code order conversion table is created by using the magnitude relation of the numerical values of the real number randomly generated, it is possible to realize code order conversion processing with a high degree of randomization, that is, code order conversion processing. It is possible to increase the non-correlation between the input series before and after the output and the output series. For this reason, for example, by using it for information processing equipment such as a mobile phone system, it is possible to improve the performance of the information processing equipment, thereby achieving the object.

  Further, the code order conversion method of the present invention generates or prepares a virtual bit sequence as a substitute for the information bit sequence prior to the code order conversion processing of the information bit sequence, and among the plurality of bits constituting the virtual bit sequence The real number label attached to each bit constituting this virtual bit sequence is randomly generated using the value of at least one of the bits, and each real number label generated and each bit assigned with each real number label are generated. In the state where the array position information in the virtual bit sequence before the code order conversion process is paired, each array position information is sequentially arranged according to the array order before the code order conversion process of each bit together with each real number label. Information bit system by dividing each array position information into a plurality of blocks and rearranging each block according to the order of numerical value of each real number label An in-line sorting table for defining an in-line sorting rule for the in-line sorting performed in each row in the code order conversion process is created for each block corresponding to each row, stored in the in-line sorting table storage means, and an information bit sequence When performing the code order conversion process, the content information indicating the value of each bit constituting the information bit sequence is sequentially arranged in the row direction in the matrix format according to the arrangement order before the code order conversion process of each bit, and the matrix format After the in-line sorting is performed, the contents after the in-line sorting arranged in a matrix form are performed after the in-line sorting is performed by using the in-line sorting table stored in the in-line sorting table storage means. Block sorter that rearranges information in line units according to predetermined block order conversion rules It performed grayed, by sequentially reading that each content information after placement block sorting in matrix form in the column direction, and is characterized in generating a bit sequence after coding sequence conversion process.

  Here, the “content information” is information indicating the value of each bit constituting the bit sequence, and is “0” or “1” information. The same applies to the following inventions.

  In such a code order conversion method of the present invention (hereinafter, the corresponding apparatus invention is also referred to as “invention of pre-in-line sorting table”), prior to performing the code order conversion processing of the information bit sequence, As the processing, an in-line sorting table is prepared in advance for each row using a real number label, and when performing the code order conversion processing of the information bit sequence, the in-line sorting table for each row already prepared is prepared. Use.

  At this time, since the in-line sorting table for each line is created using the magnitude relationship between the numerical values of randomly generated real number labels, it is possible to realize code order conversion processing with a high degree of randomization. . For this reason, for example, by using it for information processing equipment such as a mobile phone system, it is possible to improve the performance of the information processing equipment, thereby achieving the object.

  Furthermore, the code order conversion method of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit of the plurality of bits constituting the information bit sequence subject to the code order conversion process. The real number label attached to is randomly generated, and the generated real number label and the array position information in the information bit sequence before the code order conversion process of each bit attached to each real number label are paired In this state, each array position information is sequentially arranged in the row direction in a matrix format according to the array order before the code order conversion processing of each bit together with each real number label, and each array position information arranged in the matrix format is placed in each row. After performing in-line sorting that sorts the values of each real number according to the numerical order, each array position information after in-line sorting arranged in a matrix format is determined in advance. Performs block sorting that rearranges in units of rows according to the lock order conversion rule, and sequentially reads the array position information after block sorting arranged in matrix form in the column direction, thereby converting the bit sequence before code order conversion processing and code order conversion. A code order conversion table that defines the correspondence of each constituent bit with the processed bit sequence is created, and then each bit that constitutes the information bit sequence is rearranged using the code order conversion table It is.

  In such a code order conversion method of the present invention (hereinafter, the corresponding apparatus invention is also referred to as “invention of code order conversion table real time”), the code order conversion table is not prepared in advance. In addition, a code order conversion table is created in real time using a real number label generated using an information bit sequence that is a target of code order conversion processing, and code order conversion processing is performed using the code order conversion table created in real time. I do.

  At this time, the code order conversion table is created using the magnitude relationship of the numerical values of the real number randomly generated, as in the case of the code order conversion table created in advance. High code order conversion processing can be realized. For this reason, it becomes possible to aim at the improvement of the performance of information processing equipment, for example by using for information processing equipment, such as a cellular phone system.

  In addition, when the code order conversion table is created in advance, the code order conversion table is fixed, whereas the code order conversion table is created in real time so that the code order conversion table changes. Become. For this reason, when performing data communication, by transmitting the code order conversion table to the receiving side together with the transmission of the target data, it is possible to realize the confidential communication, thereby achieving the object.

  When realizing secret communication, the creation of the code order conversion table in real time and the transmission of the created code order conversion table to the receiving side are performed for each processing unit of the code order conversion process for the target data. It may be performed continuously or intermittently. In the case of intermittent creation / transmission as in the latter case, the code order conversion table created / transmitted in the most recent process may be used continuously several times until the next creation / transmission, or A fixed code order conversion table created by pre-processing may be used in combination. In addition, when transmitting the code order conversion table to the receiving side, from the viewpoint of improving confidentiality, the code order conversion table is transmitted in a converted state, and the receiving side performs processing to restore the original by using a key or the like. Preferably it is done.

  Then, the code order conversion method of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit among the plurality of bits constituting the information bit sequence to be subjected to the code order conversion process. The real number labels attached to are randomly generated, and the generated real number labels and the array position information in the information bit sequence before the code order conversion processing of each bit attached to each of these real number labels and the bit of each bit In a state in which the content information indicating the value is paired, each array position information and each content information are sequentially arranged in the row direction in a matrix format according to the array order before the code order conversion processing of each bit together with each real number label. After performing in-line sorting that rearranges each array position information and each content information arranged in step 1 according to the order of the numerical value of each real number label in each line, it is arranged in a matrix format. Block sorting is performed by rearranging each array position information and each content information after sorting in line in line units according to a predetermined block order conversion rule, and each array position information after block sorting arranged in a matrix form By sequentially reading in the column direction, a code order conversion table that defines the correspondence between the constituent bits of the bit sequence before the code order conversion process and the bit sequence after the code order conversion process is created and arranged in a matrix format. The bit sequence after the code order conversion process is generated by sequentially reading the content information after the block sorting in the column direction.

  In such a code order conversion method of the present invention (hereinafter, the corresponding apparatus invention is also referred to as “invention of code order conversion table real-time creation / content information direct rearrangement simultaneous processing”), a code order conversion table is used. Rather than creating in advance, a code order conversion table is created in real time using a real number label generated using an information bit sequence subject to code order conversion processing, and this code order conversion table is created. In this process, the code order conversion process is performed by rearranging the content information itself of each bit. Therefore, unlike the case of the above-described invention for generating the code order conversion table in real time, the rearrangement of the content information itself is not performed using the code order conversion table generated in real time, but the code order conversion table is generated. Performed concurrently with processing.

  Also in this case, since the code order conversion process is performed using the magnitude relationship of the numerical values of the randomly generated real number labels, it is possible to realize a code order conversion process with a high degree of randomization. In addition, since the code order conversion table is created in real time, it is possible to realize secret communication, thereby achieving the object.

  Also, the code order conversion method of the present invention uses the value of at least one bit among a plurality of bits constituting the information bit series to be subjected to the code order conversion process, and each bit constituting the information bit series. The real number label attached to is randomly generated, and the generated real number label and the array position information in the information bit sequence before the code order conversion process of each bit attached to each real number label are paired In this state, each array position information is sequentially arrayed together with each real number label according to the array order before the code order conversion processing of each bit, and each array position information is divided into a plurality of blocks, and each real number label in each block. By sorting according to the numerical order of the numbers of, the in-line sorting table that defines the order conversion rules for in-line sorting performed in each line It is created for each corresponding block, and then the content information indicating the value of each bit constituting the information bit sequence is sequentially arranged in the row direction in the matrix format according to the sequence order before the code order conversion processing of each bit, and the matrix format After performing the in-line sorting that rearranges each content information arranged in (1) using each in-line sorting table in each row, each content information after the in-line sorting arranged in a matrix format is set in a predetermined block order. Performs block sorting that rearranges in units of rows according to the conversion rule, and sequentially reads the content information after block sorting arranged in a matrix format in the column direction, thereby generating a bit sequence after code order conversion processing. To do.

  In such a code order conversion method of the present invention (hereinafter, the corresponding apparatus invention is also referred to as “invention of in-line sorting table real time creation”), the in-line sorting table is not created in advance, An in-line sorting table is created in real time using a real number label generated using an information bit sequence to be subjected to code order conversion processing, and code order conversion processing is performed using the in-line sorting table created in real time.

  At this time, the in-line sorting table for each line is created using the magnitude relationship of the numerical value of the real label generated randomly, as in the case of the in-line sorting table created in advance. High code order conversion processing can be realized. For this reason, it becomes possible to aim at the improvement of the performance of information processing equipment, for example by using for information processing equipment, such as a cellular phone system.

  In addition, when the in-line sorting table for each row is created in advance, the in-line sorting table is fixed, whereas the in-line sorting table for each row is created in real time, so the in-line sorting table varies. It becomes like this. For this reason, when performing data communication, it is possible to realize confidential communication by transmitting the in-line sorting table for each line to the receiving side together with the transmission of the target data, thereby achieving the purpose. The

  In addition, when realizing secret communication, the creation of the in-line sorting table for each row in real time and the transmission of the created in-line sorting table to the receiving side are performed for each processing unit of the code order conversion process for the target data. May be performed continuously or intermittently. When creating / transmitting intermittently as in the latter case, the in-line sorting table created / transmitted in the most recent process may be used continuously several times until the next creation / transmission, or in advance. A fixed in-line sorting table created by the processing may be interwoven and used. Also, when sending the in-line sorting table to the receiving side, from the viewpoint of improving confidentiality, send the in-line sorting table in a converted state, and use the key on the receiving side to restore the original. Is preferred.

  Furthermore, the code order conversion method of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit of the plurality of bits constituting the information bit sequence subject to the code order conversion process. The real number labels attached to are randomly generated, and the generated real number labels and the array position information in the information bit sequence before the code order conversion processing of each bit attached to each of these real number labels and the bit of each bit In a state in which the content information indicating the value is paired, each array position information and each content information are sequentially arranged in the row direction in a matrix format according to the array order before the code order conversion processing of each bit together with each real number label. After performing in-line sorting that rearranges each array position information and each content information arranged in step 1 according to the order of the numerical value of each real number label in each line, it is arranged in a matrix format. By sequentially reading each array position information after the in-line sorting in the row direction for each row, an in-line sorting table for defining the order conversion rule for each in-line sorting is created for each block corresponding to each row, and a matrix Performs block sorting that rearranges each content information after in-line sorting arranged in a format in line units according to a predetermined block order conversion rule, and each piece of content information after block sorting arranged in a matrix format in the column direction A bit sequence after the code order conversion process is generated by sequentially reading.

  In such a code order conversion method of the present invention (hereinafter, the corresponding apparatus invention is also referred to as “invention of simultaneous processing of real-time sorting table and direct rearrangement of content information”), the sorting table in the row is stored in advance. Instead of creating an in-line sorting table in real time using real number labels generated using information bit sequences that are subject to code order conversion processing, and in the process of creating this in-line sorting table Code order conversion processing is performed by rearranging the bit content information itself. Therefore, unlike the above-described invention for real-time creation of the in-line sorting table, the contents information itself is not rearranged by using the in-line sorting table created in real time, but at the same time as the in-line sorting table creation process. Done in parallel.

  Also in this case, since the code order conversion process is performed using the magnitude relationship of the numerical values of the randomly generated real number labels, it is possible to realize a code order conversion process with a high degree of randomization. In addition, since the in-line sorting table for each line is created in real time, it is possible to realize secret communication, and the above-described purpose is achieved.

  Then, the code order conversion method of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit among the plurality of bits constituting the information bit sequence to be subjected to the code order conversion process. Each real number is assigned to each real number in a state where the real number label attached to is randomly generated and each real number label and the content information indicating the value of each bit assigned to each real number label are paired. Along with the labels, each bit is sequentially arranged in the row direction in the matrix format according to the sequence order before the code order conversion process, and the contents information arranged in the matrix format is rearranged in the respective rows according to the order of the numerical value of each real number label. After in-line sorting, each content information after in-line sorting arranged in matrix format is rearranged in line units according to a predetermined block order conversion rule. Does locking sorting, by sequentially reading that each content information after placement block sorting in matrix form in the column direction, and is characterized in generating a bit sequence after coding sequence conversion process.

  In such a code order conversion method of the present invention (hereinafter, the corresponding device invention is also referred to as “content information direct rearrangement invention”), the magnitude relationship between the numerical values of the randomly generated real number labels is used. Thus, the code order conversion process with a high degree of randomization can be realized. For this reason, for example, by using it for information processing equipment such as a mobile phone system, it is possible to improve the performance of the information processing equipment, thereby achieving the object.

  In this case, when performing data communication, it is possible to transmit, for example, an array of real labels maintaining the arrangement order before in-line sorting to the receiving side in addition to transmission of target data. Moreover, the transmission of the array of real numbers may be continuous or intermittent, and the transmission in the converted state is preferable as in the case of the transmission of the code order conversion table and the in-line sorting table described above. is there.

In the code order conversion method described above, when generating each real number label, after calculating the real number X between the real number X _a to the real number X _b using each value of a plurality of consecutive bits, When t is a real number in the range of X _a ≦ t <(X _a + X _b ) / 2, the conditional expression g (t) + g (t + (X _b −X _a ) / 2) = Y _a + Y _b using scrambling function Y = g (X) satisfying the real the real X between the real number X _a ~ real X _b is converted into a real number Y between the real number Y _a ~ real Y _b, obtained by converting By using the value of Y as a real number label and shifting each value of a plurality of consecutive bits one bit at a time, by repeating the calculation process of the real number X and the conversion process from the real number X to the real number Y by the scrambling function, It is desirable to sequentially generate each real number label attached to each bit.

  When generating a real number label using a scrambling function in this way, the function of the scrambling function makes it possible to further increase the degree of randomization in the code order conversion processing. The performance can be further improved.

Further, in the case of performing a process of generating real labels using scrambling function described above, the process of calculating the real number X between the real number X _a ~ real X _b with the values of a plurality of consecutive bits is calculated Assuming that the number of bits used for M is M and m is an integer from ¹ to ^M , the value obtained by multiplying each value of M bits by 2 ^−m is added, and further 2 ^{− (M + 1)} is added. numerical by the a X to be a process of calculating the real number X of between 0 and 1, between real X between real X _a ~ real X _b by scrambling function of real number Y _a ~ real Y _b Is a conversion process from a real number X between 0 and 1 to a real number Y between 0 and 1, and the real number X is calculated from the real number X by the scrambling function and the real number Y. It is desirable that the conversion process to be a pseudo stochastic process generation process.

  In this way, when generating a real number label using the pseudo-probability process generation process, by applying the conventional pseudo-probability process generation process as it is, a random number real-number label generation process Can be easily realized.

  In the code order conversion method described above, the block order conversion rule is that at least two bits that are 7 bits apart from each bit constituting the bit sequence before the code order conversion process are bits after the code order conversion process. It is desirable that the rule is to avoid being arranged at a position separated by 7 bits in the sequence.

  Here, “at least” means that two bits apart from multiple bits of 7 such as 7 bits, 14 bits, 21 bits, 28 bits, etc., among the bits constituting the bit sequence before the code order conversion process are encoded order. This means that, as a rule for avoiding arrangement at positions separated by multiples of 7 bits in the bit sequence after the conversion processing as much as possible, the case of 7 bits is avoided at a minimum.

  In the case of such a block order conversion rule, it is possible to further increase the decorrelation between the input sequence and the output sequence before and after the code order conversion process. For example, when the code order conversion process is a turbo code interleaving process, a fatal input pattern that contributes most to the bit error rate in the high SNR region, that is, a low bit weight parity bit sequence is created. It is possible to realize an interleaving process that breaks the weight input pattern as much as possible, and an interleaving process that complies with the design concept of the code matched interleaver is realized.

  In the code order conversion method described above, the code order conversion process is preferably performed as a turbo code interleaving process.

  As described above, when the process according to the code order conversion method of the present invention is applied to the interleaving process of the turbo code, there is no input sequence for the two partial encoders on the encoder side or the two partial decoders on the decoder side. It is possible to further increase the degree of correlation and improve the performance of the interleaver, and consequently the performance of the information processing device including the error correction processing unit using the turbo code.

  Further, as a device for realizing the code order conversion method of the present invention described above, the following code order conversion device of the present invention can be cited.

  That is, the code order conversion apparatus of the present invention stores a code order conversion table that stores a code order conversion table that defines the correspondence between the constituent bits of a bit sequence before the code order conversion process and a bit sequence after the code order conversion process. A code order conversion table comprising: storage means; and code order conversion processing means for performing a process of rearranging each bit constituting the information bit sequence using the code order conversion table stored in the code order conversion table storage means. The code order conversion table stored in the storage means generates or prepares a virtual bit sequence as a substitute for the information bit sequence, and uses a value of at least one bit among a plurality of bits constituting the virtual bit sequence, A real number label attached to each bit constituting this virtual bit sequence is randomly generated, and each generated real number label is generated. And the bit sequence of each bit with each real number label, with each real location label paired with the sequence position information in the virtual bit sequence before the code sequence conversion processing of each bit with each real number label attached. After performing in-line sorting that sequentially arranges the array position information in the matrix format in the row direction according to the array order before conversion processing, and rearranges each array position information arranged in the matrix format according to the order of the numerical value of each real number label in each row Each block position information after block sorting arranged in a matrix format is performed by performing block sorting that rearranges each array position information after sorting in a row arranged in a matrix format in line units according to a predetermined block order conversion rule. Is a table created by sequentially reading out in the column direction.

  In such a code order conversion apparatus of the present invention, the operations and effects obtained by the above-described code order conversion method of the present invention (invention of the code order conversion table in advance) can be obtained as they are, whereby the above-mentioned object is achieved. The

  As a device for creating a code order conversion table used in the above-described code order conversion device of the present invention (invention of code sequence conversion table pre-creation), the following code order conversion table creation device of the present invention can be cited. . That is, the present invention is a code order conversion table creation device for creating a code order conversion table used when performing a code order conversion process for rearranging each bit constituting an information bit sequence, and as a substitute for the information bit sequence Real number label generation that randomly generates a real number label attached to each bit constituting the virtual bit sequence by using the value of at least one bit of the plurality of bits constituting the generated or prepared virtual bit sequence The processing means, and each real number label generated by the real number label generation processing means and the array position information in the virtual bit sequence before the code order conversion processing of each bit assigned with each real number label are paired In the state, each array position information is ordered in the row direction in a matrix format according to the array order before the code order conversion processing of each bit together with each real number label. Matrix arrangement processing means to be arranged, and in-line sorting processing means for performing in-line sorting in which each array position information arranged in a matrix format by this matrix arrangement processing means is rearranged according to the order of the numerical value of each real number label in each row; , Block sorting processing means for performing block sorting for rearranging each array position information after in-line sorting by the in-line sorting processing means in line units according to a predetermined block order conversion rule, and after block sorting by the block sorting processing means Matrix read processing means for sequentially reading the array position information in the column direction.

  Also, the code order conversion apparatus of the present invention stores an in-line sorting table that defines an order conversion rule for the in-line sorting performed in each line in the code order conversion process of the information bit sequence for each block corresponding to each line. Sorting table storage means, matrix arrangement processing means for sequentially arranging the content information indicating the value of each bit constituting the information bit sequence in the row direction in a matrix format according to the arrangement order of each bit before the code order conversion process, and the matrix In-line sorting processing means for performing in-line sorting, in which each content information arranged in a matrix format by the arrangement processing means is rearranged in each row using each in-line sorting table, and each content after in-line sorting by this in-line sorting processing means Information is aligned in line units according to a predetermined block order conversion rule. Block sorting processing means for performing block sorting to be replaced, and matrix read processing means for generating a bit sequence after the code order conversion processing by sequentially reading each content information after the block sorting by the block sorting processing means in the column direction Each in-line sorting table stored in the in-line sorting table storage means generates or prepares a virtual bit sequence as a substitute for the information bit sequence, and stores at least one bit of a plurality of bits constituting the virtual bit sequence. The real number label attached to each bit constituting this virtual bit sequence is randomly generated by using the value, and the generated real number label and the code order conversion processing of each bit assigned with each real number label are performed. In a pair with the array position information in the virtual bit sequence of Each array position information is sequentially arranged along with each real number label according to the order of the bits before the code order conversion process. Each array position information is divided into a plurality of blocks, and the numerical value of each real label is set within each block. It is a table created by rearranging in order.

  In such a code order conversion apparatus of the present invention, the operations and effects obtained by the above-described code order conversion method of the present invention (invention of in-line sorting table pre-creation) can be obtained as they are, thereby achieving the object. .

  The in-line sorting table used in the above-described code order conversion apparatus of the present invention (invention of in-line sorting table in advance) can be created by an in-line sorting table creating apparatus having the following configuration. In other words, the in-line sorting table creation device that creates an in-line sorting table that defines the order conversion rules for the in-line sorting performed within each row in the code order conversion process of the information bit sequence generates a virtual bit sequence instead of the information bit sequence. Alternatively, a real number label is generated that randomly generates a real number label attached to each bit constituting the virtual bit sequence by using the value of at least one of the plurality of bits constituting the virtual bit sequence. The processing means, and each real number label generated by the real number label generation processing means and the array position information in the virtual bit sequence before the code order conversion processing of each bit assigned with each real number label are paired In the state, each array position information and each real number label are followed according to the array order before the code order conversion processing of each bit. The array processing means for sequentially arranging the information, and the array position information arranged by the array processing means are divided into a plurality of blocks and rearranged according to the order of the numerical value of each real number label in each block, and then rearranged. An arrangement read processing means for sequentially reading the arrangement position information for each block can be employed.

  Furthermore, the code order conversion apparatus of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit among the plurality of bits constituting the information bit sequence that is the target of the code order conversion process. Real number label generation processing means for randomly generating a real number label attached to each of the real number labels generated by the real number label generation processing means, and before the code order conversion processing of each bit to which these real number labels are attached Matrix arrangement processing that sequentially arranges each array position information in the row direction in a matrix format according to the array order before the code order conversion process of each bit together with each real number label in a state where the array position information in the information bit series is paired And each array position information arranged in a matrix form by this matrix arrangement processing means is rearranged in the order of the numerical value of each real number label in each row. In-line sorting processing means for performing in-line sorting, and block sorting processing means for performing block sorting for rearranging each array position information after the in-line sorting by the in-line sorting processing means in line units according to a predetermined block order conversion rule; By sequentially reading the array position information after the block sorting by the block sorting processing means in the column direction, the correspondence between the constituent bits of the bit sequence before the code order conversion process and the bit sequence after the code order conversion process Code order conversion table creation processing means for creating a code order conversion table for determining the code order, and a code order for rearranging each bit constituting the information bit sequence using the code order conversion table created by the code order conversion table creation processing means Conversion process It is characterized in that a stage.

  In such a code order conversion apparatus of the present invention, the operations and effects obtained by the above-described code order conversion method of the present invention (invention of code order conversion table real-time creation) can be obtained as they are, thereby achieving the object. Is done.

  Then, the code order conversion device of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit among the plurality of bits constituting the information bit sequence to be subjected to the code order conversion process. Real number label generation processing means for randomly generating a real number label attached to each of the real number labels generated by the real number label generation processing means, and before the code order conversion processing of each bit to which these real number labels are attached With the array position information in the information bit sequence paired with the content information indicating the value of each bit, each array position information and each content information together with each real number label, the array order before the code order conversion processing of each bit In accordance with the matrix arrangement processing means for sequentially arranging in the row direction in a matrix format, each array position information and each content information arranged in matrix format by this matrix arrangement processing means In-line sorting processing means for performing in-line sorting to sort in accordance with the numerical order of the numerical value of each real label in each line, and each array position information and each content information after in-line sorting by this in-line sorting processing means are determined in advance. Block sorting processing means for performing block sorting for rearranging in line units according to the block order conversion rule, and the bit before the code order conversion processing by sequentially reading the array position information after the block sorting by the block sorting processing means in the column direction Code order conversion table creation processing means for creating a code order conversion table for defining the correspondence between the constituent bits of the sequence and the bit sequence after the code order conversion processing, and each content after block sorting by the block sorting processing means Is characterized in that a matrix read processing means for generating a bit sequence after coding sequence conversion processing by sequentially reading distribution in the column direction.

  In such a code order conversion apparatus of the present invention, the operations and effects obtained by the above-described code order conversion method of the present invention (code order conversion table real-time creation / content information direct rearrangement simultaneous processing invention) can be obtained as they are. This achieves the object.

  In addition, the code order conversion device of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit among the plurality of bits constituting the information bit sequence to be subjected to the code order conversion process. Real number label generation processing means for randomly generating a real number label attached to each of the real number labels generated by the real number label generation processing means, and before the code order conversion processing of each bit to which these real number labels are attached An array processing means for sequentially arranging each array position information together with each real number label in accordance with the array order before the code order conversion process of each bit in a state in which the array position information in the information bit series is paired; By dividing each array position information arranged by the above into a plurality of blocks and rearranging them in the order of the numerical value of each real number label in each block. In-line sorting table creation processing means for creating an in-line sorting table for each block corresponding to each row, and a value of each bit constituting an information bit sequence Matrix arrangement processing means for sequentially arranging the content information in the row direction in a matrix format according to the arrangement order before the code order conversion processing of each bit, and each content information arranged in a matrix format by this matrix arrangement processing means within each row In-line sorting processing means for performing in-line sorting, each of which is sorted using each in-line sorting table, and a block for rearranging the contents information after the in-line sorting by the in-line sorting processing means in units of lines according to a predetermined block order conversion rule. Block sorting process for sorting And matrix read processing means for generating a bit sequence after code order conversion processing by sequentially reading each content information after the block sorting by the block sorting processing means in the column direction. .

  In such a code order conversion apparatus of the present invention, the operations and effects obtained by the above-described code order conversion method of the present invention (invention of the in-line sorting table real time) can be obtained as they are, and thereby the above-described object is achieved. The

  Furthermore, the code order conversion apparatus of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit among the plurality of bits constituting the information bit sequence that is the target of the code order conversion process. Real number label generation processing means for randomly generating a real number label attached to each of the real number labels generated by the real number label generation processing means, and before the code order conversion processing of each bit to which these real number labels are attached With the array position information in the information bit sequence paired with the content information indicating the value of each bit, each array position information and each content information together with each real number label, the array order before the code order conversion processing of each bit In accordance with the matrix arrangement processing means for sequentially arranging in the row direction in a matrix format, each array position information and each content information arranged in matrix format by this matrix arrangement processing means In-line sorting processing means for performing in-line sorting for rearranging in order of the numerical value of each real label in each line, and by reading out each array position information after in-line sorting by this in-line sorting processing means for each line, In-line sorting table creation processing means for creating an in-line sorting table for each block corresponding to each row, which defines the order conversion rule for the in-line sorting, and each content information after the in-line sorting by the in-line sorting processing means are determined in advance. Block sorting processing means for performing block sorting for rearranging in line units in accordance with the block order conversion rule, and code order conversion processing by sequentially reading each piece of content information after block sorting by the block sorting processing means in the column direction. Is characterized in that a matrix read processing means for generating a bit sequence after.

  In such a code order conversion apparatus of the present invention, the operations and effects obtained by the above-described code order conversion method of the present invention (invention of in-line sorting table real-time creation and content information direct rearrangement simultaneous processing) can be obtained as they are. This achieves the object.

  Then, the code order conversion device of the present invention uses each bit constituting the information bit sequence by using the value of at least one bit among the plurality of bits constituting the information bit sequence to be subjected to the code order conversion process. Real number label generation processing means for randomly generating a real number label attached to the contents, content information indicating each real number label generated by the real number label generation processing means, and a value of each bit assigned to each real number label, and In a state in which each pair is paired, each content information and each real number label are sequentially arranged in the row direction in a matrix form according to the arrangement order before the code order conversion process of each bit, and the matrix arrangement processing means In-line sorting process that performs in-line sorting that sorts each piece of content information placed in step 1 in the order of the numerical value of each real label in each line. Means, block sorting processing means for performing block sorting in which each content information after the in-line sorting by the in-line sorting processing means is rearranged in line units in accordance with a predetermined block order conversion rule, and block sorting by the block sorting processing means Matrix read processing means for generating a bit sequence after the code order conversion processing by sequentially reading each subsequent content information in the column direction is provided.

  In such a code order conversion apparatus of the present invention, the operation and effect obtained by the above-described code order conversion method of the present invention (invention of content information direct rearrangement) can be obtained as it is, and thereby the above object is achieved. .

Further, in the above-described code order conversion apparatus (invention of pre-creation of code order conversion table, invention of pre-creation of in-line sorting table), the generation process of each real number label performed when the table is created includes a plurality of continuous labels. After calculating the real number X between the real number X _a and the real number X _b using each value of the bit, when t is a real number in the range of X _a ≦ t <(X _a + X _b ) / 2, g ( t) + g (t + (X _b −X _a ) / 2) = Y _a + Y _{b Using} the scrambling function Y = g (X) that satisfies the conditional expression, real number X between real number X _a and real number X _b Is converted into a real number Y between the real number Y _a and the real number Y _b , the value of the real number Y obtained by the conversion is used as a real number label, and each value of a plurality of consecutive bits is used while shifting one bit at a time, Real number X calculation processing and scrambling function to convert real number X to real number Y By repeating the conversion process, it is desirable that the process for sequentially generating each real labels applied to each bit.

Further, as described above, when a table (code order conversion table or in-line sorting table) is created using a real number label generated using a scrambling function, each value of a plurality of consecutive bits is used. processing for calculating the real X between the real number X _a ~ real X _b is the number of bits used for calculation is M, when an integer 1~M the m, multiplied by 2 ^-m, each of the values of M bits This is a process of calculating a real number X between 0 and ¹ by adding X and a value obtained by adding 2 ^{− (M + 1)} to X, and a real number X _a by a scrambling function in the conversion process from real X between ~ real X _b conversion into real numbers Y between the real number Y _a ~ real Y _b are the real Y between real X between 0-1 0-1 Yes, the calculation process of these real numbers X and the scrambling function The conversion process from a real number X to a real number Y by number is preferably a pseudo stochastic process generation process.

  In the above-described code order conversion apparatus (invention of code order conversion table pre-creation, in-line sorting table pre-creation), the block order conversion rule includes at least each bit constituting the bit sequence before the code order conversion process. It is desirable that the rule is for avoiding that two bits separated by 7 bits are arranged at positions separated by 7 bits in the bit sequence after the code order conversion process.

  In the above-described code order conversion apparatus (invention of pre-creation of code order conversion table, invention of pre-creation of in-line sorting table), it is desirable that the code order conversion process is performed as a turbo code interleaving process.

Further, the above-described code order conversion apparatus (invention of code order conversion table real-time creation, code order conversion table real-time creation / content information direct rearrangement simultaneous processing, in-line sorting table real-time creation invention, in-line sorting table actual In the invention of time creation / content information direct rearrangement simultaneous processing, content information direct rearrangement invention), the real number label generation processing means uses the values of a plurality of consecutive bits between real number _Xa and real number _Xb . And weight calculation processing means for calculating a real number X of the following: g (t) + g (t + (X _b −X _a ) / where t is a real number in the range of X _a ≦ t <(X _a + X _b ) / 2 2) Using the scrambling function Y = g (X) that satisfies the conditional expression = Y _a + Y _b , the real number X between the real number X _a and the real number X _b is changed to the real number Y between the real number Y _a and the real number Y _b. Obtained by converting to The weight / label conversion processing means that uses the value of the number Y as a real number label, and each process of the weight calculation processing means and the weight / label conversion processing means are repeated while shifting each value of a plurality of consecutive bits one by one. And a shift processing means for performing a bit shift process for this purpose.

When the real number label generation processing unit is configured to generate a real number label using a scrambling function as described above, the weight calculation processing unit sets the number of bits used for calculation to M and sets m to 1 to M. Assuming that it is an integer, a value obtained by multiplying each value of M bits by 2 ^−m and adding 2 ^{− (M + 1)} to X is set to X, and 0 to 1 The weight / label conversion processing means is configured to perform a conversion process from a real number X between 0 and 1 to a real number Y between 0 and 1, and a real number label. The generation processing means is preferably configured to perform a pseudo stochastic process generation process.

  In addition, the above-described code order conversion apparatus (invention of code order conversion table real-time creation, code order conversion table real-time creation / content information direct rearrangement simultaneous processing, in-line sorting table real-time creation invention, in-line sorting table actual In the invention of time creation / content information direct rearrangement simultaneous processing, content information direct rearrangement invention), the block sorting processing means, as a block order conversion rule, for each bit constituting at least the bit sequence before the code order conversion process Of these, it is desirable to use a rule for avoiding that two bits separated by 7 bits are arranged at positions separated by 7 bits in the bit sequence after the code order conversion process.

  Further, the above-described code order conversion apparatus (invention of code order conversion table real-time creation, code order conversion table real-time creation / content information direct rearrangement simultaneous processing, in-line sorting table real-time creation invention, in-line sorting table actual The invention of the simultaneous processing of time creation and content information direct rearrangement and the invention of content information direct rearrangement can be suitably used as an interleaver for turbo codes.

  The code order conversion apparatus described above (invention of code order conversion table real time creation, code order conversion table real time creation / content information direct rearrangement simultaneous processing, in-line sorting table real time creation invention, in-line sorting table actual In the time creation / content information direct rearrangement simultaneous processing invention and the content information direct rearrangement invention), the shift processing means is preferably constituted by a shift register. In this case, the code order conversion apparatus is mainly realized by a hardware circuit.

  The turbo code encoder of the present invention is characterized in that the above-described code order conversion apparatus is provided as a turbo code interleaver.

  Furthermore, a turbo code decoder according to the present invention is characterized by including the above-described code order conversion device as a turbo code interleaver.

  The code order conversion apparatus and code order conversion table creation apparatus of the present invention described above, or the in-line sorting table creation apparatus described above, and the turbo code encoder and decoder of the present invention are mainly configured by hardware circuits. It may be realized or may be realized mainly by software. And when realized by a hardware circuit, it is possible to have a circuit configuration that only performs comparison and addition, so that the prime interleaver described in Patent Document 1 and Non-Patent Document 1 described above is used. Compared with the case where a multiplier or a remainder calculator is required, it can be operated at high speed. For this reason, it is possible to shorten the processing time, which is particularly effective when processing is performed in real time. Further, since the processing content is simplified, it is possible to reduce the chip size and reduce the amount of heat generation.

  As described above, according to the present invention, since the code order conversion process is performed by using the magnitude relationship between the numerical values of randomly generated real number labels, the code order conversion process with a high degree of randomization, that is, before the process is performed. Code sequence conversion processing with a high degree of decorrelation between the input sequence and the processed output sequence can be realized, and the performance of the information processing device can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 shows the overall configuration of an error correction processing unit 10 using a turbo code provided in the communication system according to the first embodiment of the present invention. The first embodiment is an embodiment according to the invention of code order conversion table pre-creation. The communication system is, for example, a mobile phone system, but is not limited thereto. FIG. 2 shows the configuration of the code order conversion table creation device 50, the interleavers 23 and 33, and the deinterleaver 34. FIG. 3 is a conceptual diagram of the flow of the process for creating the code order conversion table. FIG. 4 is a flowchart showing the flow of the process for creating the code order conversion table and the code order restoration table. Further, in FIGS. 5 and 6, the flow of the interleaving process and the deinterleaving process is shown by flowcharts, respectively. FIG. 7 is an explanatory diagram of a method for generating the constituent bits of the virtual bit sequence when creating the code order conversion table. 8 and 9 are detailed explanatory diagrams of the code order conversion table creation process. FIG. 10 is an explanatory diagram of the shape of the scrambling function, FIG. 11 is an explanatory diagram of a method for creating a block order conversion rule, and FIG. 12 is a diagram showing a comparison experiment result by simulation.

  In FIG. 1, an error correction processing unit 10 using a turbo code provided in a communication system includes an encoder 20 provided on the transmitter side of the communication system and a decoder 30 provided on the receiver side. Yes.

  The encoder 20 includes a first element encoder (also referred to as a partial encoder) 21, a second element encoder 22, and an interleaver 23 that is a code order conversion device. It is configured to include.

  The decoder 30 includes a first element decoder (also referred to as a partial decoder) 31, a second element decoder 32, an interleaver 33 serving as a code order converter, It includes a deinterleaver 34 that is a code order restoration device.

  The configurations and functions of these encoders 20 and decoders 30 are the same as the conventional ones except for the contents (internal processing procedures) of the interleavers 23 and 33 and the deinterleaver 34. In the decoder 30, the following processing is performed.

First, the encoder 20, transmit subject to the information bit sequence C to the receiver side, is input to the first constituent encoder 21, a parity bit sequence V ₁ is generated. The information bit sequence C is series C ^h next sorted in the interleaver 23, the sequence C ^h is input to the second constituent encoder 22, a parity bit sequence V ₂ is generated. Then, the sequence V ₀ and the parity bit sequences V ₁ and V _{2 in} the state of the information bit sequence C are transmitted to the receiver side via the communication path 40. At this time, the transmitted sequences V ₀ , V ₁ , V ₂ are affected by noise in the communication path 40. For example, in the case of a mobile phone system, it is affected by noise in the air.

Incidentally, the number of bits serving as a processing unit of the information bit sequence C, for example if 512 bits, sequence C ^h after encoding sequence conversion process by the interleaver 23, becomes 512 bits, sequence V ₀ is also 512 bits, The parity bit sequences V ₁ and V ₂ are, for example, 518 bits by adding redundant bits of 3 bits each at the beginning and rear.

On the other hand, in the decoder 30, the sequence V ₀ and the parity bit sequences V ₁ and V _{2 in} the state of the information bit sequence C are affected by noise to become sequences R ₀ , R ₁ and R ₂ , respectively. Assuming that R ₀ , R ₁ , and R ₂ are received signals, first, in the first round of the iterative process using the turbo code, the received sequences R ₀ and R ₁ are input to the first element decoder 31. The sequence Λ _1e is output from the first element decoder 31 using these sequences R ₀ and R ₁ . Subsequently, the sequence Λ _1e output from the first element decoder 31 and the received sequence R ₀ are rearranged by the interleaver 33 to become sequences Λ _1e ^h and R ₀ ^h , and these sequences Λ _1e ^h , R ₀ ^h and the received sequence R ₂ are input to the second element decoder 32, and the sequence Λ _2e is transmitted from the second element decoder 32 using these sequences Λ _1e ^h , R ₀ ^h , R _2. Is output. Next, the sequence Λ _2e output from the second element decoder 32 is rearranged by the deinterleaver 34 to become Λ _2e ^h . In the second round, the sequence Λ _2e ^h output from the deinterleaver 34 and the received sequences R ₀ and R ₁ are input to the first element decoder 31, and these sequences Λ _2e ^h , R ₀ , A new sequence Λ _1e is output from the first element decoder 31 using R ₁ . Subsequently, the new sequence Λ _1e output from the first element decoder 31 is rearranged by the interleaver 33 to become a new sequence Λ _1e ^h . The new sequence Λ _1e ^h and the output from the interleaver 33 are output. A new sequence Λ _2e is output from the second element decoder 32 using the received sequence R ₀ ^h and the received sequence R ₂ . Next, the new sequence Λ _2e output from the second element decoder 32 is rearranged by the deinterleaver 34 to become a new Λ _2e ^h . Thereafter, after repeating the same process several times, for example, the sequence Λ ₂ finally output from the second element decoder 32 becomes the output of the decoder 30.

If the received sequence R ₀ is, for example, 512 bits and the sequences R ₁ , R ₂ are, for example, 518 bits, the sequence Λ _1e output from the first element decoder 31 is, for example, 518 bits, and the interleaver 33 Then, an interleaving process for exchanging, for example, the first 512 bits of the 518-bit sequence Λ _1e is performed. Further, the sequence Λ _2e output from the second element decoder 32 is also 518 bits, for example, and the deinterleaver 34 performs a deinterleaving process for exchanging, for example, the first 512 bits of the 518-bit sequence Λ _2e. Done.

  In FIG. 2, the interleaver 23 built in the encoder 20 has a correspondence relationship between the constituent bits of the bit sequence (input sequence) before the code order conversion process and the bit sequence (output series) after the code order conversion process. The code order conversion table storage means 23A for storing the code order conversion table 60 for determining the code order, and the bits constituting the information bit sequence are rearranged using the code order conversion table 60 stored in the code order conversion table storage means 23A. Code order conversion processing means 23B for performing processing is included.

  The interleaver 33 built in the decoder 30 includes a code order conversion table storage unit 33A that stores the same table as the code order conversion table 60 stored in the code order conversion table storage unit 23A on the encoder 20 side, The code order conversion processing unit 33B performs processing for rearranging the bits constituting the bit sequence using the code order conversion table 60 stored in the code order conversion table storage unit 33A.

  Further, the deinterleaver 34 incorporated in the decoder 30 is a code order restoration table that defines the inverse correspondence relationship with the code order conversion table 60 stored in the code order conversion table storage means 23A, 33A of the interleavers 23, 33. The code sequence restoration table storage unit 34A for storing 80 and the code sequence restoration table 80 stored in the code sequence restoration table storage unit 34A are used to rearrange and restore the bits constituting the bit sequence. Code order restoration processing means 34B.

  In the above, the code order conversion processing means 23B and 33B of the interleavers 23 and 33 and the code order restoration processing means 34B of the deinterleaver 34 are the computers constituting the encoder 20 and the decoder 30, or the encoder 20 and A central processing unit (CPU) provided in each computer (including not only a personal computer but also its higher model and lower model) constituting the information processing device including the decoder 30, and this CPU It can be realized by one or a plurality of programs that define the operation procedure. Further, each of these processing means 23B, 33B, 34B may be realized by a hardware circuit.

  The code order conversion table storage means 23A, 33A of the interleaver 23, 33 and the code order restoration table storage means 34A of the deinterleaver 34 include, for example, a hard disk, ROM, EEPROM, flash memory, RAM, MO, CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, FD, magnetic tape, or a combination thereof can be employed. At this time, when each processing means 23B, 33B, 34B is realized by a hardware circuit, each storage means 23A, 33A, 34A can be realized by a ROM or the like, for example. Further, when the processing units 23B, 33B, and 34B are realized by software, for example, the code order conversion table 60 and the code order restoration table 80 can be provided as an array on the program. In this case, the array The data may be described directly in the program, may be read from an external memory such as a hard disk, MO, or FD, may be input by an input means such as a keyboard, and finally each processing means 23B, 33B. , 34B only need to be stored in the main memory when processing is performed, and in these cases, each storage means 23A, 33A, 34A is realized by the main memory and / or an external memory. Become. In addition, when each processing means 23B, 33B, and 34B is implement | achieved by software, it is not limited to the process which has each table 60 and 80 by an array as mentioned above.

  The code order conversion table 60 and the code order restoration table 80 stored in the storage means 23A, 33A, 34A are automatically generated by the code order conversion table creation device 50 and the code order restoration table creation device 70 as shown in FIG. Can be created.

  In FIG. 2, the code order conversion table creation device 50 includes a real number label generation processing means 51, a matrix arrangement processing means 52, an in-line sorting processing means 53, a block sorting processing means 54, a matrix reading processing means 55, a scrambler. The ring function storage unit 56 and the block order conversion rule storage unit 57 are included.

  The real number label generation processing means 51 uses the value of at least one bit among a plurality of bits constituting a virtual bit series generated or prepared as a substitute for the information bit series, and each bit constituting this virtual bit series A process of randomly generating a real number label attached to is performed. The virtual bit sequence may be a bit sequence prepared in advance, but will be described here as being automatically generated.

  The real number label generation processing unit 51 includes a virtual bit sequence generation processing unit 51A, a shift processing unit 51B, a weight calculation processing unit 51C, and a weight / label conversion processing unit 51D.

  The virtual bit sequence generation processing unit 51A performs processing for automatically generating a virtual bit sequence used for creating the code order conversion table 60 in advance (see FIG. 7). The virtual bit sequence generation processing means 51A may be realized by a hardware circuit or software.

  The shift processing means 51B is a bit for repeating each process by the weight calculation processing means 51C and the weight / label conversion processing means 51D using each value of a plurality of consecutive bits constituting the virtual bit sequence while shifting one bit at a time. The shift process is performed. This shift processing means 51B may be realized by a hardware circuit or software, and in the former case, it can be easily realized by using, for example, a shift register (see FIG. 3). Here, the description will be made assuming that it is realized by a shift register.

The weight calculation processing means 51C uses a real number X between a real number X _a and a real number X _b by using each value of a plurality of consecutive bits constituting the virtual bit sequence (here, each bit value stored in the shift register). A process of calculating (a real number greater than X _a and less than X _b ) is performed. The weight calculation processing means 51C may be realized by a hardware circuit or may be realized by software. More specifically, the weight calculation processing unit 51C sets, for example, the number of bits used for calculation as M (for example, M = 32 when using a 32-bit shift register), and m is an integer from 1 to M. Then, each of the M bit values is multiplied by 2 ^−m as a weight, that is, the first bit value stored in the shift register is 2 ⁻¹ , the second bit value is 2 ⁻² ,. , multiplied by 2 ^-m in the m-th bit value so on 2 ^-M to M-th bit value, determine the overall weight by adding the values obtained, the overall weight of further determined 2− ^{(M + 1)} is added to X to obtain a real number X (a real number greater than 0 and less than 1) between 0 and 1 by performing X. . Therefore, if the bit value of the shift register is “1”, the weight corresponding to the bit is added, and if the bit value is “0”, it is not added. The reason why 2 ^{− (M + 1)} is added is to avoid that the value of the calculated real number X becomes 0 when all the bit values are “0”. Even when the bit value becomes “1”, the calculated value of the real number X never becomes 1.

Incidentally, as described above, is not limited to processing of calculating the real X between 0-1 with a power of 2, for example, may be used for 3 powers and 4 powers like, in short, real X _a ~ It suffices if the real number X between the real numbers _Xb can be calculated.

The weight / label conversion processing unit 51D uses a scrambling function Y = g (X) satisfying the following expression (1) stored in the scrambling function storage unit 56 to obtain a real number X _a to a real number X. The real number X between _b is converted into a real number Y between the real number Y _a and the real number Y _b , and the processing is performed using the value of the real number Y obtained by the conversion as a real number label. The weight / label conversion processing means 51D may be realized by a hardware circuit or software, and in the former case, the scrambling function storage means 56 may be realized by a ROM or the like, for example.

g (t) + g (t + (X b -X a) / 2) = Y a + Y b ········· (1)

Here, t is a real number in the range of X _a ≦ t <(X _a + X _b ) / 2.

  Further, the weight / label conversion processing means 51D uses the scrambling function Y = g (X) with the following expression (2) as a conditional expression as the simplest conditional expression of the above expression (1). It can be performed.

  g (t) + g (t + 1/2) = 1 (2)

  Here, t is a real number in the range of 0 ≦ t <1/2.

The above equation (2) is a case where X _a = 0, X _b = 1, Y _a = 0, Y _b = 1 in the above-described equation (1). In this case, weight / label conversion is performed. The processing unit 51D performs processing for converting the real number X between 0 and 1 into the real number Y between 0 and 1. At this time, the real number X between 0 and 1 as an input value to the scrambling function Y = g (X) can be easily calculated by using the power of power of 2 by the weight calculation processing means 51C as described above. can do. Since the output value from the scrambling function Y = g (X) is a real number Y between 0 and 1, when the above equation (2) is used as a conditional expression, the real number label generation processing means 51 Can be realized by a pseudo stochastic process generator (Fake Process Generator). Therefore, an existing pseudo stochastic process generator can be used.

  The matrix arrangement processing unit 52 includes real position labels generated by the real number label generation processing unit 51 and array position information (in the virtual bit sequence before the code order conversion process of each bit assigned with each real number label ( Information on the number of bits), and each array position information along with each real number label in the row direction (horizontal direction) in memory in a matrix format according to the array order before the code order conversion processing of each bit Are sequentially arranged (see the upper part of FIG. 8).

  The in-line sorting processing means 53 performs an in-line sorting process for rearranging the array position information arranged in the memory in the matrix format by the matrix arrangement processing means 52 within each row according to the order of the numerical value of each real number label. (See the middle part of FIG. 8).

  The block sorting processing unit 54 rearranges each array position information after the in-line sorting by the in-line sorting processing unit 53 in units of rows (block units) in accordance with the block order conversion rules stored in the block order conversion rule storage unit 57. Processing is performed (see the lower part of FIG. 8).

  The matrix read processing means 55 performs processing for sequentially reading the array position information after the block sorting by the block sorting processing means 54 in the column direction (vertical direction) from the memory (the lower part of FIG. 8 and the left side of FIG. 9). Part reference).

The scrambling function storage means 56 is a scrambling function that satisfies the above-described equation (1) for converting the real number X between the real number X _a to the real number X _b to the real number Y between the real number Y _a to the real number Y _b. Y = g (X) is stored. Further, as described above, as the simplest conditional expression, a scrambling function satisfying the above-described expression (2) for converting a real number X between 0 and 1 into a real number Y between 0 and 1 is stored. May be. More specifically, as shown in FIG. 10, it can be a scrambling function indicated by three chevron shapes having the same size. There are a large number of scrambling functions that satisfy the conditions of the expressions (1) and (2). For example, the scrambling function can have a shape having five mountains or seven mountains instead of three mountains. From the viewpoint of increasing the degree of randomization in the interleaving process, that is, the degree of decorrelation between the input sequence to the interleaver and the output sequence, and improving the performance of the turbo code, three peaks as shown in FIG. A scrambling function having a shape having

  The block order conversion rule storage means 57 stores a block order conversion rule for rearranging each array position information after in-row sorting in units of rows (block units). In this embodiment, at least two bits that are separated by 7 bits from each bit constituting the bit sequence before the code order conversion process are separated by 7 bits in the bit sequence after the code order conversion process. This is a rule for avoiding being arranged at a certain position.

  The above block order conversion rules are derived from the design concept of the code matched interleaver shown below. Code matched realizes interleave processing that destroys as much as possible the fatal input pattern that contributes most to the bit error rate in the high SNR region, that is, the low-weight input pattern that creates the lowest-weight parity bit sequence. It is.

  First, the number (array position information) of each bit in the bit sequence before the code order conversion process is set to i, and the number (array position information) in the bit sequence after the code order conversion process for the i-th bit is π ( i). That is, the i-th bit content (bit value) becomes the π (i) -th bit content (bit value) after the code order conversion process. For example, if the eighth bit content in the bit sequence before the code order conversion process becomes the fifteenth bit content after the code order conversion process, it can be expressed as π (8) = 15. At this time, the code matched interleaver generates an output sequence that satisfies the relationship of the following equation (4) for the input sequence that has the relationship of the following equation (3).

  | I-j | mod7 = 0 (3)

  | Π (i) −π (j) | mod7 ≠ 0 (4)

  Expressions (3) and (4) above are two bits separated by multiples of 7 bits, such as 7 bits, 14 bits, 21 bits, 28 bits, etc., of each bit constituting the bit sequence before the code order conversion process. This is a rule that prevents the contents from being arranged at positions separated by multiple bits of 7 within the bit sequence after the code order conversion process. However, in practice, it is impossible to destroy all the low-weight input patterns that create the lowest-weight parity bit sequence so as to satisfy the above-described equations (3) and (4). Therefore, in this embodiment, an output sequence that satisfies the relationship of the following equation (6) is generated at least for the input sequence that has the relationship of the following equation (5).

  | I-j | = 7 (5)

  | Π (i) −π (j) | ≠ 7 (6)

  Next, the block order conversion rule can be expressed in a 20-dimensional vector format, assuming that the number of rows (number of blocks) when arranged in a memory in a matrix format is 20. For example, (7, 17, 3, 2, 10, 20, 13, 6, 4, 8, 12, 14, 5, 9, 11, 15, 19, 16, 1, 18). In this example, the seventh row of the matrix before block sorting is arranged in the first row of the matrix after block sorting by the block sorting processing means 54, and the second row of the matrix after block sorting is The 17th row of the matrix before block sorting is arranged, and similarly, the 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 13th, 14th, 15th, 15th, In the 16th, 17th, 18th, 19th and 20th rows, the 3rd, 2nd, 10th, 20th, 13th, 6th, 4th, 8th, 12th, 14th, 5th, 9th, 11th, 15th and 19th rows of the matrix before block sorting. , 16th, 1st and 18th lines are respectively arranged. In this example, a numerical value of 1 to 20 is used. However, for example, even if a rule is defined using a numerical value of 0 to 19, the same thing is true.

  Such a block order conversion rule can be created as follows. As shown in FIG. 11, it is assumed that a 20-dimensional vector indicating a block order conversion rule is (..., A,..., B,...), And A and B are separated by 7 elements. That is, six numerical values are arranged between A and B. For example, the 5th row of the matrix after block sorting is arranged in the Ath row of the matrix before block sorting, and the 12th row of the matrix after block sorting is placed in the Bth row of the matrix before block sorting. Shall be placed. This is because the process of reading from the matrix memory by the matrix read processing means 55 is performed in the column direction (vertical direction), so that a position 7 bits away from the bit sequence after the interleaving process (a space of 6 bits is provided). This means that the bit of the A-th row and the bit of the B-th row of the matrix before the block sorting are arranged at the position. Here, when the absolute value of the difference between A and B is 1 (1 row), the relationship in the same column between the bits in the Ath row and the bits in the Bth row is the bit sequence before the interleaving process. There may be two bits that are 7 bits apart. For example, if the matrix memory is 20 rows × 26 columns, and A = 2 and B = 3, the Ath row (= second row) of the matrix before block sorting is the 27th bit sequence before the interleaving process. Is the 52nd bit (same after in-row sorting), and the Bth row (= third row) of the matrix before block sorting is the 53rd to 78th bit (intrarow) in the bit sequence before the interleaving process. The same is true after sorting. As a result of in-line sorting, the 48th bit is arranged in the first column in the Ath row (= second row), and the Bth row (= third row). ), If the 55th bit is arranged in the first column, two bits that are separated by 7 bits in the bit sequence before the interleaving process are arranged in the same column. However, such a situation does not occur when the absolute value of the difference between A and B is 2 or more (2 or more rows). Therefore, in a 20-dimensional vector (..., A,..., B,...) Indicating the block order conversion rule, it is only necessary to prevent A and B separated by 7 elements from being different by one (one line difference).

  In this way, in the vector indicating the block order conversion rule, A and B separated by 7 elements should not be different by one line when the number of columns is 7 or more. In the case of columns, A and B separated by 7 elements need not be different by 1 line and not by 2 lines. In the case of 3 columns, A and B separated by 7 elements are It is sufficient not to be 2 lines different and 3 lines different. In the case of 2 columns, A and B separated by 7 elements are not 3 lines different and 4 lines different. do it.

  Also, the block order conversion rule when the number of rows (number of blocks) of the matrix is 20 is not limited to the above example, and for example, (12, 18, 4, 14, 19, 3, 8, 6, 7 , 11, 5, 1, 9, 2, 20, 10, 17, 16, 15, 13), (13, 10, 6, 3, 11, 8, 16, 9, 12, 2, 7, 4, 1 , 19,5,18,14,15,17,20), (19,2,14,11,1,17,18,13,15,10,8,5,12,9,16,3,7) , 6, 20, 4), (14, 17, 13, 11, 8, 1, 18, 5, 20, 2, 9, 3, 12, 10, 19, 7, 4, 6, 15, 16), (17, 11, 19, 16, 4, 12, 10, 8, 14, 7, 9, 2, 15, 13, 18, 6, 3, 1, 5, 20), (19, 12, 18, 17 , 3, 5, 4, 8, 1, 7, 15, 10, 2, 9, 16, 11, 4, 6, 13, 20), (1, 4, 20, 13, 12, 6, 14, 10, 19, 18, 3, 7, 15, 5, 17, 2, 9, 8, 16, 11), (15, 4, 19, 13, 7, 12, 5, 14, 8, 9, 1, 17, 2, 3, 16, 11, 18, 20, 6, 10), etc., and any of them may be used. Furthermore, the number of rows (number of blocks) of the matrix is not limited to 20 and is arbitrary, and the number of dimensions of the vector indicating the block order conversion rule is also arbitrary.

  In the above, each of the processing means 51 to 55 is a central operation provided in the computer (including not only a personal computer but also a higher model or a lower model) constituting the code order conversion table creating device 50. It can be realized by a processing device (CPU) and one or a plurality of programs that define the operation procedure of the CPU. Each of these processing means 51 to 55 may be realized by a hardware circuit.

  The scrambling function storage means 56 and the block order conversion rule storage means 57 include, for example, a hard disk, ROM, EEPROM, flash memory, RAM, MO, CD-ROM, CD-R, CD-RW, DVD-ROM. DVD-RAM, FD, magnetic tape, or a combination thereof can be employed.

  The code order restoration table creation device 70 performs processing for creating a code order restoration table 80 that defines the inverse correspondence relationship from the code order conversion table 60. The code order restoration table creation device 70 may be realized mainly by software or may be realized mainly by a hardware circuit.

  In the first embodiment, the code order conversion process and the code order restoration process of the information bit sequence by the turbo code are performed as follows.

  First, as shown in FIGS. 2 and 4, a code order conversion table 60 is created by the code order conversion table creation device 50, and a code order restoration table 80 is created by the code order restoration table creation device 70. The code order conversion table 60 and the code order restoration table 80 are stored in the code order conversion table storage means 23A, 33A and the code order restoration table storage means 34A, respectively. FIG. 4 shows this specific procedure.

  In FIG. 4, the power of the code order conversion table creation device 50 (see FIG. 2) is turned on to start the table creation processing (step S1), and the virtual bit sequence generation processing means 51A (see FIG. 2) Are automatically generated (step S2). At this time, as shown in FIG. 7, the virtual bit sequence generation processing means 51A adds the M−1th bit content (bit value) and the Mth bit content stored in the shift register. Thus, the value of the bit to be input next to the shift register is automatically generated.

Subsequently, as shown in FIG. 3, configuration bits U _n one bit of the virtual bit sequence {U _n} generated by the virtual bit sequence generating means 51A (first bit shall be U _1.) The shift processing means 51B (see FIG. 2) realized by the shift register shifts the value of each bit already stored in the shift register bit by bit (step S3 in FIG. 4).

Then, as shown in FIG. 3, the weight calculation processing means 51C (see FIG. 2) multiplies the m-th bit content (bit value) of the shift register by a weight 2- ^m corresponding to the bit, These weights are all added for m = ¹ to ^M , and 2 ^{− (M + 1)} is further added to obtain the real number X (the first bit U ₁ as the overall weight ⁾ to the shift register. the obtained value as a real number X _1.) is calculated (step S4 of FIG. 4).

As shown in FIG. 3, the weight / label conversion processing means 51D (see FIG. 2) uses the scrambling function Y = g (X) stored in the scrambling function storage means 56 (see FIG. 10). From the real number X (the first is the real number X ₁ ) that is the weight calculated by the weight calculation processing means 51C, the real number Y (the first is the real number) that becomes a real number label attached to the constituent bits of the virtual bit sequence Conversion to Y ₁ ) is performed (step S5 in FIG. 4). In this embodiment, as an example, for a bit newly input to the shift register, a real number Y obtained by converting the real number X calculated by the input of this bit is attached as a real number label. Therefore, the real X _n is calculated by newly input the n-th bit U _n of the virtual bit sequence in the shift register, when a real number Y _n is obtained by converting the real X _n, is a real number Y _n It is assumed that the _nth bit Un is attached as a real number label. However, it is arbitrary whether the generated real number label is a label attached to which bit, for example, a label attached to a bit stored near the center of the shift register, or a shift register It may be a label attached to the last bit (a bit that deviates from the shift register in the next shift process), a bit before entering the shift register, a bit that has already deviated from the shift register, or the like.

Subsequently, the real number Y ₁ which is the real number label obtained by the weight / label conversion processing means 51D by the matrix arrangement processing means 52 (see FIG. 2), and the virtual bit sequence with the real number label of the real number Y ₁ { U _n } are arranged in a matrix form in memory in a state of being paired with the array position information (information indicating that it is the first bit) for the _first bit U ₁ of U _n } (step S6 in FIG. 4). ). In the present embodiment, as an example, the description will be made assuming that the matrix size P rows × Q columns is 20 rows × 26 columns (the number of elements is 520), but the present invention is not limited to this.

Then, it is determined whether or not the number of bits has reached a specified number (number of elements in the matrix) (step S7 in FIG. 4). If the number has not reached the specified number, the process returns to step S2 in FIG. Thereafter, the processes of steps S2 to S7 are repeated until the number of bits reaches the specified number, thereby generating each real number Y _n (n = 2, 3, 4,...) That is a real number label. _n and the array position information (n-th number) about each constituent bit U _n (n = 2, 3, 4,...) of the virtual bit sequence {U _n } with a real number label of each real number Y _n . These are sequentially arranged in the memory in a row direction (horizontal direction) in a matrix format in a state of being paired with information that they are bits. In addition, after all real number labels are generated for the number of elements of the matrix, each real number Y _n (n = 1, 2, 3,...) That is a real number label and these real numbers Y _n are attached. In a state where the arrangement position information (information that is the nth bit) of each constituent bit U _n (n = 1, 2, 3,...) Of the virtual bit sequence {U _n } is paired. May be arranged in a memory in a matrix format.

In the upper part of FIG. 8, each real number Y _n which is a real number label, and array position information about each constituent bit U _n of the virtual bit sequence {U _n } with the real number label of these real numbers Y _n are provided. The state of being paired and arranged in a memory in a matrix form is shown. In the first (upper left) element of the matrix, the numerical value in parentheses is the array position information, “(1)” indicates the first bit in the virtual bit sequence, and the numerical value below the parentheses Is a real number label, and “0.34” indicates that the real number label is Y ₁ = 0.34. The same applies to the other elements.

  After that, as shown in FIG. 8, the in-line sorting processing means 53 (see FIG. 2) changes the order of the array position information in each row according to the order of the numerical value of the real number label while keeping the pair with the real number label ( Step S8 in FIG. For example, the first row surrounded by a thick frame in the matrix in the upper part of FIG. 8 becomes the first row surrounded by a thick frame in the matrix in the middle part of FIG. In this example, since the smallest real number label in the first row is “0.11” paired with the array position information (26), the array position information (26) and the real number label “0.11” are Arranged in the first row. The same applies to the other pairs. In this example, the real number labels are arranged from the left side in ascending order, but may be arranged from the left side in the order from the largest real number label.

  Subsequently, as shown in FIG. 8, the block sorting processing unit 54 (see FIG. 2) sets the pair of the array position information and the real number label according to the block order conversion rule stored in the block order conversion rule storage unit 57. Replacement is performed in units of rows (block units) (step S9 in FIG. 4). For example, a 20-dimensional vector indicating a block order conversion rule is (7, 17, 3, 2, 10, 20, 13, 6, 4, 8, 12, 14, 5, 9, 11, 15, 19, 16 , 1, 18), the first row surrounded by a thick frame in the matrix in the middle part of FIG. 8 showing the state before block sorting is the lower part of FIG. 8 showing the state after block sorting. Is arranged in the 19th row surrounded by a thick frame. Similarly, the second and twentieth lines before block sorting are arranged in the fourth and sixth lines after block sorting, respectively.

  Then, the array read processing means 55 (see FIG. 2) sequentially reads the array position information arranged in the memory in the matrix format from the first column in the column direction (vertical direction). The reading direction may be from the top to the bottom or from the bottom to the top. Here, the description will be made assuming that the reading is performed from the top to the bottom as in the former case. Then, the correspondence as shown in FIG. 9 is obtained. In this example, the 30th bit of the input sequence is arranged at the 4th bit in the output sequence, and similarly, the 496th and 26th bits of the input sequence are the 6th bit in the output sequence. The correspondence relationship is arranged in the 19th and 19th bits. When the processing unit of the information bit sequence is 512 bits, “513” to “520” are unnecessary, and therefore, “513” to “520” are removed, and the numerical values are sequentially reduced. For example, in the example of FIG. 9, “519” is removed, the numerical values on the lower side are shifted upward, and the numerical value “322” immediately below surrounded by a thick frame is put in the removed portion. In this way, the code order conversion table 60 when the processing unit is 512 bits is created (step S10 in FIG. 4). If the processing unit is other than 512 bits, the matrix size may be changed. In this case, if the number of rows is not changed to 20 rows, the block order conversion rule indicated by the 20-dimensional vector described above is used. It can be used as it is.

  Next, as shown in FIG. 9, the code order restoration table 80 is created by reversing the correspondence of the code order conversion table 60 by the code order restoration table creating apparatus 70 (see FIG. 2) (see FIG. 4). Step S11).

  Then, as shown in FIG. 2, the created code order conversion table 60 is written in the code order conversion table storage means 23A of the interleaver 23 of the encoder 20 and the code order conversion table storage means 33A of the interleaver 33 of the decoder 30. And the created code order restoration table 80 is written and saved in the code order restoration table storage means 34A of the deinterleaver 34 of the decoder 30 (step S12 in FIG. 4), and the code order conversion table 60 and the code order are stored. The creation process of the restoration table 80 is terminated (step S13 in FIG. 4).

Further, the interleaving process by the interleaver 23 in the encoder 20 is performed according to the procedure shown in FIG. 5, first, the encoder 20 or the transmitter of the communication system including the encoder 20 is turned on to start the processing (step S21), and the processing target is processed by the code order conversion processing means 23B (see FIG. 2). An information bit sequence C (see FIG. 1) is input (step S22). Subsequently, the code order conversion processing unit 23B performs code order conversion processing for rearranging the constituent bits of the input information bit sequence C using the code order conversion table 60 stored in the code order conversion table storage unit 23A. After (step S23), the bit sequence ^Ch (see FIG. 1) after the conversion process is output (step S24), and the interleaving process is terminated (step S25). The interleaving process by the interleaver 33 in the decoder 30 is the same.

On the other hand, the deinterleave process by the deinterleaver 34 in the decoder 30 is performed according to the procedure shown in FIG. In FIG. 6, first, the decoder 30 or the receiver of the communication system including the decoder 30 is turned on to start the processing (step S31), and the code sequence restoration processing means 34B (see FIG. 2) The bit sequence Λ _2e output from the element decoder 32 (see FIG. 1) is input (step S32). Subsequently, the code order restoration processing unit 34B performs code order restoration processing for rearranging the constituent bits of the input bit sequence Λ _2e using the code order restoration table 80 stored in the code order restoration table storage unit 34A. After (step S33), the restored bit sequence Λ _2e ^h (see FIG. 1) is output (step S34), and the deinterleaving process is terminated (step S35).

  According to such 1st Embodiment, there exist the following effects. That is, since the code order conversion table 60 used in the interleaving process by the interleavers 23 and 33 is created using the magnitude relation of the numerical values of the real numbers generated at random, the code order conversion with a high degree of randomization is performed. Realization of processing, that is, non-correlation between the input sequence to the interleavers 23 and 33 and the output sequence can be enhanced. For this reason, the performance of the communication system can be improved.

  Further, since the code order conversion table 60 is created by performing a real number label generation process using a scrambling function (see FIG. 10), randomization in the code order conversion process is performed by the function of the scrambling function. The degree can be further increased, and the performance of the communication system can be further improved.

  Furthermore, a real number label generation process using a scrambling function Y = g (X) for converting from a real number X between 0 and 1 to a real number Y between 0 and 1 is performed to obtain the code order conversion table 60. When creating, real number label generation processing can be realized using the existing pseudo stochastic process generator (Fake Process Generator), so randomized real number label generation processing is easily realized. can do.

  Since the code order conversion table 60 is created by performing a block sorting process based on the block order conversion rules determined in accordance with the design concept of the code matched interleaver, it contributes to the bit error rate in the high SNR region. It is possible to realize an interleaving process that destroys the largest fatal input pattern, that is, the low weight input pattern that creates the lowest weight parity bit sequence as much as possible.

  Further, in order to confirm the effect of the present invention, a comparative experiment by the following simulation was performed.

  The interleaver (example) of the present invention and the prime number interleaver (comparative example) described in Patent Document 1 and Non-Patent Document 1 described above were verified for differences in decoding characteristics of turbo codes. Specifically, the encoder 20 and decoder 30 for turbo code according to the first embodiment of the present invention, the interleavers 23 and 33 and the deinterleaver 34 (see FIG. 1) included therein, and corresponding to these The devices to be configured using a prime interleaver were programmed using C ++ language and simulated.

  A bit sequence of 5120 bits was randomly generated as data to be transmitted and received, measured 300 times, and an average bit error rate (BER) was taken. The number of states was 8, and the coding rate was 1/3. As a modulation method, a BPSK (Bi-Phase Shift Keying) modulation method is assumed. A white Gaussian noise communication channel is assumed as a communication channel, and a sequence in which the noise is placed on a transmission sequence is defined as a final reception sequence.

FIG. 12 shows a comparison experiment result by simulation. The vertical axis represents the bit error rate (BER), and the horizontal axis represents the SNR changed as an experimental parameter, that is, the energy-to-noise power spectral density ratio E _b / N ₀ per bit. It means that there is less noise. Therefore, the smaller the value of the graph, the better the decoding characteristics. Note that the number of repetitions by the turbo code is eight.

According to FIG. 12, in the vicinity of E _b / N ₀ = 0.2 to 0.3, the bit error rate value of the interleaver (example) of the present invention is larger than the value of the prime interleaver (comparative example). As a result, the effect of the present invention was remarkably shown.

[Second Embodiment]
FIG. 13 shows the configuration of an interliner 200 that is a code order conversion apparatus according to the second embodiment of the present invention and an inline sorting table creation apparatus 210 that creates an inline sorting table 220 used in processing by the interleaver 200. ing. The second embodiment is an embodiment according to the invention of in-line sorting table pre-creation.

  In FIG. 13, the interleaver 200 includes a matrix arrangement processing unit 201, an in-line sorting processing unit 202, a block sorting processing unit 203, a matrix reading processing unit 204, an in-line sorting table storage unit 205, and a block order conversion rule storage. And means 206.

  The matrix arrangement processing unit 201 displays content information (information of “1” or “0”) indicating the value of each bit constituting the information bit sequence C in a matrix format according to the arrangement order before the code order conversion process of each bit. A process of sequentially arranging in the memory in the row direction is performed.

  The in-line sorting processing unit 202 uses each in-line sorting table 220 stored in the in-line sorting table storage unit 205 for each content information arranged in a matrix form by the matrix arrangement processing unit 201 in each row (in each block). The process of rearranging is performed.

  The block sorting processing unit 203 performs processing for rearranging the contents information after the in-line sorting by the in-line sorting processing unit 202 in units of rows (block units) according to the block order conversion rules stored in the block order conversion rule storage unit 206. Is.

Matrix read processing unit 204, by sequentially reading each contents information after block sorting by the block sorting processing unit 203 in the column direction, and performs processing for generating a bit sequence C ^h after encoding order conversion process.

  The in-line sorting table storage unit 205 stores an in-line sorting table 220 that defines an order conversion rule at the time of in-line sorting by the in-line sorting processing unit 202 for each row (each block). These in-line sorting tables 220 are created by the in-line sorting table creation device 210.

  The block order conversion rule storage unit 206 stores a block order conversion rule when the block sorting processing unit 203 performs block sorting. This block order conversion rule is the same as that in the first embodiment.

  The in-line sorting table creation device 210 is a device that creates the in-line sorting table 220 in advance, and includes a real number label generation processing unit 211, an array processing unit 212, an array read processing unit 213, and a scrambling function storage unit 214. It is prepared for.

  As in the case of the real label generation processing unit 51 of the first embodiment, the real number label generation processing unit 211 automatically generates a virtual bit sequence as a substitute for the information bit sequence C, and each component bit of the virtual bit sequence is generated. By calculating a real number X as a weight using the value and performing a conversion process from the real number X to the real number Y using the scrambling function Y = g (X) stored in the scrambling function storage unit 214, the virtual number X is obtained. A process of randomly generating a real number label attached to each constituent bit of the bit sequence is performed.

  The array processing means 212 has information on the position of each real number label generated by the real number label generation processing means 211 and the virtual bit sequence before the code order conversion processing of each bit to which these real number labels are attached (first order). In this state, each array position information together with each real number label is sequentially arranged in the memory according to the arrangement order before the code order conversion process of each bit. .

  The array read processing means 213 divides each array position information arrayed by the array processing means 212 into a plurality of blocks and rearranges them in each block according to the order of the numerical value of each real number label, that is, within each block. After performing the processing corresponding to the in-line sorting, the process of creating the in-line sorting table 220 is performed by sequentially reading the rearranged array position information for each block.

  The scrambling function storage means 214 stores the scrambling function Y = g (X) used in the processing by the real number label generation processing means 211, and the scrambling function storage means 56 of the first embodiment. It is the same.

  In addition, the deinterleaver of the decoder stores the reverse row sorting table storage unit for storing the reverse row sorting table for each row for performing reverse conversion to each row sorting table 220 stored in the row sorting table storage unit 205. And a block order reverse conversion rule storage means for storing a block order reverse conversion rule for performing a reverse conversion to the block order conversion rule stored in the block order conversion rule storage means 206 may be provided. Also, the interleaver 200 described above is adopted for either the encoder or decoder interleaver, and the other interleaver, as in the case of the first embodiment, is subjected to each in-line sorting table and block order conversion. A code order conversion table that defines conversion rules that are equivalent to a combination of rules may be prepared to perform interleaving. Further, as in the case of the first embodiment, the decoder deinterleaver is provided with a code order restoration table that defines a conversion rule that is equivalent to a combination of each reverse row sorting table and block order reverse conversion rule. Deinterleaving processing may be performed.

In such a second embodiment, prior to the code order conversion processing of the information bit sequence C, the in-line sorting table 220 is created in advance by the in-line sorting table creation device 210 and stored in the in-line sorting table storage means 205. Let me. When performing the code order conversion process of the information bit sequence C, the matrix arrangement processing unit 201 sequentially arranges the content information indicating the value of each bit constituting the information bit sequence C in the row direction in a matrix format, The in-line sorting processing unit 202 performs in-line sorting using the in-line sorting table 220 stored in the in-line sorting table storage unit 205 in each row, and then the block sorting processing unit 203 performs the block order conversion rule storage unit 206. performs block sorted in accordance with the stored block permutation rule, by the matrix read processing unit 204, by sequentially reading that each content information in the column direction, to generate a bit sequence C ^h after encoding order conversion process.

  According to such 2nd Embodiment, there exist the following effects. That is, each in-line sorting table 220 used in the interleaving process by the interleaver 200 is created using the magnitude relationship of the numerical value of the real number label generated at random. As in the case of the first embodiment, It is possible to realize code order conversion processing with a high degree of randomization, that is, to increase the non-correlation between the input sequence to the interleaver 200 and the output sequence. For this reason, the performance of the communication system can be improved.

  Further, each in-line sorting table 220 is created by performing a real number label generation process using a scrambling function (see FIG. 10), so that the scrambling function has the same as in the first embodiment. With the function, the degree of randomization in the code order conversion process can be further increased, and the performance of the communication system can be further improved.

  Further, the real number label generation process using the scrambling function Y = g (X) for converting the real number X between 0 and 1 to the real number Y between 0 and 1 is performed, and each in-line sorting table 220 is stored. When creating, real number label generation processing can be realized using the existing pseudo stochastic process generator (Fake Process Generator), so randomized real number label generation processing is easily realized. can do.

  Then, after in-line sorting using the in-line sorting table 220, block sorting based on the block order conversion rule defined in accordance with the design concept of the code matched interleaver is performed, so that it contributes to the bit error rate in the high SNR region. It is possible to realize an interleaving process that breaks as much as possible the fatal input pattern having the largest I, that is, the low weight input pattern that creates the lowest weight parity bit sequence.

[Third Embodiment]
FIG. 14 shows the configuration of an interleaver 300 that is a code order conversion apparatus according to the third embodiment of the present invention. The third embodiment is an embodiment according to the invention for creating a code order conversion table in real time.

  In FIG. 14, the interleaver 300 includes a real number label generation processing unit 301, a matrix arrangement processing unit 302, an in-line sorting processing unit 303, a block sorting processing unit 304, a code order conversion table creation processing unit 305, and a code order. A conversion processing unit 306, a scrambling function storage unit 307, and a block order conversion rule storage unit 308 are provided.

  The real number label generation processing means 301 is the same as that of the first embodiment except that the real number label is generated using the value of each constituent bit of the information bit sequence C to be subjected to the code order conversion process instead of the virtual bit sequence. This is the same as the case of the real number label generation processing means 51.

  The matrix arrangement processing unit 302 includes real position labels generated by the real number label generation processing unit 301, and array position information in the information bit sequence C before the code order conversion process of each bit assigned with each real number label. In such a state, the array position information is sequentially arranged in the memory in the row direction in a matrix format according to the array order before the code order conversion process of each bit together with each real number label.

  The in-line sorting processing unit 303 performs in-line sorting processing for rearranging the array position information arranged in the matrix format by the matrix arrangement processing unit 302 in the order of the numerical value of each real number label in each row.

  The block sorting processing unit 304 performs block sorting processing for rearranging each array position information after the in-line sorting by the in-line sorting processing unit 303 in units of rows according to the block order conversion rules stored in the block order conversion rule storage unit 308. It is.

  The code order conversion table creation processing unit 305 sequentially reads the array position information after the block sorting by the block sorting processing unit 304 in the column direction, so that the bit sequence before the code order conversion process and the bit sequence after the code order conversion process The code order conversion table 310 for defining the corresponding relationship between the constituent bits is generated.

The code order conversion processing unit 306 uses the code order conversion table 310 created by the code order conversion table creation processing unit 305 to rearrange the bits constituting the information bit sequence C, thereby performing the code order conversion processing after the code order conversion processing. It performs a process of generating a bit sequence C ^h.

  The scrambling function storage means 307 stores the scrambling function Y = g (X) used in the processing by the real number label generation processing means 301, and in the case of the scrambling function storage means 56 of the first embodiment. It is the same.

  The block order conversion rule storage unit 308 stores a block order conversion rule when the block sorting processing unit 304 performs block sorting. This block order conversion rule is the same as that in the first embodiment.

In such a third embodiment, the real number label generation processing means 301 randomly generates a real number label using the values of the constituent bits of the information bit sequence C to be subjected to the code order conversion process, and the matrix arrangement processing means. By 302, the real number labels and the array position information in the information bit sequence C before the code order conversion process of each bit are paired and sequentially arranged in the row direction in a matrix form. After performing in-line sorting for rearranging the array position information according to the order of the numerical values of the respective real number labels, the block sorting processing unit 304 performs each array according to the block order conversion rule stored in the block order conversion rule storage unit 308. Performs block sorting that rearranges position information in units of lines. Then, each sequence position information after block sorting is sequentially read in the column direction by the code order conversion table creation processing unit 305, whereby each of the bit sequence before the code order conversion processing and the bit sequence after the code order conversion processing is read. create a code sequence conversion table 310 to determine the correspondence between the configuration bits, then the bit sequence C ^h after encoding permutation process rearranges the bits constituting the information bit sequence C using the code sequence conversion table 310 Generate.

  Further, the code order conversion table 310 created by the code order conversion table creation processing unit 305 is called each 512 bits for each processing unit (for example, when processing a large information bit sequence divided into 512 bits). Is transmitted to the decoder continuously or intermittently every time. The decoder performs an interleaving process using the received code order conversion table, creates a code order restoration table from the code order conversion table, and performs a deinterleaving process. When the code order conversion table 310 is intermittently transmitted to the decoder, the encoder side uses the code order conversion table 310 already created until the next transmission (or is created in advance). A fixed code order conversion table may be used interlaced.) Since the processing by the code order conversion processing means 306 is performed, it is not necessary to perform the processes by the processing means 301 to 305.

  According to the third embodiment, as in the first and second embodiments, the degree of randomization by the code order conversion process using the real number label, the effect of improving the performance of the communication system, and the scrambling. By using functions to improve the degree of randomization and communication system performance, by using pseudo-stochastic process generators to facilitate real number label generation, and by using block order conversion rules in accordance with code-matched design concepts In addition to being able to obtain the effect of destroying a fatal input pattern, the code order conversion table 310 is not created in advance, but is created in real time using the information bit sequence C, thereby realizing confidential communication. be able to.

[Fourth Embodiment]
FIG. 15 shows the configuration of an interleaver 400 that is a code order conversion apparatus according to the fourth embodiment of the present invention. The fourth embodiment is an embodiment according to the invention of the code order conversion table real-time creation / content information direct rearrangement simultaneous processing. FIG. 16 shows an example of in-line sorting by the interleaver 400.

  In FIG. 15, real number label generation processing means 401, matrix arrangement processing means 402, in-line sorting processing means 403, block sorting processing means 404, code order conversion table creation processing means 405, matrix read processing means 406, A scrambling function storage unit 407 and a block order conversion rule storage unit 408 are provided.

  The real number label generation processing unit 401 uses the value of each constituent bit of the information bit sequence C to be subjected to the code order conversion process instead of the virtual bit sequence to generate a real number label of the first embodiment. This is the same as the case of the real number label generation processing means 51.

  The matrix arrangement processing unit 402 includes the real position labels generated by the real number label generation processing unit 401 and the array position information in the information bit sequence C before the code order conversion process of each bit to which these real number labels are attached. In a state where a pair of (information indicating what number bit is) and content information indicating the value of each bit (information of “1” or “0”), each array position information and each content information A process of sequentially arranging each bit in the row direction in a matrix form in accordance with the arrangement order before the code order conversion process of each bit together with each real number label (see FIG. 16).

  As shown in FIG. 16, the in-line sorting processing unit 403 arranges each array position information and each content information arranged in a matrix form by the matrix arrangement processing unit 402 according to the order of the numerical value of each real number label in each row. The in-line sorting process to be replaced is performed.

  The block sorting processing unit 404 rearranges each array position information and each content information after the in-line sorting by the in-line sorting processing unit 403 in units of rows in accordance with the block order conversion rules stored in the block order conversion rule storage unit 408. The processing is performed.

  The code order conversion table creation processing unit 405 sequentially reads the array position information after the block sorting by the block sorting processing unit 404 in the column direction, so that the bit sequence before the code order conversion process and the bit sequence after the code order conversion process The code order conversion table 410 that defines the corresponding relationship between the constituent bits is generated.

Matrix read processing unit 406 performs a process of generating a bit sequence C ^h after encoding sequence conversion processing by sequentially reading each contents information after block sorting by the block sorting processing unit 404 in the column direction.

  The scrambling function storage means 407 stores the scrambling function Y = g (X) used in the processing by the real number label generation processing means 401, and the scrambling function storage means 56 of the first embodiment. It is the same.

  The block order conversion rule storage unit 408 stores a block order conversion rule when the block sorting processing unit 404 performs block sorting. This block order conversion rule is the same as that in the first embodiment.

  In such a fourth embodiment, in each process by the matrix arrangement processing unit 402, the in-line sorting processing unit 403, and the block sorting processing unit 404, not only the real number label and the array position information are paired, but also In addition, content information is also handled in pairs, which is different from the third embodiment (see FIG. 16). Therefore, in the third embodiment, the code order conversion table 310 (see FIG. 14) is once created and then the code order conversion process is performed using the code order conversion table 310. In the embodiment, since the content information is already rearranged at the stage where the processing by the block sorting processing unit 404 is completed, the creation processing of the code order conversion table 410 and the code order conversion processing are performed in parallel. .

  According to the fourth embodiment, as in the first and second embodiments, the degree of randomization by the code order conversion process using the real number label and the effect of improving the performance of the communication system, scrambling. By using functions to improve the degree of randomization and communication system performance, by using pseudo-stochastic process generators to facilitate real number label generation, and by using block order conversion rules in accordance with code-matched design concepts In addition to being able to obtain an effect of destroying a fatal input pattern, as in the case of the third embodiment, the code order conversion table 410 is not created in advance, but the information bit sequence C is used. Since it is created in real time, secret communication can be realized.

[Fifth Embodiment]
FIG. 17 shows the configuration of an interleaver 500 that is a code order conversion apparatus according to the fifth embodiment of the present invention. The fifth embodiment is an embodiment according to the invention of creating an in-line sorting table in real time.

  In FIG. 17, the interleaver 500 includes a real number label generation processing unit 501, an array processing unit 502, an in-line sorting table creation processing unit 503, a matrix arrangement processing unit 504, an in-line sorting processing unit 505, and a block sorting processing unit. 506, a matrix reading processing unit 507, a scrambling function storage unit 508, and a block order conversion rule storage unit 509.

  The real number label generation processing unit 501 generates the real number label using the value of each component bit of the information bit sequence C that is the target of the code order conversion process, not the virtual bit sequence, except for the first embodiment. This is the same as the case of the real number label generation processing means 51.

  The array processing unit 502 includes array position information (in the information bit sequence C before the code order conversion processing of each real number label generated by the real number label generation processing unit 501 and each bit assigned with each real number label ( In this state, each array position information is sequentially arranged in the memory according to the arrangement order before the code order conversion process of each bit together with each real number label. is there.

  The in-line sorting table creation processing unit 503 divides each array position information arrayed by the array processing unit 502 into a plurality of blocks and rearranges each block according to the order of the numerical value of each real number label to thereby sort the in-line sorting processing unit The process of creating the in-line sorting table 510 used in the process of 505 for each block corresponding to each line is performed.

  The matrix arrangement processing means 504 displays the content information (information of “1” or “0”) indicating the value of each bit constituting the information bit series C in a matrix format according to the arrangement order before the code order conversion process of each bit. A process of sequentially arranging the memory in the row direction is performed.

  The in-line sorting processing unit 505 performs an in-line sorting process in which each content information arranged in a matrix format by the matrix arrangement processing unit 504 is rearranged in each row by using each in-line sorting table 510.

  The block sorting processing unit 506 performs block sorting processing for rearranging each piece of content information after the in-line sorting by the in-line sorting processing unit 505 in units of rows according to the block order conversion rules stored in the block order conversion rule storage unit 509. is there.

Matrix read processing unit 507 performs a process of generating a bit sequence C ^h after encoding sequence conversion processing by sequentially reading each contents information after block sorting by the block sorting processing unit 506 in the column direction.

  The scrambling function storage means 508 stores the scrambling function Y = g (X) used in the processing by the real number label generation processing means 501. In the case of the scrambling function storage means 56 of the first embodiment, It is the same.

  The block order conversion rule storage unit 509 stores a block order conversion rule at the time of block sorting by the block sorting processing unit 506. This block order conversion rule is the same as that in the first embodiment.

In such a fifth embodiment, the real number label generation processing means 501 randomly generates a real number label using the values of the constituent bits of the information bit sequence C to be subjected to the code order conversion process, and the array processing means 502. Thus, each real number label and each array position information are paired and sequentially arranged according to the array order before the code order conversion process of each bit, and the in-line sorting table creation processing means 503 converts each array position information to the numerical value of each real number label. By rearranging in the order of size, that is, by performing processing corresponding to in-line sorting, an in-line sorting table 510 is created for each line. Then, the matrix arrangement processing unit 504 sequentially arranges the content information of each constituent bit of the information bit series C in the row direction in a matrix format, and the in-line sorting processing unit 505 arranges each content information in each row within each in-line sorting table. After performing in-line sorting using 510, the block sorting processing unit 506 performs block sorting that rearranges each content information in units of rows according to the block order conversion rules stored in the block order conversion rule storage unit 509. the matrix read processing unit 507, it generates a bit sequence C ^h after encoding sequence conversion processing by sequentially reading each content information in the column direction.

  According to the fifth embodiment, as in the first and second embodiments, the degree of randomization by the code order conversion process using the real number label, the effect of improving the performance of the communication system, and the scrambling. By using functions to improve the degree of randomization and communication system performance, by using pseudo-stochastic process generators to facilitate real number label generation, and by using block order conversion rules in accordance with code-matched design concepts In addition to being able to obtain the effect of destroying a fatal input pattern, the in-line sorting table 510 for each line is not created in advance, but is created in real time using the information bit series C, so that confidential communication can be performed. Can be realized.

[Sixth Embodiment]
FIG. 18 shows the configuration of an interleaver 600 that is a code order conversion apparatus according to the sixth embodiment of the present invention. The sixth embodiment is an embodiment according to the invention of an in-line sorting table real-time creation / content information direct rearrangement simultaneous processing.

  In FIG. 18, an interleaver 600 includes a real number label generation processing unit 601, a matrix arrangement processing unit 602, an in-line sorting processing unit 603, an in-line sorting table creation processing unit 604, a block sorting processing unit 605, and a matrix reading process. Means 606, scrambling function storage means 607, and block order conversion rule storage means 608 are provided.

  The real number label generation processing unit 601 generates the real number label using the value of each constituent bit of the information bit sequence C to be subjected to the code order conversion process instead of the virtual bit sequence, except for the virtual bit sequence. This is the same as the case of the real number label generation processing means 51.

  The matrix arrangement processing unit 602 includes the real position labels generated by the real number label generation processing unit 601, and the array position information in the information bit sequence C before the code order conversion process of each bit assigned with each real number label. In a state where a pair of (information indicating what number bit is) and content information indicating the value of each bit (information of “1” or “0”), each array position information and each content information A process of sequentially arranging each bit in the row direction in a matrix form in accordance with the arrangement order before the code order conversion process of each bit together with each real number label (see FIG. 16).

  The in-line sorting processing means 603 performs an in-line sorting process for rearranging each array position information and each content information arranged in a matrix form by the matrix arrangement processing means 602 according to the order of the numerical value of each real number label in each line. It is.

  The in-line sorting table creation processing unit 604 sequentially reads out the array position information after the in-line sorting by the in-line sorting processing unit 603 for each row, thereby setting the in-line sorting table 610 that defines the order conversion rule for each in-line sorting to each row. A process of creating each corresponding block is performed.

  The block sorting processing unit 605 stores each piece of content information (which may be accompanied by each array position information) after the in-line sorting by the in-line sorting processing unit 603 in accordance with the block order conversion rule stored in the block order conversion rule storage unit 608. This is a block sorting process for rearranging lines.

Matrix read processing section 606 performs a process of generating a bit sequence C ^h after encoding sequence conversion processing by sequentially reading each contents information after block sorting by the block sorting processing unit 605 in the column direction.

  The scrambling function storage means 607 stores the scrambling function Y = g (X) used in the processing by the real number label generation processing means 601. In the case of the scrambling function storage means 56 of the first embodiment, It is the same.

  The block order conversion rule storage unit 608 stores a block order conversion rule at the time of block sorting by the block sorting processing unit 605. This block order conversion rule is the same as that in the first embodiment.

  In such a sixth embodiment, in each process by the matrix arrangement processing unit 602 and the in-row sorting processing unit 603, not only the real number label and the array position information are paired, but also the content information is paired. This is different from the fifth embodiment (refer to FIG. 16) in that it is handled in the same manner (the same handling may be applied to the processing by the block sorting processing means 605). Therefore, in the fifth embodiment, the in-line sorting table 510 (see FIG. 17) for each line is once created, and then the in-line sorting process is performed using the in-line sorting table 510 for each line. In the sixth embodiment, since the content information has already been rearranged at the stage where the processing by the in-line sorting processing unit 603 is completed, the creation processing of the in-line sorting table 610 for each row and the in-line sorting processing are performed in parallel. Will be done.

  According to the sixth embodiment, as in the first and second embodiments, the degree of randomization by the code order conversion process using the real number label, the effect of improving the performance of the communication system, and the scrambling. By using functions to improve the degree of randomization and communication system performance, by using pseudo-stochastic process generators to facilitate real number label generation, and by using block order conversion rules in accordance with code-matched design concepts In addition to being able to obtain the effect of destroying the fatal input pattern, as in the case of the fifth embodiment, the information bit sequence C is not created in advance, but the in-line sorting table 610 for each row is created. Since it is used and created in real time, secret communication can be realized.

[Seventh Embodiment]
FIG. 19 shows the configuration of an interleaver 700 that is a code order conversion apparatus according to the seventh embodiment of the present invention. The seventh embodiment is an embodiment according to the invention of content information direct rearrangement. FIG. 20 shows an example of in-line sorting by the interleaver 700.

  In FIG. 19, the interleaver 700 includes a real number label generation processing unit 701, a matrix arrangement processing unit 702, an in-line sorting processing unit 703, a block sorting processing unit 704, a matrix reading processing unit 705, and a scrambling function storage unit. 706 and a block order conversion rule storage unit 707.

  The real number label generation processing unit 701 generates the real number label using the value of each component bit of the information bit sequence C that is the target of the code order conversion process, not the virtual bit sequence, except for the first embodiment. This is the same as the case of the real number label generation processing means 51.

  The matrix arrangement processing unit 702 includes content information (“1” or “0” information) indicating each real number label generated by the real number label generation processing unit 701 and the value of each bit assigned with each real number label. ) Are paired with each real number label to sequentially arrange the contents information in the row direction in the memory in the matrix format according to the arrangement order before the code order conversion process of each bit (see FIG. 20). ).

  As shown in FIG. 20, the in-line sorting processing unit 703 performs an in-line sorting process in which each content information arranged in a matrix format by the matrix arrangement processing unit 702 is rearranged in each row according to the numerical value order of each real number label. Is what you do.

  The block sorting processing unit 704 performs block sorting processing that rearranges each piece of content information after the in-line sorting by the in-line sorting processing unit 703 in units of rows according to the block order conversion rules stored in the block order conversion rule storage unit 707. is there.

Matrix read processing unit 705 performs a process of generating a bit sequence C ^h after encoding sequence conversion processing by sequentially reading each contents information after block sorting by the block sorting processing unit 704 in the column direction.

  The scrambling function storage means 706 stores the scrambling function Y = g (X) used in the processing by the real number label generation processing means 701, and in the case of the scrambling function storage means 56 of the first embodiment. It is the same.

  The block order conversion rule storage unit 707 stores the block order conversion rule at the time of block sorting by the block sorting processing unit 704. This block order conversion rule is the same as that in the first embodiment.

  In such a seventh embodiment, the content information of each bit is directly rearranged according to the order of the real number labels and the block order conversion rule without using the code order conversion table or the in-line sorting table for each line.

  Also, the code side conversion performed on the encoder side is performed on the decoder side by, for example, transmitting the real number label sequence 710 in the state before in-line sorting continuously or intermittently for each processing unit. The contents of the processing can be transmitted to the decoder side.

  According to the seventh embodiment, as in the first and second embodiments, the degree of randomization by the code order conversion process using the real number label, the effect of improving the performance of the communication system, and the scrambling. By using functions to improve the degree of randomization and communication system performance, by using pseudo-stochastic process generators to facilitate real number label generation, and by using block order conversion rules in accordance with code-matched design concepts In addition to being able to obtain the effect of destroying a fatal input pattern, since the code order conversion table and the in-line sorting table for each line are not created in advance, secret communication can be realized.

[Deformation form]
Note that the present invention is not limited to the above-described embodiments, and modifications and the like within a range in which the object of the present invention can be achieved are included in the present invention.

  That is, in each of the above embodiments, the code order conversion apparatus of the present invention is applied to a turbo code interleaver provided in an error correction processing unit of a communication system such as a mobile phone system. It is not limited to the application, is not limited to the application to the error correction processing unit, is not limited to the turbo code, and is further limited to the application to the interleaver In short, the present invention can be applied to any information processing device that requires random code order conversion processing.

  Further, in each of the embodiments, the fixed block order conversion rule is used. However, the rule is not limited to this, and is not limited to this, but continuously or intermittently for each processing unit (for example, 512 bits). It may be changed. In this case, on the transmitter side, information indicating which block order conversion rule is selected and used, or information indicating the used block order conversion rule itself (for example, 20-dimensional vector information) is transmitted to the receiver side. do it. Thus, when the block order conversion rule to be used is changed, the confidentiality can be improved.

  Furthermore, each processing means of the second to seventh embodiments can be realized by a CPU and one or a plurality of programs that define the operation procedure of the CPU, and each processing means is a hardware circuit. The points that may be realized by the above are the same as in the case of the first embodiment. The storage means of the second to seventh embodiments include, for example, a hard disk, ROM, EEPROM, flash memory, RAM, MO, CD-ROM, CD-R, CD-RW, DVD-ROM, DVD -The point which can employ | adopt RAM, FD, a magnetic tape, or these combination etc. is the same as that of the case of the said 1st Embodiment.

  As described above, the code order conversion method and apparatus, the code order conversion table creation apparatus, and the turbo code encoder and decoder according to the present invention include, for example, a communication system such as a mobile phone system, and other turbo codes. Suitable for intervening information processing equipment.

The whole block diagram of the error correction process part by the turbo code provided in the communication system which concerns on 1st Embodiment of this invention. FIG. 3 is a configuration diagram of a code order conversion table creation device, an interleaver, and a deinterleaver according to the first embodiment. The conceptual diagram which shows the flow of the preparation process of the code order conversion table of 1st Embodiment. The figure of the flowchart which shows the flow of the preparation processing of the code order conversion table of 1st Embodiment, and a code order restoration table. The figure of the flowchart which shows the flow of the interleave process of 1st Embodiment. The figure of the flowchart which shows the flow of the deinterleaving process of 1st Embodiment. Explanatory drawing of the production | generation method of the component bit of a virtual bit series at the time of preparation of the code order conversion table of 1st Embodiment. The detailed explanatory view of the creation processing of the code order conversion table of the first embodiment. Another detailed explanatory drawing of the creation processing of the code order conversion table of 1st Embodiment. Explanatory drawing of the shape of the scrambling function of 1st Embodiment. Explanatory drawing of the creation method of the block order conversion rule of 1st Embodiment. The figure which shows the comparison experiment result by simulation of 1st Embodiment. The block diagram of the interleaver and in-line sorting table preparation apparatus of 2nd Embodiment. The block diagram of the interleaver of 3rd Embodiment. The block diagram of the interleaver of 4th Embodiment. The figure which shows the example of the in-line sorting by the interleaver of 4th Embodiment. The block diagram of the interleaver of 5th Embodiment. The block diagram of the interleaver of 6th Embodiment. The block diagram of the interleaver of 7th Embodiment. The figure which shows the example of the in-line sorting by the interleaver of 7th Embodiment.

Explanation of symbols

20 Coder for turbo code 23, 33, 200, 300, 400, 500, 600, 700 Interleaver 23A, 33A Code order conversion table storage means 23B, 33B, 306 Code order conversion processing means 30 Decoder for turbo code 50 Code order conversion table creation device 51, 211, 301, 401, 501, 601, 701 Real number label generation processing means 51B Shift processing means 51C Weight calculation processing means 51D Weight / label conversion processing means 52, 201 , 302, 402, 504, 602, 702 Matrix arrangement processing means 53, 202, 303, 403, 505, 603, 703 In-line sorting processing means 54, 203, 304, 404, 506, 605, 704 Block sorting processing means 55, 204,406 507, 606, 705 Matrix reading processing means 60, 310, 410 Code order conversion table 205 In-line sorting table storage means 212, 502 Array processing means 220, 510, 610 In-line sorting table 305, 405 Code order conversion table creation processing means 503 604 In-line sorting table creation processing means C Information bit sequence {U _n } Virtual bit sequence X, {X _n } Real number Y, {Y _n } Real number which is a real number label

Claims (30)

Prior to the code order conversion process of the information bit sequence, a virtual bit sequence is generated or prepared as a substitute for the information bit sequence, and the value of at least one bit of a plurality of bits constituting the virtual bit sequence is used. , Randomly generate a real number label attached to each bit constituting this virtual bit sequence,
In a state where the generated real number labels are paired with the array position information in the virtual bit sequence before the code order conversion process of the bits to which the real number labels are attached, the array position information Sequentially arranged in the row direction in a matrix form according to the arrangement order before the code order conversion processing of each bit together with each real number label,
After performing in-line sorting in which each array position information arranged in a matrix format is rearranged according to the order of the numerical value of each real number label in each line,
Performing block sorting that rearranges each array position information after the in-row sorting arranged in a matrix format in units of rows in accordance with a predetermined block order conversion rule,
Correspondence between the constituent bits of the bit sequence before the code order conversion processing and the bit sequence after the code order conversion processing by sequentially reading the array position information after the block sorting arranged in a matrix format in the column direction A code order conversion table that defines the relationship is created in advance and stored in the code order conversion table storage means,
When performing the code order conversion process of the information bit sequence, the bits constituting the information bit sequence are rearranged using the code order conversion table stored in the code order conversion table storage unit. A code order conversion method. Prior to the code order conversion process of the information bit sequence, a virtual bit sequence is generated or prepared as a substitute for the information bit sequence, and the value of at least one bit of a plurality of bits constituting the virtual bit sequence is used. , Randomly generate a real number label attached to each bit constituting this virtual bit sequence,
In a state where the generated real number labels are paired with the array position information in the virtual bit sequence before the code order conversion process of the bits to which the real number labels are attached, the array position information Arrange sequentially according to the arrangement order before the code order conversion processing of each bit together with each real number label,
By dividing each array position information arranged into a plurality of blocks and rearranging each block in accordance with the numerical order of the numerical value of each real number label, the code bit order conversion processing of the information bit sequence is performed in each row. An in-line sorting table that defines an order conversion rule at the time of sorting is created for each of the blocks corresponding to the respective rows and stored in the in-line sorting table storage means,
When performing the code order conversion processing of the information bit sequence,
The content information indicating the value of each bit constituting the information bit sequence is sequentially arranged in the row direction in a matrix form according to the arrangement order before the code order conversion processing of each bit,
After performing the in-line sorting in which each content information arranged in a matrix format is rearranged using the in-line sorting table stored in the in-line sorting table storage means in each row,
Performing block sorting that rearranges each content information after the intra-row sorting arranged in a matrix format in units of rows according to a predetermined block order conversion rule,
A code sequence conversion method comprising: generating a bit sequence after code sequence conversion processing by sequentially reading the content information after the block sorting arranged in a matrix format in a column direction. Using a value of at least one of a plurality of bits constituting the information bit sequence to be subjected to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated. ,
In a state where the generated real number labels are paired with the array position information in the information bit sequence before the code order conversion processing of the bits to which the real number labels are attached, the array position information Sequentially arranged in the row direction in a matrix form according to the arrangement order before the code order conversion processing of each bit together with each real number label,
After performing in-line sorting in which each array position information arranged in a matrix format is rearranged according to the order of the numerical value of each real number label in each line,
Performing block sorting that rearranges each array position information after the in-row sorting arranged in a matrix format in units of rows in accordance with a predetermined block order conversion rule,
Correspondence between the constituent bits of the bit sequence before the code order conversion processing and the bit sequence after the code order conversion processing by sequentially reading the array position information after the block sorting arranged in a matrix format in the column direction Create a code order conversion table that defines the relationship,
Then, the code order conversion method, wherein the bits constituting the information bit sequence are rearranged using the code order conversion table. Using a value of at least one of a plurality of bits constituting the information bit sequence to be subjected to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated. ,
Each generated real number label and the arrangement position information in the information bit sequence before the code order conversion processing of each bit to which each real number label is attached are paired with the content information indicating the value of each bit. In this state, each array position information and each content information are sequentially arranged in the row direction in a matrix format according to the array order before the code order conversion processing of each bit together with each real number label,
After performing in-line sorting in which each array position information and each content information arranged in a matrix format are rearranged according to the numerical order of the numerical value of each real number label in each line,
Performing a block sorting that rearranges each array position information and each content information after the in-row sorting arranged in a matrix format in units of rows according to a predetermined block order conversion rule,
Correspondence between the constituent bits of the bit sequence before the code order conversion processing and the bit sequence after the code order conversion processing by sequentially reading the array position information after the block sorting arranged in a matrix format in the column direction A code sequence conversion table for defining a relationship is created, and the bit sequence after the code sequence conversion process is generated by sequentially reading each content information after the block sorting arranged in a matrix format in a column direction. A code order conversion method. Using a value of at least one of a plurality of bits constituting the information bit sequence to be subjected to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated. ,
In a state where the generated real number labels are paired with the array position information in the information bit sequence before the code order conversion processing of the bits to which the real number labels are attached, the array position information Arrange sequentially according to the arrangement order before the code order conversion processing of each bit together with each real number label,
The in-line ordering rule for the in-line sorting performed in each line is determined by dividing each array position information arranged into a plurality of blocks and rearranging in accordance with the numerical order of the numerical value of each real number label in each block. Create a sorting table for each block corresponding to each row,
After that, content information indicating the value of each bit constituting the information bit sequence is sequentially arranged in the row direction in a matrix format according to the arrangement order before the code order conversion processing of each bit,
After performing the in-line sorting in which each content information arranged in a matrix format is rearranged using the in-line sorting table in each of the lines,
Performing block sorting that rearranges each content information after the intra-row sorting arranged in a matrix format in units of rows according to a predetermined block order conversion rule,
A code sequence conversion method comprising: generating a bit sequence after code sequence conversion processing by sequentially reading the content information after the block sorting arranged in a matrix format in a column direction. Using a value of at least one of a plurality of bits constituting the information bit sequence to be subjected to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated. ,
Each generated real number label and the arrangement position information in the information bit sequence before the code order conversion processing of each bit to which each real number label is attached are paired with the content information indicating the value of each bit. In this state, each array position information and each content information are sequentially arranged in the row direction in a matrix format according to the array order before the code order conversion processing of each bit together with each real number label,
After performing in-line sorting in which each array position information and each content information arranged in a matrix format are rearranged according to the numerical order of the numerical value of each real number label in each line,
By sequentially reading the array position information after the intra-row sorting arranged in a matrix form in the row direction for each row, an intra-row sorting table that defines an order conversion rule for each intra-row sorting is associated with each row. Create for each block, and perform block sorting that rearranges each content information after the in-line sorting arranged in a matrix format in units of rows according to a predetermined block order conversion rule,
A code sequence conversion method comprising: generating a bit sequence after code sequence conversion processing by sequentially reading the content information after the block sorting arranged in a matrix format in a column direction. Using a value of at least one of a plurality of bits constituting the information bit sequence to be subjected to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated. ,
In a state where each generated real number label is paired with the content information indicating the value of each bit to which each real number label is attached, each content information is converted to the code order of each bit together with each real number label. Arrange sequentially in the row direction in the matrix format according to the array order before processing,
After performing in-line sorting in which each content information arranged in a matrix format is rearranged according to the numerical order of the numerical value of each real number label in each line,
Performing block sorting that rearranges each content information after the intra-row sorting arranged in a matrix format in units of rows according to a predetermined block order conversion rule,
A code sequence conversion method comprising: generating a bit sequence after code sequence conversion processing by sequentially reading the content information after the block sorting arranged in a matrix format in a column direction. In the code order conversion method according to any one of claims 1 to 7,
When generating each real number label,
After calculating the real number X between the real number X _a and the real number X _b using each value of a plurality of consecutive bits,
When t is a real number in the range of X _a ≦ t <(X _a + X _b ) / 2,
with g (t) + g (t + (X b -X a) / 2) = Y a + Y b satisfies the condition that scrambling function Y = g (X), between the real number X _a ~ real X _b Convert real number X to real number Y between real number Y _a and real number Y _b ,
The value of the real number Y obtained by conversion is used as the real number label,
By using each value of the plurality of consecutive bits while shifting one bit at a time, it repeats the calculation process of the real number X and the conversion process from the real number X to the real number Y by the scrambling function. Each of the real number labels is sequentially generated. The code order conversion method according to claim 8,
The process of calculating the real number X between the real number X _a to the real number X _b using the values of the plurality of consecutive bits is M, where m is the number of bits used for the calculation and M is an integer from 1 to M. Calculate the real number X between 0 and ¹ by adding the value obtained by multiplying each bit value by 2 ^-m and adding 2- ^{(M + 1)} to X. Process
The conversion process from the real number X between the real number X _a to the real number X _b to the real number Y between the real number Y _a to the real number Y _b by the scrambling function is between the real number X between 0 and 1 and 0 to 1. To a real number Y,
The code order conversion method characterized in that the calculation process of the real number X and the conversion process from the real number X to the real number Y by the scrambling function are pseudo-probabilistic process generation processing. In the code order conversion method according to any one of claims 1 to 9,
In the block order conversion rule, at least two bits that are 7 bits apart from each bit constituting the bit sequence before the code order conversion process are arranged at positions separated by 7 bits in the bit sequence after the code order conversion process. The code order conversion method characterized by being a rule for avoiding this. In the code order conversion method according to any one of claims 1 to 10,
The code order conversion method, wherein the code order conversion process is performed as a turbo code interleaving process. Code order conversion table storage means for storing a code order conversion table that defines the correspondence between the constituent bits of the bit sequence before the code order conversion process and the bit sequence after the code order conversion process;
Using the code order conversion table stored in the code order conversion table storage means, code order conversion processing means for performing a process of rearranging each bit constituting the information bit sequence,
The code order conversion table stored in the code order conversion table storage means is:
A virtual bit sequence is generated or prepared as a substitute for the information bit sequence, and a value of at least one bit of the plurality of bits constituting the virtual bit sequence is used to attach to each bit constituting the virtual bit sequence. Randomly generated real number labels,
In a state where the generated real number labels are paired with the array position information in the virtual bit sequence before the code order conversion process of the bits to which the real number labels are attached, the array position information Sequentially arranged in the row direction in a matrix form according to the arrangement order before the code order conversion processing of each bit together with each real number label,
After performing in-line sorting in which each array position information arranged in a matrix format is rearranged according to the order of the numerical value of each real number label in each line,
Performing block sorting that rearranges each array position information after the in-row sorting arranged in a matrix format in units of rows in accordance with a predetermined block order conversion rule,
A code order conversion apparatus, comprising: a table created by sequentially reading the array position information after the block sorting arranged in a matrix format in a column direction. A code order conversion table creating device for creating a code order conversion table used when performing a code order conversion process for rearranging each bit constituting an information bit sequence,
Using a value of at least one bit of a plurality of bits constituting a virtual bit sequence generated or prepared as a substitute for the information bit sequence, a real number label attached to each bit constituting the virtual bit sequence Real number label generation processing means for randomly generating; and
In a state in which each real number label generated by the real number label generation processing means is paired with the array position information in the virtual bit sequence before the code order conversion process of each bit to which each real number label is attached. Matrix arrangement processing means for sequentially arranging the respective array position information together with the respective real number labels in the row direction in a matrix format according to the arrangement order before the code order conversion process of each bit;
In-line sorting processing means for performing in-line sorting in which each array position information arranged in a matrix format by the matrix arrangement processing means is rearranged according to the numerical order of the numerical value of each real number label in each row, and
Block sorting processing means for performing block sorting for rearranging each array position information after the in-line sorting by the in-line sorting processing means in line units according to a predetermined block order conversion rule;
A code order conversion table creating apparatus comprising: matrix read processing means for sequentially reading the array position information after the block sorting by the block sorting processing means in a column direction. In-line sorting table storage means for storing an in-line sorting table for each block corresponding to each row, which defines an order conversion rule for the in-line sorting performed in each row in the code order conversion processing of the information bit sequence;
Matrix arrangement processing means for sequentially arranging the content information indicating the value of each bit constituting the information bit sequence in the row direction in a matrix format according to the arrangement order before the code order conversion process of each bit;
In-line sorting processing means for performing in-line sorting in which each content information arranged in a matrix format by the matrix arrangement processing means is rearranged using the in-line sorting table in each row, and
Block sorting processing means for performing block sorting for rearranging the contents information after the in-line sorting by the in-line sorting processing means in units of lines according to a predetermined block order conversion rule;
Matrix reading processing means for generating a bit sequence after code order conversion processing by sequentially reading the content information after the block sorting by the block sorting processing means in the column direction,
Each in-line sorting table stored in the in-line sorting table storage means is:
A virtual bit sequence is generated or prepared as a substitute for the information bit sequence, and a value of at least one bit of the plurality of bits constituting the virtual bit sequence is used to attach to each bit constituting the virtual bit sequence. Randomly generated real number labels,
In a state where the generated real number labels are paired with the array position information in the virtual bit sequence before the code order conversion process of the bits to which the real number labels are attached, the array position information Sequentially arranged according to the arrangement order before the code order conversion processing of each bit together with each real number label,
The code order conversion device according to claim 1, wherein the arrangement information is a table created by dividing the arranged array position information into a plurality of blocks and rearranging the blocks in order according to the numerical order of the numerical values of the real labels. Using a value of at least one bit among a plurality of bits constituting the information bit sequence subject to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated Real number label generation processing means;
In a state where each real number label generated by the real number label generation processing means is paired with the array position information in the information bit sequence before the code order conversion processing of each bit to which each real number label is attached. Matrix arrangement processing means for sequentially arranging the respective array position information together with the respective real number labels in the row direction in a matrix format according to the arrangement order before the code order conversion process of each bit;
In-line sorting processing means for performing in-line sorting in which each array position information arranged in a matrix format by the matrix arrangement processing means is rearranged according to the numerical order of the numerical value of each real number label in each row, and
Block sorting processing means for performing block sorting for rearranging each array position information after the in-line sorting by the in-line sorting processing means in line units according to a predetermined block order conversion rule;
Correspondence between the constituent bits of the bit sequence before the code order conversion processing and the bit sequence after the code order conversion processing by sequentially reading the array position information after the block sorting by the block sorting processing means in the column direction Code order conversion table creation processing means for creating a code order conversion table for defining a relationship;
A code order conversion apparatus comprising: code order conversion processing means for rearranging each bit constituting the information bit sequence using the code order conversion table created by the code order conversion table creation processing means. . Using a value of at least one bit among a plurality of bits constituting the information bit sequence subject to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated Real number label generation processing means;
The real number labels generated by the real number label generation processing means, the array position information in the information bit sequence before the code order conversion processing of the bits to which the real number labels are attached, and the values of the bits. A matrix that sequentially arranges each array position information and each content information together with each real number label in the row direction in a matrix format according to the array order before the code order conversion process of each bit in a state in which the content information shown is paired Arrangement processing means;
In-line sorting processing means for performing in-line sorting in which each array position information and each content information arranged in a matrix format by the matrix arrangement processing means are rearranged in accordance with the numerical order of the numerical value of each real number label in each line;
Block sorting processing means for performing block sorting for rearranging the array position information and the content information after the in-line sorting by the in-line sorting processing means in units of rows according to a predetermined block order conversion rule;
Correspondence between the constituent bits of the bit sequence before the code order conversion processing and the bit sequence after the code order conversion processing by sequentially reading the array position information after the block sorting by the block sorting processing means in the column direction Code order conversion table creation processing means for creating a code order conversion table for defining a relationship;
Code order conversion comprising: matrix read processing means for generating a bit sequence after code order conversion processing by sequentially reading the content information after the block sorting by the block sorting processing means in a column direction. apparatus. Using a value of at least one bit among a plurality of bits constituting the information bit sequence subject to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated Real number label generation processing means;
In a state where each real number label generated by the real number label generation processing means is paired with the array position information in the information bit sequence before the code order conversion processing of each bit to which each real number label is attached. , Array processing means for sequentially arraying each array position information together with each real number label according to the array order before the code order conversion processing of each bit;
The order of the in-line sorting performed in each row by dividing each array position information arrayed by this array processing means into a plurality of blocks and rearranging in accordance with the order of the numerical value of each real number label in each block In-line sorting table creation processing means for creating an in-line sorting table for defining a conversion rule for each block corresponding to each row;
Matrix arrangement processing means for sequentially arranging the content information indicating the value of each bit constituting the information bit sequence in the row direction in a matrix format according to the arrangement order before the code order conversion process of each bit;
In-line sorting processing means for performing in-line sorting in which each content information arranged in a matrix format by the matrix arrangement processing means is rearranged using the in-line sorting table in each row, and
Block sorting processing means for performing block sorting for rearranging the contents information after the in-line sorting by the in-line sorting processing means in units of lines according to a predetermined block order conversion rule;
Code order conversion comprising: matrix read processing means for generating a bit sequence after code order conversion processing by sequentially reading the content information after the block sorting by the block sorting processing means in a column direction. apparatus. Using a value of at least one bit among a plurality of bits constituting the information bit sequence subject to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated Real number label generation processing means;
The real number labels generated by the real number label generation processing means, the array position information in the information bit sequence before the code order conversion processing of the bits to which the real number labels are attached, and the values of the bits. A matrix that sequentially arranges each array position information and each content information together with each real number label in the row direction in a matrix format according to the array order before the code order conversion process of each bit in a state in which the content information shown is paired Arrangement processing means;
In-line sorting processing means for performing in-line sorting in which each array position information and each content information arranged in a matrix format by the matrix arrangement processing means are rearranged in accordance with the numerical order of the numerical value of each real number label in each line;
By sequentially reading the array position information after the in-line sorting by the in-line sorting processing unit for each line, an in-line sorting table for defining an order conversion rule in the in-line sorting is obtained for each block corresponding to the each line. In-line sorting table creation processing means to be created;
Block sorting processing means for performing block sorting in which each content information after the in-line sorting by the in-line sorting processing means is rearranged in line units according to a predetermined block order conversion rule;
Code order conversion comprising: matrix read processing means for generating a bit sequence after code order conversion processing by sequentially reading the content information after the block sorting by the block sorting processing means in a column direction. apparatus. Using a value of at least one bit among a plurality of bits constituting the information bit sequence subject to code order conversion processing, a real number label attached to each bit constituting the information bit sequence is randomly generated Real number label generation processing means;
In a state where each real number label generated by the real number label generation processing unit and the content information indicating the value of each bit attached with each real number label are paired, the respective content information is set together with each real number label. Matrix arrangement processing means for sequentially arranging in the row direction in a matrix format according to the arrangement order before the code order conversion processing of each bit;
In-line sorting processing means for performing in-line sorting in which each content information arranged in a matrix format by the matrix arrangement processing means is rearranged according to the numerical order of the numerical values of each real number label in each row, and
Block sorting processing means for performing block sorting for rearranging the contents information after the in-line sorting by the in-line sorting processing means in units of lines according to a predetermined block order conversion rule;
Code order conversion comprising: matrix read processing means for generating a bit sequence after code order conversion processing by sequentially reading the content information after the block sorting by the block sorting processing means in a column direction. apparatus. The code order conversion device according to claim 12 or 14,
The processing for generating each real number label performed when the table is created is as follows.
After calculating the real number X between the real number X _a and the real number X _b using each value of a plurality of consecutive bits,
When t is a real number in the range of X _a ≦ t <(X _a + X _b ) / 2,
with g (t) + g (t + (X b -X a) / 2) = Y a + Y b satisfies the condition that scrambling function Y = g (X), between the real number X _a ~ real X _b Convert real number X to real number Y between real number Y _a and real number Y _b ,
The value of the real number Y obtained by conversion is used as the real number label,
By using each value of the plurality of consecutive bits while shifting one bit at a time, it repeats the calculation process of the real number X and the conversion process from the real number X to the real number Y by the scrambling function. The code order conversion device according to claim 1, wherein the real number labels are sequentially generated. The code order conversion device according to claim 20,
The process of calculating the real number X between the real number X _a to the real number X _b using the values of the plurality of consecutive bits is M, where m is the number of bits used for the calculation and M is an integer from 1 to M. Calculate the real number X between 0 and ¹ by adding the value obtained by multiplying each bit value by 2 ^-m and adding 2- ^{(M + 1)} to X. Process
The conversion process from the real number X between the real number X _a to the real number X _b to the real number Y between the real number Y _a to the real number Y _b by the scrambling function is between the real number X between 0 and 1 and 0 to 1. To a real number Y,
The code order conversion apparatus, wherein the real number X calculation processing and the conversion processing from the real number X to the real number Y by the scrambling function are pseudo-probability process generation processing. The code order conversion apparatus according to any one of claims 12, 14, 20, and 21,
In the block order conversion rule, at least two bits that are 7 bits apart from each bit constituting the bit sequence before the code order conversion process are arranged at positions separated by 7 bits in the bit sequence after the code order conversion process. The code order conversion apparatus characterized by being a rule for avoiding this. In the code | symbol order conversion apparatus in any one of Claim 12, 14, 20-22,
The code order conversion apparatus, wherein the code order conversion process is performed as a turbo code interleaving process. The code order conversion device according to any one of claims 15 to 19,
The real number label generation processing means includes:
Weight calculation processing means for calculating a real number X between the real number X _a and the real number X _b using each value of a plurality of consecutive bits;
When t is _a real number in the range of X _a ≦ t <(X _a + X _b ) / 2, the conditional expression g (t) + g (t + (X _b −X _a ) / 2) = Y _a + Y _b is satisfied. Using the scrambling function Y = g (X), the real number X between the real number X _a and the real number X _b is converted into the real number Y between the real number Y _a and the real number Y _b , and the real number Y obtained by the conversion Weight / label conversion processing means using the value of the real number as the real label,
Shift processing means for performing bit shift processing for repeating each processing by the weight calculation processing means and the weight / label conversion processing means using each value of the plurality of consecutive bits while shifting one bit at a time. The code | symbol order conversion apparatus characterized by the above-mentioned. The code order conversion device according to claim 24, wherein
When the number of bits used for calculation is M and m is an integer between 1 and M, the weight calculation processing means adds a value obtained by multiplying each value of M bits by 2 ^−m , and further 2 ^{− (M +1)} is added, and the numerical value obtained by X is set to be configured to perform a process of calculating a real number X between 0 and 1,
The weight / label conversion processing means is configured to perform conversion processing from a real number X between 0 and 1 to a real number Y between 0 and 1,
The real number label generation processing means is configured to perform a pseudo stochastic process generation process. In the code | symbol order conversion apparatus in any one of Claims 15-19, 24, 25,
The block sorting processing means includes:
As the block order conversion rule, at least two bits that are 7 bits apart from each bit constituting the bit sequence before the code order conversion process are arranged at positions separated by 7 bits in the bit sequence after the code order conversion process. The code order conversion device is characterized in that a rule for avoiding this is used. In the code | symbol order conversion apparatus in any one of Claims 15-19 and 24-26,
A code order conversion apparatus, characterized by being an interleaver for turbo codes. In the code | symbol order conversion apparatus of Claim 24 or 25,
The code order conversion apparatus according to claim 1, wherein the shift processing means comprises a shift register.   An encoder for turbo codes, comprising the code order conversion device according to any one of claims 12, 14 to 28 as an interleaver for turbo codes.   A decoder for turbo code, comprising the code order conversion device according to any one of claims 12, 14 to 28 as an interleaver for turbo code.

Images