JP2006013534A - Manufacturing method of semiconductor nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor nonvolatile storage device which allows a voltage drop on an operating voltage such as erasure voltage, and cost reduction to be obtained. <P>SOLUTION: This manufacturing method of the semiconductor nonvolatile storage connected with a memory transistor having a charge storage layer comprises a step of forming a semiconductor layer having a channel formation region on an insulating substrate composed of glass or plastic, and a step of forming the charge storage layer as an overlaying layer of the semiconductor layer. Further, the method comprises a step of forming a control gate above the charge storage layer, and a step of forming a source-drain region connected to the channel formation region, to form a thin-film transistor acting as a memory transistor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor nonvolatile memory device, and more particularly to a method for manufacturing a semiconductor nonvolatile memory device having a charge storage layer for storing charges between a gate electrode of a transistor and a channel formation region.

  Currently, semiconductor non-volatile memory devices are being actively developed, and various structures and configurations have been researched and developed, centering on a flash memory having a floating gate structure. This flash memory is roughly classified into a NAND type and a NOR type from the viewpoint of the cell configuration.

  Among the above, the NAND type has a plurality of memory cells connected in series and has a common selection transistor and bit line. For example, if eight memory cells are connected, half of the data input / output contacts are shared by the 8-bit memory cells, and 1/16 contacts per bit. Similarly, the selection gate and the source line are all shared by 8 bits. Therefore, as described above, the area per bit is close to the area occupied by the memory transistor, and the memory cell area is very small. Although random access is not possible due to its structure, it is advantageous in terms of high integration, large capacity, and low cost. For applications such as AV (audio and video) or data storage, a low-priced and large-capacity flash memory is required, and is suitable for replacement of magnetic recording means such as an HDD (hard disk drive).

  On the other hand, the NOR type has half the number of contacts per bit due to its structure, which is disadvantageous in terms of integration compared to the NAND type, but has the advantage that high-speed random access reading is possible. As a high-speed reading application, it is expected to be a part of the main memory in the future. The NAND type or NOR type memory transistor may be a floating gate type or a SIOS (or MONOS) type.

  A table comparing various performances of the NAND type and the NOR type is shown below.

  Here, a circuit diagram of the NOR type memory cell is shown in FIG. In erasing data, a low voltage Vcg is applied to the control gate CG, a high voltage Vs is applied to the source S, and the bit line B and the substrate Sub are opened. As a result, the electrons in the floating gate are extracted by the Fowler-Nordheim type tunnel phenomenon, and the data is erased. This erasing can be performed in batch for each erase sector.

  On the other hand, in the NAND type memory cell, as shown in FIG. 16, for example, 8-bit memory transistors are connected in series to form a NAND string, and selection transistors for selecting this NAND string are formed at both ends. Yes. As a method of erasing data in the NAND type memory cell, 0V is applied to the control gates CG of all NAND columns, and a high voltage (for example, 20V) is applied to the selection gates SG1 and SG2 of the two selection transistors and the substrate Sub. Further, the source S and the bit line B are opened. As a result, similarly to the NOR type, electrons in the floating gate are extracted by the Fowler-Nordheim type tunnel phenomenon, and the entire NAND string is erased at once.

  The present invention has been made in view of the above problems. Therefore, the present invention can reduce the operating voltage such as the erasing voltage, and can reduce the cost of the semiconductor nonvolatile memory device. An object is to provide a manufacturing method.

  In order to achieve the above object, a method for manufacturing a semiconductor nonvolatile memory device according to the present invention is a method for manufacturing a semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected, and is made of glass or plastic. Forming a semiconductor layer having a channel formation region on a conductive substrate, forming a charge storage layer above the semiconductor layer, forming a control gate above the charge storage layer, and forming the channel Forming a source / drain region connected to the region, and forming a thin film transistor to be the memory transistor.

  In the method for manufacturing a semiconductor nonvolatile memory device of the present invention, a semiconductor layer having a channel formation region is formed on an insulating substrate made of glass or plastic, a charge storage layer is formed above the semiconductor layer, and charge storage is performed. A control gate is formed above the layer, and source / drain regions connected to the channel formation region are formed. Accordingly, a thin film transistor (TFT) serving as a memory transistor having a charge storage layer can be formed on a low-cost insulating substrate made of glass or plastic between the control gate and the channel formation region in the semiconductor layer.

  According to the above method for manufacturing a semiconductor nonvolatile memory device of the present invention, a TFT serving as a memory transistor having a charge storage layer is formed on a low-cost insulating substrate such as glass. Therefore, a semiconductor nonvolatile memory device having a memory transistor that can operate at high speed can be manufactured at a significantly reduced cost.

  In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, the steps after the step of forming the semiconductor layer are preferably performed at 600 ° C. or lower. As a result, an insulating substrate made of glass or plastic having a low melting point but a low melting point can be employed, and cost reduction can be realized.

  In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of forming the semiconductor layer includes the step of forming a silicon layer and the silicon layer by an excimer laser annealing method or a low-temperature solid-phase crystallization method. Crystallizing the layer. As a result, the trap density in the film can be reduced and the gate swing value can be reduced by a low temperature process suitable for forming a TFT channel formation region on a glass substrate or plastic substrate. A polysilicon layer or a quasi-single crystal silicon layer which is a high-performance semiconductor layer can be formed.

In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, more preferably, the step of forming the silicon layer includes a CVD (chemical vapor deposition) method using Si ₂ H ₆ or SiH ₄ as a raw material. It is the process of forming by. As the CVD method, a low pressure CVD method or a plasma CVD method can be preferably used. According to a CVD method such as a low pressure CVD method or a plasma CVD method using Si ₂ H ₆ or SiH ₄ as a raw material, an insulating film is formed at a low temperature process of 500 ° C. or lower when laser light is irradiated in a later ELA process or the like. The silicon layer can be formed under conditions where there is little uptake of hydrogen into the film, which causes scattering and opening of holes.

  In the method for manufacturing a semiconductor nonvolatile memory device of the present invention, more preferably, the step of forming the silicon layer is a step of forming by a sputtering method. According to the sputtering method, the silicon layer can be formed by a low temperature process of 500 ° C. or lower.

  In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, more preferably, the step of forming the charge storage layer includes a step of forming a gate insulating film on an upper layer of the semiconductor layer, and a step of forming the gate insulating film. The method includes a step of forming a floating gate made of a conductor on the upper layer, and a step of forming an intermediate insulating film on the upper layer of the floating gate. Thus, a floating gate type semiconductor nonvolatile memory device can be obtained in which charges are confined and held in the conductive floating gate by the gate insulating film and the intermediate insulating film.

  In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, more preferably, the step of forming the charge storage layer is a step of forming an insulator having a charge trap in an upper layer of the semiconductor layer. Thereby, for example, a MONOS structure having an ONO film (a laminated insulating film of oxide film-nitride film-oxide film) or an NO film (a laminated insulating film of nitride film-oxide film) accumulates charges in an insulator having a charge trap. A semiconductor nonvolatile memory device such as an MNOS structure having a film) can be manufactured.

  More preferably, the method for manufacturing a semiconductor nonvolatile memory device according to the present invention is formed by connecting the memory transistor in a NOR type. As a result, a NOR type semiconductor nonvolatile memory device capable of high-speed random access reading and batch erasing for each erase sector can be manufactured.

  More preferably, the method for manufacturing a semiconductor nonvolatile memory device according to the present invention is formed by connecting the memory transistors in a NAND type. A NAND-type semiconductor nonvolatile memory device that is advantageous in terms of high integration, large capacity, and low cost can be manufactured.

  More preferably, the method for manufacturing a semiconductor nonvolatile memory device according to the present invention includes a step of forming an erase gate on the insulating substrate before the step of forming the semiconductor layer, and a step of forming on the erase gate. And forming a lower gate insulating film. Thus, it becomes possible to erase data by applying an erase voltage (for example, a positive voltage) to the erase gate, and by sharing the erase gate in the entire memory array or block unit, the entire memory array or block unit can be shared. It is possible to manufacture a semiconductor nonvolatile memory device that can perform batch erase for each erase sector.

  Furthermore, in order to achieve the above object, a method for manufacturing a semiconductor nonvolatile memory device according to the present invention includes a semiconductor nonvolatile memory having a first transistor that is a memory transistor having a charge storage layer and a second transistor for a peripheral circuit. A device manufacturing method, wherein a first transistor for a first transistor is formed in a first transistor formation region on an insulating substrate which is a silicon substrate whose surface is covered with a silicon oxide film or an insulating substrate made of glass or plastic. Forming a first semiconductor layer having a channel formation region, forming a second semiconductor layer having a second channel formation region for the second transistor in the second transistor formation region, and an upper layer of the first semiconductor layer Forming a charge storage layer and forming a gate insulating film on the second semiconductor layer; and Forming a control gate above the gate insulating film and forming a gate electrode above the gate insulating film; and a first source / drain region connected to the first channel formation region and a second channel formation region connected to the second channel formation region Forming two source / drain regions.

  According to the method for manufacturing a semiconductor nonvolatile memory device of the present invention, a memory transistor having a TFT structure and a peripheral circuit transistor can be formed on the same substrate at the same time. By forming gates and the like on the same substrate, it is possible to manufacture a versatile and multifunctional micro system-on-chip. Since a TFT to be a memory transistor having a charge storage layer is formed on a low-cost insulating substrate such as glass, a semiconductor nonvolatile memory having a memory transistor capable of operating at a high speed, which can reduce a voltage such as an erasing voltage. The device can be manufactured at a much lower cost. When a silicon substrate whose surface is coated with a silicon oxide film is used as a substrate, it is possible to use a high-temperature process such as a thermal oxidation method in the formation process of a gate insulating film or a tunnel insulating film, and high-quality gate insulation. A film or a tunnel insulating film can be formed.

  Furthermore, in order to achieve the above object, a method for manufacturing a semiconductor nonvolatile memory device according to the present invention is a method for manufacturing a semiconductor nonvolatile memory device having a first transistor having a charge storage layer and a second transistor for a peripheral circuit. In the first transistor formation region, an erase gate is formed on a silicon substrate whose surface is covered with a silicon oxide film or an insulating substrate made of glass or plastic, and a lower gate is formed above the erase gate. Forming an insulating film; forming a first semiconductor layer having a first channel forming region for the first transistor on an upper layer of the lower gate insulating film; and forming the first semiconductor layer on the substrate in a second transistor forming region. Forming a second semiconductor layer having a second channel formation region for two transistors, and forming an electric current on the upper layer of the first semiconductor layer. Forming a storage layer, forming a gate insulating film above the second semiconductor layer, forming a control gate above the charge storage layer, and forming a gate electrode above the gate insulating film; Forming a first source / drain region connected to the first channel formation region and a second source / drain region connected to the second channel formation region.

  According to the above method for manufacturing a semiconductor nonvolatile memory device of the present invention, a memory transistor having a TFT structure and a peripheral circuit transistor can be simultaneously formed on the same substrate, and the memory transistor has an erase gate. Can be formed as Thus, a semiconductor nonvolatile memory device having a structure shared by the entire memory array or block unit, which has been difficult with the NAND type TFT memory transistor, and capable of batch erasure for each erase sector of the entire memory array or block unit Can be manufactured. Since a TFT to be a memory transistor having a charge storage layer is formed on a low-cost insulating substrate such as glass, a semiconductor nonvolatile memory having a memory transistor capable of operating at a high speed, which can reduce a voltage such as an erasing voltage. The device can be manufactured at a much lower cost. When a silicon substrate whose surface is coated with a silicon oxide film is used as a substrate, it is possible to use a high-temperature process such as a thermal oxidation method in the formation process of a gate insulating film or a tunnel insulating film, and high-quality gate insulation. A film or a tunnel insulating film can be formed.

  According to the method for manufacturing a semiconductor nonvolatile memory device of the present invention, the semiconductor nonvolatile memory device of the present invention can be easily manufactured, and the charge storage layer is provided on a low-cost insulating substrate such as glass. Since a TFT to be a memory transistor is formed, a semiconductor non-volatile memory device having a memory transistor capable of operating at a high speed can be manufactured at a significantly reduced cost because a voltage such as an erasing voltage can be lowered. In addition, a structure having an erase gate can be formed under the semiconductor layer through a lower gate insulating film, and the erase gate is shared by the entire memory array or block unit, thereby erasing the entire memory array or block unit. It is possible to manufacture a NAND-type semiconductor nonvolatile memory device that can be erased collectively for each sector and is advantageous in terms of integration.

  Embodiments of a method for manufacturing a semiconductor nonvolatile memory device according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. A memory transistor is formed in the left region of the drawing. For example, a base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed on an insulating substrate 10 made of a glass substrate such as non-alkali glass or a plastic substrate, and made of polysilicon, for example, on the upper layer. A semiconductor layer 31b having a channel formation region is formed.

  A thin tunnel insulating film 22a made of, for example, silicon oxide is formed on the upper layer of the semiconductor layer 31b, and a floating gate 32a made of, for example, polysilicon is formed on the upper layer, and an ONO film (oxidized film) is formed on the upper layer. A film-nitride film-oxide film laminate) or an intermediate insulating film 23a made of a silicon oxide film is formed, and a control gate 33a made of polysilicon, for example, is formed thereon. Further, in the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. As a result, a TFT field effect transistor having a floating gate 32a insulated by an insulating film between the control gate 33a and the channel formation region in the semiconductor layer 31b is obtained.

  In the field effect transistor having the above structure, the floating gate 32a has a function of holding charges in the film, and the tunnel insulating film 22a and the intermediate insulating film 23a have a role of confining charges in the floating gate 32a. By applying an appropriate voltage to the control gate 33a and a source / drain diffusion layer (not shown) in the semiconductor layer 31b, a Fowler-Nordheim type tunnel current is generated, and electrons are transferred from the semiconductor layer 31b to the floating gate 32a through the tunnel insulating film 22a. Or electrons are emitted from the floating gate 32a to the semiconductor layer 31b. When electric charges are accumulated in the floating gate 32a, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor is changed and the memory transistor can store data. For example, data can be erased by accumulating charges in the floating gate 32a, and data can be written by releasing the charges accumulated in the floating gate 32a.

  On the other hand, a peripheral circuit transistor is formed in the right region of the drawing. A base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed on an upper layer of the substrate 10 on which the memory transistor is formed, and a semiconductor layer 31b having a channel formation region made of, for example, polysilicon, on the upper layer. Is formed. A stacked insulating film of, for example, silicon oxide and ONO film or a thin gate insulating film 25a made of a silicon oxide film is formed on the semiconductor layer 31b, and a gate electrode 33a ′ made of, for example, polysilicon is formed on the upper layer. Is formed. Further, in the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. Thus, a field effect transistor having a TFT structure is obtained.

  The above-described semiconductor nonvolatile memory device can realize significant cost reduction by using a low-cost substrate such as a glass substrate. In addition, TFTs formed on an insulating substrate such as a glass substrate can make the junction capacitance of a transistor almost zero, and since it is a fully depleted type, the depletion layer capacitance is so small that it can be ignored. Is determined only by the trap density in the semiconductor layer, sharp inversion characteristics can be obtained, a voltage such as an erase voltage can be lowered, and a memory transistor that can operate at high speed can be obtained. In particular, by forming the semiconductor layer 31b from polysilicon or quasi-single crystal silicon, the trap density in the semiconductor layer can be reduced, and the gate swing value can be reduced to further reduce the voltage such as the erase voltage. .

  In the above-described semiconductor nonvolatile memory device, peripheral circuit transistors are also formed on the same substrate, and a fine circuit can be integrated on the substrate at low cost. By forming logic gates such as CMOS composed of TFTs on the same substrate, it is possible to realize a versatile and multifunctional micro system on chip.

  When the gate electrode of the peripheral circuit transistor is formed of polysilicon, as shown in FIG. 2A, the gate width W is set to be larger than the gate length L and the average grain size L ′ of the polysilicon forming the gate. Largely formed. As a result, the characteristics of the peripheral circuit transistor can be improved and the uniformity of the characteristics can be improved. When the peripheral circuit transistor is formed of CMOS, it can be easily formed by a fine rule. FIG. 2B shows a case where the gate width W is smaller than that of FIG. 2A and is about the same as the gate length L and the average particle diameter L ′ of the polysilicon forming the gate. And its uniformity is not good.

FIG. 3A is an equivalent circuit diagram of a semiconductor nonvolatile memory device in which memory transistors having the structure shown in FIG. 1 are connected in a NOR type. The control gates of the _two memory transistors MT ₁ and MT ₂ are connected to the _nth word line W _n , and the source is opened to the ground (G-O) or supplied with the source potential. The drain is connected to the nth bit line _Bn and the (n + 1) th bit line _{Bn + 1} . The other two memory transistors MT ₃ and MT ₄ are also connected to the word line and bit line in the same manner as described above.

  As a data erasing method in the NOR type semiconductor nonvolatile memory device, as shown in FIG. 3B, a low voltage Vcg is applied to the control gate CG, a high voltage Vs is applied to the source S, and the bit line B is open. In this way, data can be erased by a source erase operation that pulls out electrons in the floating gate due to the Fowler-Nordheim tunneling phenomenon, and since it is a NOR type, the entire memory array or erase sector can be erased collectively. Can do.

  Next, a method for manufacturing the semiconductor nonvolatile memory device according to the present embodiment will be described. First, as shown in FIG. 4A, an insulating substrate 10 made of a glass substrate such as non-alkali glass or a plastic substrate is used. In the subsequent steps, when a low-melting-point substrate such as the glass substrate is used, the process temperature is set to 600 ° C. or lower. For example, in forming an insulating film, a sputtering method or chemical vapor deposition is performed. (Chemical Vapor Deposition; hereinafter referred to as CVD). On this insulating substrate 10, silicon oxide, silicon nitride, or the like is deposited to a thickness of 200 nm in the case of silicon nitride or 400 nm in the case of silicon oxide, for example, by plasma enhanced CVD or sputtering. A film 20 is formed.

Next, as shown in FIG. 4B, amorphous silicon is deposited to a thickness of 40 nm on the base insulating film 20 by, eg, sputtering or CVD to form a semiconductor layer 31. In particular, according to the sputtering method or the low pressure CVD method, when laser light is irradiated in a later ELA process or the like, the incorporation of hydrogen into the film that causes the insulating film to scatter and open holes is reduced. preferable. Furthermore, according to the low pressure CVD method using SiH ₄ or Si ₂ H ₆ as a raw material, a silicon layer can be formed by a low temperature process of 500 ° C. or lower.

Next, as shown in FIG. 4C, the amorphous silicon semiconductor layer 31 is crystallized, for example, by ELA treatment to form a polysilicon semiconductor layer 31a. As the ELA process, various beam shot methods can be considered. For the top gate TFT, the flatness, smoothness, and uniformity of the silicon film are regarded as important, and single shot or multi-shot for each chip is preferable. Further, the crystallinity can be improved and crystallized by heating the substrate. For example, a step-and-repeat ELA process is performed with a uniform 2 × 2 cm ² excimer laser beam at 400 ° C. with an energy of 300 mJ / cm ² . This crystallization can also be performed by a low temperature solid phase crystallization method (SPC), an ELA treatment after the SPC treatment, or the like.

  Next, as shown in FIG. 5D, the resist film is patterned and the semiconductor layer 31a is patterned by a photolithography process to form a semiconductor layer 31b in which the elements are separated in an island shape. Since the TFT structure is used, element isolation can be easily performed as compared with an element isolation method such as a LOCOS method usually used in a conventional semiconductor device formed on a silicon wafer.

  Next, as shown in FIG. 5E, silicon oxide is deposited to a thickness of about 9 nm by, for example, plasma CVD to form a tunnel insulating film 22. The tunnel insulating film 22 is required to be a particularly high quality film, and is preferably formed by an ECR (Electron Cyclotron Resonance) type plasma CVD method in order to form it by a low temperature process.

  Next, as shown in FIG. 5F, polysilicon containing conductive impurities is deposited on the tunnel insulating film 22 by, for example, a CVD method to form a floating gate layer 32. Alternatively, conductive impurities may be ion-implanted after polysilicon is deposited.

  Next, as shown in FIG. 6G, a resist film R1 for protecting the memory transistor formation region is patterned by a photolithography process, and etching such as RIE (reactive ion etching) is performed to form a peripheral circuit transistor. The floating gate layer 32 deposited in the region is removed.

  Next, as shown in FIG. 6 (h), after removing the resist film R1, for example, a floating gate layer 32 is covered and the entire surface is laminated by an ONO film (oxide film-nitride film-oxide film) by, eg, CVD. Insulating film) or a silicon oxide film is deposited to form an intermediate insulating film 23. At this time, in the peripheral circuit transistor formation region, the tunnel insulating film 22 and the intermediate insulating film 23 are laminated to form the gate insulating film 25 of the peripheral circuit transistor.

  Next, as shown in FIG. 6I, a control gate layer 33 is formed by depositing polysilicon on the intermediate insulating film 23 by, eg, CVD.

  Next, as shown in FIG. 7J, a resist film R2 having a pattern of the control gate of the memory transistor and the gate electrode of the peripheral circuit transistor is formed by patterning by a photolithography process.

  Next, as shown in FIG. 7K, etching such as RIE is performed using the resist film R2 as a mask, and in the memory transistor formation region, the control gate 33a, the intermediate insulating film 23a, the floating gate 32a, and the tunnel insulating film 22a. Are patterned in a self-aligning manner. At the same time, in the peripheral circuit transistor formation region, the gate electrode 33a 'and the gate insulating film 25a are patterned in a self-aligning manner.

Next, after removing the resist film R2, using the control gate 33a and the gate electrode 33a ′ as a mask, for example, P is ion-implanted into the source / drain diffusion layer formation region at a dose of 2 × 10 ¹⁵ ions / cm ² , for example. Then, a source / drain diffusion layer (not shown) is formed, and an annealing process is performed by an ELA method or an RTA (Rapid Thermal Annealing) method under a condition that the glass does not melt, for example. Activate. Thus, the device shown in FIG. 1 can be formed. As a subsequent process, an interlayer insulating film is formed by covering the control gate, contacts and the like are opened, and an upper layer wiring such as a bit line is formed, whereby a desired semiconductor nonvolatile memory device can be obtained.

  According to the manufacturing method of the semiconductor nonvolatile memory device of the present embodiment described above, since a TFT that becomes a memory transistor having a charge storage layer is formed on a low-cost insulating substrate such as glass, a voltage such as an erasing voltage is low. A semiconductor nonvolatile memory device having a memory transistor that can be voltageized and can operate at high speed can be manufactured at a significantly reduced cost. Since peripheral circuit transistors are formed on the same substrate at the same time, a logic gate such as a CMOS composed of TFTs can be formed on the same substrate, making it possible to manufacture a versatile and multifunctional micro system on chip. Become.

  In the present embodiment, a silicon substrate whose surface is coated with a silicon oxide film can be used as the substrate. In this case, since a channel formation region is not formed in the silicon substrate, a silicon substrate having a low quality and a price of 1/2 to 1/3 of that of a normal MOSLSI silicon substrate can be used. Significant cost reduction can be realized. In addition, since a high-temperature process such as a thermal oxidation method can be employed, a high-quality gate insulating film and tunnel insulating film can be formed.

Second Embodiment FIG. 8 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. For example, a base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed on an insulating substrate 10 made of a glass substrate such as non-alkali glass, or a plastic substrate. A semiconductor layer 31b made of crystalline silicon and having a channel formation region is formed. A thin tunnel insulating film (bottom insulating film) 22a made of, for example, silicon oxide is formed on the semiconductor layer 31b, and a charge trap insulating film 24a made of, for example, silicon nitride is formed on the upper layer of the semiconductor layer 31b. A top insulating film 23a made of, for example, silicon oxide is formed on the upper layer. From the bottom insulating film 22a, the charge trap insulating film 24a, and the top insulating film 23a, a laminated insulating film having a charge trap level and having a charge storage capability is formed. A control gate 33a made of, for example, polysilicon is formed on the top insulating film 23a. Further, in the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. As a result, the field effect transistor has a stacked insulating film having charge storage capability between the control gate 33a and the channel formation region in the semiconductor layer 31b, and the memory transistor has a MONOS structure in which the charge storage layer is an ONO film.

  In the field effect transistor having the above structure, the laminated insulating film including the bottom insulating film 22a, the charge trap insulating film 24a, and the top insulating film 23a has a function of holding charges in the film. By applying an appropriate voltage to the source / drain diffusion layers (not shown) in the control gate 33a and the semiconductor layer 31b, a Fowler-Nordheim type tunnel current is generated, and charges injected from the semiconductor layer 31b through the bottom insulating film 22a are generated. Charges are discharged at the charge trap level in the charge trap insulating film 24a or at the charge trap level at the interface between the charge trap insulating film 24a and the top insulating film 23a, or from these trap levels through the bottom insulating film 22a. Is done. When electric charges are accumulated in the stacked insulating film, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor is changed, whereby a memory transistor capable of storing data is obtained. For example, data can be erased by accumulating charges in the stacked insulating film, and data can be written by releasing charges accumulated in the stacked insulating film.

  As in the first embodiment, the above-described semiconductor nonvolatile memory device can achieve a significant cost reduction by using a low-priced substrate such as a glass substrate, and can reduce a voltage such as an erase voltage. The memory transistor can operate at high speed. In particular, by forming the semiconductor layer 31b from polysilicon or quasi-single crystal silicon, the trap density in the semiconductor layer can be reduced, and the gate swing value can be reduced to further reduce the voltage such as the erase voltage. .

  In the semiconductor nonvolatile memory device of the present embodiment described above, the charge trap insulating film 24a is formed by depositing silicon nitride by, for example, the CVD method in place of the polysilicon floating gate layer in the manufacturing method of the first embodiment. Others can be formed in the same manner as in the manufacturing method of the first embodiment. Instead of the intermediate insulating film of the ONO film, the top insulating film 23a may be formed by depositing silicon oxide by, for example, a CVD method.

  In the present embodiment, a silicon substrate whose surface is coated with a silicon oxide film can be used as the substrate. In this case, since a channel formation region is not formed in the silicon substrate, a silicon substrate having a low quality and a price of 1/2 to 1/3 of that of a normal MOSLSI silicon substrate can be used. Significant cost reduction can be realized. In addition, since a high-temperature process such as a thermal oxidation method can be employed, a high-quality gate insulating film and tunnel insulating film can be formed.

Third Embodiment FIG. 9 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. Except for the fact that the insulators 22a and 23a for holding therein the nanocrystals 32c made of a conductor having an average particle diameter of 2 to 5 nm are formed as the charge storage layer, the semiconductor nonvolatile semiconductor of the second embodiment is substantially provided. The memory transistor is similar to a volatile memory device, and can be significantly reduced in cost by using a low-priced substrate such as a glass substrate. can do. In particular, by forming the semiconductor layer 31b from polysilicon or quasi-single crystal silicon, the trap density in the semiconductor layer can be reduced, and the gate swing value can be reduced to further reduce the voltage such as the erase voltage. .

  In the manufacturing method of the first embodiment, the semiconductor nonvolatile memory device of the present embodiment described above includes the tunnel insulating film 22a and the intermediate insulating film instead of the process from the tunnel insulating film forming process to the intermediate insulating film forming process. First, a silicon oxide film corresponding to the film 23a is formed, and silicon ions are controlled by controlling energy from the upper surface so that a Fowler-Nordheim tunnel current having a distance of several nanometers from the lower layer in the film can be generated. It can be formed in the same manner as in the manufacturing method of the first embodiment except that the nanocrystal 21c is formed in the silicon oxide film corresponding to the tunnel insulating film 22a and the intermediate insulating film 23a by ion implantation.

Fourth Embodiment FIG. 10 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. For example, a base insulating film 20 made of, for example, silicon nitride or silicon oxide is formed on an upper layer of an insulating substrate 10 made of a glass substrate such as non-alkali glass or a plastic substrate. An erase gate 30 made of a conductor such as metal or polysilicon is formed. On the upper layer, a lower gate insulating film 21 made of, for example, silicon oxide is formed. A semiconductor layer 31b made of, for example, polysilicon and having a channel formation region is formed thereon.

  A thin tunnel insulating film 22a made of, for example, silicon oxide is formed on the upper layer of the semiconductor layer 31b, and a floating gate 32a made of, for example, polysilicon is formed on the upper layer, and an ONO film (oxidized film) is formed on the upper layer. An intermediate insulating film 23a is formed, and a control gate 33a made of, for example, polysilicon is formed thereon. Further, in the semiconductor layer 31b, a source / drain diffusion layer (not shown) connected to the channel formation region is formed. As a result, a TFT field effect transistor having a floating gate 32a insulated by an insulating film between the control gate 33a and the channel formation region in the semiconductor layer 31b is obtained.

  In the field effect transistor having the above structure, the floating gate 32a has a function of holding charges in the film, and the tunnel insulating film 22a and the intermediate insulating film 23a have a role of confining charges in the floating gate 32a. By applying an appropriate voltage to the control gate 33a and a source / drain diffusion layer (not shown) in the semiconductor layer 31b, a Fowler-Nordheim type tunnel current is generated, and electrons are transferred from the semiconductor layer 31b to the floating gate 32a through the tunnel insulating film 22a. Or electrons are emitted from the floating gate 32a to the semiconductor layer 31b. When electric charges are accumulated in the floating gate 32a, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor is changed and the memory transistor can store data. For example, data can be erased by accumulating charges in the floating gate 32a, and data can be written by releasing the charges accumulated in the floating gate 32a.

  The semiconductor nonvolatile memory device has the erase gate 30 below the semiconductor layer 31b through the lower gate insulating film 21. Data can be erased by applying an erase voltage (for example, a positive voltage) to the erase gate 30. Further, the erase gate 30 is formed by being connected to the erase gate of the adjacent memory transistor, so that the entire memory array or the block unit can be shared, and the entire memory array or the erase sector of the block unit can be collectively erased. It is.

  FIG. 11 is an equivalent circuit diagram of a NAND type semiconductor nonvolatile memory device in which memory transistors having the structure shown in FIG. 10 are connected in 8-bit series. Two selection transistors for selecting this NAND string are arranged at both ends of the NAND string composed of 8-bit memory transistors. One of the source / drain diffusion layers of the NAND string is connected to the bit line B and the other is connected to the source line S. The erase gate is formed by connecting between 8 bits. The erase gate can be configured to be shared by the entire memory array or in units of blocks. The number of memory transistors to be connected is not limited to eight and may be any number.

  In the above-mentioned NAND type semiconductor nonvolatile memory device, 1/2 contacts for data input / output are shared by 8-bit memory cells, and 1/16 contacts per bit. Similarly, the select gate and the source line are all shared by 8 bits, the area per bit is close to the area occupied by the memory transistor, the memory cell area can be very small, high integration, large capacity, and low This is advantageous in terms of cost.

  As a data erasing method in the above NAND type semiconductor nonvolatile memory device, as shown in FIG. 11, 0V or a low voltage Vcg is applied to the control gates CG of all NAND columns, and the selection gates SG1, SG2 of the two selection transistors are applied. High voltages V1 and V2 are applied to. Further, the high voltage Vbg is also applied to the erase gate BG. Further, the source S and the bit line B are opened. As a result, similarly to the NOR type, the electrons in the floating gate can be drawn out by the Fowler-Nordheim type tunnel phenomenon, and the entire NAND string can be erased collectively.

  A semiconductor non-volatile memory device having such a structure can realize a significant cost reduction by using a low-priced substrate such as a glass substrate, can reduce a voltage such as an erasing voltage, and can operate at high speed. It can be a transistor. In particular, by forming the semiconductor layer 31b from polysilicon or quasi-single crystal silicon, the trap density in the semiconductor layer can be reduced, and the gate swing value can be reduced to further reduce the voltage such as the erase voltage. . In addition, the semiconductor nonvolatile memory device has NAND memory cells that are advantageous in terms of integration, and can erase data at once by having an erase gate.

  In general, a structure having a conductor (erase gate 30) via an insulator (lower gate insulating film 21) below a source / drain causes a capacitance between the two and causes a decrease in reading speed. By using the TFT structure, the junction capacitance is close to zero, and by increasing the thickness of the insulator (lower gate insulating film 21) between the source / drain and the conductor (erase gate 30), the erase voltage is Although it becomes higher, the above capacity can be reduced. In AV applications and data storage applications, cost and capacity increase have priority, and the demand for read speed is often not so strong.

  Next, a method for manufacturing the semiconductor nonvolatile memory device according to the present embodiment will be described. First, as shown in FIG. 12A, an insulating substrate 10 made of a glass substrate such as non-alkali glass or a plastic substrate is used. In the subsequent steps, when a low-melting-point substrate such as the glass substrate is used, the process temperature is set to 600 ° C. or lower. For example, in forming an insulating film, a sputtering method or chemical vapor deposition is performed. (Chemical Vapor Deposition; hereinafter referred to as CVD). On this insulating substrate 10, silicon oxide, silicon nitride, or the like is deposited by, for example, a CVD method to form a base insulating film 20. Next, an erase gate 30 is formed by depositing a metal such as Cr or Mo on the upper layer by sputtering, or by depositing polysilicon by sputtering, plasma enhanced CVD (PECVD), or low pressure CVD. Next, an insulator such as silicon oxide or silicon nitride is deposited to a thickness of, for example, 20 nm on the upper layer by, for example, sputtering or PECVD (preferably biased ECR (Electron Cyclotron Resonance) type PECVD). A side gate insulating film 21 is formed. The thinner the lower gate insulating film 21 is, the lower the erase voltage can be set.

Next, as shown in FIG. 12B, amorphous silicon is deposited in a film thickness of 40 nm on the lower gate insulating film 21 by, for example, sputtering or CVD to form a semiconductor layer 31. In particular, according to the sputtering method or the low pressure CVD method, when laser light is irradiated in a later ELA process or the like, the incorporation of hydrogen into the film that causes the insulating film to scatter and open holes is reduced. preferable. Furthermore, according to the low pressure CVD method using SiH ₄ or Si ₂ H ₆ as a raw material, a silicon layer can be formed by a low temperature process of 500 ° C. or lower.

Next, as shown in FIG. 12C, the amorphous silicon semiconductor layer 31 is crystallized, for example, by ELA treatment to form a polysilicon semiconductor layer 31a. As the ELA process, various beam shot methods can be considered. For the top gate TFT, the flatness, smoothness, and uniformity of the silicon film are regarded as important, and single shot or multi-shot for each chip is preferable. In addition, since the erase gate 30 is provided in the lower layer and the thermal efficiency is not good, it is possible to crystallize with good crystallinity and energy efficiency by heating the substrate. For example, a step-and-repeat ELA process is performed with a uniform 2 × 2 cm ² excimer laser beam at 400 ° C. with an energy of 300 mJ / cm ² . This crystallization can also be performed by a low temperature solid phase crystallization method (SPC), an ELA treatment after the SPC treatment, or the like.

  Next, as shown in FIG. 13D, the resist film is patterned and the semiconductor layer 31a is patterned by a photolithography process to form a semiconductor layer 31b in which the elements are separated in an island shape. Since the TFT structure is used, element isolation can be easily performed as compared with an element isolation method such as a LOCOS method usually used in a conventional semiconductor device formed on a silicon wafer.

  Next, as shown in FIG. 13E, silicon oxide is deposited to a thickness of about 9 nm by, for example, plasma CVD to form a tunnel insulating film 22. The tunnel insulating film 22 is required to be a particularly high quality film, and is preferably formed by an ECR (Electron Cyclotron Resonance) type plasma CVD method in order to form it by a low temperature process.

  Next, as shown in FIG. 13F, polysilicon containing conductive impurities is deposited on the tunnel insulating film 22 by, eg, CVD, to form a floating gate layer 32. Alternatively, conductive impurities may be ion-implanted after polysilicon is deposited. Next, for example, the floating gate layer 32 is covered, and an ONO film (a laminated insulating film of oxide film-nitride film-oxide film) is deposited on the entire surface by, for example, the CVD method to form the intermediate insulating film 23. Next, a control gate layer 33 is formed by depositing polysilicon on the intermediate insulating film 23 by, eg, CVD.

Next, patterning is performed by a photolithography process to pattern the control gate 33a, the intermediate insulating film 23a, the floating gate 32a, and the tunnel insulating film 22a in a self-aligning manner. Next, using the control gate as a mask, for example, P is ion-implanted into the source / drain diffusion layer formation region at a dose of 2 × 10 ¹⁵ ions / cm ² to form a source / drain diffusion layer (not shown), and ELA An annealing process is performed by an RTA (Rapid Thermal Annealing) method under conditions where the glass does not melt, for example, by line scanning, to activate impurity ions in the source / drain diffusion layers. Thus, the device shown in FIG. 10 can be formed. As a subsequent process, an interlayer insulating film is formed by covering the control gate, contacts and the like are opened, and an upper layer wiring such as a bit line is formed, whereby a desired semiconductor nonvolatile memory device can be obtained.

  According to the manufacturing method of the semiconductor nonvolatile memory device of the present embodiment described above, since a TFT that becomes a memory transistor having a charge storage layer is formed on a low-cost insulating substrate such as glass, a voltage such as an erasing voltage is low. A semiconductor nonvolatile memory device having a memory transistor that can be voltageized and can operate at high speed can be manufactured at a significantly reduced cost. In addition, a structure having an erase gate can be formed under the semiconductor layer through a lower gate insulating film, and the erase gate is shared by the entire memory array or block unit, thereby erasing the entire memory array or block unit. It is possible to manufacture a NAND-type semiconductor nonvolatile memory device that can be erased collectively for each sector and is advantageous in terms of integration.

  In the present embodiment, a silicon substrate whose surface is coated with a silicon oxide film can be used as the substrate. In this case, since a channel formation region is not formed in the silicon substrate, a silicon substrate having a low quality and a price of 1/2 to 1/3 of that of a normal MOSLSI silicon substrate can be used. Significant cost reduction can be realized. In addition, since a high-temperature process such as a thermal oxidation method can be employed, a high-quality gate insulating film and tunnel insulating film can be formed.

Fifth Embodiment FIG. 14 is a sectional view of a semiconductor nonvolatile memory device according to this embodiment. As the charge storage layer, a thin tunnel insulating film (bottom insulating film) 22a made of, for example, silicon oxide is formed, and a charge trap insulating film 24a made of, for example, silicon nitride is formed on the upper layer. Except for the point that the top insulating film 23a made of, for example, silicon oxide is formed, it is substantially the same as the semiconductor nonvolatile memory device of the fourth embodiment, and a low-cost substrate such as a glass substrate is used. As a result, a significant reduction in cost can be realized, and a voltage such as an erase voltage can be reduced, and a memory transistor that can operate at high speed can be obtained. In particular, by forming the semiconductor layer 31b from polysilicon or quasi-single crystal silicon, the trap density in the semiconductor layer can be reduced, and the gate swing value can be reduced to further reduce the voltage such as the erase voltage. . In addition, the semiconductor nonvolatile memory device has NAND memory cells that are advantageous in terms of integration, and can erase data at once by having an erase gate.

  In the semiconductor nonvolatile memory device according to the present embodiment, the charge trap insulating film 24a is formed by depositing silicon nitride by, for example, the CVD method instead of the polysilicon floating gate layer in the manufacturing method of the fourth embodiment. Others can be formed in the same manner as the manufacturing method of the fourth embodiment. Since a TFT to be a memory transistor having a charge storage layer is formed on a low-cost insulating substrate such as glass, a semiconductor nonvolatile memory having a memory transistor capable of operating at a high speed, which can reduce a voltage such as an erasing voltage. The device can be manufactured at a much lower cost. In addition, a structure having an erase gate can be formed under the semiconductor layer through a lower gate insulating film, and the erase gate is shared by the entire memory array or block unit, thereby erasing the entire memory array or block unit. It is possible to manufacture a NAND-type semiconductor nonvolatile memory device that can be erased collectively for each sector and is advantageous in terms of integration.

  The method for manufacturing the semiconductor nonvolatile memory device of the present invention is not limited to the above embodiment. For example, in the second and fifth embodiments, the memory transistor has a MONOS structure, but may have a MNOS structure. Further, although the control gate and the floating gate have a single layer structure, they may have a two-layer structure such as polycide, which is a stacked body of polysilicon and tungsten silicide, or a multilayer structure of three or more layers. As the substrate, in addition to a glass substrate and a plastic substrate, a silicon substrate whose surface is coated with a silicon oxide film can be used. Further, the source / drain may adopt various structures such as an LDD structure. The injection of charge into the charge storage layer may correspond to either data writing or erasing. In addition, various modifications can be made without departing from the scope of the present invention.

  The method for manufacturing a semiconductor nonvolatile memory device of the present invention can be applied to a method for manufacturing a semiconductor nonvolatile memory device having a charge storage layer for storing charges between a gate electrode of a transistor and a channel formation region.

FIG. 1 is a cross-sectional view of a semiconductor nonvolatile memory device according to a first embodiment of the present invention. FIG. 2 is a diagram showing the relationship between the gate width, the gate length, and the average grain size of the polysilicon forming the gate of the peripheral circuit transistor of the semiconductor nonvolatile memory device according to the first embodiment. FIG. 3A is an equivalent circuit diagram of the NOR type semiconductor nonvolatile memory device according to the first embodiment, and FIG. 3B is an equivalent circuit diagram for explaining the erase operation. 4A and 4B are cross-sectional views showing the manufacturing process of the method for manufacturing the semiconductor nonvolatile memory device according to the first embodiment. FIG. 4A shows the process until the formation of the base insulating film, and FIG. 4B shows the process until the deposition process of the silicon semiconductor layer. (C) shows up to the crystallization process of the silicon semiconductor layer. FIG. 5 is a cross-sectional view showing a continuation process of FIG. 4, (d) up to the element isolation process of the semiconductor layer, (e) up to the tunnel insulating film formation process, and (f) up to the formation of the floating gate layer. The process is shown. 6A and 6B are cross-sectional views showing the subsequent steps of FIG. 5, where FIG. 6G shows the step of removing the floating gate layer in the peripheral circuit transistor formation region, FIG. 6H shows the step of forming the intermediate insulating film, and FIG. Indicates the process up to the formation of the control gate layer. 7 is a cross-sectional view showing a continuation process of FIG. 6, wherein (j) is a process up to a resist film forming process of a control gate of a memory transistor and a gate electrode pattern of a peripheral circuit transistor, and (k) is a control gate of the memory transistor. The process up to the patterning process of the gate electrode pattern of the peripheral circuit transistor is also shown. FIG. 8 is a sectional view of a semiconductor nonvolatile memory device according to the second embodiment of the present invention. FIG. 9 is a sectional view of a semiconductor nonvolatile memory device according to the third embodiment of the present invention. FIG. 10 is a sectional view of a semiconductor nonvolatile memory device according to the fourth embodiment of the present invention. FIG. 11 is an equivalent circuit diagram for explaining an erasing operation of the semiconductor nonvolatile memory device according to the fourth embodiment. 12A and 12B are cross-sectional views showing the manufacturing process of the method for manufacturing the semi-semiconductor nonvolatile memory device according to the fourth embodiment. FIG. 12A shows the process for forming the lower gate insulating film, and FIG. Up to the deposition step, (c) shows up to the crystallization step of the silicon semiconductor layer. FIG. 13 is a cross-sectional view showing a continuation process of FIG. 12, (d) until the element isolation process of the semiconductor layer, (e) until the tunnel insulating film formation process, and (f) the formation of the control gate layer. The process is shown. FIG. 14 is a cross-sectional view of a semiconductor nonvolatile memory device according to the fifth embodiment of the present invention. FIG. 15 is an equivalent circuit diagram for explaining an erasing operation of a conventional NOR type semiconductor nonvolatile memory device. FIG. 16 is an equivalent circuit diagram for explaining an erasing operation of a NAND type semiconductor nonvolatile memory device formed on a conventional bulk silicon semiconductor substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Insulating substrate, 20 ... Base insulating film, 21 ... Lower gate insulating film, 22, 22a ... Tunnel insulating film (bottom insulating film), 23, 23a ... Intermediate insulating film (top insulating film), 24a ... Charge accumulation Insulating film 25, 25a ... Gate insulating film (peripheral circuit transistor), 30 ... Erase gate, 31, 31a, 31b ... Semiconductor layer, 32 ... Floating gate layer, 32a ... Floating gate, 33 ... Control gate layer, 33a ... Control gate, 33a '... Gate electrode (peripheral circuit transistor)

Claims (16)

A method for manufacturing a semiconductor nonvolatile memory device to which a memory transistor having a charge storage layer is connected,
Forming a semiconductor layer having a channel formation region on an insulating substrate made of glass or plastic;
Forming a charge storage layer on the semiconductor layer;
Forming a control gate above the charge storage layer;
Forming a source / drain region connected to the channel formation region,
A method for manufacturing a semiconductor nonvolatile memory device, wherein a thin film transistor to be the memory transistor is formed. The method for manufacturing a semiconductor nonvolatile memory device according to claim 1, wherein steps after the step of forming the semiconductor layer are performed at 600 ° C. or lower. The semiconductor nonvolatile memory device according to claim 1, wherein the step of forming the semiconductor layer includes a step of forming a silicon layer and a step of crystallizing the silicon layer by an excimer laser annealing method or a low-temperature solid phase crystallization method. Manufacturing method. The method for manufacturing a semiconductor nonvolatile memory device according to claim 3, wherein the step of forming the silicon layer is a step of forming by a CVD (chemical vapor deposition) method using Si ₂ H ₆ as a raw material. The method for manufacturing a semiconductor nonvolatile memory device according to claim 3, wherein the step of forming the silicon layer is a step of forming by a CVD (chemical vapor deposition) method using SiH ₄ as a raw material. The method for manufacturing a semiconductor nonvolatile memory device according to claim 4, wherein the CVD method is a low pressure CVD method or a plasma CVD method. The method for manufacturing a semiconductor nonvolatile memory device according to claim 3, wherein the step of forming the silicon layer is a step of forming by a sputtering method. The step of forming the charge storage layer includes a step of forming a gate insulating film over the semiconductor layer, a step of forming a floating gate made of a conductor over the gate insulating film, and a layer over the floating gate. The method for manufacturing a semiconductor nonvolatile memory device according to claim 1, further comprising: forming an intermediate insulating film. The method of manufacturing a semiconductor nonvolatile memory device according to claim 1, wherein the step of forming the charge storage layer is a step of forming an insulator having a charge trap on the semiconductor layer. The method for manufacturing a semiconductor nonvolatile memory device according to claim 8, wherein the memory transistor is formed by being connected in a NOR type. The method for manufacturing a semiconductor nonvolatile memory device according to claim 8, wherein the memory transistor is formed to be connected in a NAND type. 10. The method according to claim 8, further comprising a step of forming an erase gate on the insulating substrate and a step of forming a lower gate insulating film on the erase gate before the step of forming the semiconductor layer. Manufacturing method of semiconductor nonvolatile memory device. A method for manufacturing a semiconductor nonvolatile memory device having a first transistor, which is a memory transistor having a charge storage layer, and a second transistor for a peripheral circuit,
A first semiconductor having a first channel forming region for the first transistor in a first transistor forming region on an insulating substrate which is a silicon substrate whose surface is covered with a silicon oxide film or an insulating substrate made of glass or plastic. Forming a layer, and forming a second semiconductor layer having a second channel formation region for the second transistor in the second transistor formation region;
Forming a charge storage layer on the first semiconductor layer and forming a gate insulating film on the second semiconductor layer;
Forming a control gate above the charge storage layer and forming a gate electrode above the gate insulating film;
Forming a first source / drain region connected to the first channel formation region and a second source / drain region connected to the second channel formation region. Forming a charge storage layer on the first semiconductor layer; forming a tunnel insulating film on the first semiconductor layer; forming a floating gate on the tunnel insulating film; and The method for manufacturing a semiconductor nonvolatile memory device according to claim 13, further comprising: forming an intermediate insulating film on an upper layer of the gate. The method for manufacturing a semiconductor nonvolatile memory device according to claim 13, wherein the step of forming a charge storage layer over the first semiconductor layer is a step of forming an insulator having a charge trap over the first semiconductor layer. A method for manufacturing a semiconductor nonvolatile memory device having a first transistor having a charge storage layer and a second transistor for a peripheral circuit,
Forming an erase gate on an insulating substrate which is a silicon substrate whose surface is covered with a silicon oxide film or an insulating substrate made of glass or plastic in the first transistor formation region;
Forming a lower gate insulating film on an upper layer of the erase gate;
A first semiconductor layer having a first channel formation region for the first transistor is formed on the lower gate insulating film, and a second channel formation for the second transistor is formed on the substrate in the second transistor formation region. Forming a second semiconductor layer having a region;
Forming a charge storage layer on the first semiconductor layer and forming a gate insulating film on the second semiconductor layer;
Forming a control gate above the charge storage layer and forming a gate electrode above the gate insulating film;
Forming a first source / drain region connected to the first channel formation region and a second source / drain region connected to the second channel formation region.

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