JP2006013328A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus having a large parasitic capacitance in order to achieve a highly reliable semiconductor apparatus. <P>SOLUTION: The semiconductor apparatus includes a semiconductor substrate 1 including a projected portion 1b extending in the first direction. A gate insulating film 11 is disposed on the upper surface of the projected portion and on a side surface along the first direction. A gate electrode 12 includes the first portion 12a and the second portion 12b. The first portion crosses the projected portion and is arranged on a gate insulating film on the upper surface of the projected portion. The second portion is disposed on the gate insulating film on the side surface of the projected portion and the length thereof in the first direction is longer than the length in the first direction for the first portion. A pair of source and drain regions 13 is formed on the surface of the projected portion to hold the lower region of the first portion of the gate electrode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, for example, an SRAM (Static Random Access Memory) memory cell and a latch circuit.

  In a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a noise current may be generated due to various causes. This noise current includes, for example, a noise current due to the substrate current of the FET, a noise current induced by α-rays generated from the package and various semiconductor materials entering the silicon substrate, and high-energy neutrons flying from above are silicon atoms. To generate secondary particles (heavy ions, α rays, etc.), and there are noise currents and the like induced by the secondary particles running in the silicon substrate.

  In recent years, as the miniaturization of semiconductor devices progresses, the gate capacitance and the diffusion layer capacitance are reduced, and the power supply voltage is also reduced. For this reason, memory cells and latch circuits of complete CMOS (Complementary Metal Oxide Semiconductor) SRAMs using planar MISFETs have become very weak in resistance to the above-described noise currents. As a result, there is an increased possibility that the latch circuit cannot be inverted and a correct output cannot be transmitted without being able to withstand a small noise current, the data of the SRAM memory cell is easily inverted, and the like.

Japanese Patent Application Laid-Open No. 7-31009 (Patent Document 1) discloses a structure in which a trench is formed in a channel portion of a MISFET along a gate length direction or a gate width direction, and a gate electrode is embedded in the trench. It is disclosed.
Japanese Laid-Open Patent Publication No.7-131009

  The present invention is intended to provide a highly reliable semiconductor device without greatly increasing the manufacturing cost.

  A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate having a projecting portion extending in a first direction, and a gate insulating film disposed on an upper surface of the projecting portion and a side surface along the first direction. A first portion that intersects with the protrusion and is disposed on the gate insulating film on the upper surface of the protrusion, and is disposed on the gate insulating film on the side surface of the protrusion. The gate electrode having a second portion whose length in the first direction is longer than the length in the first direction of the first portion, and the protrusion so as to sandwich a region below the first portion of the gate electrode And a pair of source / drain regions formed on the surface of the part.

  According to the present invention, it is possible to provide a semiconductor device having a high current driving capability and a large parasitic capacitance, and a highly reliable semiconductor device using such a semiconductor device.

  The inventors have studied a semiconductor device having high reliability in the course of development of the present invention. As a result, the present inventors have obtained knowledge as described below.

  A structure (Fin type FET) in which a gate electrode wraps the substrate surface and the side surface of the channel region of the MISFET is known. Since this MISFET has three channels (the upper surface of the substrate and two side surfaces), the effective length of the channel generally increases and a large increase in current driving capability can be expected. The Fin type MISFET has a structure that suppresses the parasitic capacitance that causes a reduction in switching speed as low as possible (although it is a general improvement in characteristics of the MISFET, not limited to the Fin type).

  As described above, a Fin type MISFET can flow a large current. For this reason, it is considered that the resistance to the noise current can be improved by using the MISFET in the location where the current flows in the direction of canceling the noise current of the SRAM memory cell or latch circuit.

  In order to further improve the noise immunity of the SRAM memory cell or the latch circuit, it is effective to increase the time constant of the SRAM memory cell. One way to achieve this is to increase the capacitance value in the memory cell. However, as described above, since the Fin type MISFET makes the parasitic capacitance small, even if this MISFET is used in an SRAM memory cell or a latch circuit, improvement in noise resistance due to the large current driving capability can be expected. The improvement in noise resistance due to the increase in capacity cannot be expected greatly.

  In addition, since the channels formed on the three surfaces overlap each other, there arises a problem that the subthreshold current increases in this portion. Further, there is a problem that a GIDL (Gate Induced Drain Leakage) current increases due to the influence of the electric field of the gate electrode formed on the three surfaces. Since unnecessary consumption current increases due to the subthreshold current and GIDL current, the conventional Fin-type MISFET cannot be used for a large capacity, low power consumption SRAM memory cell.

  Hereinafter, an embodiment of the present invention configured based on such knowledge will be described with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a perspective view schematically showing main parts of a semiconductor device (MISFET) according to a first embodiment of the present invention. FIG. 2 is a view in which the spacer of FIG. 1 is omitted for easier viewing of FIG. FIG. 3 is a plan view of FIG. 4 (a), FIG. 4 (b), FIG. 4 (c), and FIG. 4 (d) are respectively the IVA-IVA line, IVB-IVB line, IVC-IVC line, and IVD-IVD line in FIG. FIG.

  As shown in FIGS. 1, 2, 3, and 4 (a) to 4 (d), for example, a semiconductor substrate 1 such as p-type silicon has a first portion 1 a and a top surface higher than the first portion 1 a. And a second portion (protruding portion) 1b. The second portion 1b of the semiconductor substrate 1 protrudes from the first portion 1a, has a prismatic shape along a certain direction (first direction), and has a trapezoidal shape in which the width of the lower portion is slightly wider than the width of the upper portion. Have. The reason will be described later. The angle formed by the upper surface and the side surface of the first portion 1a of the semiconductor substrate 1 (hereinafter simply referred to as the semiconductor substrate 1a) is 90 ° or more and 120 ° or less. Alternatively, this corner may have a roundness with a radius of curvature of 1 nm or more, as shown in a circle by a broken line in FIG.

  On the semiconductor substrate 1a, for example, an element isolation insulating film 2 having an STI (Shallow Trench Isolation) structure is provided. The element isolation insulating film 2 is made of, for example, a silicon oxide film, TEOS (Tetraehylorthosilicate), or the like. The element isolation insulating film 2 includes a first portion 2a and a second portion 2b having a higher upper surface than the first portion 2a. The second portion 2b of the element isolation insulating film 2 (hereinafter simply referred to as the element isolation insulating film 2b) has a prismatic shape protruding from the first portion 1a, and has a distance along the same direction as the semiconductor substrate 1b. Extend. The element isolation insulating film 2b has a higher upper surface than the second portion 1b of the semiconductor substrate 1 (hereinafter simply referred to as the semiconductor substrate 1b). The first portion 2a of the element isolation insulating film 2 extends along the semiconductor substrate 1a adjacent to the semiconductor substrate 1b. A trench 3 is formed with the first portion 2a of the element isolation insulating film as a bottom and the element isolation insulating film 2b and the semiconductor substrate 1b as side surfaces.

On the surface of the semiconductor substrate 1, wells 4 (4a, 4b) are formed. The conductivity type of the well 4a is determined according to the conductivity type of a transistor formed in a source / drain region 13 (described later) formed in the semiconductor substrate 1b. When the conductivity types of the wells 4 a and 4 b are different from each other, a pn junction is formed under the element isolation insulating film 2. In the case of a so-called triple well structure, for example, wells 4a and 4b are formed in an n ⁻ type well (not shown). In general, it is said that the resistance to soft errors can be increased by adopting a triple well structure.

  The upper surface and side surfaces of the semiconductor substrate 1b are covered with a gate insulating film 11 such as a silicon oxide film. 4A, the thickness of the gate insulating film 11 on the side surface of the semiconductor substrate 1b in (100) is larger than the thickness on the upper surface of the semiconductor substrate 1b. This is because the side surface is more likely to be oxidized due to the difference in the plane orientation between the upper surface and the side surface of the semiconductor substrate 1b. The upper and side oxide film thicknesses can be arbitrarily set. 4B, the upper surface of the gate insulating film 11 is removed. A contact (not shown) for connecting the source / drain region 13 and the upper wiring is formed in this portion.

  On the element isolation insulating film 2 and the semiconductor substrate 1, a gate electrode 12 made of, for example, conductive polysilicon is provided. The gate electrode 12 includes a first portion 12a and a second portion 12b. The first portion 12a of the gate electrode 12 (hereinafter simply referred to as the gate electrode 12a) extends in a direction intersecting the semiconductor substrate 1b, and extends over the element isolation insulating film 2b and above the semiconductor substrate 1b. The gate electrode 12a is provided on the gate insulating film 11 on the semiconductor substrate 1b at the intersection with the semiconductor substrate 1b. The corners of the surface of the gate electrode 12a in contact with the gate insulating film 11 are rounded as desired (not shown). By doing so, the concentration of the electric field at the corner is alleviated.

  The gate electrode 12b (hereinafter simply referred to as the gate electrode 12b) is provided so as to fill the groove 3, and the upper surface thereof is located slightly lower than the semiconductor substrate 1b. Therefore, the gate electrode 12b has a prismatic shape along the semiconductor substrate 1b. The length of the gate electrode 12b in the first direction is longer than the length of the gate electrode 12a in the first direction. The gate electrode 12 has the structure as described above and surrounds the semiconductor substrate 1b.

  A pair of source / drain regions 13 are formed in the surface of the semiconductor substrate 1b so as to sandwich the channel region below the gate electrode 12a. For example, the front side of the gate electrode 12a is a drain region, and the back side is a source region. The source / drain region 13 may be composed of a low concentration source / drain extension region and a high concentration source / drain region, if desired. The gate electrode 12b is formed to reach at least both the source / drain regions 13.

  A spacer 14 made of, for example, a silicon oxide film or a silicon nitride film is provided on the side surface of the gate electrode 12a. The spacer 14 is also embedded in the groove 3, and as a result, the gate electrode 12 b is covered with an insulating film constituting the spacer 14.

  Next, with respect to the method of manufacturing the semiconductor device having the above-described structure, FIGS. 5, 6, 7A, 7B, 7C to 13A, 13B, This will be described below with reference to FIG. FIG. 5 is a plan view of the main part of the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment, and corresponds to a cross section taken along the line AA of FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, FIG. 12A, and FIG. 13A show the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view sequentially illustrating a part of the manufacturing process of FIG. 5 and corresponds to a cross section taken along the line AA of FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11B, FIG. 12B, and FIG. 13B show the semiconductor device according to the first embodiment. It is sectional drawing which shows a part of manufacturing process of this in order, and respond | corresponds to the cross section along the BB line of FIG. 7C, FIG. 8C, FIG. 9C, FIG. 10C, FIG. 11C, FIG. 12C, and FIG. 13C show the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view sequentially illustrating a part of the manufacturing process of FIG. 5 and corresponds to a cross section taken along line CC in FIG. 5.

First, as shown in FIG. 6, a groove is formed at a position corresponding to a region where the element isolation insulating film 2 is to be formed on the surface of the semiconductor substrate 1 by, for example, a lithography process and anisotropic etching such as RIE (Reactive Ion Etching). Is done. Next, the trench is filled with, for example, an oxide film, so that the element isolation insulating film 2 is formed. As a result, the second portion 1b of the semiconductor substrate is defined. By implanting ions from the surface of the semiconductor substrate 1, desired n-type or p-type wells 4 and channels are formed. In the case of the triple well structure, for example, an n ⁻ type well is formed by ion implantation at a deeper position prior to the step of forming the well 4.

  Next, as shown in FIGS. 7A, 7 B, and 7 C, a mask material 21 such as a resist is deposited on the entire surface of the semiconductor substrate 1. Next, an opening is formed in the mask material 21 at a position corresponding to the region where the semiconductor substrate 1b and the groove 3 adjacent to the semiconductor substrate 1b and the trench 3 to be formed are formed, for example, by lithography and RIE. At this time, the surface of the semiconductor substrate 1 is slightly etched, so that the upper surface of the second portion 1 b becomes lower than the position of the original surface of the semiconductor substrate 1. Next, a process of rounding the corners of the semiconductor substrate 1b is performed as desired. Even if rounded corners are formed, FIG. 7 (a), FIG. 7 (b), FIG. 7 (c) to FIG. 13 (a), FIG. 13 (b), FIG. ) For simplicity of the drawings. Next, the mask material 21 is removed.

  Next, as shown in FIGS. 8A, 8B, and 8C, the corners of the semiconductor substrate 1b are rounded and a sacrificial oxide film 22 is formed on the surface for removing damage by RIE. It is formed.

  Next, as shown in FIGS. 9A, 9B, and 9C, after the sacrificial oxide film 22 is removed, the gate insulating film is formed on the surface of the semiconductor substrate 1b by, for example, thermal oxidation. 11 is formed.

  Next, as shown in FIGS. 10A, 10B, and 10C, a material film of the gate electrode 12 is deposited on the entire surface of the semiconductor substrate 1. FIG. Next, the material film is patterned by using, for example, a lithography process and anisotropic etching such as RIE to form the gate electrode 12a. At this time, the material film remains in the groove 3 by appropriately setting the etching conditions. As a result, the gate electrode 12b is formed simultaneously. Thereafter, if desired, the corner of the surface of the gate electrode 12 in contact with the gate insulating film 11 is rounded by an oxidation process. Even if rounded corners are formed, FIG. 10 (a), FIG. 10 (b), FIG. 10 (c) to FIG. 13 (a), FIG. 13 (b), FIG. ) For simplicity of the drawings.

  Next, as shown in FIGS. 11A, 11B, and 11C, an oxide film 23 is deposited on the surface of the gate electrode 12. Next, ions are implanted into the surface of the semiconductor substrate 1b and annealed to form source / drain extension regions 13a.

  Next, as shown in FIG. 12A, FIG. 12B, and FIG. 12C, the material film 24 of the spacer 14 is deposited on the entire surface of the semiconductor substrate 1. At this time, the groove 3 is also filled with the material film 24.

  Next, as shown in FIGS. 13A, 13B, and 13C, the spacer 14 is formed by etching the material film 24 by anisotropic etching such as RIE. The At this time, the material film 24 in the groove 3 is not removed.

  Thereafter, a salicide layer is formed in the source / drain region 13, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 1, and a contact reaching the semiconductor substrate 1, a wiring layer, and the like are formed in the interlayer insulating film. (None are shown).

  According to the semiconductor device (MISFET) according to the first embodiment of the present invention, the channel region is formed on the upper surface and both side surfaces of the semiconductor substrate 1b when the transistor is turned on. For this reason, the transistor current drive capability increases as the effective channel length increases. At this time, the threshold voltage of the transistor remains unchanged. In addition, since the area of the region where the gate electrode 12 and the channel region face each other is large, a large gate capacitance can be realized.

  In the semiconductor device according to the first embodiment, the gate electrode 12 b is provided on the side surface of the source / drain region 13. For this reason, the area of the region facing the gate electrode 12 and the source / drain region 13 is increased, and a larger overlap capacitance than that of the conventional Fin type transistor can be realized. That is, it is possible to realize a transistor that can simultaneously obtain a large current driving capability and a large parasitic capacitance.

  In the semiconductor device according to the first embodiment, the semiconductor substrate 1b has a trapezoidal shape. For this reason, the following effects (advantages) can be obtained. That is, at the corner of the semiconductor substrate 1b, the channel on the upper surface and the channel on the side surface of the second portion 1b intersect when the transistor is turned on. For this reason, the subthreshold current at this intersection increases. In order to keep this subthreshold current small, it is effective to reduce the area of the portion where two channels overlap. Therefore, by making the semiconductor substrate 1b trapezoidal, the overlapping portion of the channel can be reduced. From the above viewpoint, as shown in FIG. 4A, the angle θ formed by the upper surface and the side surface of the second portion 1b is desirably 90 ° to 110 °. Further, by rounding this portion, it is possible to suppress the concentration of the electric field generated from the gate electrode 11 at this portion, so that leakage current flowing from the source region 13 to the drain region 13 can be reduced.

  In the semiconductor device according to the first embodiment, the gate electrode 12 b is covered with the insulating film that constitutes the spacer 14. For this reason, it has the following effects. That is, an interlayer insulating film is formed on the entire surface of the structure of FIG. 1 and a contact hole for contact with the source / drain region 13 is formed by a subsequent process. At this time, part of the contact hole may be located above the gate electrode 12b due to mask misalignment or the like. When a conductive material is buried in such a contact hole, a short circuit occurs. On the other hand, according to the semiconductor device according to the first embodiment, since the gate electrode 12b is covered with the insulating film, the occurrence of such a short circuit can be avoided.

  The overlap capacitance is increased by increasing the length of the second portion 12b of the gate electrode 12 in the direction connecting the source / drain regions 13 to each other (length L in FIG. 4D). Can do. Further, by increasing the length in the depth direction of the second portion 12b of the gate electrode 12 (the length D in FIG. 4A), the current driving capability and capacity can be increased.

(Second Embodiment)
The second embodiment relates to a configuration in which the semiconductor device (transistor) according to the first embodiment is applied to an SRAM memory cell.

  FIG. 14 is a plan view schematically showing a main part of a semiconductor device (SRAM) according to the second embodiment of the present invention, and shows a mode in which the transistor according to the first embodiment is applied to an SRAM memory cell. It is a top view. In FIG. 14 and FIGS. 17 to 26 described later, only the element region (semiconductor substrate 1), the element isolation region (element isolation insulating film 2), and the gate electrode 12 are shown for the sake of simplicity. The spacers 14, contacts, wirings, etc. are omitted. Further, although a point symmetric cell is shown as an example of the second embodiment, a line symmetric cell can be realized in the same manner.

  As shown in FIG. 14, the element isolation insulating film 2 defines four rows of element regions 1 along the vertical direction of the drawing. In addition, two rows of gate electrodes 12a are provided across the element region 1 and the element isolation region 2 along the horizontal direction of the drawing. The two gate electrodes 12a separated from each other are divided on the element isolation region 2, so that four gate electrodes 12a are shown in the drawing.

  The upper right gate electrode 12a and the rightmost element region 1 constitute a part of the transistor Q1D, and the gate electrode 12a and the second element region 1 from the right constitute a part of the transistor Q1L. In the transistors Q1D and Q1L, of the source / drain regions 13 (not shown) formed in the element regions 1 on both the upper and lower sides of the gate electrode 12a, for example, the upper side corresponds to the source and the lower side corresponds to the drain.

  Similarly, the lower left gate electrode 12a and the leftmost element region 1 constitute a part of the transistor Q2D, and the gate electrode 12a and the second element region 1 from the left constitute a part of the transistor Q2L. In the transistors Q2D and Q2L, of the source / drain regions 13 (not shown) formed in the element regions 1 on both the upper and lower sides of the gate electrode 12a, for example, the upper side corresponds to the drain and the lower side corresponds to the source.

  The transistors Q1L and Q2L have the configuration of the transistor according to the first embodiment. Therefore, as shown in the figure, the gate electrodes 12b are provided on both the left and right sides of the element region 1.

  FIG. 15 is an equivalent circuit diagram showing a main part of the semiconductor device according to the second embodiment, and is a circuit diagram of an SRAM memory cell partially including the configuration of FIG. As shown in FIG. 15, a p-type load MIS transistor Q1L and an n-type driving MIS transistor Q1D connected in series are connected between a power supply line Vdd and a ground line Vss. The gate of the transistor Q1L and the gate of the transistor Q1D are connected to each other, and these connection nodes are connected to one end of a resistance element (resistance element) R1. A connection node between the transistor Q1L and the transistor Q1D is connected to the bit line BL1 via an n-type transfer transistor Q1T. Transistor Q1T has its gate connected to a word line.

  A p-type load MIS transistor Q2L and an n-type drive MIS transistor Q2D connected in series are connected between the power supply line Vdd and the ground line Vss. The gate of the transistor Q2L and the gate of the transistor Q2D are connected to each other, and these connection nodes are connected to one end of the resistance element R2. A connection node between the transistor Q2L and the transistor Q2D is connected to the bit line BL2 via an n-type transfer transistor Q2T. Transistor Q2T has its gate connected to a word line.

  The other end of resistance element R1 is connected to a connection node between transistor Q2L and transistor Q2D. The other end of resistance element R2 is connected to a connection node between transistor Q1L and transistor Q1D.

  As described above, by adopting the transistor according to the first embodiment as the load transistor Q1L, the parasitic capacitances C11 and C12 of the transistor are added in parallel with the transistor Q1L. Similarly, by adopting the transistor according to the embodiment of the present invention as the load transistor Q2L, the parasitic capacitances C22 and C22 of the transistor are added in parallel to the transistor Q2L.

  Next, effects obtained by the semiconductor device (SRAM) according to the second embodiment will be described below. As described above, by using the transistor according to the first embodiment as the transistors Q1L and Q2L, the current driving capability can be increased without changing the threshold values of the transistors Q1L and Q2L. Here, for example, when the connection node between the transistor Q1L and the transistor Q1D is in a high level state, a noise current directed to the low level is input (for example, electrons generated by α rays gather at the high level connection node). think of. In this case, since the transistor Q1L that is turned on has a high current driving capability, a current (hole) that cancels the noise current flows into the connection node. Therefore, the possibility that the potential of the connection node is inverted to a low level can be greatly reduced. The same applies to the connection node of transistor Q2L and transistor Q2D.

  In addition, the transistors according to the first embodiment increase the capacitance of the transistors Q1L and Q2L. As a result, the amount of charge on the gates of the transistors Q1L and Q2L required for the transistors Q1L and Q2L to invert increases. For this reason, for example, when the connection node between the transistor Q1L and the transistor Q1DL is in a high level state, the possibility that the transistor Q2L easily inverts can be greatly reduced even when a noise current that goes to the low level is input. The same applies to the connection node between transistor Q2L and transistor Q2D and the relationship between transistor Q1L.

  In addition, since the time constant increases due to the increase in capacitance of the transistors Q1L and Q2L, there is a high possibility that a current that cancels the noise current is supplied before the transistors Q1L and Q2L are inverted. Similarly, by providing the resistance elements R1 and R2, the time constant further increases, and it is possible to secure a time for supplying a current that cancels the noise current.

Note that it does not matter what form the resistance elements R1 and R2 are actually formed on the semiconductor substrate 1, but for example, the following method can be employed. For example, a gate electrode made of a semiconductor material such as polysilicon is usually implanted with a high concentration of impurities (for example, 1 × 10 ²⁰ cm ⁻³ or more) in order to reduce interface resistance with a contact made of a metal material. On the other hand, when the impurity concentration in the contact portion between the gate electrode and the contact is lowered (for example, about 1 × 10 ¹⁹ cm ⁻³ ), the interface resistance of this portion increases. By utilizing this phenomenon, it is possible to realize the resistance elements R1 and / or R2 of FIG. 15 easily and without causing an increase in memory cell area.

  Furthermore, electrical connection between the gate electrode 12 and the adjacent source / drain region 13 can be realized by so-called share contact. The share contact has a configuration in which the contact is formed so as to cover from the gate electrode 12 to the source / drain region 13. In this case, of course, it is also possible to use a configuration in which the interface resistance between the gate electrode 12 and the contact is positively increased. FIG. 16 is a plan view when a shear contact and a high interface resistance are used in this embodiment. In FIG. 16, reference numeral 322 indicates a share contact, and reference numeral 31 indicates an interface resistance between the gate electrode 12 and the share contact 32.

  According to the semiconductor device according to the second embodiment of the present invention, the transistor according to the first embodiment is used as a transistor constituting a part of the SRAM memory cell. Therefore, the transistor can have a large current driving capability. it can. Therefore, a large amount of current for canceling out the noise current can be passed through this transistor, and an SRAM memory cell having high resistance to noise can be realized.

  According to the second embodiment, since the transistor according to the first embodiment is used as a transistor constituting a part of the SRAM memory cell, the transistor can have a large capacitance. For this reason, by increasing the time constant of the portion including this transistor in the SRAM memory cell, it is possible to avoid that the on / off of this transistor is easily inverted by the noise current. Therefore, an SRAM memory cell having high resistance to noise can be realized.

  Further, according to the second embodiment, the resistance elements (resistance elements) R1 and R2 having one ends connected to the gates of the transistors Q1L, Q1D, Q2L, and Q2D are provided. Therefore, the time constant of the portion including these transistors Q1L, Q1D, Q2L, and Q2D in the SRAM memory cell can be further increased. Therefore, an SRAM memory cell with high resistance to noise can be realized by avoiding that the on / off states of these transistors Q1L, Q1D, Q2L, and Q2D are easily inverted by the noise current.

  Furthermore, according to the second embodiment, the parasitic capacitance of the transistor according to the first embodiment is used, so that the capacity of the transistor constituting a part of the SRAM memory cell is increased. For this reason, unlike the case of adding an independent capacitive element, it is possible to avoid an increase in the area of one memory cell due to the increase in capacitance. Further, by realizing the resistance elements R1 and R2 by utilizing the interface resistance, an increase in the area of the memory cell can be prevented.

  In addition, since the transistor according to the first embodiment is used in a part of the SRAM memory cell, a low power consumption SRAM can be realized by reducing the subthreshold current.

  In the present embodiment, the SRAM memory cell has been described as an example. However, the latch circuit has the same operation principle as that of the SRAM memory cell, and the same effect as described above can be obtained when the present embodiment is applied to the latch circuit.

(Modification of the second embodiment)
Next, a modification of the second embodiment will be described below with reference to FIGS. 17 to 26 are plan views schematically showing main parts of a semiconductor device according to a modification of the second embodiment. In the above description, the example in which the transistor according to the first embodiment is adopted as the load transistors Q1L and Q2L is taken up. However, the transistors according to the first embodiment can also be used as the driving transistors Q1D and Q2D. It can also be applied to a load transistor and a driving transistor.

  In the configuration shown in FIG. 17, the driving transistors Q1D and Q2D are configured by the transistors according to the first embodiment. In the configuration shown in FIG. 18, the load transistors Q1L and Q2L and the drive transistors Q1D and Q2D are both configured by the transistors according to the first embodiment. In the configuration shown in FIG. 19, in addition to the configuration of FIG. 18, the gate electrode 12b between the transistors Q1L and Q1D and the gate electrode 12b between the transistors Q2L and Q2D are connected to each other.

  In the transistor according to the first embodiment, the gate electrode 12b is provided on both side surfaces of the semiconductor substrate 1b. However, either one can be used.

  In the configuration shown in FIG. 20, the transistors Q1L and Q2L are configured by the transistors according to the first embodiment. The gate electrode 12b of the transistor Q1L is provided only on the side opposite to the transistor Q1D. The gate electrode 12b of the transistor Q2L is provided only on the side opposite to the transistor Q2D.

  In the configuration shown in FIG. 21, the transistors Q1D and Q2D are configured by the transistors according to the first embodiment. The gate electrode 12b of the transistor Q1D is provided only on the opposite side to the transistor Q1L. The gate electrode 12b of the transistor Q2D is provided only on the opposite side to the transistor Q2L.

  In the configuration shown in FIG. 22, the transistors Q1L, Q2L, Q1D, and Q2D are configured by the transistors according to the first embodiment. The gate electrode 12b of the transistor Q1L is provided only on the side opposite to the transistor Q1D. The gate electrode 12b of the transistor Q1D is provided only on the opposite side to the transistor Q1L. The gate electrode 12b of the transistor Q2L is provided only on the side opposite to the transistor Q2D. The gate electrode 12b of the transistor Q2D is provided only on the opposite side to the transistor Q2L.

  In the configuration shown in FIG. 23, the transistors Q1L, Q2L, Q1D, and Q2D are configured by the transistors according to the first embodiment. The gate electrodes 12b of the transistors Q1L and Q1D are provided only on the sides facing the transistors Q1D and Q1L, respectively. The gate electrodes 12b of the transistors Q2L and Q2D are provided only on the sides facing the transistors Q2D and Q2L, respectively.

  In the configuration shown in FIG. 24, in addition to the configuration in FIG. 23, the gate electrodes 12b between the transistors Q1L and Q1D are connected to each other. The gate electrodes 12b between the transistors Q2L and Q2D are connected to each other.

  In the configuration shown in FIG. 25, in addition to the configuration in FIG. 24, a gate electrode 12b is provided on the opposite side of the transistor Q1D from the transistor Q1L. A gate electrode 12b is also provided on the opposite side of the transistor Q2D from the transistor Q2L.

  In the configuration shown in FIG. 26, in addition to the configuration in FIG. 24, the gate electrode 12b is provided on the opposite side of the transistor Q1L from the transistor Q1D. A gate electrode 12b is also provided on the opposite side of the transistor Q2L from the transistor Q2D.

  Also by the modification shown in FIGS. 17 to 26, the effect obtained by the second embodiment described above can be obtained. As the number of positions where the gate electrode 12b is provided increases, the current driving capability and parasitic capacitance of the transistor increase. Therefore, the degree of the effect obtained by the increase of the current driving capability and parasitic capacitance increases. That is, when the transistors according to the first embodiment are adopted as the load transistors Q1L and Q2L and the drive transistors Q1D and Q2D (examples of FIGS. 18 and 19), the noise increases in the semiconductor device due to the further increase in capacitance. Resistance can be further increased.

  20, 21, and 22 reduce the area of the gate electrode 12 b, the current driving capability and the parasitic capacitance are reduced, and the above effect is slightly reduced. The effect of. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. As shown in FIG. 27, the gate electrode 12 b is not provided in the portion from the p-type well 4 to the p-type source / drain region 13 on the n-type well 4. Therefore, even when a potential for turning on the transistor is supplied to the gate electrode 12b, the p-type well 4, the n-type well 4, and the p-type source / drain region 13 become PNP vertical transistors. It is avoided that the region facing the insulating film of the n-type well 4 corresponding to this channel is inverted. By avoiding the inversion of this portion, it is possible to prevent a large leak current from flowing between the p-type well 4 and the p-type source / drain region 13 or latch-up.

(Third embodiment)
The third embodiment relates to a transistor structure and relates to suppression of GIDL current generated in the drain region.

  FIG. 28 is a perspective view schematically showing a main part of a semiconductor device (MISFET) according to the third embodiment of the present invention. In FIG. 28, for simplicity of illustration, the spacers are omitted as in FIG. FIG. 29 is a plan view of FIG. 30 (a), FIG. 30 (b), FIG. 30 (c), and FIG. 30 (d) are respectively the XXXA-XXXA line, XXXB-XXXB line, XXXC-XXXC line, and XXXD-XXXD line of FIG. FIG.

  As shown in FIG. 28, FIG. 29, FIG. 30 (a) to FIG. 30 (d), the gate electrode 12b is located on the source region 13 (S) side of both sides of the gate electrode 12a (the back and front of the page). Only, and does not reach the side surface of the drain region. An element isolation insulating film 2 is provided on the side surface of the semiconductor substrate 1b on the drain region 13 (D) side. The end of the gate electrode 12b on the drain region 13 (D) side is located at substantially the same position as the end of the gate electrode 12a on the drain region 13 (D) side. Other configurations are the same as those of the first embodiment.

  Next, effects obtained by the semiconductor device according to the third embodiment will be described below. For example, taking a p-type MISFET as an example, the surface of the n-type well is depleted by the potential of the p-type gate electrode (power supply potential VDD) when the MISFET is off. By forming the depletion layer at the boundary between the p-type drain region and the well, a tunnel leakage current flows between the drain region to which the ground potential VSS is applied and the well. This leakage current (GIDL current) deteriorates the characteristics of the MISFET. In order to suppress the GIDL current, it is effective to avoid the formation of a depletion layer at the boundary between the drain region and the well due to the potential of the gate electrode. Therefore, it is conceivable to reduce the area where the drain region and the gate electrode face each other. Therefore, in the third embodiment, the GIDL current caused by the gate electrode 12b can be reduced by not providing the gate electrode 12b in the portion facing the drain region 13 (D).

  As can be seen from FIG. 30 (c), the edge of the drain region 13 (D) is located slightly closer to the center than the end of the gate electrode 12a. For this reason, in the case of the configuration shown in FIGS. 28, 29, and 30A to 30D, this edge portion of the drain region 13 (D) overlaps with the gate electrode 12a. On the other hand, the end of the gate electrode 12a in the element isolation insulating film 2 on the drain region 13 (D) side is connected to the gate electrode 12a as shown in FIGS. 31 and 32 (a) to 32 (d). It can also be arranged from the center. FIG. 31 is a plan view of a semiconductor device (MISFET) according to another example of the third embodiment. 32 (a), FIG. 32 (b), FIG. 32 (c), and FIG. 32 (d) respectively correspond to the XXXIIA-XXXIIA line, the XXXIIB-XXXIIB line, the XXXIIC-XXXIIC line, and the XXXIID-XXXII line in FIG. FIG. The perspective view is the same as FIG.

  As shown in FIGS. 31 and 32 (a) to 32 (d), the gate electrode 12 does not overlap the drain region 13 (D) at all. By doing so, the GIDL current can be greatly reduced.

  According to the semiconductor device of the third embodiment of the present invention, since the gate electrode 12b is provided on the side surface of the semiconductor substrate 1b as in the first embodiment, the same effect as in the first embodiment can be obtained. Further, according to the third embodiment, the gate electrode 12b is provided only on the side surface of the source region 13 (S). Therefore, compared with the first embodiment, the capacitance formed by the gate electrode 12 and the source / drain region 13 is small, but the GIDL current can be reduced.

  In addition, the third embodiment can obtain the effects obtained because of the same configuration as that of the first embodiment, that is, the effects of lowering the subthreshold current and avoiding short-circuiting of the gate electrode 12b.

(Fourth embodiment)
In the fourth embodiment, the transistor according to the third embodiment relates to a configuration in which the transistor according to the third embodiment is applied to an SRAM memory cell, as in the second embodiment.

  FIG. 33 is a plan view schematically showing the main part of a semiconductor device (SRAM) according to the fourth embodiment of the present invention, and shows a mode in which the transistor according to the first embodiment is applied to an SRAM memory cell. It is a top view. In FIG. 33 and FIGS. 34 to 43 to be described later, only the semiconductor substrate 1, the element isolation insulating film 2, and the gate electrode 12 are shown to simplify the drawing. It is omitted. A line-symmetric cell can also be realized in the same manner. The circuit diagram is the same as FIG. 15 of the second embodiment.

  As shown in FIG. 33, in the transistor Q1L, the gate electrode 12b does not reach the side surface of the drain region (below the gate electrode 12b in the drawing). Although not shown in FIG. 33, the gate electrode 12 may partially overlap the drain region below the gate electrode 12a (FIG. 30D) or may not overlap at all (FIG. 32D). )). The same applies to FIGS. 34 to 43.

  Similarly, in transistor Q2L, gate electrode 12b is not provided on the side surface of the drain region (above the gate electrode in the drawing).

  According to the semiconductor device of the fourth embodiment of the present invention, the transistor according to the third embodiment is used as a transistor constituting a part of the SRAM memory cell. For this reason, the same effect as when the transistor of the first embodiment is used in the SRAM memory cell can be obtained, and an SRAM memory cell with high noise resistance, small area and low power consumption can be realized.

  Further, according to the fourth embodiment, by using the transistor according to the third embodiment, the GIDL current can be reduced, and an SRAM memory cell with less power consumption can be realized.

(Modification of the fourth embodiment)
Next, a modification of the fourth embodiment will be described below with reference to FIGS. 34 to 43 are plan views schematically showing main parts of a semiconductor device according to a modification of the fourth embodiment.

  In the configuration shown in FIG. 34, the driving transistors Q1D and Q2D are configured by the transistors according to the third embodiment. In the configuration shown in FIG. 35, the load transistors Q1L and Q2L and the drive transistors Q1D and Q2D are both configured by the transistors according to the third embodiment. In the configuration shown in FIG. 36, in addition to the configuration of FIG. 35, the gate electrode 12b between the transistors Q1L and Q1D and the gate electrode 12b between the transistors Q2L and Q2D are connected to each other. Yes.

  The following is an example in which the gate electrode 12b is provided on one side surface of the semiconductor substrate 1b. First, in the configuration shown in FIG. 37, the transistors Q1L and Q2L are configured by the transistors according to the third embodiment. The gate electrode 12b of the transistor Q1L is provided only on the side opposite to the transistor Q1D. The gate electrode 12b of the transistor Q2L is provided only on the side opposite to the transistor Q2D.

  In the configuration shown in FIG. 38, the transistors Q1D and Q2D are configured by the transistors according to the third embodiment. The gate electrode 12b of the transistor Q1D is provided only on the opposite side to the transistor Q1L. The gate electrode 12b of the transistor Q2D is provided only on the opposite side to the transistor Q2L.

  In the configuration shown in FIG. 39, the transistors Q1L, Q2L, Q1D, and Q2D are configured by the transistors according to the third embodiment. The gate electrode 12b of the transistor Q1L is provided only on the side opposite to the transistor Q1D. The gate electrode 12b of the transistor Q1D is provided only on the opposite side to the transistor Q1L. The gate electrode 12b of the transistor Q2L is provided only on the side opposite to the transistor Q2D. The gate electrode 12b of the transistor Q2D is provided only on the opposite side to the transistor Q2L.

  In the configuration shown in FIG. 40, the transistors Q1L, Q2L, Q1D, and Q2D are configured by the transistors according to the third embodiment. The gate electrodes 12b of the transistors Q1L and Q1D are provided only on the sides facing the transistors Q1D and Q1L, respectively. The gate electrodes 12b of the transistors Q2L and Q2D are provided only on the sides facing the transistors Q2D and Q2L, respectively.

  In the configuration shown in FIG. 41, in addition to the configuration in FIG. 40, the gate electrodes 12b between the transistors Q1L and Q1D are connected to each other. The gate electrodes 12b between the transistors Q2L and Q2D are connected to each other.

  In the configuration shown in FIG. 42, in addition to the configuration in FIG. 41, a gate electrode 12b is provided on the opposite side of the transistor Q1D from the transistor Q1L. A gate electrode 12b is also provided on the opposite side of the transistor Q2D from the transistor Q2L.

  In the configuration shown in FIG. 43, in addition to the configuration in FIG. 41, a gate electrode 12b is provided on the opposite side of the transistor Q1L from the transistor Q1D. A gate electrode 12b is also provided on the opposite side of the transistor Q2L from the transistor Q2D.

  Also by the modification shown in FIGS. 34 to 43, the effect obtained by the above-described fourth embodiment can be obtained. In addition, the effects of these modifications are the same as those of the modification of the second embodiment. For example, in the example where the area of the gate electrode 12b is large, the degree of the effect obtained by increasing the current driving capability and the parasitic capacitance increases. In a transistor that does not have the gate electrode 12b on the adjacent transistor side, the current drive capability and the parasitic capacitance are reduced, but a large leak current can be prevented from flowing.

(Fifth embodiment)
The fifth embodiment relates to the structure of a transistor and relates to suppression of a GIDL current generated in a drain region.

  FIG. 44 is a plan view of a semiconductor device (MISFET) according to the fifth embodiment of the present invention. 45 (a), 45 (b), 45 (c), and 45 (d) are respectively the XLVA-XLVA line, XLVB-XLVB line, XLVC-XLVC line, and XLVD-XLVD line of FIG. FIG.

  As shown in FIGS. 44 and 45 (a) to 45 (d), a portion of the gate electrode 12b in contact with the semiconductor substrate 1b on which the drain region 13 (D) is formed is from the lower surface of the drain region 13 (D). It is in a low position. Other configurations are the same as those of the first embodiment. In this manner, the GIDL current can be suppressed by eliminating a portion where the gate electrode 12b and the drain region 13 (D) overlap.

  Note that making the height of the gate electrode 12b different between the source region 13 (S) side and the drain region 13 (D) side may complicate the manufacturing process. Therefore, as shown in FIGS. 46 and 47 (a) to 47 (d), the gate electrode 12b on the source region 13 (S) side can also have the same height as the drain region 13 (D) side. . FIG. 46 is a plan view of a semiconductor device (MISFET) according to another example of the fifth embodiment of the present invention. 47 (a), 47 (b), 47 (c), and 47 (d) respectively correspond to the XLVIIA-XLVIIA line, XLVIIB-XLVIIB line, XLVIIC-XLVIIC line, and XLVIID-XLVIID line of FIG. FIG. 46 and 47 (a) to 47 (d), an increase in manufacturing steps is avoided.

  According to the semiconductor device of the fifth embodiment of the present invention, since the gate electrode 12b is provided on the side surface of the semiconductor substrate 1b as in the first embodiment, the same effect as in the first embodiment can be obtained.

  Further, according to the fifth embodiment, the gate electrode 12b and the drain region 13 (D) do not overlap. For this reason, the parasitic capacitance due to the gate electrode 12b and the drain region 13 (D) cannot be obtained, but the GIDL current can be further reduced.

  In addition, the fifth embodiment can also obtain the effects obtained because the configuration is the same as that of the first embodiment, that is, the effects such as the reduction of the subthreshold current and the short circuit of the gate electrode 12b.

(Sixth embodiment)
The sixth embodiment relates to a transistor structure and relates to suppression of a GIDL current generated in the drain region.

  FIG. 48 is a plan view of a semiconductor device (MISFET) according to the fifth embodiment of the present invention. 49 (a), FIG. 49 (b), FIG. 49 (c), and FIG. 49 (d) respectively correspond to the XLIXA-XLIXA line, XLIXB-XLIXB line, XLIXC-XLIXC line, and XLIXD-XLIXD line of FIG. FIG.

  As shown in FIGS. 48 and 49 (a) to 49 (d), the gate insulating film 11 on the side surface of the semiconductor substrate 1b where the drain region 13 (D) is formed is thick enough to suppress the GIDL current sufficiently. Has the value of Typically, it is thicker than the other portion of the gate insulating film, for example, the gate insulating film 11 on the side surface of the semiconductor substrate 1b where the source region 13 (S) is formed. It is known that the GIDL current can be suppressed by increasing the distance between the gate electrode and the drain region. For this reason, the GIDL current can be kept low by adopting the configuration according to the sixth embodiment.

  According to the semiconductor device of the sixth embodiment of the present invention, since the gate electrode 12b is provided on the side surface of the semiconductor substrate 1b as in the first embodiment, the same effect as in the first embodiment can be obtained.

  Moreover, according to the sixth embodiment, the gate insulating film 11 on the side surface of the semiconductor substrate 1b where the drain region 13 (D) is formed is formed thick. For this reason, the GIDL current can be suppressed.

  In addition, the sixth embodiment can obtain the effects obtained because of the same configuration as that of the first embodiment, that is, the effects such as the reduction of the subthreshold current and the avoidance of the short circuit of the gate electrode 12b.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 3 is a perspective view showing a part of the semiconductor device according to the first embodiment. The top view of FIG. Sectional drawing of each part of FIG. FIG. 3 is a plan view of the main part of the semiconductor device according to the first embodiment. Sectional drawing which shows typically a part of manufacturing process of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. FIG. 11 is a cross-sectional view showing a step following FIG. 10. Sectional drawing which shows the process following FIG. Sectional drawing which shows the process following FIG. The top view which shows the principal part of the semiconductor device which concerns on 2nd Embodiment. The equivalent circuit diagram which shows the principal part of the semiconductor device which concerns on 2nd Embodiment. The top view which shows an example of the principal part of the semiconductor device which concerns on 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 2nd Embodiment. FIG. 23 is a cross-sectional view of FIG. 22. The perspective view which shows the principal part of the semiconductor device which concerns on 3rd Embodiment. The top view of FIG. Sectional drawing of each part of FIG. The top view which shows the principal part of the semiconductor device which concerns on the other example of 3rd Embodiment. Sectional drawing of each part of FIG. FIG. 6 is a plan view showing a main part of a semiconductor device according to a fourth embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. The top view which shows the principal part of the semiconductor device which concerns on the modification of 4th Embodiment. FIG. 9 is an exemplary plan view showing a main part of a semiconductor device according to a fifth embodiment; Sectional drawing of each part of FIG. The top view which shows the principal part of the semiconductor device which concerns on the other example of 5th Embodiment. Sectional drawing of each part of FIG. The top view which shows the principal part of the semiconductor device which concerns on 6th Embodiment. FIG. 49 is a cross-sectional view of each part of FIG. 48.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... 1st part of semiconductor substrate, 1b ... 2nd part of semiconductor substrate, 2 ... Element isolation insulating film, 2a ... 1st part of element isolation insulating film, 2b ... 2nd of element isolation insulating film Part 3, groove 4, 4 a, 4 b, well, 11 gate insulating film, 12 gate electrode, 12 a gate part first part, 12 b gate electrode second part, 13 source / drain region, 13a ... Source / drain extension region, 13b ... Source / drain region, 14 ... Spacer, 21 ... Mask material, 22 ... Sacrificial oxide film, 23 ... Oxide film, 24 ... Material film, 31 ... Resistance element, 32 ... Contact.

Claims (5)

A semiconductor substrate having a protrusion extending in the first direction;
A gate insulating film disposed on an upper surface of the protruding portion and on a side surface along the first direction;
A first portion that intersects the protrusion and is disposed on the gate insulating film on the upper surface of the protrusion, and is disposed on the gate insulating film on the side surface of the protrusion and A gate electrode having a second portion having a length in one direction longer than a length of the first portion in the first direction;
A pair of source / drain regions formed on the surface of the protruding portion so as to sandwich a region below the first portion of the gate electrode;
A semiconductor device comprising:   2. The position of the upper surface of the portion of the gate electrode facing the one of the source / drain regions is located below the lower end of the one of the source / drain regions. The semiconductor device described.   The semiconductor device according to claim 1, wherein the second portion of the gate electrode is covered with an insulating film. A first p-type MISFET;
A first n-type MISFET electrically connected in series with the first p-type MISFET and having a gate electrically connected to a gate of the first p-type MISFET;
A second p-type MISFET whose gate is electrically connected to a connection node of the first p-type MISFET and the first n-type MISFET;
A second n-type MISFET electrically connected in series with the second p-type MISFET and having a gate electrically connected to a gate of the second p-type MISFET;
Comprising
2. The semiconductor device according to claim 1, wherein at least one of the first p-type MISFET, the first n-type MISFET, the second p-type MISFET, and the second n-type MISFET is configured by the semiconductor device according to claim 1.   And a resistance element formed between a connection node between the gate of the first p-type MISFET and the gate of the first n-type MISFET and a connection node between the second p-type MISFET and the second n-type MISFET. The semiconductor device according to claim 4.

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