JP2006013042A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a storage electrode having a low contact resistance and an excellently roughened surface. <P>SOLUTION: First and second amorphous silicon layers 2 and 3 having different impurity concentrations are laminated, a third amorphous silicon layer 4 is formed on the side wall of the laminated structure, and an HSG silicon film 5 is formed on the surfaces of the second and third amorphous silicon layers 3 and 4, thus constituting the storage electrode 1. In each layer, the impurity concentration is formed by satisfying the relationship of the second amorphous silicon layer 3≤the third amorphous silicon layer 4<the first amorphous silicon layer 2. The resistance is lowered by bringing the first amorphous silicon layer 2 having the highest impurity concentration into contact with a substrate 8, the HSG silicon film 5 is formed on the surfaces of the second and third amorphous silicon layers 3 and 4 having the lower impurity concentrations, and the surface is roughened. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a capacitor structure and a manufacturing method thereof.

  One of the memory cell structures of DRAM (Dynamic Random Access Memory) widely used as a large capacity memory is a stacked capacitor structure. By adopting such a memory cell structure for the DRAM, it is possible to secure a sufficient capacitor capacity even when the memory cell area is reduced.

  Further, in recent years, by devising the shape of the storage electrode constituting the capacitor, the effective area has been increased to increase the capacity. For example, a method of increasing the surface area by roughening the surface of the storage electrode has been proposed.

  As a method for roughening the surface of the storage electrode, for example, after forming a plurality of storage electrodes with polysilicon on the wafer, amorphous silicon is formed on the entire surface, and this is etched back to separate each storage electrode. There has been proposed a method in which an annealing process is performed later to form a concavo-convex HSG (Hemi-Spherical Grained) silicon film on the surface of each storage electrode (see, for example, Patent Document 1).

In this proposal, along with the roughening of the surface of the storage electrode by the HSG silicon film, the formation of the concave and convex HSG silicon film on the entire surface and then etching it back to separate the storage electrodes from each other, This prevents the capacitor capacity from decreasing due to the reduction in surface area.
JP-A-5-315543

  In recent years, storage electrodes of DRAMs are often formed using doped amorphous silicon having a single impurity concentration. However, when the surface of the storage electrode is roughened by forming an HSG silicon film on the amorphous silicon surface for the purpose of increasing the capacity as described above, in order to form a good concavo-convex HSG silicon film, HSG It is necessary to lower the impurity concentration of amorphous silicon compared to when the silicon film is not formed.

  However, when amorphous silicon having a low impurity concentration is used for the storage electrode, a good HSG silicon film can be formed, but there is a problem that the contact resistance with the substrate at the bottom of the storage electrode is increased.

  For this reason, a countermeasure may be considered in which a storage electrode is formed by laminating amorphous silicon having a high impurity concentration in the lower layer and amorphous silicon having a low impurity concentration in the upper layer, and an HSG silicon film is formed on the surface thereof. However, in the case of such a laminated structure, a good HSG silicon film cannot be formed on the side wall of the lower layer portion with a high impurity concentration, and it becomes difficult to secure a necessary capacitor capacity.

  Further, as in the prior art, when the amorphous silicon formed on the surface of the storage electrode is etched back before the HSG silicon film is formed to separate the storage electrodes, or after the formation, the HSG silicon film is etched back to store each storage electrode. When the electrodes are separated, there is a possibility that a so-called film reduction occurs in which the storage electrode is etched during the etch back and the thickness becomes thinner than expected. If such film reduction occurs in the storage electrode, the capacitor capacity naturally decreases.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device having a storage electrode having a low contact resistance and a good roughened surface, and a method for manufacturing the same.

  In order to solve the above problems, the present invention provides a semiconductor device that can be realized with the configuration illustrated in FIG. The semiconductor device of the present invention is a semiconductor device having a storage electrode, wherein a stacked structure in which a plurality of amorphous silicon layers are stacked, an amorphous silicon layer formed on a side wall of the stacked structure, and an amorphous layer in the uppermost layer of the stacked structure. And a storage electrode including an uneven silicon film formed on the surface of the silicon layer and the surface of the amorphous silicon layer formed on the side wall.

  The semiconductor device illustrated in FIG. 1 includes a surface of the uppermost second amorphous silicon layer 3 in a stacked structure in which two layers of first and second amorphous silicon layers 2 and 3 are stacked, and sidewalls of the stacked structure. A concave-convex HSG silicon film 5 is formed on the surface of the third amorphous silicon layer 4 formed on the storage electrode 1. Therefore, if the first amorphous silicon layer 2 is made to have a high impurity concentration and the second and third amorphous silicon layers 3 and 4 are made to have a low impurity concentration at which the HSG silicon film 5 can be formed, the contact resistance can be reduced and improved. A roughened storage electrode can be obtained.

  According to the present invention, in a method of manufacturing a semiconductor device having a storage electrode, a step of stacking a plurality of amorphous silicon layers to form a stacked structure, a step of forming an amorphous silicon layer on a sidewall of the stacked structure, Forming a concavo-convex silicon film on the surface of the uppermost amorphous silicon layer of the multilayer structure and on the surface of the amorphous silicon layer formed on the sidewall of the multilayer structure. Is provided.

  According to such a method of manufacturing a semiconductor device, an amorphous silicon layer is further formed on the side wall of the laminated structure in which a plurality of amorphous silicon layers are laminated, and the amorphous silicon layer surface and the laminated structure side wall are formed on the top layer of the laminated structure. An uneven silicon film is formed on the surface of the amorphous silicon layer. For this reason, the impurity concentration of the uppermost layer of the multilayer structure and the amorphous silicon layer on the side wall where the uneven silicon film is formed on the surface can be set independently of the impurity concentration of the amorphous silicon layer of the lowermost layer of the multilayer structure. Therefore, if the amorphous silicon layer at the bottom of the stacked structure is made high in impurity concentration and the amorphous silicon layer on the top layer of the stacked structure and the amorphous silicon layer on the side walls are made low in impurity concentration, a storage electrode having a low contact resistance and a good rough surface can be formed. Will come to be.

  In the present invention, an amorphous silicon layer is formed on a sidewall of a laminated structure in which a plurality of amorphous silicon layers are laminated, and an uneven silicon film is formed on the surface of the amorphous silicon layer on the uppermost layer of the laminated structure and the sidewall. A storage electrode is formed. As a result, it is possible to form a storage electrode having a low contact resistance and a well-roughened surface, and a semiconductor device having a large capacitor capacity can be realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking a stacked capacitor structure DRAM as an example.
FIG. 1 is an explanatory diagram of a storage electrode of a DRAM.

  The storage electrode 1 shown in FIG. 1 has a structure in which a first amorphous silicon layer 2 and a second amorphous silicon layer 3 having different impurity concentrations are laminated, and a third amorphous silicon layer is formed on the sidewalls thereof. Layer 4 is formed. Then, an HSG silicon film 5 is formed on the surface of the second amorphous silicon layer 3 on the upper layer of the laminated structure and the third amorphous silicon layer 4 on the side wall of the laminated structure, and the storage electrode 1 having a rough surface is formed. Has been.

  The first amorphous silicon layer 2 in the lower layer of the stacked structure has a bottom surface of a source / drain 9a of a MOS (Metal Oxide Semiconductor) transistor 9 formed in a substrate 8 via a contact hole 7 penetrating the bulk interlayer film 6. It is connected to the.

  Here, the first amorphous silicon layer 2 is an amorphous silicon layer doped with impurities, and is formed with an impurity concentration that makes electrical contact with the substrate 8. The second and third amorphous silicon layers 3 and 4 are an amorphous silicon layer doped with impurities or an amorphous silicon layer not doped with impurities, and an uneven HSG silicon film 5 can be formed on the surface thereof. It is formed with a high impurity concentration.

  Therefore, the first and second amorphous silicon layers 2 and 3 having a stacked structure have an impurity concentration of the second amorphous silicon in consideration of the contact resistance with the substrate 8 and the ease of forming the HSG silicon film 5. The layer 3 is formed to satisfy the relationship of the first amorphous silicon layer 2.

  The third amorphous silicon layer 4 on the side wall of the stacked structure of the storage electrode 1 has an impurity concentration capable of forming the HSG silicon film 5 and is the same as or higher than the second amorphous silicon layer 3 on the upper layer of the stacked structure. The impurity concentration is higher than that of the first amorphous silicon layer 2 in the lower layer of the stacked structure. This considers the etching rate of the second and third amorphous silicon layers 3 and 4 at the time of etch back described later in addition to the ease of forming the HSG silicon film 5.

  Therefore, in the electrode portion composed of the first, second, and third amorphous silicon layers 2, 3, and 4 shown in FIG. 1, the impurity concentration of the second amorphous silicon layer 3 ≦ the third amorphous layer The silicon layer 4 is formed to satisfy the relationship of the first amorphous silicon layer 2.

  Thus, the storage electrode 1 is contacted to the substrate 8 via the first amorphous silicon layer 2 having the highest impurity concentration, and the second and third amorphous silicon layers 3 and 4 having a lower impurity concentration than this. An HSG silicon film 5 is formed on the surface. By configuring the storage electrode 1 as described above, it is possible to form a good HSG silicon film 5 on the entire surface while keeping the contact resistance with the substrate 8 low. As a result, the storage electrode 1 has a large surface area, and a large capacitor capacity can be secured.

  Although FIG. 1 shows a structure in which two layers of first and second amorphous silicon layers 2 and 3 are laminated, the number of layers in the laminated structure is not limited to this, and three or more layers are laminated. It doesn't matter. However, in that case, the first and second amorphous silicon layers 2 and 3 as described above are between the impurity concentration of the lowermost amorphous silicon layer and the impurity concentration of the uppermost amorphous silicon layer. It must be similar to the relationship it has. Then, according to the impurity concentration, the third amorphous silicon layer 4 is formed with an appropriate impurity concentration according to the above relationship.

Next, an example of a method for forming the storage electrode 1 having the above configuration will be specifically described with reference to FIGS.
2 is an explanatory view of a bulk interlayer film forming process, FIG. 3 is an explanatory view of a contact hole forming process, FIG. 4 is an explanatory view of an amorphous silicon first forming process, FIG. 5 is an explanatory view of an etching process, and FIG. FIG. 7 is an explanatory diagram of the etch back process, and FIG. 8 is an explanatory diagram of the HSG silicon film forming process.

  First, as shown in FIG. 2, a field oxide film is formed on a p-type silicon substrate 8a by a LOCOS (Local Oxidation of Silicon) method to form an element isolation 8b. Then, the gate electrode 9b is formed on the p-type silicon substrate 8a by a conventionally known method, the source / drain 9a is formed in the surface region, and the MOS transistor 9 is formed.

  Subsequently, after forming a bit line (not shown), a bulk interlayer film 6 is formed on the p-type silicon substrate 8a. The bulk interlayer film 6 is formed by laminating a BPSG (Boro Phospho Silicate Glass) with a film thickness of about 1400 nm on a TEOS (Tetra Ethyl Ortho Silicate) with a film thickness of about 50 nm. Thereafter, the bulk interlayer film 6 is planarized by CMP (Chemical Mechanical Polishing), and the film thickness from the surface of the p-type silicon substrate 8a is set to about 495 nm.

  Next, as shown in FIG. 3, a contact hole 7 used to contact the storage electrode 1 to be formed later and the source / drain 9a formed on the p-type silicon substrate 8a is formed on the flattened bulk interlayer film 6. To do.

The contact hole 7 is first formed by performing RIE (Reactive Ion Etching) after patterning with an opening corresponding to the source / drain 9a formed in the p-type silicon substrate 8a. For this etching, a parallel plate RIE etcher is used. The etching gas conditions are C ₄ F ₈ / CO ₂ / Ar / O ₂ = 10 sccm / 100 sccm / 400 sccm / 6 sccm (1 sccm = 1 ml / min (0 ° C., 101.3 kPa); the same applies hereinafter). The pressure is 40 mTorr (1 Torr = 133.322 Pa, the same applies hereinafter), the RF applied power density of the anode electrode is 6.4 W / cm ² , and the RF applied power density of the cathode electrode is 4.5 W / cm ² .

  Next, as shown in FIG. 4, first and second amorphous silicon layers 2 and 3 are formed over the entire surface, and then resist patterning for forming the storage electrode 1 is performed. For example, plasma CVD (Chemical Vapor Deposition) can be used to form the first and second amorphous silicon layers 2 and 3.

Here, the first amorphous silicon layer 2 has a film forming temperature of 530 ° C. and PH ₃ or the like so that phosphorus ions (P ⁺ ) have a concentration of about 1.4 × 10 ²¹ cm ^−3. The film thickness of the contact hole 7 portion from the surface of the p-type silicon substrate 8a is about 650 nm. By forming the first amorphous silicon layer 2 with such an impurity concentration, the contact resistance with the source / drain 9a can be kept low.

Following the formation of the first amorphous silicon layer 2, the second amorphous silicon layer 3 is formed at a film formation temperature of 530 ° C. without doping P ⁺ and the film thickness from the surface of the first amorphous silicon layer 2 is increased. It forms so that it may become about 100 nm. Thus, since the second amorphous silicon layer 3 is not doped with impurities, it is optimal for forming a good HSG silicon film 5 on the surface.

  After the formation of the first and second amorphous silicon layers 2 and 3, the resist pattern 10 for forming the laminated structure constituting the electrode portion is formed with a thickness of about 0.73 μm and a width of about 0.34 μm and patterned.

Next, using the resist pattern 10 as a mask, the first and second amorphous silicon layers 2 and 3 are etched as shown in FIG. For etching, an ECR (Electron Cyclotron Resonance) plasma etcher is used, and the etching gas condition is HBr / O ₂ = 80 sccm / 4 sccm. Etching is performed at a pressure of 1.5 mTorr, a microwave power of 1.2 kW, and a cathode electrode side RF applied power density of 0.14 W / cm ² . By adopting such etching conditions, the first and second amorphous silicon layers 2 and 3 have etching selectivity with respect to the underlying bulk interlayer film 6, and the first and second amorphous silicon layers 1 and 2 shown in FIG. A laminated structure of the second amorphous silicon layers 2 and 3 is formed.

  Next, as shown in FIG. 6, a third amorphous silicon layer 4 is formed. The third amorphous silicon layer 4 is formed by using, for example, a plasma CVD method, as shown in FIG. 6, first of all, that is, the surface of the first and second amorphous silicon layers 2 and 3 after etching and the bulk interlayer film 6. Formed on the surface.

The third amorphous silicon layer 4 has a film forming temperature of 530 ° C., and P ⁺ is diffused into the film using PH ₃ or the like so that its concentration becomes about 0.8 × 10 ²⁰ cm ⁻³ . The film is formed with a thickness of about 50 nm. As described above, the third amorphous silicon layer 4 has an impurity concentration range in which the HSG silicon film 5 can be formed on the surface thereof, and has an impurity concentration lower than that of the first amorphous silicon layer 2. The impurity concentration is higher than that of the amorphous silicon layer 3.

Next, as shown in FIG. 7, the third amorphous silicon layer 4 formed on the entire surface is etched back. The etch back is performed by overetching the amount corresponding to 50% of the thickness of the third amorphous silicon layer 4 in addition to the thickness of about 50 nm. An ECR plasma etcher is used for etching, and the etching gas condition is Cl ₂ / O ₂ = 75 sccm / 14 sccm. Etching is performed with a pressure of 1.3 mTorr, a microwave power of 1.2 kW, and an RF power of 65 W applied to the cathode electrode side.

  By the over-etching of the third amorphous silicon layer 4, adjacent ones of the electrode parts constituted by the first, second and third amorphous silicon layers 2, 3, 4 are separated. At that time, the third amorphous silicon layer 4 remains as a sidewall on the sidewall of each electrode portion.

  Normally, when the third amorphous silicon layer 4 is over-etched in this way, after the third amorphous silicon layer 4 on the upper surface of the electrode portion is removed, the second amorphous silicon layer 3 below the third amorphous silicon layer 4 is also etched. . However, there is a difference between the impurity concentrations of the second and third amorphous silicon layers 3 and 4 here, and the etching rate is lower at the low impurity concentration. The etching rate of the silicon layer 3 is drastically lowered, and the film loss can be minimized. Even when the impurity concentrations of the second and third amorphous silicon layers 3 and 4 are the same, the etching rate is not significantly increased only for the second amorphous silicon layer 3, and the film loss is suppressed. Is possible.

  Thus, at the stage where the etch-back is completed, the sidewalls of the first and second amorphous silicon layers 2 and 3 are covered with the etched-back third amorphous silicon layer 4, and the surface of the electrode portion is HSG silicon. The surface on which the film 5 can be formed is exposed.

  Next, as shown in FIG. 8, an uneven HSG silicon film 5 is formed on the surfaces of the second and third amorphous silicon layers 3 and 4. The HSG silicon film 5 can be formed using, for example, a LPCVD (Low Pressure Chemical Vapor Deposition) method.

For example, as a pretreatment, first, a natural oxide film on the surfaces of the second and third amorphous silicon layers 3 and 4 is removed using HF or the like, washed with pure water, and dried. Next, it is placed in a predetermined chamber, SiH ₄ is supplied at 650 ° C. in a He atmosphere, and seeding is performed for 20 minutes, whereby amorphous is formed on the surfaces of the second and third amorphous silicon layers 3 and 4. A silicon / polysilicon mixed phase layer is formed. Then, at that temperature, SiH ₄ is switched to PH ₃ and doping is performed for 60 minutes, and then the supply of PH ₃ is stopped at that temperature and annealing is performed for 40 minutes. Thereby, migration is generated with the polysilicon in the mixed phase as a nucleus, and the uneven HSG silicon film 5 is formed.

By the above formation method, the storage electrode 1 whose surface is roughened by the HSG silicon film 5 is formed.
In this way, by forming the storage electrode 1 in which the impurity concentration of each layer satisfies the relationship of the second amorphous silicon layer 3 ≦ the third amorphous silicon layer 4 <the first amorphous silicon layer 2, Since the amorphous silicon layer 2 is in contact with the second and third amorphous silicon layers 3 and 4 having a low impurity concentration and a wide contact area, the contact resistance between the storage electrode 1 and the substrate 8 can be kept low. become.

  In addition, since the HSG silicon film 5 is formed on the surfaces of the second and third amorphous silicon layers 3 and 4 having a lower impurity concentration than the first amorphous silicon layer 2, a good HSG is formed on the entire surface of the storage electrode 1. The silicon film 5 can be formed. Thereby, the surface area of the storage electrode 1 can be increased.

  Furthermore, the third amorphous silicon layer 4 is formed so that its impurity concentration is the same as or higher than the impurity concentration of the second amorphous silicon layer 3. Therefore, it is possible to suppress the second amorphous silicon layer 3 from being etched by the etch back of the third amorphous silicon layer 4 and the electrode portion from being reduced in film thickness.

  Therefore, while maintaining the contact resistance between the storage electrode 1 and the substrate 8 low, the entire surface is roughened to increase the surface area, thereby increasing the capacity of the DRAM.

  Note that the above formation conditions are merely examples, and when forming the storage electrode 1, the formation conditions can be changed as appropriate according to the size, design rules, required characteristics, and the like of the DRAM.

For example, the first amorphous silicon layer 2 is formed so as to have an impurity concentration of approximately 1.4 × 10 ²¹ cm ⁻³ or more, although it varies depending on the contact required characteristics. The second amorphous silicon layer 3 is formed to have an impurity concentration of about 0 cm ^{−3 to} 1.0 × 10 ²⁰ cm ⁻³ . Further, the third amorphous silicon layer 4 has an impurity concentration of about 0 cm ^{−3 to} 1.0 × 10 ²⁰ cm ^{−3 and} is between the impurity concentrations of the first and second amorphous silicon layers 2 and 3. It is formed at such an impurity concentration as to enter. As a result, it is possible to obtain the storage electrode 1 having a low contact resistance and a good rough surface.

  Further, for example, the third amorphous silicon layer 4 is formed so as to have an impurity concentration of about 1.2 times or more that of the second amorphous silicon layer 3. As a result, an effective etching rate difference is generated between the two layers at the time of etch back, and excessive etching of the second amorphous silicon layer 3 can be suppressed and film loss can be suppressed.

It is explanatory drawing of the storage electrode of DRAM. It is explanatory drawing of a bulk interlayer film formation process. It is explanatory drawing of a contact hole formation process. It is explanatory drawing of an amorphous silicon 1st formation process. It is explanatory drawing of an etching process. It is explanatory drawing of an amorphous silicon 2nd formation process. It is explanatory drawing of an etch-back process. It is explanatory drawing of a HSG silicon film formation process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Storage electrode 2 1st amorphous silicon layer 3 2nd amorphous silicon layer 4 3rd amorphous silicon layer 5 HSG silicon film 6 Bulk interlayer film 7 Contact hole 8 Substrate 8a p-type silicon substrate 8b Element isolation 9 MOS transistor 9a Source / Drain 9b Gate electrode 10 Resist pattern

Claims (5)

In a semiconductor device having a storage electrode,
A laminated structure in which a plurality of amorphous silicon layers are laminated;
An amorphous silicon layer formed on a side wall of the laminated structure;
An uneven silicon film formed on the surface of the uppermost amorphous silicon layer of the laminated structure and the surface of the amorphous silicon layer formed on the side wall;
A semiconductor device comprising a storage electrode comprising:   2. The semiconductor device according to claim 1, wherein the uppermost amorphous silicon layer is formed with a lower impurity concentration than the lowermost amorphous silicon layer of the stacked structure.   The amorphous silicon layer formed on the side wall is formed with the same impurity concentration as that of the uppermost amorphous silicon layer or at a higher impurity concentration than that of the uppermost amorphous silicon layer. Semiconductor device. In a method for manufacturing a semiconductor device having a storage electrode,
Laminating a plurality of amorphous silicon layers to form a laminated structure;
Forming an amorphous silicon layer on the side wall of the laminated structure;
Forming a concavo-convex silicon film on the surface of the uppermost amorphous silicon layer of the laminated structure and the surface of the amorphous silicon layer formed on the sidewall of the laminated structure;
A method for manufacturing a semiconductor device, comprising: In the step of forming an amorphous silicon layer on the side wall of the laminated structure,
Amorphous silicon is formed so as to cover the laminated structure and have the same impurity concentration as the uppermost amorphous silicon layer or a higher impurity concentration than the uppermost amorphous silicon layer,
5. The method of manufacturing a semiconductor device according to claim 4, wherein an amorphous silicon layer is formed on a side wall of the laminated structure by etching back the formed amorphous silicon.

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