JP2006012047A - Characteristic analysis device and substrate layout design/verification device constituted by including the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform characteristic analysis with sufficient accuracy and in processing time shorter than that in the conventional case after layout design of a circuit substrate and to perform efficient substrate layout design with satisfactory signal quality. <P>SOLUTION: This characteristic analysis device performs numerical analysis of characteristics of the circuit board. The characteristic analysis device is provided with: a minuteness instruction part which instructs minuteness of the characteristic analysis; an input part which inputs circuit information regarding a circuit, a substrate layout information regarding layout of a substrate on which the circuit is mounted, and circuit/layout correspondence information regarding correspondence between the circuit and the substrate layout; a model generation part which generates a model for characteristic analysis of the circuit substrate corresponding to the minuteness instructed on the basis of the inputted circuit information, substrate layout information and circuit/layout correspondence information; a characteristic analysis part which performs the characteristic analysis using the generated model for the characteristic analysis of the circuit substrate; and an output part which outputs an analysis result. The characteristic analysis device outputs the analysis result of the minuteness in accordance with the instruction of the minuteness instruction part. In addition, a substrate layout design/verification device constituted by comprising the characteristic analysis device is used. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a characteristic analysis apparatus for performing characteristic analysis of a circuit board and a board layout design / verification apparatus including the characteristic analysis apparatus.

  When designing circuit boards used for electronic devices, especially boards that handle high frequencies, the influence of electromagnetic coupling not shown on the circuit diagram, for example, the current flowing in the wiring pattern on the board is induced to other signal lines. Signal quality deterioration or malfunction due to this, and adverse effects on human bodies and other devices due to unnecessary radiation become problems. The countermeasures against such electromagnetic effects are based on prototyping and measurement, clarifying the problems, repeating the work from the circuit design stage, and gradually converging to a design that satisfies the specifications. This has been achieved by accelerating convergence based on the designer's experience and know-how.

  However, this method is not based on a theory, but based on experience and know-how. Therefore, the quality of the board layout and the design period largely depend on the ability of the designer.

  Therefore, as means for solving this problem, there are known design support apparatuses and design support methods that support board layout design by providing electromagnetic information (see, for example, Patent Documents 1 and 2).

In the above document, a procedure for generating an electromagnetic field analysis model based on layout information output by a board layout CAD, etc., analyzing it, obtaining an electromagnetic field distribution, and displaying it to a board layout designer Step on. As a result, the user can improve the board layout to reduce radiation noise based on the displayed information, and repeat the process of re-analysis, so that the board layout can be done without actually making a prototype or measuring. It becomes possible to improve the quality of the.
JP 2001-318961 A JP-A-7-302278

  In the electromagnetic field analysis, since the calculation processing load is large, it is difficult to perform analysis with sufficient accuracy on the entire board at the time of designing with the board layout CAD and use the analysis result in real time. An example of a technique often used to perform electromagnetic field analysis is to subdivide the three-dimensional structure of a substrate into a mesh and model minute elements as points of electromagnetic radiation sources, and calculate the current distribution in the substrate by the circuit applied voltage. It is quantified as an integral equation and obtained using a numerical integration method such as the moment method. The obtained current distribution is superimposed on each applied voltage to obtain the current distribution in the substrate. And the method of analyzing the electromagnetic field of each point based on the calculated | required electric current distribution is taken. According to the method of moments described above, an integral equation can be replaced with a linear equation and solved to obtain an approximate solution. However, since the amount of calculation is still large, the calculation process requires a lot of time. If the mesh of the division is made rough, the number of elements can be reduced and the amount of computation can be reduced. However, since the electromagnetic influence is obtained by point approximation, the error increases as the elements become large. In particular, near the electromagnetic radiation source, the error is large unless the mesh is made fine.

  The present invention has been made in consideration of such circumstances, and is a circuit board characteristic analysis apparatus for performing verification after design without making a circuit board as a prototype, and sufficient accuracy can be obtained. It is an object of the present invention to provide an apparatus capable of performing characteristic analysis in a shorter processing time than before.

  The present invention relates to a degree-of-detail instruction unit for instructing a degree of detail when numerically analyzing a characteristic of a circuit board, circuit information about the circuit, board layout information about a layout of a board on which the circuit is mounted, and the circuit and board layout. An input unit for inputting circuit / layout correspondence information related to correspondence, and generating a model for circuit board characteristic analysis according to the specified level of detail based on the input circuit information, board layout information, and circuit / layout correspondence information A model generation unit that performs analysis, a characteristic analysis unit that performs characteristic analysis using the generated circuit board characteristic analysis model, and an output unit that outputs an analysis result of a detail level according to an instruction from the detail level instruction unit A characteristic analysis apparatus characterized by the above is provided.

  The characteristic analysis apparatus according to the present invention includes a detail level instruction unit that indicates a level of detail of characteristic analysis, and a model generation unit that generates a model for circuit board characteristic analysis corresponding to the specified level of detail. Since the analysis result of the degree of detail according to the instruction of the part is output, sufficient accuracy can be obtained and real-time characteristic analysis can be performed by instructing the optimum degree of detail. Therefore, by using the apparatus of the present invention, after the layout design of the circuit board, the characteristic analysis is performed with sufficient accuracy and in a shorter processing time than the conventional one, thereby realizing an efficient board layout design with good signal quality. Can do.

  The characteristic analysis apparatus according to the present invention includes a detail level instruction unit that indicates a level of detail when numerically analyzing the characteristics of a circuit board, circuit information related to the circuit, board layout information related to a layout of the board on which the circuit is mounted, and the circuit An input unit for inputting circuit / layout correspondence information relating to the correspondence with the board layout, and circuit board characteristic analysis corresponding to the level of detail instructed based on the inputted circuit information, board layout information and circuit / layout correspondence information A model generation unit that generates a model of the model, a characteristic analysis unit that performs a characteristic analysis using the generated model for circuit board characteristic analysis, and an output unit that outputs an analysis result of a detail level according to an instruction from the detail level instruction unit It is characterized by providing.

Here, the characteristic analysis refers to obtaining the characteristics related to the designed board layout by numerical calculation without making a prototype, for example, electromagnetic field analysis, but is not limited to this, and in heat distribution analysis, waveform analysis, etc. There may be. In numerical analysis, actual characteristics are modeled for analysis, and the model is used to perform arithmetic processing to obtain analysis results. However, approximation to a model or calculation method to reduce the amount of calculation that can be performed by the characteristic analyzer. Is used. The level of detail refers to the degree of approximation, and an analysis performed with a high level of detail is expected to provide accurate results, but the amount of computation is large and processing takes time. The circuit information is, for example, information on component characteristics such as IC and resistance (that is, resistance value of resistor component, frequency characteristics, data of typical simulator SPICE of IC, etc.) and connection between component terminals. The board layout information is, for example, information relating to the layer configuration, layer thickness, material characteristics of the printed circuit board, and the layout of the circuit board wiring pattern and the components mounted on the board. The circuit / layout correspondence information is information representing the correspondence between the terminals and wirings in the circuit information and the terminals and wirings in the board layout information.
The detail level instruction unit has a level of detail level counter, and the characteristic analysis is performed by increasing the level of detail of the analysis model generated by changing the value of the level of detail level counter, and more detailed analysis results are sequentially output. You may comprise as follows. In this way, it is possible to collectively manage the processing related to the level of detail by the level of detail level counter. In addition, if the analysis is repeated while changing the counter value, more detailed analysis results can be output in sequence, so the analysis results with low accuracy are output immediately and the board layout designer is informed of the outline. In addition, detailed analysis results can be output, and the board layout designer can judge the design results. As a result, the board layout designer grasped the outline of the analysis result without waiting for a long time, repeated the analysis until it was judged that the analysis result with sufficient accuracy was obtained, and the analysis result with the required accuracy was obtained. The analysis can be terminated at that point. Providing the analysis result in this way is convenient for the designer.

  In addition, an initialization unit for initializing the detail level counter is further provided, and when the initialization unit detail level counter is initialized, the analysis in progress is interrupted and the characteristics at the initialized detail level are obtained. Analysis may be started. In this way, if the user intends to redo the analysis during the execution of the analysis, the analysis can be immediately redone.

  Furthermore, the initialization unit may be tracked by a layout change operation by a user. In this way, when the user changes the layout of the board during the execution of the analysis, the analysis based on the layout that is immediately changed according to the change can be started.

  Furthermore, the model generation unit divides the entire analysis region into a size corresponding to the level of detail, and further divides each divided analysis region into elements based on the characteristic analysis algorithm to generate an analysis model for each element. It may be. In this way, the model accuracy can be changed for each analysis region according to the level of detail, and the distribution of the model accuracy for the region can be made independent of the analysis algorithm. For this reason, in various analysis algorithms or analysis of various characteristics, analysis according to the degree of detail can be performed.

The characteristic analysis of the characteristic analysis unit includes an electromagnetic field characteristic analysis, and the analysis model for each element is an electromagnetic characteristic model, and the characteristic analysis unit determines the influence of the electromagnetic model on each other electromagnetically. A characteristic analysis may be performed by calculation.
Here, the analysis model may include electromagnetic physical variables such as current, magnetic current, potential, magnetic vector potential, electric charge, and magnetic flux for each element. Then, the characteristic analysis may be performed by calculating the influence exerted by these electromagnetic physical variables using an electromagnetic field analysis algorithm based on the electromagnetic theory.

  In addition, the input unit inputs a signal line that has a large influence on the electromagnetic field characteristics as an important signal line, and the model generation unit determines the size of each analysis area based on the positional relationship between the important signal line and each analysis area. It may be determined. In this way, near the important signal lines that are susceptible to electromagnetic influences from the important signal lines, the analysis area is made smaller than in the distant place and analysis is performed with high accuracy. By making the area larger and reducing the amount of computation processing, it is possible to realize an analysis that achieves both high accuracy and fast computation processing time as a whole.

  Furthermore, the substrate may be composed of a plurality of layers, and the model generation unit may further determine the size of each analysis region in consideration of the layer where the important signal line is arranged.

  The circuit information may include a circuit attribute for identifying an important signal line, and the input unit may be configured to extract the important signal line from the circuit attribute. The circuit attribute may be, for example, the signal frequency of the signal line or the magnitude of the signal current. In this way, the layout designer can save the trouble of specifying the important signal lines, and not only can the important signal lines be selected semi-automatically, but also the omission of selection can be eliminated. Therefore, it is possible to realize analysis with high speed and high accuracy.

  The present invention also provides a board layout design / verification apparatus that includes the above-described characteristic analysis apparatus and board layout design apparatus, and performs layout design of the circuit board and characteristic analysis of the designed circuit board. Since the board layout design / verification apparatus according to the present invention includes the characteristic analysis apparatus described above, the characteristic analysis can be performed with sufficient accuracy and with a shorter processing time than before after the layout design of the circuit board. Therefore, it is possible to realize an efficient board layout design with good signal quality.

  Hereinafter, the present invention will be described in more detail with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of an analysis apparatus of the present invention and a board layout design / verification apparatus including the same. In FIG. 1, the board layout design / verification apparatus 1 includes a board layout CAD 10 including a user interface (hereinafter referred to as UI) and an electromagnetic field analysis unit 20. The electromagnetic field analysis unit 20 corresponds to the characteristic analysis apparatus of the present invention.

  A board layout CAD 10 including a UI includes circuit information generated by a circuit CAD and physical information such as board shape, layer information, element shape, terminal shape, and placement constraints (not shown). 2) or an input operation unit (not shown) operated by the user, and restricts the board layout input by the user, thereby supporting the board layout design that satisfies the condition.

  The electromagnetic field analysis unit 20 takes in board layout information, circuit information, and circuit / layout correspondence information from the board layout CAD 10 and performs electromagnetic field analysis, and displays the result. The electromagnetic field analysis unit 20 is characterized by improving the level of detail of information to be displayed over time by performing a detailed analysis loop process that repeats analysis by replacing an analysis model from a simple one to a more detailed one. To do.

  More specifically, the electromagnetic field analysis unit 20 performs characteristic analysis using a control unit 210 including a detail level instruction unit and an input unit, a model generation unit 220 that generates a model for analysis, and a model generated by the model generation unit 220. And a display unit 240 as an output unit.

  The control unit 210 holds and manages a detail level counter 200 indicating the progress of detailing, fetches board layout information, circuit information, and circuit / layout correspondence information from the board layout CAD 10, and these information and detail level Based on the value of the counter, the model generation unit 220 generates a simplification parameter used for model simplification, and outputs it to the model generation unit 220 together with board layout information, circuit information, and circuit / layout correspondence information.

  In addition, the control unit 210 manages operation state information such as “processing completed”, “interrupt completed”, and “error occurrence” from the model generating unit 220, the characteristic analyzing unit 230, and the display unit 240, and based on the information. Operation control information such as “operation start” and “interruption” is sent to each unit. Thus, the processing state of the electromagnetic field analysis unit 20 is controlled.

The model generation unit 220 receives the simplified parameters, the board layout information, the circuit information, and the circuit / layout correspondence information from the control unit 210, and generates the electromagnetic field analysis model data with the degree of detail corresponding to the simplified parameters. And output to the characteristic analysis unit 230.
The characteristic analysis unit 230 receives the electromagnetic field analysis model data sent from the model generation unit 220 as input, performs electromagnetic field analysis calculation, and outputs the electromagnetic field analysis result to the display unit 240.
The display unit 240 displays the electromagnetic field analysis result from the characteristic analysis unit 230 in a display format designated by the user.
(First embodiment)
Below, the process which the electromagnetic field analysis part 20 performs is demonstrated in detail.
FIG. 2 is a flowchart in the first embodiment of the electromagnetic field analysis method in the electromagnetic field analysis unit 20.

[Detail level counter initialization]
When the electromagnetic field analysis is started, the control unit 210 initializes the level of detail level counter to 1 (Step S1). Thereafter, the control unit 210 enters a detailed analysis loop process.

(Simplified parameter generation)
Based on the level of detail expressed by the value of the level of detail level counter and the layout information of the important signal lines obtained from the board layout information, circuit information, and circuit / layout correspondence information, the control unit 210 Simplification parameters used for model simplification are generated and passed to the model generation unit 220 together with board layout information, circuit information, and circuit / layout correspondence information (Step S2). Here, the simplified parameter is generated from the value of the level of detail level counter and the arrangement of the important signal line. The size of each element of the model generated in the subsequent processing step can be determined based on such information. It is for doing so.

[Generate simplified model for analysis]
Next, the control unit 210 instructs the model generation unit 220 to start processing. When the model generation unit 220 receives a processing operation start instruction from the control unit 210, the model generation unit 220 adds a simplification based on the simplification parameters to the board layout information, the circuit information, and the circuit / layout correspondence information. The information is converted into information, and is further output to the characteristic analysis unit 230 as electromagnetic field analysis model data to which a signal source and lumped constant elements included in the circuit information are added, and the control unit 210 is notified of the completion of processing (Step S3). Details of the format of the electromagnetic field analysis model data and the operation of the model generation unit 220 will be described later.

(Electromagnetic field analysis)
Upon receiving the processing completion notification from the model generation unit 220, the control unit 210 next instructs the characteristic analysis unit 230 to start the operation of the characteristic analysis unit.
When the characteristic analysis unit 230 receives an operation start instruction from the control unit 210, the characteristic analysis unit 230 performs electromagnetic field analysis on the electromagnetic field analysis model data given from the model generation unit 220, and outputs the electromagnetic field analysis result to the display unit 240. Then, the control unit 210 is notified of the completion of processing (Step S4). Here, as a specific electromagnetic field analysis calculation method, for example, a moment method can be used.
The method of moments approximates the unknown current and magnetic current distribution on the conductor and dielectric surface with unknown current and magnetic current elements, finds an expression representing the electromagnetic field distribution generated by each element, substitutes it into the boundary condition, converts it to simultaneous equations, By solving this, the current and magnetic current distribution is obtained, and the electromagnetic field state is analyzed.
Patent Document 2 is a document that describes the method of moments in detail.

[Display update]
Upon receiving the characteristic analysis unit process completion notification from the characteristic analysis unit 230, the control unit 210 notifies the display unit 240 of update of analysis data. Upon receiving the analysis data update notification from the control unit 210, the display unit 240 newly takes in the electromagnetic field analysis result from the characteristic analysis unit 230 and updates the display (Step S5).

[End judgment]
Based on the value of the level of detail level counter, the control unit 210 determines whether the detailing loop has ended (Step S6). If the detailing analysis loop is continued, the level of detail level counter is incremented (Step S7). Return to the top of the analysis loop process (Step S2).
In the case of the end of the detailed analysis loop, the control unit 210 performs a detailed analysis loop end process to complete the operation of the analysis unit 20.
Next, the simplified parameter and model generation unit 220 will be described in more detail.
Here, the simplification parameter is a combination of important signal line position information representing the position of an important signal line and a detail level that is a detail level counter value.

  For important signal lines, clock lines etc. are set in advance as circuit attributes of important signal lines, and the positions of signal lines with those attributes are automatically extracted from circuit information, circuit / board layout correspondence information, and board layout information. The position on the board is directly designated by the user.

  FIG. 3 is a block diagram illustrating a detailed configuration of the model generation unit 220. The model generation unit 220 includes a model conversion control unit 221, a block division unit 222, an in-block structure meshing unit 223, and an analysis model synthesis unit 224.

  The model conversion control unit 221 controls the processing state of the entire model generation unit 220 in accordance with instructions from the control unit 210. Specifically, the processing state of the model generation unit 220 is controlled by “in operation”, “processing complete”, and “error” output from the block division unit 222, the intra-block structure meshing unit 223, and the analysis model synthesis unit 224. Understand the status of each part based on internal operation status information such as `` occurrence '', determine the next operation based on it, and send internal operation control information such as `` Start '', `` Suspend '' to each part To do.

  When the characteristic analysis unit 230 performs the electromagnetic field analysis, the block dividing unit 222 is an entire region in which unknown numbers such as current, magnetic current, potential, magnetic vector potential, electric charge, and magnetic flux for each element can be arranged (hereinafter, analysis). The entire target area and description) are obtained from the board layout information, and are divided into a plurality of analysis area blocks having different sizes based on the simplified parameters.

The in-block structure meshing unit 223 includes, from the board layout information, circuit information, and circuit / board layout correspondence information, the conductors included in each analysis area block, the physical property information and arrangement information of the dielectric, and the approximate analysis block. Information such as circuit information of a circuit connected to an existing terminal is extracted, and the information is converted into in-block analysis model data in a format that can be processed by the analysis algorithm of the characteristic analysis unit 230.
The specific format of the electromagnetic field analysis model data varies depending on the configuration of the characteristic analysis unit. For example, when the electromagnetic field analysis algorithm used in the characteristic analysis unit is based on the moment method described in Patent Document 2. The unknown current distribution on the conductor surface, the unknown current distribution on the dielectric surface, the unknown current approximating the unknown magnetic current distribution, the arrangement information of the magnetic current element, the boundary condition information on the conductor surface and the dielectric interface, the unknown current element, The magnetic current element and the connection relation information between each element are included. The current, magnetic current distribution accuracy, and analysis time are controlled by increasing or decreasing the number of unknown currents and magnetic current elements according to the value of the simplified parameter.
The analysis model synthesis unit 224 synthesizes all the in-block analysis model data corresponding to each analysis area block, and generates one electromagnetic field analysis model data.

  FIG. 4 is a flowchart illustrating model generation processing performed by the model generation unit. As shown in FIG. 4, when the model conversion control unit 221 receives control information for starting the model conversion control unit operation from the control unit 210, the model conversion control unit 221 first instructs the block division unit 222 to start the block division unit operation (Step S10).

[Analysis area block division processing]
When the block dividing unit 222 receives the block dividing unit operation start instruction from the model conversion control unit 221, the block dividing unit 222 obtains the entire analysis target area from the board layout information, and calculates the analysis area blocks having different sizes based on the simplified parameters. An analysis area block division process is performed to divide into (Step S11). A more detailed description of the analysis area block division processing will be described later. The dividing process by the block dividing unit does not depend on the electromagnetic field analysis algorithm, but determines the size of each analysis area block based on the degree of detail and divides it. Thereafter, the division information for all the divided analysis region blocks is output to the intra-block structure meshing unit 223, and the model conversion control unit 221 is notified of the completion of the block division unit processing, thereby completing the processing.

  Upon receiving the block division unit processing completion notification from the block division unit 222, the model conversion control unit 221 instructs the intra-block structure meshing unit 223 to start operation.

[In-block mesh processing]
When receiving the operation start instruction from the model conversion control unit 221, the intra-block structure meshing unit 223 includes, for each analysis region block received from the block division unit 222, a conductor, a dielectric, and a circuit included in the corresponding analysis region block. A structure such as an element is extracted from board layout information, circuit information, and circuit / board layout correspondence information, and the structure is converted into in-block analysis model data in a format that can be processed by the characteristic analysis unit 230 (Step S12).
The intra-block structure meshing unit converts the inside of each analysis region block into a model depending on the electromagnetic field analysis algorithm. The conversion algorithm used for this processing is performed using a known electromagnetic field analysis algorithm. Therefore, the mesh division is performed regardless of the shape of the analysis region block except for the boundary of the outer shape, and each analysis region block is divided into substantially equal numbers by applying the same algorithm to each analysis region block. That is, the block size and the mesh size are almost proportional. As a result, the calculation amount (number of elements) of each analysis area block becomes substantially equal. As described above, the size of each area block is determined and divided based on the degree of detail, and as a result, more calculation amount is assigned to an important part.
Thus, in the present invention, the model accuracy is changed for each region in accordance with the degree of detail, and the distribution of the model accuracy for the region does not depend on the electromagnetic field analysis algorithm. For this reason, in the electromagnetic field analysis using various electromagnetic field analysis algorithms, analysis according to the degree of detail can be performed.
That is, since the mesh division width of the model is determined in proportion to the size of the analysis region block, the simplified analysis model data in the block is applied to a larger analysis region block.

Next, the intra-block structure meshing unit 223 outputs all the converted intra-block analysis model data to the analysis model synthesis unit 224, notifies the model conversion control unit 221 of the completion of the intra-block structure meshing unit processing, and performs processing. Complete.
When the model conversion control unit 221 receives the in-block structure meshing unit processing completion notification from the in-block structure meshing unit 223, the model conversion control unit 221 next instructs the analysis model synthesis unit 224 to start the operation of the analysis model synthesis unit.

[Analysis model synthesis processing]
When the analysis model synthesis unit 224 receives the analysis model synthesis unit operation start instruction from the model conversion control unit 221, the analysis model synthesis unit 224 synthesizes all the in-block analysis model data corresponding to each analysis region block into one analysis model. It outputs to the characteristic analysis part 230 (Step S13). Thereafter, the model conversion control unit 221 is notified of the completion of the analysis model synthesis unit process, and the process is completed.
When the model conversion control unit 221 receives the analysis model synthesis unit process completion notification from the analysis model synthesis unit 224, the model conversion control unit 221 notifies the control unit 210 of the completion of the model conversion process and completes the model conversion process.

Next, the analysis area block division processing performed by the block division unit 222 will be described in more detail.
The block division unit 222 has two lists, a pre-processing list having the analysis area block before the division process as an element and a post-processing list having the analysis area block after the division process as an element, and an analysis being processed in the loop. The area block is stored in the processing block storage as a processing block.
FIG. 5 is a flowchart of analysis area block division processing performed by the block division unit 222.

[Pre-processing / Post-processing list initialization]
The block dividing unit 222 first initializes the pre-processing list and the post-processing list as empty as initialization processing. Further, the entire analysis target area is obtained from the board layout information, and is registered in the pre-processing list as an analysis area block (Step S20).
After the initialization process, the block division unit 222 enters a block division loop process.

[Pre-processing list-> Processing block]
The block division unit 222 extracts one arbitrary element from the pre-processing list at the head of the loop and sets it as a processing block, and at the same time deregisters from the pre-processing list (Step S21).

[Block division judgment]
Next, the block division unit 222 performs block division determination on the block being processed.
In block division determination, the distance d (X, Y) between the important signal line position X and the processing block Y included in the simplification parameter, the representative value L (Y) of the size of the processing block Y, and the simplification parameter are used. It is performed using the value D of the level of detail level counter included and the wavelength λ determined by the signal frequency and the dielectric constant or permeability of the medium.

  An example of the block division determination condition is an expression represented by the following formula 1. The block division unit 222 determines to perform block division when the condition of the following expression is satisfied (Step S22). However, Dmax is the maximum value of the level of detail level counter. In Equation 1, when the value of d (X, Y) is constant, the right side of the equation monotonously decreases with respect to the value of the detail level counter, that is, the value of detail D. By giving such a function, it is possible to obtain a conditional expression in which the number of block divisions monotonously increases as the level of detail increases.

  In the following expression, the maximum value function max is used so that the value on the right side does not take a value equal to or less than the wavelength λ. By doing so, it is guaranteed that the loop processing that repeats the block division determination as long as the determination condition is satisfied ends with a finite number of times.

ここで、ｄ（Ｘ，Ｙ）は、重要信号線位置Ｘと処理中ブロックＹとの距離であるが、詳細には、図６に示すように重要信号線位置Ｘに含まれる点xと処理中ブロックＹに含まれる点yの２点x、y間距離ｄ（x，y）を定義したとき、任意にとったx、yの２点間の最小距離と定義する。ただし、ｄ（x，y）は一般的なユークリッド距離であってもよいが、層内と層間で重みを変えた距離など、下記の数２で示される式を満足するような任意の定義を用いることが可能である。

Here, d (X, Y) is the distance between the important signal line position X and the block Y being processed. Specifically, as shown in FIG. When the distance d (x, y) between two points x and y of the point y included in the middle block Y is defined, it is defined as the minimum distance between the two points x and y taken arbitrarily. However, d (x, y) may be a general Euclidean distance, but an arbitrary definition that satisfies the expression shown in the following formula 2, such as a distance in which a weight is changed between layers, may be defined. It is possible to use.

また、処理中ブロックＹの大きさの代表値Ｌ（Ｙ）は、例えば、処理中ブロックの長軸の長さをその値に用いてもよい。

Further, as the representative value L (Y) of the size of the block Y being processed, for example, the length of the major axis of the block being processed may be used as the value.

[Block division]
When the result of the division determination is true, the block division unit 222 adds eight new analysis area blocks obtained by dividing the block being processed into two equal parts in the x, y, and z directions to the pre-processing list. Register (Step S25) and return to the top of the loop.
[Processing block-> Processing completion list]
When the division determination is false, the block dividing unit 222 registers the block being processed in the post-processing list (Step S23).

[End judgment]
Next, it is determined whether the pre-processing list is empty. If the pre-processing list is not empty, the process returns to the head of the block division loop.
If the pre-processing list is empty, the block division unit 222 ends the block division loop processing, and outputs all analysis region blocks held in the post-processing list to the in-block structure meshing unit 223, The conversion control unit 221 is notified of the operation completion (Step S24).

The analysis region block division processing by the block division unit 222 described above has a feature that the division becomes coarser as the distance from the important signal line existence position becomes larger. FIG. 7 is an explanatory diagram illustrating an example of blocks divided by the division determination process of this embodiment.
(Second Embodiment)

FIG. 8 is a flowchart illustrating an example of a different processing procedure of the electromagnetic field analysis process of the electromagnetic field analysis unit 20.
In this embodiment, during the loop processing in the simplified model generation unit 220 and the characteristic analysis unit 230, interruption determination (Steps S34 and S42) referring to the interruption instruction from the control unit 210 is performed, and interruption termination processing (Step S36 and Step S36 and Step S36) is performed. The difference from the first embodiment is that S44) is added. As a result, when the layout designer wants to suspend or redo the analysis, it is possible to immediately suspend the characteristic analysis being performed and proceed to the next processing.

  The interruption command may be interrupted by providing an electromagnetic field analysis interruption unit for interrupting the analysis process by a user operation. Further, the interruption command may be generated by a user changing the board layout. In this case, for example, when the layout change operation moves the part from the current position to another position, the content of the fact that a repeated interruption command is generated during the movement indicates whether there is a change operation at regular time intervals. You may make it determine. In this way, it is possible to control the frequency of occurrence of interruption commands, avoid duplication of processing such as re-initialization of the electromagnetic field analysis unit due to interruption, and reduce time loss caused by frequent interruption determination can do.

  In the development of electronic equipment products that are required to process large amounts of data at high speed, the design support device of the present invention can be used to improve the board layout design quality, reduce the required number of prototypes, and shorten the design period. Can be obtained.

It is a block diagram showing an example of a structure of the analyzer of this invention, and a board | substrate layout design and verification apparatus provided with the same. 3 is a flowchart illustrating an example of an electromagnetic field analysis method in an electromagnetic field analysis unit 20. (Embodiment 1) It is a block diagram showing the detailed structure of the model production | generation part 220 of FIG. It is a flowchart which shows the process of the model generation which the model generation part concerning this invention performs. It is a flowchart of the analysis area block division process which the block division part 222 performs. In block division determination, it is explanatory drawing which shows the definition of distance D (X, Y) of an important signal line position and a block in process. It is explanatory drawing which shows an example of the block divided | segmented by the block division | segmentation determination process based on this invention. It is a flowchart showing an example of a different process sequence of the electromagnetic field analysis process which the electromagnetic field analysis part of this invention performs.

Explanation of symbols

1 Board layout design / verification device 10 Board layout CAD including user interface
20 Electromagnetic field analysis unit, characteristic analysis device 200 Detail level counter 210 Control unit 220 Model generation unit 221 Model conversion control unit 222 Block division unit 223 In-block structure meshing unit 224 Analysis model synthesis unit 230 Characteristic analysis unit 240 Display unit

Claims (10)

A level of detail indicating unit that indicates the level of detail when numerically analyzing the characteristics of the circuit board;
An input unit for inputting circuit information relating to a circuit, board layout information relating to a layout of a board on which the circuit is mounted, and circuit / layout correspondence information relating to correspondence between the circuit and the board layout;
A model generation unit for generating an analysis model for circuit board characteristic analysis in accordance with the specified level of detail based on the input circuit information, board layout information and circuit / layout correspondence information;
A characteristic analysis unit for performing characteristic analysis using the generated circuit board characteristic analysis model;
A characteristic analysis apparatus comprising: an output unit that outputs an analysis result of a detail level according to an instruction from a detail level instruction unit.   The detail instruction unit has a detail level counter, and the characteristic analysis is performed by increasing the detail of the analysis model generated by changing the value of the detail level counter, and more detailed analysis results are sequentially output. The characteristic analysis apparatus according to claim 1, which is configured as follows.   An initialization unit for initializing the detail level counter, and when the detail level counter is initialized during analysis execution by the initialization unit, the analysis being executed is interrupted and the level of detail initialized The characteristic analysis apparatus according to claim 2, wherein the characteristic analysis is started.   4. The board layout design support apparatus according to claim 3, wherein the initialization unit is activated by a layout change operation by a user.   The model generation unit divides an entire analysis region into a size corresponding to the level of detail, further divides each divided analysis region into elements based on a characteristic analysis algorithm, and generates an analysis model for each element. Characteristic analysis device.   The characteristic analysis of the characteristic analysis unit includes electromagnetic field characteristic analysis, and the analysis model for each element is an electromagnetic characteristic model, and the characteristic analysis unit calculates the influence of each electromagnetic characteristic model on each other electromagnetically. 6. The characteristic analysis apparatus according to claim 5, wherein the characteristic analysis is performed by performing the analysis. The input unit inputs signal lines that have a large influence on the electromagnetic field characteristics as important signal lines,
The characteristic analysis apparatus according to claim 6, wherein the model generation unit determines the size of each analysis region based on a positional relationship between the important signal line and each analysis region. The substrate comprises a plurality of layers;
The characteristic analysis apparatus according to claim 5, wherein the model generation unit further determines a size of each analysis region in consideration of a layer in which the important signal line is arranged. The circuit information includes circuit attributes for identifying important signal lines;
The characteristic analysis apparatus according to claim 7, wherein the input unit extracts an important signal line from the circuit attribute.   10. A board layout design / verification apparatus comprising the characteristic analysis apparatus according to claim 1 and a board layout design apparatus, and performing layout design of a circuit board and characteristic analysis of the designed circuit board.

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