JP2006011398A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reflection type and semi-transmission type LCD which has a high aperture ratio and whose power consumption is low. <P>SOLUTION: A 1st substrate 40 is equipped with TFTs as switching elements provided to each pixel. An auxiliary capacitor CSC is composed of an active layer 42 of a TFT, a silicon thin film 43 as a common layer, an auxiliary capacitance line formed by patterning a 1st metallic layer 46 laminated across a gate insulating film 44. An inter-layer insulating film 48 and a flattening insulating film 54 are laminated in order covering the auxiliary capacitance line 26. A reflecting layer 56 and a pixel electrode 28 are provided on the flattening insulating film 54. Consequently, the auxiliary capacitance line is not a disturbance to the aperture of a pixel in a reflection type area where the reflection layer 56 is formed and a transmission type area where the reflection layer 56 is not formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device, and more particularly to a reflective or transflective liquid crystal display device having a function of reflecting external light.

  Liquid crystal display devices that can be reduced in thickness and size and have low power consumption are currently used as displays for various devices. This liquid crystal display device (hereinafter referred to as LCD) has a structure in which two substrates each having an electrode formed on the opposite surface side are sealed with liquid crystal interposed therebetween, and a voltage signal is applied between the electrodes. Display is performed by controlling the light transmittance from the light source by controlling the alignment of the liquid crystal whose optical characteristics change depending on the alignment state.

  Here, it is known that when a DC voltage is continuously applied between the electrodes formed on the opposite surface side of the substrate, the alignment state of the liquid crystal molecules is fixed, that is, a so-called burn-in problem occurs. Conventionally, as a voltage signal for driving a liquid crystal, an AC voltage signal whose polarity with respect to a reference voltage is periodically inverted is employed.

  The timing of the polarity inversion of the liquid crystal drive voltage signal is the inversion for each frame and the inversion for each vertical scanning (1 V) period (or one field period) in a liquid crystal display device in which a plurality of pixels are arranged in a matrix. Inversion every 1 horizontal scanning (1H) period is known inversion every 1 pixel (1 dot) period.

  An active matrix LCD that inherently has high display quality, particularly high-quality video display compared to other methods, has a plurality of pixels arranged in a matrix within the display area. A switching element such as a thin film transistor (TFT), an auxiliary capacitor, and a liquid crystal capacitor including a counter electrode facing the pixel electrode with a liquid crystal layer interposed therebetween are provided. Then, with respect to the voltage signal (common voltage signal) Vcom applied to the counter electrode (common electrode) side, the polarity of the pixel voltage VP connected to the TFT and applied to the individual pixel electrode for each pixel is periodically inverted. ing. By periodically changing the correction of both the counter electrode and the auxiliary capacitor, deterioration of the liquid crystal is prevented, and at the same time, the voltage amplitude of the H driver that outputs a data signal to each data line is reduced, and the H driver has low power consumption. Was realized.

  However, in the horizontal inversion counter electrode AC drive that inverts the video voltage signal polarity applied to each data line every horizontal period, the polarity of the voltage of the counter electrode and all the auxiliary capacitance lines is inverted every horizontal period. And the capacitive loads in all the auxiliary capacity lines and the power consumption due to them were still large.

  Therefore, in order to achieve further reduction in power consumption, the present applicant divides the wiring for applying voltage to the counter electrode and the auxiliary capacitor, and sets the voltage of the counter electrode (Vcom) having a large capacitive load. A driving method (hereinafter referred to as “SC driving”) is proposed in which the current and voltage of the H driver are lowered by inverting the polarity of the voltage of all auxiliary capacitance lines.

  Here, inversion driving methods for periodically inverting the polarity of the voltage applied to the liquid crystal are roughly classified into two types: “line inversion driving” and “dot inversion driving”. In the case of line inversion driving in which the polarity is inverted for each line in the vertical or horizontal direction, the voltage amplitude of the video voltage is suppressed to half that of dot inversion driving by inverting Vcom together with the data signal. However, flickering is easily noticeable due to a slight luminance difference between the positive and negative lines, and plus or minus is lined up in the horizontal or vertical direction, and the inversion frequency (the frame rate when inverting every frame) ), The horizontal or vertical lines are likely to appear as flicker. Therefore, the line inversion drive has to increase the frame rate. On the other hand, in the case of dot inversion driving in which the opposite polarity is applied to all the pixels adjacent to the upper, lower, left, and right sides, Vcom (counter electrode) is made constant, and a video voltage having a polarity inverted to plus / minus on the basis of Vcom is applied. . Therefore, as a display device in which pixels are integrated, the positive and negative poles are uniformly mixed, and flickering is not noticeable even in a low frame, but a large voltage amplitude is required. Since the power consumption of the liquid crystal is determined by the driving frequency and the amplitude of the voltage, it is difficult to reduce the power consumption in either method.

  Therefore, in the dot inversion driving method, a method has been proposed in which an auxiliary capacitor that holds a data signal voltage provided for each pixel is used to reduce the voltage amplitude necessary for driving to achieve a significant reduction in power consumption. (For example, see Patent Document 2). In this driving method, after the data signal voltage is written to the pixel electrode and the auxiliary capacitor, the pixel voltage is shifted to the high potential side or the low potential side by changing one electrode voltage of the auxiliary capacitor. Thereafter, the pixel voltage is made to correspond to the data signal voltage of the conventional dot inversion drive. By this voltage shift operation, a desired voltage necessary for display control can be applied to the pixel. As a result, in dot inversion driving that is resistant to flicker noise even when the frame rate is lowered, the amplitude of the driving voltage can be kept low, and a significant reduction in power consumption can be realized.

JP 2000-81606 A JP 2003-150127 A

  However, in the transmissive liquid crystal display device that performs dot inversion driving described in Patent Document 2, two auxiliary capacitor lines are provided in one column in the column direction in order to apply voltages having different polarities to adjacent columns of the auxiliary capacitors. is necessary. Since the auxiliary capacitance line is formed of a metal that does not transmit light, the two auxiliary capacitance lines in the pixel region reduce the aperture ratio of the pixel.

  The present invention is an active matrix liquid crystal display device in which a plurality of pixels are arranged in a matrix, and a voltage applied to the liquid crystal in each pixel is controlled. The active matrix liquid crystal display device extends in the row direction and is applied with a gate voltage. A plurality of gate lines, a plurality of data lines extending in the column direction, to which a data signal is applied, a switching element disposed for each pixel corresponding to an intersection of the gate line and the data line, and each pixel A pixel electrode connected to the switching element; a reflective layer that is provided in at least a part of a region where the pixel electrode is provided and reflects light that has passed through the liquid crystal layer; and The first and second auxiliary capacitance lines respectively provided for the auxiliary capacitance lines are formed by superimposing auxiliary capacitance electrodes on the auxiliary capacitance lines via an insulating film. And the first and second auxiliary capacitance lines pass through the opposite side to the side where the liquid crystal layer is located in the reflective layer formation region in each pixel. It is characterized by being arranged.

  The gate line is preferably disposed between the first and second auxiliary capacitance lines.

  The reflective layer is provided only in a part of the portion where light passes through the liquid crystal layer of each pixel, and the light that has passed through the liquid crystal layer is left as it is in the portion where the reflective layer is not provided. It is preferable to transmit.

  In addition, it is preferable that the reflective layer is provided only in a central portion of the pixel in the row direction.

  According to the present invention, the two auxiliary capacitance lines are arranged so as to pass through the reflective layer forming region in each pixel. For this reason, since the two auxiliary capacitance lines in the pixel region do not hinder the opening of the pixel region, a high aperture ratio can be obtained.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.

[Configuration of liquid crystal display device]
First, the outline of the configuration and the arrangement of auxiliary capacity lines (hereinafter referred to as SC lines) will be described. FIG. 1 is a diagram schematically showing the configuration of a transflective LCD 10 that is an LCD according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of several pixels of the LCD 10.

  As shown in FIG. 1, the LCD 10 according to the present embodiment is an active matrix LCD with a built-in driver. The LCD 10 has an H driver 12, a V driver 14, and an auxiliary capacitor driver (SC driver) on the same substrate. 16 and a display area 20 for displaying. The H driver 12 sequentially supplies the data signal for each pixel from the video signal line to the data line extending in the vertical direction (vertical scanning direction) arranged for each column. The V driver 14 sequentially outputs a selection signal for sequentially selecting the pixels 18 in the display area 20 to each pixel in the display area 20 via a plurality of gate lines (GL) extending in the horizontal direction (horizontal scanning direction). The SC driver 16 applies a voltage to the storage capacitor via the storage capacitor line SC1 and the second storage capacitor line SC2 that extend in the horizontal direction to each pixel in the display area 20.

  A plurality of pixels 18 are arranged in a matrix in the display area 20. Each pixel 18 includes a data line (DL) that is a wiring pattern from the H driver 12, a gate line (GL) that is a wiring pattern from the V driver 14, and a first auxiliary that is a wiring pattern from the SC driver. The capacitor line SC1 and the second auxiliary capacitor line SC2 are wired. GL and SC1 and SC2 are arranged in parallel in the horizontal direction.

  As shown in FIG. 2, the pixel 18 is provided with a TFT 30 having a double gate structure as a switching element. That is, as shown in the figure, the TFT 30 has two gates connected in series and a common gate electrode. The TFT 30 has a gate electrode connected to the GL, a drain (or source) connected to the DL, and a source (or drain) connected to one electrode of the liquid crystal capacitor CLC (a pixel electrode provided individually for each pixel) and an auxiliary. It is connected to one electrode (auxiliary capacitor electrode) of the capacitor CSC. The other electrode of the liquid crystal capacitor CLC is connected to a common electrode common to all pixels. A common voltage signal (Vcom) is supplied to the common electrode, and the voltage is maintained at Vcom. A liquid crystal is connected between the pixel electrode and the common electrode. The layers are sandwiched to form a liquid crystal capacitor CLC. The other electrode of the auxiliary capacitance CLC is formed as a part of either one of the auxiliary capacitance lines SC1 or SC2. Further, since the other electrode of the auxiliary capacitor CLC is connected to the auxiliary capacitor line SC1 or SC2 every other electrode, the auxiliary capacitor lines used in adjacent pixels are different.

  FIG. 3 is a schematic plan view of the first substrate side (substrate on which the pixel electrodes and the TFTs 30 are formed) of the transflective LCD 10 according to the present embodiment. FIGS. 4, 5, and 6 are FIGS. It is a schematic sectional drawing of LCD10 in the position along the AA line, BB line, and CC line.

  As shown in FIG. 3, the gate line GL24 is arranged in the horizontal direction, and the data line DL22 is arranged in the vertical direction. A TFT 30 serving as a switching element is disposed near the intersection between the GL 24 and the DL 22. This TFT 30 has an active layer whose drain is connected to DL 22, and this active layer once extends parallel to the data line DL and passes below the thickness direction of the GL 24, and then makes a U-turn and again below the GL 24. Has passed. Therefore, the portion where the active layer exists below the GL 24 is the gate electrode 30g of the TFT 30, the portion connected to the DL 22 of the active layer is the drain region 30d, and the other end side of the active layer is the source region 30s.

  A source electrode 52 is connected to the source region 30s through a contact. The source electrode 52 has an inverted L-shape extending in two directions from the center of the portion corresponding to the source region 30s. . One end of the inverted L of the source electrode 52 is connected to the auxiliary capacitance electrode 32 via a contact. The auxiliary capacitance electrode 32 is formed of a semiconductor layer formed by the same process as the semiconductor active layer used for the TFT 30. Therefore, the auxiliary capacitance electrode 32 can be formed by extending the semiconductor active layer of the TFT 30 as it is. However, in this example, the auxiliary capacitance electrode 32 is formed separately from the active layer of the TFT 30 and connected by the source electrode 52. The auxiliary capacitance electrode 32 extends below the auxiliary capacitance line SC1 or SC2, and forms an auxiliary capacitance CLC with a gate insulating film interposed between the auxiliary capacitance electrode 32 and the auxiliary capacitance line.

  On the other hand, the other end of the inverted L of the source electrode 52 is connected to the upper pixel electrode 28 via a contact. The pixel electrode (first electrode) 28 is formed of a transparent conductive material such as ITO (Indium Tin Oxide). In this example, the portion where the TFT 30 and the source electrode 52 are present is the center, and the shape is an elongated rectangle extending on both sides.

  The first auxiliary capacitance line (SC1) 26a and the second auxiliary capacitance line (SC2) 26b are arranged in parallel so as to sandwich the GL24. That is, three lines extend parallel to the horizontal direction. In one pixel, the auxiliary capacitance electrode 32 is formed below only one of the auxiliary capacitance lines 26a or 26b to form the auxiliary capacitance CSC. The auxiliary capacitance line 26 serving as an electrode of the auxiliary capacitance CSC has a width. The capacity of the auxiliary capacity CSC is secured.

  Here, a part of the inverted L-shaped source electrode 52 has a protruding portion and reaches the gate line GL24. That is, the protruding portion is located on the gate line GL24 via the interlayer insulating film. In a normally black liquid crystal panel, if the TFT 30 is always turned on due to an abnormality, the pixel becomes a bright spot. In the present embodiment, by irradiating the projecting portion with laser, the source electrode 52 can be short-circuited with the gate line GL24, and the pixel can be darkened.

  Further, a light-shielding pattern 34 is formed in a peripheral portion of the rectangular pixel and a portion corresponding to the outside of the two SC lines 26a and 16b. In other words, the region between the two SC lines 26a and 26b and the region between the SC lines 26a and 26b and the light shielding pattern 34 are shielded from light by increasing the width of the data line DL22. Accordingly, a rectangular pixel, that is, a peripheral portion of the pixel electrode 28 is covered with any one of the light shielding pattern 34, the data line 22 or the SC lines 26a and 26b, and the pixel periphery is shielded as a whole. As a result, display is performed for each pixel, and a clear display can be achieved.

  As shown in FIG. 4, the TFT 30 is formed on the first substrate 40 side, and a pixel electrode (first electrode) 28 provided for each pixel is connected to the TFT 30.

  A transparent substrate such as glass is used for the first and second substrates 40 and 70, and in the case of a color display liquid crystal device, a color filter 68 is provided on the second substrate 70 side facing the first substrate 40. 28, and a counter electrode 66 that is a second electrode made of a transparent conductive material is formed on the color filter 68 (liquid crystal side). As the transparent conductive material of the counter electrode 66, IZO (Indium Zinc Oxide), ITO, or the like is employed. The counter electrode 66 is formed as a common electrode common to the pixels. A second alignment film 64 made of polyimide or the like is formed on the counter electrode 66.

  On the first substrate 40, an active layer 42 made of polysilicon is formed in a predetermined region. In this example, the TFT 30 has a double gate configuration. One end of the active layer 42 is a drain region 42d, next to the channel region 42c, next to the source and gate region, next to the channel region 42c, and the other end to the source. This is a region 42s. A gate insulating film 44 is formed on the active layer 42, and the gate line GL 46 is positioned above the channel region 42 c on the gate insulating film 44. An interlayer insulating film 48 is formed so as to cover the gate line 44, a metal layer 50 to be the data line DL is formed on the upper surface, and a source electrode 52 is formed. The metal layer 50 is connected to the drain region 42d of the TFT 30 via a contact, and the source electrode 52 is connected to the source region 42s via a contact.

  As shown in FIG. 5, the source electrode 52 is also connected to a polycrystalline silicon thin film 43 formed by the same process as the active layer 42 through a contact. The polycrystalline silicon thin film 43 forms the capacity electrode 32 of the auxiliary capacity CSC. That is, the portion where the polycrystalline silicon thin film 43 and the first metal layer 46 which becomes the SC line 26 are opposed to each other through the gate insulating film 44 is the auxiliary capacitance CSC.

  Further, a contact hole is formed in the planarization insulating film 54 on the source electrode 52, and the pixel electrode 28 formed on the planarization insulating film 54 is connected by a connection metal layer 55 formed here. . A reflective layer 56 is formed in a predetermined portion between the pixel electrode 28 and the planarization insulating film 54. As can be seen from FIGS. 3 to 5, the reflective film 56 is formed so as to cross the central portion of the pixel where the TFT 30, the capacitor line SCL 46 and the like are disposed. Accordingly, by setting a portion where light is not transmitted due to wiring or the like as the reflective region, it is possible to secure the reflective region while securing the area of the transmissive region.

  Further, FIG. 6 shows a portion of the auxiliary capacitor CLC. As described above, the polycrystalline silicon thin film 43 forming the capacitor electrode reaches the adjacent pixel below the metal layer 46 forming the auxiliary capacitor line SCL, and the gate insulating film 44 is interposed between these layers. ing. Therefore, a part of the auxiliary capacitor CLC exists in adjacent pixels. Since the portion where the auxiliary capacitance line SCL exists does not transmit light, even if the auxiliary capacitance is formed here, the area of the transmission region is not affected. Further, in the present embodiment, there are two auxiliary capacitance lines SCL, and adjacent pixels use different auxiliary capacitance lines SCL. Therefore, it is preferable to form a part of the auxiliary capacitor in the adjacent pixel.

  The first metal layer 46 to be the gate line GL24 and the SC line 26 is formed in the same process immediately above the gate insulating film 44 on the first substrate 40, and an interlayer insulating layer made of SiNx or the like is formed thereon so as to cover them. A film 48 is formed. The second metal layer 50 made of Al, Mo or the like and serving as the data line DL22 is formed by the same process as the source electrode 52 and the like. That is, they are formed together by etching and patterning after forming the metal layer. Further, the planarization insulating film 54 formed thereon is formed from acrylic resin or the like.

  In order to form a reflective region of the transflective LCD on the planarization insulating film 54, a reflective layer 56 that reflects incident light from the second substrate side is formed. The reflective layer 56 is made of Al, Ag, or an alloy thereof such as an Al—Nd alloy.

  Further, the pixel electrode 28 and the first alignment film 60 are sequentially formed on the reflective layer 56 to constitute a first substrate, and the liquid crystal layer 62 is sandwiched between the first substrate and the second substrate.

  FIG. 7 is a plan view showing the arrangement of the reflective layer 56 in the LCD 10 according to the present embodiment. A reflective layer 56 is disposed in a region sandwiched between SC1 and SC2 of the pixel 18, the reflective region where the reflective layer 56 is disposed functions as a reflective LCD, and the transmissive region where the reflective layer 56 is not disposed functions as a transmissive LCD. To do.

  By adopting such a configuration, in the reflective region including the reflective layer 56, light incident from the second substrate 70 side is reflected by the reflective layer 56 and returns to the second substrate 70 side. There is no problem even if exists. Further, since there is no SC line in the transmissive region where the reflective layer 56 is not provided, the opening of the pixel region is not hindered by the SC line. Therefore, in an LCD that performs dot inversion driving that requires two SC lines per pixel row, the pixel area can be efficiently used to increase the substantial aperture ratio.

  Here, in this embodiment, as shown in FIGS. 3 and 4, a top gate type is adopted as the TFT 30. As the active layer 42, polycrystalline silicon (p-Si) obtained by polycrystallizing amorphous silicon (a-Si) by laser annealing is used. The TFT 30 is not limited to the top gate type p-Si, but may be a bottom gate type, and a-Si may be used for the active layer 42.

  Impurities doped in the source / drain regions 42s and 42d of the active layer 42 of the TFT 30 shown in FIG. 4 may be either n-conductivity type or p-conductivity type. In this embodiment, n-conductivity impurities such as phosphorus are used. Doped and n-ch TFT 30 is employed. Then, a channel region 42c that is not doped with impurities is formed. The source region 42 s of the active layer 42 of the TFT 30 is connected to the source electrode 52 through a contact, and the source electrode 52 is further connected to the auxiliary capacitance electrode 32 x formed of the active layer 42 of the TFT 30 and the polycrystalline silicon thin film 43 through the contact. It is connected.

  As shown in FIGS. 3 and 6, the first auxiliary capacitance 32a includes an auxiliary capacitance electrode 32x opposed to the gate insulating film 44 and an auxiliary capacitance electrode 32y formed extending from the first auxiliary capacitance line 26a. It is formed with. The second auxiliary capacitance 32b is formed by the auxiliary capacitance electrode 32x opposed to the gate insulating film 44 and the auxiliary capacitance electrode 32z formed extending from the second auxiliary capacitance line 26b. The auxiliary capacitance electrode 32x is formed by patterning a polycrystalline silicon thin film formed by the same process as that of the active layer 42 into a region overlapping the first auxiliary capacitance line 26a and the second auxiliary capacitance line 26b by an etching process. The

As shown in FIG. 6, the gate insulating film 44 is formed of, for example, a laminated structure of SiNx and SiO ₂ or any one so as to cover the active layer 42, and a first metal such as Cr, Ta, or Mo is formed thereon. The layer 46 is patterned to form the auxiliary capacitance line SCL. The gate line GL24 is also formed by the same process as the auxiliary capacitance line SCL. The light shielding pattern 34 is formed by the same process as that of the first metal layer 46 (see FIG. 5).

  Further, as shown in FIG. 4, the second metal layer 50 and the source electrode 52 to be the DL 22 are connected to the source region 42s and the drain region 42d formed in the active layer 42 by contacts provided in the interlayer insulating film 48. Has been.

  Further, a flattening insulating film 54 for flattening is formed to have a thickness of about 1 μm or more so as to cover the TFT 30 and the interlayer insulating film 48. For the planarization insulating film 54, for example, SOG (Spin On Glass), BPSG (Boro-phospho-Silicate Glass), acrylic resin, or the like is used. Further, the reflection type region includes a reflection layer 56 on the planarization insulating film 54, and includes a reflection region where the reflection layer 56 and the reflection layer 56 are provided, and a transmission region where the reflection layer 56 is not provided. A pixel electrode 28 is formed in the entire pixel region. A transparent conductive film such as ITO is used for the pixel electrode 28. The pixel electrode 28 is connected to the source electrode 52 of the TFT 30 through a contact provided on the planarization insulating film 54 by the connecting metal layer 55.

The conditions required for the connecting metal layer 55 that connects the pixel electrode 28 and the source electrode 52 of the TFT 30 are:
(I) An electrical connection with the pixel electrode 28 made of IZO, ITO, or the like can be obtained.
(Ii) It can be electrically contacted with a source electrode 52 such as Al of the TFT 30, and when the source electrode 52 is omitted, it can be electrically connected to a semiconductor (here, polycrystalline silicon) active layer;
(Iii) When the reflective layer 56 is patterned into individual shapes for each pixel, the reflective layer 56 is not removed by the etching solution.
Etc. As such a connection metal layer 55, it is preferable to use a refractory metal material such as Mo, Ti, or Cr.

  In the configuration of FIG. 5, an inclined surface having a desired angle is formed on the surface of the planarizing insulating film 54 so that the transmissive region side is thin in the vicinity of the boundary between the reflective region and the transmissive region in each pixel region. . Therefore, by laminating the reflective layer 56 so as to cover the planarization insulating film 54, a similar inclination is formed on the surface of the reflective layer 56. If such an inclined surface is formed at an appropriate angle and position, the direction of the reflected light in each pixel can be controlled and emitted. Of course, such an inclined surface does not necessarily exist.

  Furthermore, by making the planarization insulating film 54 sufficiently thick in the reflective region and reducing the thickness of the liquid crystal layer in the reflective region, the optical path length of the liquid crystal layer can be matched between the reflective region and the non-reflective region.

  As described above, the reflective layer 56 is made of a conductive material such as an Al—Nd alloy, but the pixel electrode 28 laminated on the reflective layer 56 and the reflective layer 56 are electrically insulated. The reason for the insulation is that the surface of the reflective layer 56 made of Al or the like is oxidized on the surface by being exposed to a sputtering atmosphere when IZO or ITO or the like is formed as a material of the pixel electrode 28 by sputtering. This is because the reaction takes place and is covered with a natural oxide film. Therefore, in the present embodiment, a voltage corresponding to the display content is applied to the liquid crystal layer 62 using the transparent conductive layer formed on the reflective layer 56 as the pixel electrode 28.

  Further, as shown in FIGS. 4 to 6, for example, polyimide is used as an alignment film for aligning liquid crystal molecules in the vertical direction on almost the entire surface of the first substrate 40 so as to cover the pixel electrode 28. One vertical alignment film 60 is formed.

  The first substrate side on which each element as described above is formed and the second substrate side disposed opposite to each other with the liquid crystal layer 62 interposed therebetween are made of glass or the like, similar to the first substrate. As shown in FIG. 2, a second vertical alignment film 64 using, for example, polyimide is formed on the surface facing the first substrate 40 as an alignment film for aligning liquid crystal molecules in the vertical direction.

  On the second substrate 70 side of the second vertical alignment film 64, as shown in FIGS. 4 to 6, the counter electrode 66, which is a second electrode made of ITO or the like for driving the liquid crystal with the opposing pixel electrode 28. Is formed. In addition, RGB color filters 68 are formed in a predetermined arrangement on the second substrate 70 side of the counter electrode 66 so as to correspond to the pixel electrodes 28. A black matrix 72 is provided between the pixels 18 of the color filter 68 in order to avoid light interference with adjacent pixels. As shown in FIG. 5, in the present embodiment, both the light shielding pattern 34 and the black matrix 72 are provided, but usually only one of them is provided.

  Next, functions of the above-described configuration will be described. A first data signal voltage VDa and a second data signal voltage VDb having opposite polarities are input to the H driver 12. Normally, these data signal voltages VDam and VDb are supplied by a video signal line, and are supplied as separate signals for each of RGB.

  The H driver 12 supplies the data signal voltages VDa and VDb to the corresponding data line DL according to the input horizontal clock signal. That is, each data line DL is connected to the video signal line via a switch, and the H driver 12 sequentially turns on the switch to correspond to the data signal voltages VDa and VDb supplied to the video signal line. Supply to the data line DL. The V driver 16 sequentially selects the GL 24 and applies the gate signal GV.

  The first auxiliary capacitance line 26a is supplied with a first auxiliary capacitance voltage, and the second auxiliary capacitance line 26b is supplied with a second auxiliary capacitance having a polarity opposite to that of the first auxiliary capacitance voltage. Voltage is supplied.

  The first auxiliary capacitor 32a and the second auxiliary capacitor 32b hold the charge due to the data signal voltage VD supplied from the DL 22 via the TFT 30 for one frame period.

  A constant voltage Vcom is applied to the counter electrode 66, and the liquid crystal is driven by the voltage difference of the data signal voltage VD applied to the pixel electrode 28.

  In the present embodiment, the first and second auxiliary capacitance lines are configured to alternately have auxiliary capacitance electrodes in the row direction in units of one pixel electrode in order to reduce image unevenness and flicker as much as possible. . However, the present invention is not limited to this, and an auxiliary capacitance electrode to be used may be alternately changed in units of a plurality of pixels. For example, a configuration may be adopted in which three pixels that display RGB are used as one unit, and either the first or second auxiliary capacitance line is used for each unit.

  In this embodiment, a double gate type TFT is exemplified, but the present invention is not limited to this, and the number of gate electrodes may be one or three or more. Further, although the auxiliary capacitance line is formed in the same layer as the gate line, the auxiliary capacitance line may be formed in a layer different from the gate line.

  In the present embodiment, the pixels of the same color in the display area 20 are arranged in a stripe arrangement in a straight line in the vertical direction, but the arrangement of the pixels is not limited to the stripe arrangement. For example, the pixels may have a delta arrangement as shown in FIG.

  In the liquid crystal display device shown in FIG. 8, the auxiliary capacitance electrode 32x formed of the polycrystalline silicon thin film 43 extends to both adjacent pixel regions adjacent to the pixel to which the corresponding liquid crystal capacitance CLC belongs. According to this configuration, the width of the auxiliary capacitance electrode 32x is not limited to the width of the pixel. Since the auxiliary capacitance CSC is proportional to the area of the auxiliary capacitance electrode 32x overlapping the active layer 42, the area of the auxiliary capacitance electrode 32x within the pixel is desired by minimizing the pixel pitch, reducing the SC line width, or the like. Even when the auxiliary capacitance CSC cannot be secured, the desired auxiliary capacitance CSC can be secured by extending the auxiliary capacitance electrode 32x to the adjacent pixel region. This configuration can be realized because the auxiliary capacitors are configured by alternately using different auxiliary capacitor lines 26a and 26b between pixels adjacent in the row direction. Therefore, the boundary of the auxiliary capacitance electrode 32x is a position where it can be insulated from the auxiliary capacitance electrode 32x belonging to the pixel constituting the auxiliary capacitance by the two adjacent auxiliary capacitance lines. That is, if a region narrow enough to ensure insulation from the center of adjacent pixels is provided, the auxiliary capacitance electrodes of the pixels on both sides can be extended to that extent. In the liquid crystal display device shown in FIG. 8, an active layer of the TFT 30 and the auxiliary capacitance electrode 32x are integrally formed in the polycrystalline silicon thin film constituting the TFT 30 as a switching element. That is, as in the previous embodiment, the source region 52 is not connected to the source region of the TFT 30 via the source electrode 52, but the polycrystalline silicon thin film 43 forming the source region is extended as it is, and the auxiliary capacitor electrode It has become.

  In addition, the liquid crystal display device 10 according to the present embodiment is preferably of a vertically aligned type (VA). In addition, adopting the VA type, in order to further expand the viewing angle of LCD and improve display quality, the absence of electrodes (windows) or protrusions are provided in the pixels to divide the liquid crystal alignment within one pixel. Is preferred. For example, as shown in FIG. 9, an X-shaped electrode absence portion is formed in the counter electrode 66 as an alignment control window 80 in a region facing each pixel electrode 28. One alignment control window 80 due to the absence of the electrode is provided in the reflection region of each pixel and one in each of the two transmission regions, and the alignment of the liquid crystal is divided in each region.

  This alignment division by the absence of the electrode utilizes the gradient of the weak electric field when a voltage starts to be applied between the pixel electrode 28 and the counter electrode 66. Under this weak electric field, the electric lines of force from the electrode absent portion are inclined so as to spread from the end of the orientation control window 80 by the electrode absent portion, that is, from the end of the electrode toward the center of the electrode absent portion. Then, since the minor axis of the liquid crystal having negative dielectric anisotropy is aligned along the oblique lines of electric force, the liquid crystal molecules follow the rise in the voltage applied to the liquid crystal and the initial vertical liquid crystal molecules The direction of falling from the orientation state is defined by the oblique electric field.

  In addition, when the protrusions are formed on the counter electrode 66 or below the electrodes, the alignment film 64 formed so as to cover them has an inclination corresponding to the protrusion. Since the liquid crystal is aligned perpendicular to the surface of the alignment film 64, therefore, the alignment of the liquid crystal can be divided here with the protrusion provided on the counter electrode 66 side as a boundary. In the above description, the electrode absence structure is provided on the counter electrode, but may be provided on the pixel electrode side.

[Operation of liquid crystal display]
FIG. 10 is a timing chart showing the relationship between the control signals in the liquid crystal display device 10 according to the present embodiment. The gate signal GV (GV1 to GV3), the potential Vsca of the first auxiliary capacitance line SC1, and the second auxiliary signal. The timing of the potential Vscb of the capacitor line SC2 is shown.

  First, a pulse is generated in the vertical start signal STV at the beginning of one frame, and STV rises for a predetermined time. In order to supply the data signal voltage to each horizontal line in response to the fall of the vertical start signal STV, the gate signals GV1, GV2,... Sequentially become H level within one horizontal scanning period. That is, first, the gate signal GV1 rises, and the gate signal GV1 is supplied to GL1 in the first row. Accordingly, the TFT 30 connected to GL1 is turned on. The pulse of the horizontal start signal STH is sequentially transferred according to the horizontal clock signal CKH to the horizontal transfer shift register in the H drive.

  During the period (H level period) in which the gate signal GV1 is supplied to the gate line GL1 in the first row, the horizontal clock signal CKH rises and falls repeatedly at a predetermined cycle. This cycle is synchronized with the switching of the data signal voltage VD of the video signal consisting of the data signal voltage VD for each pixel. Therefore, the switch is turned on by the register that takes in the H level of STH and connected to the data line DL. The data signal voltage VD for the current pixel is sequentially supplied. In addition, after the GL falls to the L level, the two capacitor lines SCL are inverted from each other and maintained in that state for one frame. That is, after the data voltage is written to the auxiliary capacitor and the TFT 30 is closed, the voltage of the capacitor line SCL shifts. Therefore, the shift direction is inverted for each pixel for each frame. Note that the data voltage VD in one pixel is also inverted every frame, and the direction of voltage shift by the capacitor line SCL is always set to the direction in which the voltage held in the holding capacitor is away from Vcom.

  When the data signal voltage VD is applied to all the DLs, the gate signal GV1 of the gate line GL1 in the first row becomes the Low level, and the TFT 30 connected thereto is turned off. Then, the pulses of the gate signal GV2 and the gate signal GV3 sequentially rise, the gate signal GV2 is applied to the second gate line GL2, and the gate signal GV3 is applied to the third gate line GL3, and the above operation is repeated. .

  When the gate signal GV is sequentially supplied to all the gate lines GL, the pulse of the vertical start signal STV rises again, and the gate signal GV is supplied to the gate line GL1 in the first row in synchronism with this, so that the same operation is performed. repeat.

  FIG. 11 is a signal waveform diagram showing a driving method of the liquid crystal display device 10 according to this embodiment, and shows a signal waveform between one frame in a pixel region adjacent in the gate line direction. 11A shows the signal waveform of the first auxiliary capacitor 32a, and FIG. 11B shows the signal waveform of the second auxiliary capacitor 32b.

  11A and 11B show a gate voltage VG, a pixel voltage VP, a source voltage VS, a data signal voltage VD, an auxiliary capacitance voltage VSC, and a counter electrode voltage Vcom applied to one pixel. FIG. 11A shows a pixel to which the data voltage VD having a voltage higher than Vcom is written, and FIG. 11B shows a pixel to which the data voltage VD having a voltage lower than Vcom is written.

  The gate voltage VG has one horizontal period (on period of the TFT 30) once per frame. During the ON period of the gate voltage VG, the gate voltage VG applied to the GL is at a high level (hereinafter referred to as “High”). During this period, the TFT 30 is turned on and the drain-source is made conductive, and the source voltage VS follows the data signal voltage VD applied to the data line DL to the same level, and the liquid crystal capacitor CLC and the auxiliary capacitor CSC. (One of CSCa or CSCb). When the gate is turned off, the gate voltage VG becomes low level and the TFT 30 is turned off, the source voltage VS is determined, and the level is lowered by ΔVs as the gate voltage VG falls, and the voltage of the source electrode (= pixel The voltage of the electrode is VPL. Note that ΔVs is a voltage determined by the amount of change in the gate line voltage VG, parasitic capacitance, and the like.

  On the other hand, the counter electrode voltage Vcom is a constant voltage and is at a level that is lower than the center level VC of the data signal voltage VD by a drop ΔVs of the source voltage VS in advance.

  Each auxiliary capacitance line is applied with an auxiliary capacitance voltage VSC that is inverted after the fall of the gate voltage VG applied to the corresponding gate line GL. The auxiliary capacitance voltage VSC is inverted between two levels, VSCH and VSCL. For example, in the positive polarity period in which the source voltage VS is higher than the common electrode voltage Vcom, as shown in FIG. 11A, after the fall of the gate voltage VG. , Rising from the low level VSCL to the high level VSCH. Therefore, the pixel voltage VP once the source voltage VS can be determined by the fall of the gate voltage VG rises by ΔVP due to the influence of the rise of the auxiliary capacitance voltage VSC via the auxiliary capacitance CSC. The pixel voltage VP at this time is held during the gate OFF period.

  As described above, the pixel voltage VP shifts in accordance with the amount of change in the auxiliary capacitance voltage due to the rise of the auxiliary capacitance voltage VSC. However, charge redistribution occurs between the liquid crystal capacitance CLC and the auxiliary capacitance CSC, and the pixel voltage VP is , ΔVP = VPH−VPL.

  In addition, in the negative electrode period in which the source voltage VS is lower than the counter electrode voltage Vcom, as shown in FIG. 11B, the auxiliary capacitance voltage VSC falls from the positive side to the negative side, so the pixel voltage VP drops by ΔVP.

  As a result, in either case of FIG. 11A or FIG. 11B, the amplitude of the pixel voltage VP (difference from Vcom) increases due to the change of the auxiliary capacitance voltage VSC, and the voltage applied to the liquid crystal capacitance CLC is increased. Can do. That is, by inverting the auxiliary capacitance voltage VSC to two levels, the amplitude of the data signal voltage VD can be reduced even when the counter electrode voltage Vcom is constant, and dot inversion driving can be performed with low power consumption. it can. As described above, in a pixel adjacent in the row direction, the data voltage VD that is connected to a different auxiliary capacitance line SCL of the two auxiliary capacitance lines SCLa or SCLb and supplied to the data line DL is also inverted in polarity. Therefore, dot inversion driving has been achieved. Note that AC drive is achieved because the polarity of the data voltage VD supplied for each frame and the H level and L level of the auxiliary capacitance voltage VSC are inverted in each pixel.

It is a figure which shows the outline of a structure of the transflective liquid crystal display device which concerns on embodiment of this invention. FIG. 2 is a plan view schematically showing a first substrate side of the transflective liquid crystal display device of FIG. 1. It is a figure which shows the equivalent circuit of the transflective liquid crystal display device of FIG. It is a figure which shows schematic sectional structure of the transflective liquid crystal display device in the position along the AA line of FIG. It is a figure which shows schematic sectional structure of the transflective liquid crystal display device in the position along the BB line of FIG. It is a figure which shows schematic sectional structure of the transflective liquid crystal display device in the position along the CC line | wire of FIG. FIG. 2 is a plan view showing an arrangement of a reflective layer 56 in the transflective liquid crystal display device shown in FIG. 1. It is a top view of the transflective liquid crystal display device made into the delta arrangement. It is a figure which shows the orientation control window of a VA type transflective liquid crystal display device. 4 is a timing chart showing the relationship between control signals in the liquid crystal display device according to the present embodiment. It is a signal waveform diagram which shows the drive method of the liquid crystal display device which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 12, 14, 16 Driver, 18 pixels, 20 Display area, 22 Data line, 24 Gate line, 26 Auxiliary capacity line, 28 Pixel electrode, 30 TFT, 32 Auxiliary capacity, 34 Shading pattern, 40, 70 Substrate, 42 active layer, 43 silicon thin film, 44 gate insulating film, 46 first metal layer, 48 interlayer insulating film, 50 second metal layer, 52 source electrode, 52g short-circuited region, 54 planarization insulating film, 55 for connection Metal layer, 56 reflective layer, 60, 64 alignment film, 62 liquid crystal layer, 66 counter electrode, 68 color filter, 72 black matrix, 80 alignment control window.

Claims (4)

A plurality of pixels are arranged in a matrix, and an active matrix liquid crystal display device that controls an applied voltage to liquid crystal in each pixel,
A plurality of gate lines extending in the row direction to which a gate voltage is applied;
A plurality of data lines extending in the column direction to which data signals are applied;
A switching element disposed for each pixel corresponding to the intersection of the gate line and the data line;
A pixel electrode provided for each pixel and connected to the switching element;
A reflective layer that is provided in at least a part of a region where the pixel electrode is provided and reflects light that has passed through the liquid crystal layer;
First and second auxiliary capacitance lines respectively provided for each row of the pixels;
An auxiliary capacitance formed by superimposing an auxiliary capacitance electrode on the auxiliary capacitance line through an insulating film;
Have
The first and second auxiliary capacitance lines are arranged so as to pass through the opposite side to the side where the liquid crystal layer is located in the reflective layer formation region in each pixel. Liquid crystal display device. The liquid crystal display device according to claim 1.
The liquid crystal display device, wherein the gate line is disposed between the first and second auxiliary capacitance lines. The liquid crystal display device according to claim 1 or 2,
The reflection layer is provided only in a part of the portion where light passes through the liquid crystal layer of each pixel, and the light passing through the liquid crystal layer is transmitted as it is in a portion where the reflection layer is not provided. A liquid crystal display device characterized by the above. The liquid crystal display device according to claim 3.
The liquid crystal display device, wherein the reflective layer is provided only at a central portion in a row direction of pixels.

Images