JP2006005386A - Power-on / reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-on / reset circuit capable of suppressing increase in the chip area and quickly and stably initializing a logic part at application of power to an analog / digital mixed LSI. <P>SOLUTION: The power-on / reset circuit 1 comprises: a band gap reference circuit 2 comprising a startup section 4 and a band gap reference generating section 5; and a detector 3. In the operation of the power-on / reset circuit 1, first power is supplied to the startup section 4 and the band gap reference generating section 5 at application of power. Then the startup section 4 starts its operation and outputs a startup signal to the band gap reference generating section 5. Succeedingly, the band gap reference generating section 5 receives the startup signal, carries out its circuit operation and outputs a detection signal to the startup section 4 and the detector 3. The detector 3 receiving this detection signal outputs a reset signal to a logic section 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a power-on reset circuit that initializes a logic unit when power is turned on in an analog / digital mixed LSI.

  Electronic devices such as portable information terminals, personal computers, and audio devices are provided with a power-on reset circuit that generates a reset signal for initializing a logic unit and the like when the power is turned on. An RC time constant circuit provided inside or outside the semiconductor integrated circuit is used for the power-on reset circuit (see, for example, Patent Document 1). In addition, a logic circuit provided inside a semiconductor integrated circuit is used (for example, see Patent Document 2).

  However, when the RC time constant circuit is used, the discharge time of the RC time constant circuit is extended by increasing the resistance and capacitance in order to prevent malfunction due to power supply noise or instantaneous power interruption. For this reason, when the RC time constant circuit is provided outside the semiconductor integrated circuit, there is a problem that the substrate area of the electronic device increases. When the RC time constant circuit is provided inside the semiconductor integrated circuit, the chip area of the semiconductor integrated circuit is reduced. There are increasing problems. Furthermore, there is a problem that it takes time from initialization of the logic unit to initialization of the logic unit.

On the other hand, when a logic circuit is used for the power-on reset circuit, the initial value of the logic circuit is unstable in a transient state immediately after the power is turned on, resulting in a problem that the noise margin is reduced and the resistance to noise is reduced. . Further, when this logic circuit is provided inside the semiconductor integrated circuit, there is a problem that the chip area of the semiconductor integrated circuit increases.
JP-A-5-335915 (page 3, FIG. 2) JP-A-9-83327 (page 6, FIG. 1)

  It is an object of the present invention to provide a power-on-reset circuit that suppresses an increase in chip area and can quickly and stably perform initialization of a logic unit at power-on in an analog / digital mixed LSI. .

  To achieve the above object, a power-on reset circuit according to an aspect of the present invention includes a startup unit that outputs a startup signal after power-on, a bandgap reference generation unit that outputs a detection signal based on the startup signal, and A bandgap reference circuit that outputs a bandgap power supply to an analog unit after the start-up unit stops outputting the start-up signal to the bandgap reference generation unit by inputting the detection signal; and And a detector that outputs a reset signal to the logic unit based on the detection signal and stops the output of the reset signal when the detection signal level is switched.

  In order to achieve the above object, a power-on reset circuit according to another aspect of the present invention includes a start-up unit that outputs a start-up signal after power-on, and a bandgap reference generation that outputs a detection signal based on the start-up signal. And a resistance dividing unit that is provided between the high-potential-side power source and the low-potential-side power source and includes first and second resistors connected in cascade, and the start-up unit inputs the detection signal After stopping the start-up signal output to the bandgap reference generation unit, a bandgap reference circuit for outputting a bandgap power supply to the analog unit, a resistance by the detection signal and the first and second resistors Based on the divided potential, a reset signal is output to the logic unit, and the detection signal level is switched. Characterized in that it sometimes and a detector for stopping the output of the reset signal.

  According to the present invention, there is provided a power-on-reset circuit that suppresses an increase in chip area and can quickly and stably initialize a logic unit when power is turned on in an analog / digital mixed LSI. Can do.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a power-on reset circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram for explaining initialization of a logic unit using a power-on-reset circuit at power-on, and FIG. 2 is a circuit diagram showing the power-on-reset circuit.

  As shown in FIG. 1, the analog / digital mixed LSI 10 includes a power-on reset circuit 1, an analog unit 6, and a logic unit 7. The power-on reset circuit 1 includes a band gap reference circuit 2 including a startup unit 4 and a band gap reference generation unit 5, and a detector 3.

  In the operation of the power-on reset circuit 1, first, when the power is turned on, the power is supplied to the start-up unit 4 and the band gap reference generation unit 5. Next, the startup unit 4 starts operation and outputs a startup signal to the band gap reference generation unit 5. Subsequently, the bandgap reference generation unit 5 inputs a startup signal, performs a circuit operation, and outputs a detection signal to the startup unit 4 and the detector 3. The start-up unit 4 receiving this detection signal stops outputting the start-up signal to the band gap reference generation unit 5.

  After the power is turned on, the bandgap reference circuit 2 enters a steady state and supplies power, for example, a constant current to the analog unit 6. On the other hand, the detector 3 outputs a reset signal to the logic unit 7 until the detection signal is switched, and stops transmitting the reset signal to the logic unit 7 when the detection signal is switched. At this time, the logic unit 7 is released from the reset state and starts circuit operation. For this reason, since the reset of the logic unit 7 is reliably continued until the power is turned on, the malfunction of the logic unit 7 when the power is turned on can be prevented.

  Here, the power supplied to the detector 3 is a digital circuit power source (shared with the logic unit 7) that starts simultaneously with the power supplied to the start-up unit 4 and the bandgap reference generation unit 5. The power supplied to the unit 4, the band gap reference generation unit 5, and the analog unit 6 may be used. Alternatively, the same power may be used for the power-on reset circuit 1, the analog unit 6, and the logic unit 7.

  As shown in FIG. 2, the detector 3 uses an inverter circuit. The startup unit 4 is composed of resistors R1 and R2 and NPN transistors N1 and N2. One end of the resistor R1 is connected to the high potential side power source Vcc. The NPN transistor N1 has a collector connected to the other end of the resistor R1, a base connected to the collector, and an emitter connected to the low potential side power source Vss. The base of the NPN transistor N2 is connected to the base and collector of the NPN transistor N1. The resistor R2 has one end connected to the emitter of the NPN transistor N2 and the other end connected to the low potential side power source Vss. The NPN transistors N1 and N2 constitute a current mirror circuit.

  The bandgap reference generator 5 includes capacitors C1 and C2, resistors R3 to R10, PNP transistors P1 to P5, and NPN transistors N3 to N5. One end of the resistor R3 is connected to the high potential side power source Vcc. The PNP transistor P1 has an emitter connected to the other end of the resistor R3 and a collector connected to one end of the resistor R2. The resistor R4 has one end connected to the high potential side power source Vcc. The emitter of the PNP transistor P2 is connected to the other end of the resistor R4. The NPN transistor N3 has a collector connected to the collector of the PNP transistor P2.

  One end of the resistor R5 is connected to the high potential side power source Vcc. The emitter of the PNP transistor P3 is connected to the other end of the resistor R5. The NPN transistor N4 has a collector connected to the collector of the PNP transistor P3 and the collector of the NPN transistor N2. The resistor R6 has one end connected to the emitters of the NPN transistors N3 and N4, and the other end connected to the low potential side power source Vss.

  One end of the resistor R7 is connected to the high potential side power source Vcc. The emitter of the PNP transistor P4 is connected to the other end of the resistor R7. One end of the capacitor C1 is connected to the high potential side power source Vcc, and the other end is connected to the bases of the PNP transistors P3 and P4. The resistor R8 has one end connected to the collector of the PNP transistor P4 and the base of the NPN transistor N3, and the other end connected to the collector of the NPN transistor N5. The base of the NPN transistor N5 is connected to the collector and the base of the NPN transistor N4.

  The resistor R9 has one end connected to the emitter of the NPN transistor N5 and the other end connected to the low potential side power source Vss. One end of the capacitor C2 is connected to the bases of the NPN transistors N4 and N5, and the other end is connected to the low potential side power source Vss. The resistor R10 has one end connected to the high potential side power supply Vcc. The PNP transistor P5 has an emitter connected to the other end of the resistor R10, and a base connected to the bases of the PNP transistors P1 to P4. Of the band gap reference generator 5, resistors R4, R5, R6, PNP transistors P2, P3, and NPN transistors N3, N4 are configured such that the collector of the PNP transistor P4 is connected to the base of the NPN transistor N3. A signal output from the connection node of the resistor R8 is input, and the circuit operates as a feedback amplifier circuit that inputs a feedback signal to the base of the NPN transistor N4.

  Here, the power of the power-on reset circuit 1, for example, a constant current (Iout) is output from the collector of the PNP transistor P5. The startup signal of the startup unit 4 is output from the collector of the NPN transistor N2 between the collector of the PNP transistor P3 of the bandgap reference generation unit 5 and the collector of the NPN transistor N4, and the detection signal of the bandgap reference generation unit 5 is The voltage is output between the collector of the transistor P1 and the resistor R2 to the emitter of the NPN transistor N2 in the start-up unit 4 and the inverter as the detector 3.

  This detection signal is “Low” level from when the power is turned on until the high potential side power supply Vcc of the bandgap reference circuit 2 rises, and after the operation of the start-up unit 4 is stopped, Become. For this reason, when the operation of the start-up unit 4 stops, the signal output from the inverter operating as the detector 3 changes from “High” to “Low”. At this time, the logic unit 7 is released from reset and starts circuit operation. Note that while the operation of the start-up unit 4 is stopped and the analog / digital mixed LSI 10 is operating, the signal output from the inverter operating as the detector 3 maintains the “Low” state.

  Next, start-up of the analog unit and logic unit of the analog / digital mixed LSI will be described with reference to FIGS. FIG. 3 is a diagram showing start-up of the analog unit and logic unit, FIG. 3 (a) is a diagram showing start-up of the analog unit and logic unit of this embodiment, and FIG. 3 (b) is a conventional analog unit and logic unit. FIG. 4 is a diagram showing the start-up of the analog unit and the logic unit when the power-up is relatively slow.

  As shown in FIG. 3, conventionally, for example, a logic unit 7 that starts operation earlier at time T <b> 2 in an unstable power supply startup state than an analog unit 6 that starts operation at time T <b> 1 after power-on, for example, After the power is sufficiently raised by an external reset circuit using an RC time constant circuit provided outside the analog / digital mixed LSI 10, the operation is started at time T3. Here, the time T3 is, for example, 72 ms, which is delayed by two digits or more from the time T1 when the analog unit 6 starts to operate, and changes only by the RC time constant regardless of the time T1.

  On the other hand, in this embodiment, when the bandgap reference circuit 2 operates stably, the detection signal output from the bandgap reference generation unit 5 changes from “Low” to “High” and is output from the inverter operating as the detector 3. The signal to be changed changes from “High” to “Low”. When this signal is input to the logic unit 7 and the reset of the logic unit 7 is released and the circuit operation is started, the time for starting the circuit operation is T1 + ΔT, and the band gap reference circuit 2 operates stably to supply power to the analog unit 6, It is only delayed by ΔT compared to the time T1 when the analog unit 6 starts operation.

  Here, the time T1 is, for example, 100 μs, which is two orders of magnitude faster than the time T3, and the time ΔT, for example, is 3 μs, which is three orders of magnitude or more earlier than the time T3. When the reset is released, the time for starting the circuit operation can be made earlier than before. In addition, since only an inverter that operates as the detector 3 is added, an increase in the chip area of the analog / digital mixed LSI 10 can be suppressed, and it is not necessary to optimize the RC multiplier according to the rising speed of the power supply voltage.

  Then, as shown in FIG. 4, when the power-on is relatively slow, the logic unit 7 is released from reset and starts circuit operation for a time T4 when the analog unit 6 starts operation, for example, 111 μs. The time T5 is, for example, 109 μs, which is 2 μs earlier than the time T4, and similarly to FIG. 3A, the time when the logic unit 7 is reset and the operation is started can be made earlier than before.

  As described above, in the power-on reset circuit according to this embodiment, the detection signal output from the bandgap reference generation unit 5 is output to the start-up unit 4 and the detector 3. The start-up unit 4 receiving this detection signal stops outputting the start-up signal to the bandgap reference generation unit 5, the bandgap reference circuit 2 enters a steady state and supplies power to the analog unit 6. Starts operation. On the other hand, the detector 3 outputs a reset signal to the logic unit 7 until the detection signal is switched, and stops outputting the reset signal to the logic unit 7 when the detection signal is switched. At this time, the logic unit 7 releases the reset. Then, the circuit operation is started. Therefore, the initialization of the logic unit 7 of the analog / digital mixed LSI at power-on can be performed more quickly and stably than in the prior art.

  Furthermore, since only the detector 3 for initializing the logic unit 7 is added to the analog / digital mixed LSI 10, an increase in the chip area can be suppressed.

In this embodiment, a PNP transistor and an NPN transistor are used for the power-on reset circuit 1, but an Nch MOS transistor and a Pch MOS transistor may be used, and a SiNxOy film obtained by thermally nitriding a silicon oxide film, a silicon nitride film ( An NchMIS transistor and a PchMIS transistor in which a stacked film of Si ₃ N ₄ ) / silicon oxide film or a high dielectric film (High-K gate insulating film) or the like serves as a gate insulating film may be used. Further, the power-on reset circuit 1 may have a BiCMOS configuration.

  Next, a power-on reset circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram showing a power-on reset circuit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 5, the power-on reset circuit 1a includes a band gap reference circuit 2a including a start-up unit 4, a band gap reference generating unit 5, and a resistance dividing unit 6, and a detector 3a. In the resistance divider 6, resistors R11 (first resistor) and R12 (second resistor) are cascade-connected between the high potential side power source Vcc and the low potential side power source Vss.

  Here, a comparator is used for the detector 3a. The comparator operating as the detector 3a inputs and compares and amplifies the detection signal of the bandgap reference generator 5 output from between the collector of the PNP transistor P1 and the resistor R2 and the potential divided by the resistors R11 and R12. . The operation of the comparator that operates as the detector 3a is as follows. First, the detection signal is “Low” and the connection point between the resistors R11 and R12 from when the power is turned on until the high potential side power supply Vcc of the band gap reference circuit 2a rises. The potential becomes “High”. For this reason, the signal transmitted from the comparator operating as the detector 3a to the logic unit 7 becomes “High”, and the logic unit 7 maintains the reset state.

  Next, when the operation of the startup unit 4 stops, the detection signal changes from “Low” to “High”, so the signal transmitted from the comparator operating as the detector 3 a to the logic unit 7 changes to “Low”. To do. At this time, the logic unit 7 is released from reset and starts circuit operation. Note that while the operation of the start-up unit 4 is stopped and the analog / digital mixed LSI is operating, the signal output from the comparator operating as the detector 3a maintains the "Low" state.

  As described above, in the power-on reset circuit of this embodiment, the detection signal of the band gap reference generator 5 output from between the collector of the PNP transistor P1 and the resistor R2 and the potential divided by the resistors R11 and R12. And a comparator that operates as a detector 3a that compares and amplifies. When this detection signal is switched, the comparator operating as the detector 3a changes from “High” to “Low”. At this time, the logic unit 7 is released from the reset state and starts circuit operation. Therefore, it has the same effect as the first embodiment.

  Next, a power-on reset circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing a power-on reset circuit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the power-on reset circuit 1 b includes a band gap reference circuit 2 b including a startup unit 4, a band gap reference generation unit 5 a, and a resistance dividing unit 6 a, and a detector 3. The detector 3 uses an inverter circuit. The band gap reference generation unit 5a includes capacitors C1 and C2, resistors R3 to R10, PNP transistors P1 to P5, and NPN transistors N3 to N5, and an inverter serving as a detector 3 detects a detection signal of the band gap reference generation unit 5a. Since it is the same as FIG.

  In the resistance divider 6a, a resistor R11 (first resistor) and PNP transistors P6 and R12 (second resistor) are cascade-connected between a high potential side power source Vcc and a low potential side power source Vss. The resistor R11 has one end connected to the high potential side power supply Vcc and the other end connected to the emitter of the PNP transistor P6. The base of the PNP transistor P6 is connected to the bases of the PNP transistors P1 to P5. The resistor R12 has one end connected to the collector of the PNP transistor P6 and the other end connected to the low potential side power source Vss. The inverter operating as the detector 3 receives the resistance-divided potential of the resistance divider 6a output from between the collector of the PNP transistor P6 and the resistor R12.

  This resistance-divided potential is “Low” level from when the power is turned on until the high-potential side power supply Vcc of the bandgap reference circuit 2b rises, and the high-potential side power supply Vcc of the bandgap reference circuit 2b rises. After the operation of the unit 4 is stopped, the PNP transistor P6 of the resistor dividing unit 6a is operated, and the potential divided by the resistors R11 and 12 rises and becomes a “High” level signal. For this reason, when the operation of the start-up unit 4 stops, the signal output from the inverter operating as the detector 3 changes from “High” to “Low”. At this time, the logic unit 7 is released from reset and starts circuit operation. Note that while the operation of the start-up unit 4 is stopped and the analog / digital mixed LSI 10 is operating, the signal output from the inverter operating as the detector 3 maintains the “Low” state.

  As described above, in the power-on reset circuit of this embodiment, an inverter that operates as the detector 3 that inputs the potential divided by the resistors R11 and R12 is provided. When the PNP transistor P6 of the resistance divider 6a operates and the resistance-divided potential rises, the inverter operating as the detector 3 changes from “High” to “Low”. At this time, the logic unit 7 is released from the reset state and starts circuit operation. Therefore, it has the same effect as the first embodiment.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in this embodiment, a feedback amplifier circuit is used for the band gap reference circuit, but a circuit configuration in which two stages of current mirror circuits are cascade-connected may be used.

1 is a circuit block diagram for explaining initialization of a logic unit using a power-on reset circuit when power is turned on according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a power-on reset circuit according to Embodiment 1 of the present invention. The figure which shows starting of the analog part and logic part which concern on Example 1 of this invention. FIG. 3 is a diagram illustrating start-up of an analog unit and a logic unit when the power-on is relatively slow according to the first embodiment of the present invention. FIG. 6 is a circuit diagram showing a power-on reset circuit according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram showing a power-on reset circuit according to Embodiment 3 of the present invention.

Explanation of symbols

1, 1a, 1b Power-on reset circuit 2, 2a, 2b Band gap reference circuit 3 Detector (inverter)
3a Detector (Comparator)
4 Start-up unit 5, 5a Bandgap reference generation unit 6, 6a Resistor division unit 10... Analog / digital mixed LSI
C1, C2 Capacitances N1 to N5 NPN transistors P1 to P6 PNP transistors R1 to R12 Resistor Vcc High potential side power supply Vss Low potential side power supply

Claims (5)

A startup unit that outputs a startup signal after power is turned on; and a bandgap reference generation unit that outputs a detection signal based on the startup signal; and the startup unit inputs the detection signal and the bandgap reference generation unit A bandgap reference circuit that outputs a bandgap power supply to the analog unit after stopping outputting the startup signal to
Based on the detection signal, a reset signal is output to the logic unit, and a detector that stops the output of the reset signal when the detection signal level is switched;
A power-on reset circuit comprising: A start-up unit that outputs a start-up signal after power-on, a bandgap reference generation unit that outputs a detection signal based on the start-up signal, and a cascade-connected second power source provided between a high-potential side power source and a low-potential side power source A resistance dividing unit including a first resistor, a transistor, and a second resistor, and after the start-up signal unit stops outputting the detection signal, the bandgap power supply is output to the analog unit. A band gap reference circuit;
Based on the potential divided by the first and second resistors, a reset signal is output to the logic unit, and when the transistor operates and the potential divided by the first and second resistors rises, A detector that stops the output of the reset signal;
A power-on reset circuit comprising:   The power-on reset circuit according to claim 1, wherein the detector is an inverter. A start-up unit that outputs a start-up signal after power-on, a bandgap reference generation unit that outputs a detection signal based on the start-up signal, and a cascade-connected second power source provided between a high-potential side power source and a low-potential side power source A resistance dividing unit composed of a first resistor and a second resistor, and the analog input unit after the startup unit inputs the detection signal and stops outputting the startup signal to the bandgap reference generation unit. A bandgap reference circuit that outputs a bandgap power supply to
A detector that outputs a reset signal to the logic unit based on the detection signal and the potential divided by the first and second resistors, and stops outputting the reset signal when the detection signal level is switched;
A power-on reset circuit comprising:   The power-on reset circuit according to claim 4, wherein the detector is a comparator.

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