JP2006005035A - Ceramic package assembly for storing electronic component and ceramic package - Google Patents

Ceramic package assembly for storing electronic component and ceramic package Download PDF

Info

Publication number
JP2006005035A
JP2006005035A JP2004177799A JP2004177799A JP2006005035A JP 2006005035 A JP2006005035 A JP 2006005035A JP 2004177799 A JP2004177799 A JP 2004177799A JP 2004177799 A JP2004177799 A JP 2004177799A JP 2006005035 A JP2006005035 A JP 2006005035A
Authority
JP
Japan
Prior art keywords
wiring board
conductor
hole
ceramic package
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004177799A
Other languages
Japanese (ja)
Inventor
Katsuhiro Nishikawa
勝裕 西川
Yutaka Yamagata
豊 山形
Shigeki Kawamura
茂樹 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal SMI Electronics Device Inc
Original Assignee
Sumitomo Metal SMI Electronics Device Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal SMI Electronics Device Inc filed Critical Sumitomo Metal SMI Electronics Device Inc
Priority to JP2004177799A priority Critical patent/JP2006005035A/en
Publication of JP2006005035A publication Critical patent/JP2006005035A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board assembly and a wiring board or a ceramic package capable of obtaining the ceramic package that can prevent burrs and conductor foreign matters from being generated and can secure a large bonding area for soldering. <P>SOLUTION: The wiring board assembly for manufacturing the ceramic packages stores electronic components having castellations on side walls formed with a conductive film for connecting a conductive portion on the top face, and a conductive portion on the bottom face. The assembly has through holes 6 formed with the conductive film which become the castellations after being divided into individual packages. The conductive film formed on the inner wall of the through holes is continuous inside the through holes, but away from a position from which the wiring board assembly is going to be divided into individual packages in a lower part of the through holes. Moreover, the conductor pattern 8 on the bottom face which become external connection terminals by being connected to the conductive film 4 on the through holes is also away from the position from which the assembly is going to be divided into individual packages. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、電子部品が搭載される配線基板を有するセラミックパッケージの集合体、およびその集合体から作製されるセラミックパッケージに関する。   The present invention relates to an assembly of ceramic packages having a wiring board on which electronic components are mounted, and a ceramic package manufactured from the assembly.

近年、半導体素子、水晶振動子、圧電素子等の電子回路部品素子を収納するための電子部品収納用セラミックパッケージは、電子部品素子を用いる小形装置、たとえば携帯電話やノート型パソコン等の高機能化に伴い、より一層の小型化および高信頼性化が要求されている。   In recent years, ceramic packages for storing electronic components for storing electronic circuit component elements such as semiconductor elements, crystal resonators, and piezoelectric elements have become highly functional in small devices using the electronic component elements, such as mobile phones and notebook personal computers. Accordingly, further downsizing and high reliability are required.

このセラミックパッケージとは、導体パターンを持つ配線基板、基板に接合された枠体および上部の蓋体からなり、導体パターンと導電ワイヤーなどで接続された電子回路部品素子をその中に収納し、蓋体を枠体上部に接合して気密に封止するものである。この基板上の導体パターンは、基板等を貫通するビア内の導体、あるいは導体膜を備えた基板側壁面の凹部(以下キャスタレーションとも言う)を通じて外部接続用端子パッドに接続されており、この端子パッドは、マザープリント回路板など外部回路基板のランドとはんだなどにより接合される。   This ceramic package consists of a wiring board having a conductor pattern, a frame joined to the board, and an upper lid, and an electronic circuit component element connected to the conductor pattern by a conductive wire or the like is housed therein, and the lid The body is joined to the upper part of the frame and hermetically sealed. The conductor pattern on the substrate is connected to an external connection terminal pad through a conductor in a via penetrating the substrate or the like, or a recess (hereinafter also referred to as castellation) on a substrate side wall surface provided with a conductor film. The pad is bonded to a land of an external circuit board such as a mother printed circuit board by solder or the like.

図2(A)にセラミックパッケージの一例について模式図を示すが、電子部品素子接続用ランド3のような導体パターンを持つ基板1に枠体2が接合された形状をしている。このような配線基板あるいはセラミックパッケージは、通常図2(B)に示すような配線基板集合体の形で製作し、これを分割して個々のパッケージにする。このセラミックパッケージおよびその集合体をひっくり返して下面を上に向けて見た場合を図3(A)および(B)に示す。   FIG. 2A shows a schematic diagram of an example of a ceramic package, in which a frame body 2 is bonded to a substrate 1 having a conductor pattern such as an electronic component element connection land 3. Such a wiring board or ceramic package is usually manufactured in the form of a wiring board assembly as shown in FIG. 2B, and is divided into individual packages. FIGS. 3A and 3B show a case where the ceramic package and its assembly are turned upside down and viewed from below.

このセラミックパッケージに電子部品素子を装荷し、マザープリント回路板などにはんだで接合された場合のキャスタレーション部分における断面を、模式的に示した例が図4である。電子部品12は配線基板上の導体パターン3に接続され、枠体2の上面の導体上に蓋体13が接合され封止された後、回路板14上の接続ランド15の上にはんだ16で接合される。この接合は、パッケージ内部の電子部品素子とマザープリント回路板とを電気的に接続すると共に、回路板へパッケージを固着する目的もある。   FIG. 4 is an example schematically showing a cross section of a castellation portion when an electronic component element is loaded on the ceramic package and joined to a mother printed circuit board by soldering. The electronic component 12 is connected to the conductor pattern 3 on the wiring board. After the lid body 13 is joined and sealed onto the conductor on the upper surface of the frame body 2, the solder 16 is placed on the connection land 15 on the circuit board 14. Be joined. This bonding has the purpose of electrically connecting the electronic component elements inside the package and the mother printed circuit board and also fixing the package to the circuit board.

図5に、これのようなパッケージなど配線基板集合体および配線基板の製造工程の例を示す。まず所定の厚さに成形されたグリーンシートに、キャスタレーション4になる貫通孔6を開け、この貫通孔の内壁面にスルーホール印刷法により導体膜となるタングステンなどのペーストを印刷する。次に、この導体膜に接続させて、上面に接続ランドパターンの導体ペーストを印刷する。また積層するシートにより、下面にもマザープリント回路板などに接続するための端子用ランドとしての導体パターンなども印刷される。配線基板が複層の場合は、貫通孔位置は同じにして、異なる導体パターンあるいは上下層接続のためのビアを形成したグリーンシートをそれぞれ作製し、これらを積層する。さらに要すれば枠体も圧着される。   FIG. 5 shows an example of a manufacturing process of a wiring board assembly such as a package and a wiring board. First, a through-hole 6 that becomes a castellation 4 is formed in a green sheet formed to a predetermined thickness, and a paste such as tungsten that becomes a conductor film is printed on the inner wall surface of this through-hole by a through-hole printing method. Next, the conductor paste of the connection land pattern is printed on the upper surface so as to be connected to the conductor film. In addition, a conductor pattern as a terminal land for connecting to a mother printed circuit board or the like is also printed on the lower surface of the laminated sheet. When the wiring board has a plurality of layers, the through-hole positions are the same, green sheets each having a different conductor pattern or via for connecting the upper and lower layers are produced, and these are laminated. If necessary, the frame is also crimped.

積層後、図2(B)または図3(B)に示したように、上下面に貫通孔と直交する位置で分割用の溝7を形成し、一体化焼成をおこなう。 焼成後、表面に露出している回路パターンや貫通孔内壁の導体膜に対し、導電性改善のためのニッケルメッキおよび金メッキが施される。このようにして作製された配線基板集合体を、貫通孔位置にて分割用溝に沿って割れば、図2(A)あるいは図3(A)の配線基板(セラミックパッケージ)ができあがる。それにより、内面に導電体膜が形成された貫通孔6は、パッケージあるいは配線基板の側壁のキャスタレーション4となる。   After lamination, as shown in FIG. 2B or FIG. 3B, dividing grooves 7 are formed on the upper and lower surfaces at positions orthogonal to the through holes, and integrated firing is performed. After firing, the circuit pattern exposed on the surface and the conductor film on the inner wall of the through hole are subjected to nickel plating and gold plating for improving conductivity. If the wiring board assembly produced in this way is divided along the dividing grooves at the positions of the through holes, the wiring board (ceramic package) shown in FIG. 2 (A) or FIG. 3 (A) is completed. Thereby, the through-hole 6 in which the conductor film is formed on the inner surface becomes the castellation 4 on the side wall of the package or the wiring board.

このとき、基板材料はアルミナなど脆いセラミックなので、きれいに分離切断されるが、導電体部分はメッキによってニッケルや金など延性に富んだ軟質材料が付着しており、分割する際に分離性を悪くしたり、バリを発生させたりするおそれがある。このバリは、マザープリント回路板などにはんだで接合する際に、パッケージを浮き上がらせるなど接続不良の原因になったり、後で脱落して導体異物となり、隣接する他のパッケージなど他部品との短絡の原因になったりして、電子回路の品質を低下させる。   At this time, since the substrate material is brittle ceramic such as alumina, it is separated and cut cleanly, but the conductor part is attached with a soft material with high ductility such as nickel and gold by plating, which makes the separation property worse when dividing. Or may generate burrs. This burr may cause a connection failure such as floating the package when soldering to the mother printed circuit board, etc., or it will drop off later and become a conductive foreign object, resulting in a short circuit with other components such as adjacent packages. Cause the quality of the electronic circuit to deteriorate.

このようなバリや導体異物の発生を抑止するため、たとえば特許文献1には、基板表面上の導電体パターンの側端部を分割端面から離れた位置とする基板の発明が提示されている。この特許文献1の発明は、図3(B)に示した下面を上にして見た配線基板集合体をA−A’の位置にて分割したときの貫通孔周辺の状態として説明すれば次のようになる。 図6に示したA−A’位置での分割面を手前にした斜視図にて、(A)のように配線基板集合体9の下面上に形成させた導体パターンは、分割予定位置あるいは分割溝7にお
いて相互に繋がっていると、分割したとき導体からバリが発生し、これがはんだ付け不良や誤配線の原因になる。そこで、特許文献1に開示された発明の配線基板集合体では図6(B)のように、基板上導体パターンを分割端面に位置する側端と分割位置との間に、隙間を設けた形状としている。
In order to suppress the occurrence of such burrs and conductive foreign objects, for example, Patent Document 1 proposes an invention of a substrate in which the side end portion of the conductor pattern on the substrate surface is positioned away from the divided end surface. The invention of Patent Document 1 can be described as a state around the through hole when the wiring board assembly viewed from the bottom side shown in FIG. 3B is divided at the position AA ′. become that way. FIG. 6 is a perspective view with the divided surface at the position AA ′ shown in FIG. 6, and the conductor pattern formed on the lower surface of the wiring board assembly 9 as shown in FIG. If the grooves 7 are connected to each other, burrs are generated from the conductor when divided, which causes soldering defects and miswiring. Therefore, in the wiring board assembly of the invention disclosed in Patent Document 1, as shown in FIG. 6 (B), a shape in which a gap is provided between the side end of the conductor pattern on the board located on the split end face and the split position. It is said.

また、キャスタレーションとなる貫通孔の内壁は、スルーホール印刷により導体ペーストの塗布がおこなわれるが、その場合、印刷用のマスクは貫通孔の孔径より大きい開口部のものが用いられ、貫通孔周辺の基板面にも導体ペーストが印刷される。特許文献2には、この導体ペーストの貫通孔周辺における分割溝への回り込みが、分割性を悪くしたり絶縁不良や短絡問題を生じたりする原因になるとして、印刷用のマスクを貫通孔の分割溝位置には導体ペーストが印刷されないようにした配線基板集合体の発明が開示されている。この方法によれば、基板集合体上面の貫通孔端部の分割位置には導体膜を無くすことができ、この位置での導体を分割することによるバリの問題はなくなるが、貫通孔内部の導体膜も縦方向に分割されたものとなる。   In addition, the inner wall of the through-hole that becomes the castellation is coated with a conductive paste by through-hole printing. In this case, a mask for printing with an opening that is larger than the diameter of the through-hole is used. The conductor paste is also printed on the substrate surface. In Patent Document 2, it is assumed that the wraparound of the conductor paste around the through-holes causes deterioration of the partitionability, poor insulation, and short-circuit problems. An invention of a wiring board assembly in which conductor paste is not printed at the groove position is disclosed. According to this method, the conductor film can be eliminated at the dividing position of the end portion of the through hole on the upper surface of the substrate assembly, and the problem of burrs caused by dividing the conductor at this position is eliminated. The film is also divided in the vertical direction.

さらに特許文献3には、このような基板表面の導体パターンに接続した貫通孔内の導体膜がそれぞれ分離絶縁されている、配線基板集合体およびそれから得られた配線基板についての発明が開示されている。   Further, Patent Document 3 discloses an invention relating to a wiring board assembly and a wiring board obtained therefrom, in which the conductor films in the through holes connected to the conductor pattern on the surface of the board are separately insulated. Yes.

特開平10−313157号公報JP-A-10-313157 特公平7−67001号公報Japanese Patent Publication No. 7-67001 特開平11−26639号公報Japanese Patent Laid-Open No. 11-26639

本発明者らは、このようなセラミックパッケージあるいは配線基板の製造において、集合体分割の際に生じるバリによる不具合の発生、あるいは導体異物の紛れ込みを排除すべく種々検討をおこなった。このバリや導体異物は、焼成によって作られた導体膜の上に施される軟質のニッケルメッキや金メッキが、分割時に変形分離して生じており、特許文献1示されるように、基板表面上の導電体パターンの側端部を分割端面から離れた位置とするのがよいと思われた。しかしながら、このような基板表面パターン形状の改良の実施のみでは、バリや異物の低減効果はあまり大きくなかった。   In the manufacture of such a ceramic package or wiring board, the present inventors have made various studies in order to eliminate the occurrence of defects due to burrs generated during assembly division or the inclusion of conductive foreign matter. The burrs and conductor foreign matter are produced by soft nickel plating or gold plating applied on the conductor film made by firing, which is deformed and separated at the time of division. It seemed that the side edge of the conductor pattern should be positioned away from the split end face. However, the effect of reducing burrs and foreign matters was not so great only by implementing such improvement of the substrate surface pattern shape.

さらに調べてみると、図7に示すようにバリ18や導体異物は、スルーホ−ル印刷の際に付着した基板表面に回り込んだ貫通孔端部周辺の導体膜17上に形成された、ニッケルメッキおよび金メッキから主として生じており、ことに導体パターンを印刷後分割溝を形成させたときに発生しやすいことがわかった。これは、導体が溝の凹形に変形しているため、メッキの密着性が悪くなっていることがあり、さらにメッキ時には凸部により多くメッキの金属が付着しやすくなるので、基板面と貫通孔との角の部分に他の部分より多くの軟質な金属が存在することになることも原因していることがわかってきた。分割によるバリの発生、あるいは金属片の分離は、ほとんどがここに起因しているのである。   Upon further examination, as shown in FIG. 7, the burrs 18 and the conductive foreign matter are formed on the conductive film 17 around the end of the through-hole that wraps around the surface of the substrate attached during through-hole printing. It has been found that it is mainly generated from plating and gold plating, and in particular, it is likely to occur when dividing grooves are formed after printing a conductor pattern. This is because the conductor is deformed into the concave shape of the groove, so that the adhesion of the plating may be deteriorated, and more plating metal tends to adhere to the convex part at the time of plating. It has been found that this is also caused by the presence of more soft metal in the corners of the holes than in other parts. The generation of burrs due to division or separation of metal pieces is mostly caused by this.

そこで、特許文献2あるいは3に示されているように、貫通孔の分割位置には導体膜を印刷しないようにして、キャスタレーションを形成させてみた。たとえば図8(A)に示すように、貫通孔6の分割溝7のある部分には、導体ペーストが塗布されない形状の印刷マスク19として、スルーホール印刷をおこなう。この場合、貫通孔内における導体膜の形状は、図8(B)に示すキャスタレーション4のように縦方向の帯状となるが、配線基板集合体の上面の分割位置または分割溝7上には導体メッキは存在せず、バリや導体異物の発生は抑止できる。   Therefore, as shown in Patent Document 2 or 3, the castellation was formed without printing the conductor film at the through hole division positions. For example, as shown in FIG. 8A, through-hole printing is performed on a portion of the through hole 6 where the dividing groove 7 is present as a printing mask 19 having a shape to which no conductor paste is applied. In this case, the shape of the conductor film in the through hole is a vertical band like the castellation 4 shown in FIG. 8 (B). There is no conductor plating, and the generation of burrs and foreign conductors can be suppressed.

しかしながら、セラミックパッケージの場合、キャスタレーションは電気的接続だけでなく、はんだによる固定の機能も必要とする。たとえば前出図4のセラミックパッケージをマザープリント回路板などにはんだで接合した場合のキャスタレーション部分の断面を模式的に示した図からわかるように、パッケージ配線基板底面の端子パッド8と共にキャスタレーション4にも、同時にはんだ16を付着させてメニスカスを形成させ、マザープリント回路板14の接続ランド15との接合をより強固にしている。   However, in the case of a ceramic package, the castellation requires not only an electrical connection but also a fixing function by solder. For example, as can be seen from the diagram schematically showing the cross-section of the castellation portion when the ceramic package of FIG. 4 is joined to a mother printed circuit board by soldering, the castellation 4 together with the terminal pads 8 on the bottom surface of the package wiring board. At the same time, the solder 16 is attached to form a meniscus so that the bonding of the mother printed circuit board 14 to the connection land 15 is further strengthened.

ところがキャスタレーションの導体膜の形状が図8(B)の4に見られるように狭くなると、はんだの濡れ面積が減少し、固定のための強度が十分確保できなくなる。またこの場合、配線基板集合体上の導体パターンは、いずれもそれぞれ電気的に独立したものとなっているが、導体膜に電解メッキをおこなうとき、メッキの効率を高めるには、同一貫通孔にて隣接する導体パターンは相互に接続されている方が好ましい。   However, when the shape of the conductor film of the castellation becomes narrow as seen in 4 of FIG. 8B, the solder wet area decreases, and sufficient strength for fixing cannot be secured. Also, in this case, the conductor patterns on the wiring board assembly are all electrically independent, but when performing electroplating on the conductor film, the same through-hole can be used to increase the plating efficiency. The adjacent conductor patterns are preferably connected to each other.

本発明の要旨は次のとおりである。
(1) 側壁に上面の導体部が下方に接続される導体膜を備えたキャスタレーションを有する電子部品収納用セラミックパッケージを作製するための配線基板集合体であって、分割後パッケージのキャスタレーションとなる導体膜を内壁に装着した貫通孔を有し、貫通孔内壁の導体膜は、貫通孔内では接続しているが貫通孔下部では分割予定位置から離れており、かつ下面の貫通孔導体膜に接続して外部接続端子となる導体パターンが、集合体の分割予定位置から離れていることを特徴とするセラミックパッケージ集合体。
The gist of the present invention is as follows.
(1) A wiring board assembly for producing a ceramic package for storing electronic components having a castellation provided with a conductor film having a conductor film connected to a lower surface on a side wall, the caster A conductive film on the inner wall, the conductive film on the inner wall of the through hole is connected in the through hole, but is separated from the planned division position in the lower part of the through hole, and the through hole conductive film on the lower surface A ceramic package assembly characterized in that a conductor pattern that is connected to and serves as an external connection terminal is separated from a predetermined division position of the assembly.

(2) 配線基板部が2層以上からなり、キャスタレーションとなる貫通孔内面の導体膜が、上側の層では内壁面全面にあり、最下層では分割予定位置から離れ、かつ下面の導体パターンが分割予定位置もしくは分割用溝から離れていることを特徴とする上記(1)のセラミックパッケージ集合体。   (2) The wiring board part consists of two or more layers, and the conductor film on the inner surface of the through-hole that becomes the castellation is on the entire inner wall surface in the upper layer, away from the planned division position in the lowermost layer, and the conductor pattern on the lower surface The ceramic package assembly according to the above (1), wherein the ceramic package assembly is separated from a predetermined dividing position or a dividing groove.

(3) 上記(1)または(2)のセラミック配線基板集合体を分割したことを特徴とする電子部品収納用セラミックパッケージ。   (3) A ceramic package for storing electronic parts, wherein the ceramic wiring board assembly according to (1) or (2) is divided.

本発明の配線基板集合体は、電子部品が搭載されるセラミック製配線基板の製造において、その集合体を分割して個々の配線基板とするとき、バリや導体異物の発生が抑止され、電子回路の品質向上に有効である。さらに、この集合体から得られた基板あるいはこの基板を用いたセラミックパッケージは、マザープリント回路板などへはんだで接続固定されるときに十分な接続強度を得ることができる。   In the production of a ceramic wiring board on which electronic components are mounted, when the wiring board assembly of the present invention is divided into individual wiring boards, the generation of burrs and conductive foreign matter is suppressed, and the electronic circuit It is effective for improving the quality. Furthermore, a substrate obtained from this assembly or a ceramic package using this substrate can obtain sufficient connection strength when connected and fixed to a mother printed circuit board or the like with solder.

本発明のセラミックパッケージ用配線基板集合体は、分割後キャスタレーションとなる導体膜を内壁に備えた貫通孔を有し、下面の外部接続用端子パッドとなる導体パターン端は集合体の分割予定位置から離れ、かつこれらと装荷電子部品等の接続端子に接続する貫通孔内壁の導体膜は下面においてはその分割予定位置から離れ、上部では接続しているものである。   The wiring substrate assembly for a ceramic package of the present invention has a through-hole having a conductor film that becomes a castellation after division on the inner wall, and the end of the conductor pattern that becomes a terminal pad for external connection on the lower surface is a planned division position of the assembly The conductor film on the inner wall of the through hole connected to the connection terminal of the loaded electronic component or the like is separated from the scheduled division position on the lower surface and connected on the upper portion.

セラミックパッケージの配線基板集合体は、たとえば、上面から見ると図2(B)、下面から見ると図3(B)に示すような形態をしていて、配線基板層9の上面には電子回路部品素子を接続するための導体パターン3があり、その導体パターンは貫通孔内面の導体膜4と接続しており、これが配線基板層9下面の導体パターン8すなわち外部接続用端子パッドに接続されている。この貫通孔6は分割され個々のセラミックパッケージとなったとき、パッケージ内の導体と外部回路とを接続するキャスタレーション4を形成する。   The wiring substrate assembly of the ceramic package has, for example, a form as shown in FIG. 2B when viewed from the upper surface and as shown in FIG. 3B when viewed from the lower surface, and an electronic circuit is formed on the upper surface of the wiring substrate layer 9. There is a conductor pattern 3 for connecting the component elements, and the conductor pattern is connected to the conductor film 4 on the inner surface of the through hole, and this is connected to the conductor pattern 8 on the lower surface of the wiring board layer 9, that is, the external connection terminal pad. Yes. When this through hole 6 is divided into individual ceramic packages, a castellation 4 is formed to connect a conductor in the package and an external circuit.

この下面導体パターンとそれに接続する貫通孔内面の導体膜の形状を、一例として下面を上にした図1に示すようなものであることとする。すなわち、下面の導体パターン8はその端部が分割用溝など分割予定位置から離れており、この導体パターンに接続する貫通孔の導体膜4は、下面および貫通孔の下部(図1では上面および上部)では分割予定位置より離れているが、貫通孔の上方(図1では下方)では内面の導体膜が一体となっており接続している。このような表面導体パターンおよび貫通孔内壁の導体膜形状とすることにより、分割時のバリの発生や導体異物の発生が抑制される。 The shape of the lower surface conductor pattern and the conductor film on the inner surface of the through-hole connected to the lower surface conductor pattern is as shown in FIG. That is, the end of the conductor pattern 8 on the lower surface is separated from the planned dividing position such as a dividing groove, and the conductor film 4 of the through hole connected to this conductor pattern is formed on the lower surface and the lower portion of the through hole (in FIG. In the upper part, the conductor film on the inner surface is integrated and connected above the through hole (lower part in FIG. 1). By using such a surface conductor pattern and the shape of the conductor film on the inner wall of the through hole, the generation of burrs and the occurrence of conductive foreign objects during division are suppressed.

さらに、貫通孔周辺の導体パターンが相互に接続、たとえば図2(B)または図3(B)においては4個または2個の導体パターンが接続されていることにより、電解メッキが容易になり、加えて、配線基板キャスタレーションの導体膜部分の面積が大きくなり、マザープリント回路など外部の回路板にはんだにて接続固定する場合、十分な固定用ランドを提供できる。   Furthermore, the conductive patterns around the through holes are connected to each other, for example, in FIG. 2 (B) or FIG. 3 (B), four or two conductive patterns are connected, thereby facilitating electrolytic plating. In addition, the area of the conductor film portion of the wiring board castellation is increased, and a sufficient fixing land can be provided when connecting and fixing to an external circuit board such as a mother printed circuit with solder.

貫通孔内面の導体膜を図1に示すような形状にするには、配線基板を2層以上の積層とするのがよい。その場合下面側(図1では上面側)の第1層20は貫通孔内面の導体を、図8に示したような縦方向の帯状のものとし、その下の第2層21は、第1層と同じ位置に貫通孔を設け、その貫通孔は内面全面に導体膜を印刷したものとする。この第1層と第2層とを重ねて配線基板とすれば、貫通孔下面での分割位置に金属導体は存在せず、導体パターンは貫通孔内で接続しており、かつ形成されたキャスタレーションは、十分な面積のはんだ用ランドを有するものとすることができる。   In order to form the conductor film on the inner surface of the through hole as shown in FIG. 1, the wiring board is preferably formed of two or more layers. In this case, the first layer 20 on the lower surface side (the upper surface side in FIG. 1) has a conductor on the inner surface of the through hole as a vertical belt as shown in FIG. 8, and the second layer 21 below the first layer 20 A through hole is provided at the same position as the layer, and the through hole has a conductor film printed on the entire inner surface. If the first layer and the second layer are overlapped to form a wiring board, there is no metal conductor at the dividing position on the lower surface of the through hole, the conductor pattern is connected in the through hole, and the caster formed The solder can have a solder land with a sufficient area.

配線基板部分の回路が2層以上の場合には、上記の方法にて容易に目的の貫通孔内導体形状にすることができるが、1層でよい配線基板であっても、上記形状の貫通孔内部導体とするために2層とするのがよい。また、配線基板の回路が3層以上の場合、第3層以上の層にも最下面の第1層および次の第2層と同じ位置に貫通孔を設け、内壁全面に導体を装着させるのが好ましいが、はんだによる接続および固定が十分できるのであれば、第3層以上の層における貫通孔内壁の導体はなくてもよい。   When the circuit of the wiring board portion has two or more layers, it can be easily formed into the desired shape of the conductor in the through-hole by the above method. In order to make the hole inner conductor, two layers are preferable. In addition, when the circuit of the wiring board has three or more layers, a through-hole is provided in the same position as the first layer and the second layer on the lowermost surface in the third and higher layers, and a conductor is attached to the entire inner wall. However, the conductor on the inner wall of the through hole in the third and higher layers may be omitted as long as the connection and fixing by solder can be sufficiently performed.

このように最下面の導体パターンの端部を分割位置から離し、キャスタレーションの下面に近い最下部にて分割位置に導体が存在しないようにする導体パターンおよび貫通孔内導体の形状は、配線基板の下面のみならず上面にも適用できる。   As described above, the shape of the conductor pattern and the conductor in the through hole is such that the end portion of the conductor pattern on the lowermost surface is separated from the division position and no conductor exists at the division position in the lowermost portion near the lower surface of the castellation. The present invention can be applied not only to the lower surface but also to the upper surface.

図9に本発明のパッケージの下面を上にして示した場合を例示する。蓋体を接着する枠体上面の導体と、下面の外部接続用端子パッドとを接続する場合、図4左側に示したように枠体内にビア11を設けてもよいが、図9のキャスタレーション部に導体膜22として示したように、枠体表面部の貫通孔内導体を下面の場合と同様にしたキャスタレーションにして接続してもよい。   FIG. 9 illustrates a case where the lower surface of the package of the present invention is shown upward. When connecting the conductor on the upper surface of the frame to which the lid is bonded and the external connection terminal pad on the lower surface, vias 11 may be provided in the frame as shown on the left side of FIG. As shown as the conductor film 22 in the portion, the conductor in the through hole on the surface of the frame body may be connected by a castellation similar to the case of the lower surface.

本発明の一実施形態であるセラミック配線基板集合体の、下面導体パターンおよびその導体パターンに接続する貫通孔内壁の導体膜形状を示すため、分割面を手前にして模式的に示した斜視図である。FIG. 2 is a perspective view schematically showing a divided surface facing forward in order to show a lower surface conductor pattern and a conductor film shape of an inner wall of a through hole connected to the conductor pattern of a ceramic wiring board assembly according to an embodiment of the present invention. is there. セラミック配線基板集合体、およびそれから分割して得られるパッケージ用配線基板を上面から見た模式図である。It is the schematic diagram which looked at the ceramic wiring board aggregate | assembly and the wiring board for packages obtained by dividing | segmenting from it from the upper surface. セラミック配線基板集合体、およびそれから分割して得られるパッケージ用配線基板を下面から見た模式図である。It is the schematic diagram which looked at the ceramic wiring board aggregate | assembly and the wiring board for packages obtained by dividing | segmenting it from the lower surface. セラミックパッケージをマザープリント回路板などに、はんだで接合した場合のキャスタレーション部分の断面を模式的に示した図である。It is the figure which showed typically the cross section of the castellation part at the time of joining a ceramic package to a mother printed circuit board etc. with the solder. セラミック配線基板の製造工程を示す図である。It is a figure which shows the manufacturing process of a ceramic wiring board. 下面から見たセラミックパッケージ集合体のキャスタレーションとなる貫通孔周辺の、導体膜の状態を説明する図である。It is a figure explaining the state of the conductor film of the periphery of the through-hole used as the castellation of the ceramic package aggregate | assembly seen from the lower surface. 配線基板集合体を分割したときのバリの発生を説明する図である。It is a figure explaining generation | occurrence | production of the burr | flash when a wiring board aggregate | assembly is divided | segmented. 分割位置に導電ペーストを付着させないスルーホール印刷を説明する図である。It is a figure explaining through-hole printing which does not make a conductive paste adhere to a division position. 本発明のセラミックパッケージの1例を下面側から見た図である。It is the figure which looked at one example of the ceramic package of this invention from the lower surface side.

符号の説明Explanation of symbols

1 セラミックパッケージ基板部 2 セラミックパッケージ枠体部
3 導体パターン 4 キャスタレーションまたは貫通孔内導 体膜
5 枠体上面導体膜 6 貫通孔
7 分割用溝 8 外部接続用端子パッド(下面導体パタ ーン)
9 集合体配線基板層 10 集合体枠体層
11 枠体内ビア 12 電子部品素子
13 蓋体 14 マザープリント回路板
15 回路板接続ランド 16 はんだ
17 貫通孔端部周辺導体膜 18 バリ
19 印刷用マスク 20 配線基板用第一層
21 配線基板用第二層 22 上面導体接続用導体膜
DESCRIPTION OF SYMBOLS 1 Ceramic package board | substrate part 2 Ceramic package frame part 3 Conductor pattern 4 Conductor film in castellation or through-hole 5 Frame body upper surface conductor film 6 Through-hole 7 Dividing groove 8 External connection terminal pad (lower surface conductor pattern)
DESCRIPTION OF SYMBOLS 9 Assembly wiring board layer 10 Assembly frame body layer 11 Via in frame 12 Electronic component element 13 Lid body 14 Mother printed circuit board 15 Circuit board connection land 16 Solder 17 Through-hole edge peripheral conductor film 18 Burr 19 Printing mask 20 First layer 21 for wiring board Second layer for wiring board 22 Conductor film for upper surface conductor connection

Claims (3)

側壁に上方の導体部が下方に接続される導体膜を備えたキャスタレーションを有する電子部品収納用セラミックパッケージを作製するための配線基板集合体であって、分割後パッケージのキャスタレーションとなる導体膜を内壁に装着した貫通孔を有し、貫通孔内壁の導体膜は、貫通孔内では接続しているが貫通孔下部では分割予定位置から離れており、かつ下面の貫通孔導体膜に接続して外部接続端子となる導体パターンが集合体の分割予定位置から離れていることを特徴とするセラミックパッケージ集合体。   A wiring board assembly for producing a ceramic package for housing an electronic component having a castellation provided with a conductor film having an upper conductor portion connected to a lower side on a side wall, the conductor film serving as a castellation of a package after division The conductor film on the inner wall of the through hole is connected in the through hole, but is separated from the planned division position in the lower part of the through hole, and connected to the through hole conductor film on the lower surface. A ceramic package assembly characterized in that a conductor pattern serving as an external connection terminal is separated from a scheduled division position of the assembly. 配線基板部が2層以上からなり、キャスタレーションとなる貫通孔内面の導体膜が、上側の層では内壁面全面にあり、最下層では分割予定位置から離れ、かつ下面の導体パターンが分割予定位置もしくは分割用溝から離れていることを特徴とする請求項1に記載のセラミックパッケージ集合体。   The wiring board part consists of two or more layers, and the conductor film on the inner surface of the through-hole that becomes the castellation is on the entire inner wall surface in the upper layer, away from the planned division position in the lowermost layer, and the conductive pattern on the lower surface is the planned division position 2. The ceramic package assembly according to claim 1, wherein the ceramic package assembly is separated from the dividing groove. 請求項1または2に記載のセラミック配線基板集合体を分割したことを特徴とする電子部品収納用セラミックパッケージ。

A ceramic package for storing electronic components, wherein the ceramic wiring board assembly according to claim 1 or 2 is divided.

JP2004177799A 2004-06-16 2004-06-16 Ceramic package assembly for storing electronic component and ceramic package Pending JP2006005035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004177799A JP2006005035A (en) 2004-06-16 2004-06-16 Ceramic package assembly for storing electronic component and ceramic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004177799A JP2006005035A (en) 2004-06-16 2004-06-16 Ceramic package assembly for storing electronic component and ceramic package

Publications (1)

Publication Number Publication Date
JP2006005035A true JP2006005035A (en) 2006-01-05

Family

ID=35773171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004177799A Pending JP2006005035A (en) 2004-06-16 2004-06-16 Ceramic package assembly for storing electronic component and ceramic package

Country Status (1)

Country Link
JP (1) JP2006005035A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009010103A (en) * 2007-06-27 2009-01-15 Ngk Spark Plug Co Ltd Multiple patterning ceramic substrate
JP2013239559A (en) * 2012-05-15 2013-11-28 Denso Corp Method for manufacturing multilayer circuit board
WO2018216693A1 (en) * 2017-05-23 2018-11-29 京セラ株式会社 Multi-piece wiring substrate, electronic component housing package, and electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021594A (en) * 1983-07-15 1985-02-02 株式会社東芝 Method of producing circuit board
JPH01261884A (en) * 1988-04-13 1989-10-18 Matsushita Electric Ind Co Ltd Conductor pattern for through hole printing
JPH1126639A (en) * 1997-07-09 1999-01-29 Ngk Spark Plug Co Ltd Wiring board aggregate and wiring boards obtd. therefrom
JP2002232099A (en) * 2001-01-31 2002-08-16 Kyocera Corp Ceramic circuit board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021594A (en) * 1983-07-15 1985-02-02 株式会社東芝 Method of producing circuit board
JPH01261884A (en) * 1988-04-13 1989-10-18 Matsushita Electric Ind Co Ltd Conductor pattern for through hole printing
JPH1126639A (en) * 1997-07-09 1999-01-29 Ngk Spark Plug Co Ltd Wiring board aggregate and wiring boards obtd. therefrom
JP2002232099A (en) * 2001-01-31 2002-08-16 Kyocera Corp Ceramic circuit board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009010103A (en) * 2007-06-27 2009-01-15 Ngk Spark Plug Co Ltd Multiple patterning ceramic substrate
JP2013239559A (en) * 2012-05-15 2013-11-28 Denso Corp Method for manufacturing multilayer circuit board
WO2018216693A1 (en) * 2017-05-23 2018-11-29 京セラ株式会社 Multi-piece wiring substrate, electronic component housing package, and electronic device
CN110612780A (en) * 2017-05-23 2019-12-24 京瓷株式会社 Multi-connection wiring board, package for housing electronic component, and electronic device
JPWO2018216693A1 (en) * 2017-05-23 2020-03-19 京セラ株式会社 Multi-cavity wiring board, electronic component storage package, and electronic device
CN110612780B (en) * 2017-05-23 2022-04-19 京瓷株式会社 Multi-connection wiring board, package for housing electronic component, and electronic device

Similar Documents

Publication Publication Date Title
JP5100081B2 (en) Electronic component-mounted multilayer wiring board and manufacturing method thereof
US9082550B2 (en) Electronic component
JP5333680B2 (en) Component built-in substrate and manufacturing method thereof
US10014111B2 (en) Substrate terminal mounted electronic element
JPH0936549A (en) Printed board for bare chip mounting use
US20100032196A1 (en) Multilayer wiring board, semiconductor package and method of manufacturing the same
JPWO2012056879A1 (en) Module substrate and module substrate manufacturing method
JP2009194079A (en) Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same
WO2006112337A1 (en) Semiconductor device and semiconductor device manufacturing method
JP2004158595A (en) Circuit device, circuit module, and method for manufacturing circuit device
JP2005252227A (en) Film substrate, and the manufacturing method and image display substrate
JP5383407B2 (en) Multi-wiring board
JP2012209590A (en) Electronic component mounting multilayer wiring board and manufacturing method of the same
JP2006339277A (en) Substrate for connection and manufacturing method thereof
JP4708915B2 (en) Manufacturing method of encapsulated printed circuit board
JP2006253247A (en) Flexible printed wiring board and its manufacturing method
JP2006005035A (en) Ceramic package assembly for storing electronic component and ceramic package
JP2013145847A (en) Printed wiring board and manufacturing method of the same
JP2005197648A (en) Method for manufacturing a circuit board wired by electroplating
JP2006202870A (en) Three-dimensional electronic circuit module, its manufacturing method, and electronic apparatus using them
JPH1092968A (en) Semiconductor bare chip mounting board
JP2848346B2 (en) Electronic component mounting method
JP4749165B2 (en) Multi-wiring board
JP2003224356A (en) Printed wiring board with edge face cut through-hole and electronic component
JP6366509B2 (en) Electronic component and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070417

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070731

A131 Notification of reasons for refusal

Effective date: 20100324

Free format text: JAPANESE INTERMEDIATE CODE: A131

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100907