JP2006004226A - Data arithmetic unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data arithmetic unit suitable for improving the processing efficiency of a processor and reducing a program cost and a manufacturing cost. <P>SOLUTION: A data arithmetic part 12 comprises a register file composed of a plurality of registers and a computing element 202 performing operation by use of data of the register file 200. The data access between the register file 200 and a data memory 10 is performed in a group register unit consisting of four registers. The data arithmetic unit further comprises an index register file 208 storing, in case that two group registers are grouped as a register block, element index data designating the position of data in the register block, and selectors 204 and 206 selectively outputting, based on the element index data of the index register file 208, data of any one register among the registers of the register block to the computing element 202. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to an apparatus and method for calculating data, and more particularly to a data calculation apparatus suitable for improving the processing efficiency of a processor and reducing program cost and manufacturing cost.

When digital signal processing is performed by a processor, a plurality of data may be collectively read or written by one data access to the memory. This occurs, for example, when data having a long word length is required by the arithmetic unit, or when parallel processing is performed by the arithmetic unit in order to improve processing efficiency.
The 32-bit RISC processor configures a group register by grouping registers each having a storage capacity of 1 byte (8 bits) in units of four, and data access between the register file and the memory is performed in units of group registers (units of four bytes). To do. For the memory, 4 bytes of data are collectively read into the group register with an address that is an integer multiple of 4 as the start address, and the group register data is collectively written with an address that is an integer multiple of 4 as the start address. For example, when reading data sequentially from the beginning of the memory, the group register reads the data at addresses 0000h to 0003h at the first data access and the data at addresses 0004h to 0007h at the second data access. It is.

  When performing such data access, a problem arises when the top address of the data on the memory is not an integral multiple of the access unit of the processor. This situation is called boundary-misaligned data access because the address boundary of data on the memory (hereinafter referred to as data boundary) does not match the address boundary accessible by the processor (hereinafter referred to as access boundary). .

A problem caused by boundary misaligned data access can be a reduction in processing efficiency. For a 32-bit RISC processor, the access boundary is an integer multiple of four. When processing data of 4 bytes length, data of 4 bytes length is read from the memory, but if the head address of the data is not a multiple of 4, two data accesses are required to obtain the desired 4 bytes. Further, since the rearrangement is performed by software, the processing efficiency is lowered. In order to solve such a problem, in the RISC processor program, all data is arranged so that the data boundary and the access boundary coincide with each other at the time of compilation, so that the unaligned data access does not occur at the time of execution. .
However, if the logical structure of data overlaps, the compiler cannot handle it.

FIG. 10 is a diagram showing the arrangement of data on the memory.
In FIG. 10, the memory stores 16 bytes of data s [0] to s [15] at addresses 0000h to 000Fh, and 16 bytes of data r [0] to addresses 0100h to 010Fh. r [15] is stored.
The logical structure of data is duplicated. S [0] to s [3] constitute one group data, but s [1] to s [4] and s [2] to s [5] And s [3] to s [6] also constitute one group data. For example, when performing a correlation operation as shown in the following equations (1) to (4), it is not possible to avoid boundary misaligned data access.

p [0] = r [0] * s [0] + r [1] * s [1] + r [2] * s [2] + r [3] * s [3] +… (1)
p [1] = r [0] * s [1] + r [1] * s [2] + r [2] * s [3] + r [3] * s [4] +… (2)
p [2] = r [0] * s [2] + r [1] * s [3] + r [2] * s [4] + r [3] * s [5] +… (3)
p [3] = r [0] * s [3] + r [1] * s [4] + r [2] * s [5] + r [3] * s [6] +… (4)

In addition, four programs must be created.
First, to obtain p [0], the program includes the following steps (1) to (5). The same applies to p [4], p [8], ..., p [4n].
(1) Read s [0] to s [3] into the group register.
(2) to (5) Based on the group register data, r [0] * s [0], r [1] * s [1], r [2] * s [2], r [3] * Calculate s [3].

Next, to obtain p [1], the program includes the following steps (1) to (6). The same applies to p [5], p [9],..., p [4n + 1].
(1) Read s [0] to s [3] into the group register.
(2) to (4) Calculate r [0] * s [1], r [1] * s [2], r [2] * s [3] based on the data in the group register.
(5) Read s [4] to s [7] into the group register.
(6) Calculate r [3] * s [4] based on the group register data.

Next, to obtain p [2], the program includes the following steps (1) to (6). The same applies to p [6], p [10],..., p [4n + 2].
(1) Read s [0] to s [3] into the group register.
(2), (3) Calculate r [0] * s [2] and r [1] * s [3] based on the group register data.
(4) Read s [4] to s [7] into the group register.
(5), (6) Calculate r [2] * s [4] and r [3] * s [5] based on the group register data.

Next, to obtain p [3], the program includes the following steps (1) to (6). The same applies to p [7], p [11], ..., p [4n + 3].
(1) Read s [0] to s [3] into the group register.
(2) Calculate r [0] * s [3] based on the group register data.
(3) Read s [4] to s [7] into the group register.
(4) to (6) r [1] * s [4], r [2] * s [5], and r [3] * s [6] are calculated based on the group register data.

  As described above, when the logical structure of the data overlaps, boundary-aligned data access occurs, so that the processing efficiency is reduced, and the program cost (the time required for creating the program, the data capacity and complexity of the program) is reduced. There is a problem that increases. In order to solve such problems, digital signal processors described in Patent Document 1 and Non-Patent Document 1 have been proposed.

FIG. 11 is a block diagram showing the configuration of a conventional digital signal processor.
As shown in FIG. 11, the invention described in Patent Document 1 and Non-Patent Document 1 includes a register file 200 and a data alignment buffer 900 that aligns data, and the register file is transferred from the data memory 10 via the data alignment buffer 900. 200 reads the data.
Data alignment buffer 900 includes an alignment buffer 910 and a multiplexer / barrel shifter 912.

The multiplexer / barrel shifter 912 receives 64 bits of data including 32 bits from the data memory 10 and 32 bits from the output of the alignment buffer 910, and in response to a given offset signal, 32 of the 64 bits of data. A bit is selected as its input, and the selected 32-bit data is supplied to the register file 200.
The data alignment buffer 900 can be used for boundary aligned data access (referring to a situation where the data boundary matches the access boundary) and boundary unaligned data access. In aligned data access, a specified operand is supplied to the register file 200 from a single memory line via the multiplexer / barrel shifter 912. In boundary misaligned data access, the specified operand is supplied to the register file 200 from two memory lines via the alignment buffer 910 and the multiplexer / barrel shifter 912.

FIG. 12 is a diagram for explaining the operation of a conventional digital signal processor.
In FIG. 12, the data memory 10 stores 8-byte data s [0] to s [7] at addresses 0000h to 0007h.
When performing boundary misalignment data access for reading s [1] to s [4], first, s [0] to s [3] are read into the alignment buffer 910. Next, for example, as shown in FIG. 12A, when an offset signal indicating “0” is given to the multiplexer / barrel shifter 912, data selection is performed by the multiplexer / barrel shifter 912, and s [1] is stored in the register file 200. ~ S [4] is supplied.

Further, when performing boundary misalignment data access for reading s [2] to s [5], for example, as shown in FIG. 12B, an offset signal indicating “1” is given to the multiplexer / barrel shifter 912. The multiplexer / barrel shifter 912 selects data, and s [2] to s [5] are supplied to the register file 200.
Further, when performing boundary misalignment data access for reading s [3] to s [6], for example, as shown in FIG. 12C, an offset signal indicating “2” is given to the multiplexer / barrel shifter 912. The multiplexer / barrel shifter 912 selects data, and s [3] to s [6] are supplied to the register file 200.
Japanese translation of PCT publication No. 2002-509912 “ADSP-TS201 TigerSHARCR Processor Programming Reference” Analog Devices, Inc., Revision 0.1, June 2003, Part Number 82-000810-01, p. 7-24

However, in the inventions described in Patent Document 1 and Non-Patent Document 1, it is necessary to provide an alignment buffer 910 having a storage capacity (32 bits in the example of FIG. 11) corresponding to at least a processor access unit. There was a problem that the cost increased.
In the example of FIG. 12, three boundary misaligned data access patterns are shown. However, if only these three access patterns are supported, the offset signal may be 2 bits. However, for example, when trying to support other access patterns such as boundary misaligned data access for reading s [0], s [1], s [4], and s [5], the number of bits of the offset signal is further increased. There is a problem that the manufacturing cost increases. Incidentally, in the example of FIG. 12, since there are ₈ C ₄ −2 = 68 total access patterns for boundary misaligned data access, 7 bits are required for the offset signal in order to support all access patterns.
Therefore, the present invention has been made paying attention to such an unsolved problem of the conventional technology, and is suitable for improving the processing efficiency of the processor and reducing the program cost and the manufacturing cost. The object is to provide an arithmetic device.

  In order to achieve the above object, a data operation device according to claim 1 according to the present invention comprises: a register file comprising a plurality of registers; and an arithmetic unit that performs an operation using data in the register, wherein the register file A data arithmetic unit that performs data access between a register and an external unit in a group register unit including a plurality of registers, the index file storing index data, and the register file based on the index data of the index register And a selector that selects data of one or a plurality of the registers from at least two of the group registers and outputs the selected data to the arithmetic unit.

  With such a configuration, first, a data group that may cause boundary-unaligned data access is collectively read into at least two group registers. When the index data is stored in the index register, the selector selects one or a plurality of register data from the group register based on the index data of the index register and outputs the selected data to the arithmetic unit. Is done. Therefore, if index data storage, selection by the selector, and calculation by the arithmetic unit are repeated, data necessary for the calculation is sequentially selected from the group of data read in the group register and output to the arithmetic unit. The Which data is used for the calculation can be selected by the index data, so that it is possible to handle the group data for boundary aligned data access and the group data for boundary unaligned data access without distinction. That is, for group data to be boundary aligned data access, data may be selected in order from the first register of the group register, and for group data to be boundary unaligned data access, a register at a predetermined position of the group register You can select the data in order.

Here, the selector may have any configuration as long as it can select data of one or a plurality of registers. For example, when selecting data of a plurality of registers, the selector is continuous in the group register. The data of the registered registers may be used, or the data of the registers distributed in the group register may be used.
The index register stores the index data by any means and at any time. The index register may store the index data in advance, or without storing the index data in advance. The index data may be stored by an external input or the like during operation.

  Furthermore, the data operation device according to claim 2 according to the present invention includes a register file composed of a plurality of registers, and an arithmetic unit that performs an operation using the data of the register, and the data operation device between the register file and the outside A data operation device that performs data access in units of a group register composed of a plurality of registers, wherein when at least two of the group registers of the register file are grouped as a register block, An index register for storing element index data for designating a position of data; and based on the element index data of the index register, the data of any one of the registers is selected from the registers of the register block, and the arithmetic unit Out And a selector that.

  With such a configuration, first, a data group that may cause a boundary misaligned data access is collectively read into the register of the register block. When the element index data is stored in the index register, the selector selects one register data from the register block registers based on the element index data in the index register, and outputs the selected register data to the arithmetic unit. The calculation is performed by the instrument. Therefore, if the element index data is stored, the selection by the selector, and the operation by the arithmetic unit are repeated, the data necessary for the operation is sequentially selected from the data group read together in the register of the register block, and the operation unit is selected. Is output. Which data is used for the calculation can be selected by the index data, so that it is possible to handle the group data for boundary aligned data access and the group data for boundary unaligned data access without distinction. That is, for group data to be boundary aligned data access, data may be selected in order from the first register of the group register, and for group data to be boundary unaligned data access, a register at a predetermined position of the group register You can select the data in order.

Here, grouping of the group registers may be performed physically or logically. In the former case, for example, in the register file, the group register belonging to the register block and the other registers can be configured separately. Hereinafter, the same applies to the data calculation method according to the seventh aspect.
The index register stores element index data at any time and at any time, and may store element index data in advance, or without storing element index data in advance. The element index data may be stored by an external input or the like when the apparatus is operating.

  Furthermore, the data operation device according to claim 3 according to the present invention is the data operation device according to claim 2, wherein the data operation device is further based on an index register file including a plurality of the index registers and given select data. A second selector that selects element index data of any one of the index registers from the index register file and outputs the selected element index data to the selector.

  In such a configuration, when the select data is given, the element index data of any one of the index registers is selected from the index register file by the second selector and output to the selector, and is input by the selector. Based on the element index data, the data in one of the registers in the register block is selected and output to the computing unit.

Furthermore, the data operation device according to claim 4 according to the present invention is the data operation device according to claim 3, wherein the index data update further updates the element index data output to the selector and stores it in the index register file Means.
With such a configuration, the index data update means updates the element index data output to the selector and stores it in the index register file.

  Furthermore, the data operation device according to claim 5 of the present invention is the data operation device according to any one of claims 2 to 4, further comprising bundle index data specifying the register block. In addition, based on the given bundle index data and the element index data of the index register, the register block specified by the bundle index data and the second element index data indicating the position of the data in the register block are generated. Index data generating means for performing the processing, and the selector selects one of the registers of the plurality of register blocks based on the second element index data generated by the index data generating means. And outputs to the operation unit to select other data.

  In such a configuration, when bundle index data is given, a register block designated by the bundle index data and its register block based on the given bundle index data and element index data by the index data generating means Second element index data indicating the position of the data within is generated. Then, based on the generated second element index data, the selector selects one register data from the registers of the plurality of register blocks and outputs the selected register data to the arithmetic unit.

  Furthermore, the data operation device according to claim 6 of the present invention is the data operation device according to claim 5, wherein the index data generation means uses two or more first predetermined number of group registers as the register block. A bundle that designates one of a first bundle mode for grouping and a second bundle mode for logically grouping a second predetermined number of group registers larger than the first predetermined number as the register block When the mode data is given, the second element index data is generated based on the given bundle mode data, the bundle index data, and the element index data.

With such a configuration, when bundle mode data designating either the first bundle mode or the second bundle mode is given, the given bundle mode data, bundle index data, and elements are given by the index data generating means. Second element index data is generated based on the index data.
On the other hand, in order to achieve the above object, a data operation method according to claim 7 according to the present invention includes a register file including a plurality of registers, and an arithmetic unit that performs an operation using data of the registers, A data operation method for performing an operation using a data operation device that performs data access between a register file and the outside in units of a group register composed of a plurality of registers, wherein at least two of the registers of the register file When the group register is grouped as a register block, a data reading step for reading data from the outside into each group register of the register block, and element index data for designating the position of the data in the register block in the index register Index data to store A storage step; a data selection step of selecting data of any one of the registers from the registers of the register block based on element index data of the index register; and outputting the data to the computing unit; and And a calculation step for performing a calculation.
Furthermore, the data operation method according to claim 8 of the present invention is the data operation method according to claim 7, further comprising an iterative operation step of repeatedly performing the index data storage step, the data selection step, and the operation step. .

  As described above, according to the data operation device of the first aspect of the present invention, even when boundary unaligned data access occurs or when the logical structure of data overlaps, the data of the register file is stored. Since the number of readings does not increase extremely, an effect that the processing efficiency can be improved is obtained. In addition, even when the logical structure of data is duplicated, it is possible to cope with a slight change in the program, so that an effect of reducing the program cost can be obtained. Furthermore, it is only necessary to provide an index register and a selector, and even when dealing with many boundary-unaligned data access patterns, it is not necessary to increase the number of bits of the index data. And the effect that manufacturing cost can be reduced is also acquired.

  Furthermore, according to the data operation device of the second aspect of the present invention, the number of times data is read into the register file is extremely small even when boundary-aligned data access occurs or when the logical structure of data is duplicated. Therefore, there is an effect that the processing efficiency can be improved. In addition, even when the logical structure of data is duplicated, it is possible to cope with a slight change in the program, so that an effect of reducing the program cost can be obtained. Furthermore, it is only necessary to provide an index register and a selector, and even when dealing with many boundary-unaligned data access patterns, it is not necessary to increase the number of bits of the element index data. In comparison, the manufacturing cost can be reduced.

Furthermore, according to the data arithmetic device according to claim 3 of the present invention, a plurality of element index data can be stored in the index register file, and the element index data can be selectively used by the select data. As a result, it is possible to improve the usability of the index register and to facilitate the creation of a program.
Furthermore, according to the data operation device of claim 4 according to the present invention, since the element index data is automatically updated every time it is used, it is not necessary to update the element index data by software, and the operation speed is increased. The effect that it can improve is acquired.

Furthermore, according to the data arithmetic device according to claim 5 of the present invention, when there are a plurality of register blocks in the register file, the register blocks can be selectively used by the bundle index data. Usability is improved, and it is easy to create a program.
Furthermore, according to the data arithmetic device according to claim 6 of the present invention, since the logical structure of the register block can be changed by the bundle mode data, the usability of the register is further improved, and the program can be more easily created. The effect is obtained.

  On the other hand, according to the data operation method of the seventh aspect of the present invention, even if the logical structure of data is duplicated, it is possible to cope with a slight change in the program, so that the program cost can be reduced. The effect that it is possible is also acquired. Furthermore, it is only necessary to use an index register, and even when dealing with many boundary-unaligned data access patterns, it is not necessary to increase the number of bits of element index data so much, compared with the invention described in Patent Document 1. And the effect that manufacturing cost can be reduced is also acquired.

  Furthermore, according to the data operation method of the present invention, the number of times data is read into the register file is extremely small even when boundary-aligned data access occurs or when the logical structure of data overlaps. Therefore, there is an effect that the processing efficiency can be improved.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1 to 6 are diagrams showing a first embodiment of a data arithmetic device according to the present invention.
In this embodiment, as shown in FIG. 1, the data operation device according to the present invention is applied to the data operation unit 12 in a 32-bit RISC type digital signal processing device 100 that performs digital signal processing.

First, the configuration of the digital signal processing apparatus 100 will be described with reference to FIG.
FIG. 1 is a block diagram illustrating a hardware configuration of the digital signal processing apparatus 100.
As shown in FIG. 1, the digital signal processing apparatus 100 includes a data memory 10 that stores data for calculation, a data calculation unit 12 that reads data from the data memory 10 and performs calculation, and a data address of the data memory 10. A data address generation unit 14 to be generated, a program memory 16 that stores a control program for the entire digital signal processing device 100, and a program sequencer 18 that controls the entire digital signal processing device 100 based on the control program in the program memory 16. Has been. The data memory 10, the data operation unit 12, the data address generation unit 14, and the program sequencer 18 are connected to each other via a bus 20 that is a signal line for transferring data, and the program memory 16 is a program sequencer. 18 is directly connected.

The data memory 10 stores data to be calculated by the data calculation unit 12 and calculation result data of the data calculation unit 12. Further, the value of a register in the data address generation unit 14 or the program sequencer 18 may be stored.
The data operation unit 12 performs data access to the data memory 10 in units of 4 bytes using an address (0000h, 0004h, 0008h, 000Ch...) That is an integer multiple of 4 as an access boundary. Hereinafter, the access boundary of the data operation unit 12 is referred to as a group address.

  The data address generation unit 14 generates a data address necessary for executing data transfer between the data memory 10 and the data calculation unit 12, the data address generation unit 14, or the program sequencer 18. Further, a signal for controlling the data memory 10 is generated in accordance with the generation of the data address. These operations are defined by control signals from the program sequencer 18.

FIG. 2 shows the data structure of the data address.
Data address, as shown in FIG. 2 consists of m bits of data, constitutes a accessible address memory space of 2 ^m bytes minimum storage unit of the data memory 10 as a byte by one byte. In the data address, upper (m−2) bits b _m−1 ,..., B ₂ constitute a group address, and lower 2 bits b ₁ and b ₀ constitute a subdivided address between group addresses.

More specifically, the data address generation unit 14 has a plurality of pointer registers, outputs a group address among the data addresses to the data memory 10, and outputs lower 2 bits of the data address to the data operation unit 12, respectively. To do.
Returning to FIG. 1, the program sequencer 18 reads the control program from the program memory 16, and controls the data memory 10, the data calculation unit 12, the data address generation unit 14, the program memory 16, and the program sequencer 18 according to the read control program. . A control signal is output via the bus 20 to the data memory 10, the data calculation unit 12, and the data address generation unit 14, and the program memory 16 directly outputs the control signal.

Next, the configuration of the data calculation unit 12 will be described in detail with reference to FIGS. 3 and 4.
FIG. 3 is a block diagram illustrating a hardware configuration of the data calculation unit 12.
As shown in FIG. 3, the data operation unit 12 includes a register file 200 composed of a plurality of registers, a calculator 202 that performs operations using data in the register file 200, and a selector that selects data from the register file 200. 204, 206, an index register file 208 composed of a plurality of index registers, selectors 210, 212 for selecting data from the index register file 208, a calculator 214 for updating data in the index register file 208, and a calculator And a selector 216 for selecting data on the bus 20.

The register file 200 includes n group registers R _{0 to} R _n−1 . The group register R ₀ includes four registers R ₀ [0] to R ₀ [3], and each register R ₀ [0] to R ₀ [3] has a storage capacity of 1 byte. The other group registers R _{1 to} R _n-1 have the same configuration.
The selector 204 connects the group registers R ₀ and R ₁ as the register block A to each register of the register block A, and selects one of the registers of the register block A based on the select data from the selector 210. Data is selected, and the selected data is output to the computing unit 202 as the first operand of the computing unit 202.

The select data from the selector 210 consists of 3 bits. When the most significant bit of the select data is “0”, the selector 204 selects the data of the register designated by the value of the lower 2 bits of the group register R ₀ . That is, when the select data is “000”, the data in the register R ₀ [0] is stored. When the select data is “001”, the data in the register R ₀ [1] is stored. When the select data is “010”, the register R ₀ [ ₀ ] is displayed. When the data in [2] is “011”, the data in the register R ₀ [3] is selected. When the most significant bit of the select data is “1”, the register data designated by the value of the lower 2 bits of the group register R ₁ is selected. In other words, the select data is the data of "100" when it is the register R ₁ [0], the data of "101" at which time the register R ₁ [1], "110" when it is the register R ₁ [ When the data of 2] is “111”, the data of the register R ₁ [3] is selected.

The selector 206 connects the group registers R ₂ and R ₃ as the register block B to each register of the register block B, and selects one of the registers of the register block B based on the select data from the selector 212. Data is selected, and the selected data is output to the computing unit 202 as the second operand of the computing unit 202. The data selection procedure is the same as that of the selector 204.
The index register file 208 stores element index data in each index register.

FIG. 4 is a diagram showing the data structure of element index data.
As shown in FIG. 4, the element index data is composed of 3-bit data. The most significant bit b ₂ indicates the group register R ₀ , R ₁ (R ₂ , R ₃ ), and the lower 2 bits b ₁ , b ₀ indicates the group register. Each bit of the element index data corresponds to each bit of the select data from the selectors 210 and 212. The lower 2 bits b _1, b ₀ of the element index data corresponds to the lower 2 bits b _1, b ₀ of the data address.

  Returning to FIG. 3, the selector 210 selects element index data of any one of the index registers from the index register file 208 based on the select data from the program sequencer 18 and outputs the selected element index data to the selector 204. When the program sequencer 18 executes an instruction code that controls the selector 210, the program sequencer 18 outputs an operand corresponding to the instruction code to the selector 210 as select data.

  The selector 212 selects element index data of any one of the index registers from the index register file 208 based on the select data from the program sequencer 18 and outputs it to the selector 206. When the program sequencer 18 executes an instruction code that controls the selector 212, the program sequencer 18 outputs an operand corresponding to the instruction code to the selector 212 as select data.

  The calculator 214 updates the element index data output as select data from the selector 210 or the selector 212 and outputs it to the selector 216. The element index data is updated so that the data can be selected in that order when the order of obtaining the data from the registers of the register blocks A and B is determined in advance. For example, when data is continuously selected from the head direction to the tail direction of the register blocks A and B, the data is updated by adding “1” to the element index data. When data is continuously selected from the tail direction to the head direction, the data is updated by subtracting “1” from the element index data.

  Based on the select data from the program sequencer 18, the selector 216 selects either the lower 2 bits of the data address from the data address generator 14 or the element index data from the calculator 214. Store in the index register file 208. Note that when the instruction code for controlling the selector 216 is executed, the program sequencer 18 outputs an operand corresponding to the instruction code to the selector 216 as select data.

Next, the operation of the present embodiment will be described with reference to FIGS.
First, the case where the digital signal processing apparatus 100 performs the correlation calculation shown in the above equation (1) will be described. However, it is assumed that s [n] and r [n] are stored in the data memory 10 as shown in FIG.
FIG. 5 is a flowchart showing processing executed by the program sequencer 18.
In the program sequencer 18, the control program is read from the program memory 16, and the correlation calculation processing shown in the flowchart of FIG. 5 is executed in the order of steps S100 to S150 in accordance with the read control program.

  In step S100, when the instruction code for setting the data address of r [0] in the pointer register P0 is executed, the data address generator 14 stores the group address in the data address of r [0] in the pointer register P0. Is done. In the data operation unit 12, the lower 2 bits of the data address of r [0] are stored in the index register file 208. Since the lower 2 bits of the data address of r [0] are “00”, the most significant bit is “0” and 3-bit data “000” is stored as element index data r.

  In step S102, when an instruction code for setting the data address of s [0] in the pointer register P1 is executed, the data address generator 14 stores the group address in the data address of s [0] in the pointer register P1. Is done. In the data operation unit 12, the lower 2 bits of the data address of s [0] are stored in the index register file 208. Since the lower 2 bits of the data address of s [0] are “00”, the most significant bit is “0” and 3-bit data “000” is stored as element index data s.

In step S104, the instruction code to initialize the contents of the register A0 (either Group Register R ₄ ~R _n-1) is executed, the data calculating unit 12, "0" is set in the register A0 .
In step S108, when the instruction code for reading the data of the group address indicated by the pointer register P1 into the group register _R0 is executed, the data operation unit 12 stores s [0] to s [3] from the data memory 10 into the group register. Read into _R0 .

In step S110, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, s [4] that is 4 bytes ahead is indicated.
In step S112, when the instruction code read data of the group address pointer register P1 pointed to the group registers R ₁ is executed, the data calculating unit 12, s [4] from the data memory 10 ~s [7] is Group Register It is loaded into R _1.

In step S114, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, s [8] that is 4 bytes ahead is indicated.
At step S116, the instruction code reads data group address pointer register P0 pointed to a group register R ₂ is executed, the data calculating unit 12, r [0] from the data memory 10 ~r [3] is Group Register It is loaded into R _2.
In step S118, when the instruction code for adding the pointer register P0 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P0. On the data memory 10, it points to r [4] 4 bytes ahead.

In step S120, when an instruction code for calculating the register data of the register blocks A and B (hereinafter referred to as a block operation instruction code) is executed, the data operation unit 12 is based on the select data from the program sequencer 18. The element index data s “000” is selected by the selector 210 and outputted to the selector 204, and the data s [0] of the register R ₀ [0] is selected by the selector 204 and outputted to the computing unit 202. Further, based on the select data from the program sequencer 18, the element index data r “000” is selected by the selector 212 and output to the selector 206, and the selector 206 outputs the data r [0] of the register R ₂ [0]. Is selected and output to the computing unit 202. Then, s [0] and r [0] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the first term of the above equation (1) is obtained. Further, “1” is added to the element index data s and r by the calculator 214 and stored in the index register file 208.

In step S122, when the block operation instruction code is further executed, the data operation unit 12 selects the element index data s “001” by the selector 210 based on the select data from the program sequencer 18 and selects the selector 204. The selector 204 selects the data s [1] of the register R ₀ [1] and outputs it to the computing unit 202. Further, based on the select data from the program sequencer 18, the element index data r “001” is selected by the selector 212 and output to the selector 206, and the selector 206 outputs the data r [1] of the register R ₂ [1]. Is selected and output to the computing unit 202. The computing unit 202 multiplies s [1] and r [1], adds the multiplication result to the value of the register A0, and stores the result in the register A0. Thereby, the calculation results of the first term and the second term of the above formula (1) are obtained. Further, “1” is added to the element index data s and r by the calculator 214 and stored in the index register file 208.

At step S124, the further the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₀ [2], data of _{R 2 [2] s [2} ], r [2] is selected. Then, s [2] and r [2] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 3rd term of the above formula (1) is obtained.

In step S126, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₀ [3], the data s of _{R 2 [3] [3]} , Each r [3] is selected. Then, s [3] and r [3] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 4th term of the above formula (1) is obtained.

In step S128, when an instruction code for reading the data of the group address indicated by the pointer register P1 into the group register _R0 is executed, the data operation unit 12 stores s [8] to s [11] from the data memory 10 into the group register. Read into _R0 .
In step S130, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, s [12] that is 4 bytes ahead is indicated.

In step S132, when the instruction code read data group address pointer register P0 pointed to a group register R ₃ is executed, the data calculating unit 12, r [4] from the data memory 10 ~r [7] is Group Register It is loaded into R _3.
In step S134, when the instruction code for adding the pointer register P0 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P0. On the data memory 10, it points to r [7] 4 bytes ahead.

In step S136, when the block operation instruction code is executed, the data operation unit 12 similarly uses the selectors 204 and 206 to store the data s [4] and r [[] in the registers R ₁ [0] and R ₃ [0]. 4] is selected respectively. Then, s [4] and r [4] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation results of the first to fifth terms of the above equation (1) are obtained.

In step S138, when the block operation instruction code is further executed, the data operation unit 12 similarly uses the selectors 204 and 206 to store the data s [5], Rs [1], R3 [1] in the registers R ₁ [1], R ₃ [1]. r [5] is selected. Then, s [5] and r [5] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 6th term of the above formula (1) is obtained.

In step S140, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₁ [2], data s of _{R 3 [2] [6]} , Each r [6] is selected. Then, s [6] and r [6] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 7th term of the above formula (1) is obtained.

In step S142, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₁ [3], the data s [7] of R ₃ [3], Each r [7] is selected. Then, s [7] and r [7] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 8th term of the above formula (1) is obtained.

In step S144, when the instruction code read data of the group address pointer register P1 pointed to the group registers R ₁ is executed, the data calculating unit 12, s [12] from the data memory 10 ~s [15] is Group Register It is loaded into R _1.
In step S146, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, it points to s [16] 4 bytes ahead.

In step S148, when the instruction code read data group address pointer register P0 pointed to a group register R ₂ is executed, the data calculating unit 12, r [8] from the data memory 10 ~r [11] is Group Register It is loaded into R _2.
In step S150, when the instruction code for adding the pointer register P0 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P0. On the data memory 10, it points to r [12] 4 bytes ahead.
In the following, the processes in steps S120 to S150 may be repeated as many times as necessary.

Next, the case where the digital signal processing apparatus 100 performs the correlation calculation shown in the above equation (2) will be described. However, it is assumed that s [n] and r [n] are stored in the data memory 10 as shown in FIG.
FIG. 6 is a flowchart showing processing executed by the program sequencer 18.
In the program sequencer 18, the control program is read from the program memory 16, and the correlation calculation processing shown in the flowchart of FIG. 6 is executed in the order of steps S200 to S250 in accordance with the read control program.

In step S200, the same process as step S100 is executed.
In step S202, when the instruction code for setting the data address of s [1] in the pointer register P1 is executed, the data address generation unit 14 stores the group address in the data address of s [1] in the pointer register P1. Is done. Further, in the data operation unit 12, the lower 2 bits of the data address of s [1] are stored in the index register file 208. Since the lower 2 bits of the data address of s [1] are “01”, the most significant bit is “0” and 3-bit data “001” is stored as element index data s.

In steps S204 to S218, the same processing as in steps S104 to S118 is executed.
In step S220, when the block operation instruction code is executed, the data operation unit 12 selects the element index data s “001” by the selector 210 based on the select data from the program sequencer 18 and outputs it to the selector 204. Then, the selector 204 selects the data s [1] of the register R ₀ [1] and outputs it to the computing unit 202. Further, based on the select data from the program sequencer 18, the element index data r “000” is selected by the selector 212 and output to the selector 206, and the selector 206 outputs the data r [0] of the register R ₂ [0]. Is selected and output to the computing unit 202. Then, s [1] and r [0] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the first term of the above equation (2) is obtained. Further, “1” is added to the element index data s and r by the calculator 214 and stored in the index register file 208.

In step S222, when the block operation instruction code is further executed, the data operation unit 12 selects the element index data s “010” by the selector 210 based on the select data from the program sequencer 18 and selects the selector 204. The selector 204 selects the data s [2] of the register R ₀ [2] and outputs it to the computing unit 202. Further, based on the select data from the program sequencer 18, the element index data r “001” is selected by the selector 212 and output to the selector 206, and the selector 206 outputs the data r [1] of the register R ₂ [1]. Is selected and output to the computing unit 202. Then, s [2] and r [1] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation results of the first term and the second term of the above equation (2) are obtained. Further, “1” is added to the element index data s and r by the calculator 214 and stored in the index register file 208.

In step S224, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₀ [3], the data s of _{R 2 [2] [3]} , r [2] is selected. Then, s [3] and r [2] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 3rd term of the above formula (2) is obtained.

In step S226, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₁ [0], data s of _{R 2 [3] [4]} , Each r [3] is selected. The computing unit 202 multiplies s [4] and r [3], adds the multiplication result to the value of the register A0, and stores the result in the register A0. Thereby, the calculation result of the 1st term-the 4th term of the above formula (2) is obtained.

In steps S228 to S234, the same processing as steps S128 to S134 is executed.
In step S236, when the block operation instruction code is executed, the data operation unit 12 similarly uses the selectors 204 and 206 to cause the data s [5] and r [[] in the registers R ₁ [1] and R ₃ [0]. 4] is selected respectively. Then, s [5] and r [4] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation results of the first to fifth terms of the above equation (2) are obtained.

In step S238, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₁ [2], data s of _{R 3 [1] [6]} , r [5] is selected. Then, s [6] and r [5] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 6th term of the above formula (2) is obtained.

In step S240, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₁ [3], the data s [7] of R ₃ [2], Each r [6] is selected. Then, s [7] and r [6] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation results of the first to seventh terms of the above equation (2) are obtained.

In step S242, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₀ [0], the data s [8] of R ₃ [3], Each r [7] is selected. Then, s [8] and r [7] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 8th term of the above formula (2) is obtained.

In steps S244 to S250, the same processing as steps S144 to S150 is executed.
In the following, the processes in steps S220 to S250 may be repeated as many times as necessary.
As described above, what is different from the case where the correlation calculation shown in the above equation (1) is performed is the processing of steps S202, S220 to S226, and S236 to S242, but the control program of the program sequencer 18 is described in step S202. Only the difference. The same applies to the case where the correlation calculation shown in the above equations (3) and (4) is performed.

Thus, in this embodiment, a register file 200 composed of a plurality of group registers R _{0 to} R _n−1 , an arithmetic unit 202 that performs an operation using the data of the register file 200, and element index data are stored. And two group registers R ₀ , R ₁ (R ₂ , R ₃ ) as register blocks based on the index register to be registered and the element index data of the index register, the registers R ₀ [0] to R ₁ [3] of the register block Selectors 204 and 206 that select data from any one of the registers (R ₂ [0] to R ₃ [3]) and output the selected data to the computing unit 202 are provided.

  As a result, the number of times data is read into the register file 200 does not increase extremely even when boundary misaligned data access occurs or when the logical structure of data overlaps, thereby improving processing efficiency. Can do. In addition, even when the logical structure of data is duplicated, it can be handled by a slight change in the program, so that the program cost can be reduced. Furthermore, it is only necessary to provide index registers and selectors 204 and 206, and even when dealing with many patterns of boundary-unaligned data access, it is not necessary to increase the number of bits of element index data. Compared to the invention, the manufacturing cost can be reduced.

Further, in the present embodiment, element index data of any one of the index registers is selected from the index register file 208 based on the index register file 208 composed of a plurality of index registers and the given select data. Selectors 210 and 212 that output to the selectors 204 and 206 are provided.
As a result, a plurality of element index data can be stored in the index register file 208, and the element index data can be selectively used by the select data, thereby improving the usability of the index register and making it easy to create a program. Become.

Furthermore, the present embodiment includes a calculator 214 that updates the element index data output to the selectors 204 and 206 and stores it in the index register file 208.
As a result, since the element index data is automatically updated every time it is used, the element index data need not be updated by software, and the calculation speed can be improved.

  In the first embodiment, the element index data corresponds to the index data according to claims 1 to 4 or 7, the selectors 204 and 206 correspond to the selector according to claims 1 to 4, and the selectors 210, 212 corresponds to the second selector according to claim 3, and the calculator 214 corresponds to the index data update means according to claim 4.

Next, a second embodiment of the present invention will be described with reference to the drawings. 7 to 9 are diagrams showing a second embodiment of the data arithmetic device according to the present invention.
In the present embodiment, the data arithmetic device according to the present invention is applied to the data arithmetic unit 12 in the 32-bit RISC type digital signal processing device 100 that performs digital signal processing. The difference is that the number of group registers included in the register block is dynamically changed. Hereinafter, only the parts different from the first embodiment will be described, and the same parts as those in the first embodiment will be denoted by the same reference numerals and the description thereof will be omitted.

Next, the configuration of the data calculation unit 12 will be described in detail with reference to FIGS.
FIG. 7 is a block diagram illustrating a hardware configuration of the data calculation unit 12.
As shown in FIG. 7, the data calculation unit 12 includes a register file 200, a calculator 202, selectors 224 and 226 that select data from the register file 200, and an index register file 228 including a plurality of index registers. , Selectors 230 and 232 for selecting data from the index register file 228, a calculator 234 for updating data in the index register file 228, and a selector 236 for selecting data on the calculator 234 and the bus 20. Yes.

FIG. 8 is a diagram illustrating a configuration of a register block.
In the present embodiment, bundle mode 0 for grouping one group register as one register block, bundle mode 1 for grouping two group registers as one register block, and one register for four group registers. A bundle mode 2 for grouping as a block and a bundle mode 3 for grouping eight group registers as one register block are defined.

In the bundle mode 0, as shown in FIG. 8, the group register R ₀ is set as a register block 0 (referred to as a register block specified by a bundle number “0”, hereinafter abbreviated in the same manner). R _{2 to} R ₇ are grouped as register blocks 1 to 7, respectively.
In the bundle mode 1, the group registers R ₀ and R ₁ are the register block 0, the group registers R ₂ and R ₃ are the register block 1, the group registers R ₄ and R ₅ are the register block 2, and the group registers R ₆ and R ₇ is grouped as a register block 3 respectively.

In the bundle mode 2, the group registers R _{0 to} R ₃ are grouped as the register block 0 and the group registers R _{4 to} R ₇ are grouped as the register block 1, respectively.
In the bundle mode 3, the group registers R _{0 to} R ₇ are grouped as a register block 0, respectively.
Returning to FIG. 7, the selector 224 is connected to each of the registers of the group registers R _{0 to} R ₇ , and based on the select data from the selector 230, the data in any one of the group registers R _{0 to} R _7. And the selected data is output to the computing unit 202 as the first operand of the computing unit 202.

The select data from the selector 230 consists of 5 bits. When the upper 3 bits of the select data is “000”, the selector 224 selects the register data specified by the lower 2 bits of the group register R ₀ , and the upper 3 bits of the select data is “001”. when "a selects the data of the register specified by the lower two bits of the value of the group registers R _1. Similarly, when the upper 3 bits of the select data are “010”, “011”, “100”, “101”, “110” and “111”, the lower 2 bits of the group registers R _{2 to} R ₇ Select the register data specified by the value of.

The selector 226 is connected to the respective registers of the group registers R ₀ to R _7, based on the select data from the selector 232 selects the data of one of the registers from among Group Register R ₀ to R _7, selected The obtained data is output to the computing unit 202 as the second operand of the computing unit 202. The data selection procedure is the same as that of the selector 224.
The index register file 228 stores element index data in each index register.

FIG. 9 is a diagram illustrating a data structure of element index data.
As shown in FIG. 9, the element index data consists of 5-bit data. In the bundle mode 0, the lower 2 bits of the 5 bits are used, and the lower 2 bits b ₁ and b ₀ are stored in the group registers. Indicates the different register.
In the bundle mode 1, the lower 3 bits of the 5 bits are used, the upper third bit b ₂ indicates the group register R ₀ , R ₁ (R ₂ , R _3, etc.), and the lower 2 bits b ₁ and b ₀ indicate the group registers.

In the bundle mode 2, the lower 4 bits of the 5 bits are used, and the upper and second bits b ₃ and b ₂ indicate the group registers R _{0 to} R ₃ (R _{4 to} R ₇ ). The lower 2 bits b ₁ and b ₀ indicate the group registers.
In the bundle mode 3, the first to third bits b _{4 to} b ₂ indicate the group registers R _{0 to} R ₇ , and the lower two bits b ₁ and b ₀ indicate the group registers. . Each bit of the element index data corresponds to each bit of select data from the selectors 230 and 232. The lower 2 bits b _1, b ₀ of the element index data corresponds to the lower 2 bits b _1, b ₀ of the data address.

  Returning to FIG. 7, the selector 230 selects element index data of any one of the index registers from the index register file 228 based on the select data from the program sequencer 18, and selects the selected element index data and the program sequencer. Register index data is generated based on the bundle mode data and bundle index data from 18, and the generated register index data is output to the selector 224.

  The bundle index data is 5-bit data indicating the bundle number. When bundle mode data indicating the bundle mode 0 is given, the lower 3 bits of the bundle index data are combined as the upper bits, the lower 2 bits of the selected element index data are combined as the lower bits, and the 5-bit register index data is Generate and output.

When bundle mode data indicating bundle mode 1 is given, the lower 2 bits of the bundle index data are combined as the upper bits, the lower 3 bits of the selected element index data are combined as the lower bits, and the 5-bit register index data is Generate and output.
When bundle mode data indicating the bundle mode 2 is given, the lower 1 bit of the bundle index data is combined as the upper bit, the lower 4 bits of the selected element index data is combined as the lower bit, and the 5-bit register index data is Generate and output.

When bundle mode data indicating the bundle mode 3 is given, the selected element index data is output as register index data as it is.
When the program sequencer 18 executes an instruction code for controlling the selector 230, the program sequencer 18 outputs an operand corresponding to the instruction code to the selector 230 as select data. When an instruction code for setting a bundle mode or bundle number is executed, an operand corresponding to the instruction code is output to the selector 230 as bundle mode data or bundle index data.

  The selector 232 selects element index data of any one of the index registers from the index register file 228 based on the select data from the program sequencer 18, and selects the selected element index data and the bundle mode from the program sequencer 18. Register index data is generated based on the data and bundle index data, and the generated register index data is output to the selector 226. The register index data generation procedure is the same as that of the selector 230. When the instruction code for controlling the selector 232 is executed, the program sequencer 18 outputs an operand corresponding to the instruction code to the selector 232 as select data. When an instruction code for setting a bundle mode or a bundle number is executed, an operand corresponding to the instruction code is output to the selector 232 as bundle mode data or bundle index data.

  The calculator 234 updates the register index data output as select data from the selector 230 or the selector 232 and outputs it to the selector 236. The register index data is updated so that data can be selected in the order in which the data acquisition order is determined in advance from the register of the register block. The procedure for updating the register index data can be performed in the same manner as the procedure for updating the element index data by the calculator 214 in the first embodiment.

  Based on the select data from the program sequencer 18, the selector 236 selects either the lower 2 bits of the data address from the data address generator 14 or the register index data from the calculator 234. Store in the index register file 228. When the instruction code for controlling the selector 236 is executed, the program sequencer 18 outputs an operand corresponding to the instruction code to the selector 236 as select data.

Next, the operation of the present embodiment will be described.
First, a case where calculation is performed in the bundle mode 1 will be described.
In the program sequencer 18, when the instruction code set to the bundle mode 1 is executed, bundle mode data indicating the bundle mode 1 is output to the data calculation unit 12. When the instruction code for setting the bundle number “0” is executed, “00000” is output to the data operation unit 12 as bundle index data.

In the data operation unit 12, when bundle mode data and bundle index data are given, the element index data is selected by the selectors 230 and 232, and the selected element index data and the given bundle mode data and bundle index data are selected. Based on this, register index data is generated and output to the selectors 224 and 226. At this time, since the lower 2 bits of the bundle index data are “00”, “00xxx” (“x” indicates the bit of the selected element index data. Hereinafter, the same is expressed) is output as the register index data. Is done. Then, based on the given register index data “00xxx” by the selectors 224 and 226, the data of any _one of the group registers R ₀ and R ₁ is selected and output to the arithmetic unit 202.

Since the selection data given to the selectors 230 and 232 is different, the selection by the selectors 224, 226, 230, and 232 is performed independently.
In the program sequencer 18, when the instruction code for setting the bundle number “1” is executed, “00001” is output to the data operation unit 12 as bundle index data.

In the data operation unit 12, since the lower 2 bits of the bundle index data are “01”, the selectors 230 and 232 generate and output “01xxx” as the register index data. Then, based on the given register index data “01xxx” by the selectors 224 and 226, the data of any one of the group registers R ₂ and R ₃ is selected and output to the computing unit 202.
The same applies to the case where the instruction code for setting the bundle number “2” or “3” is executed, and the data of any one register is selected from among the group registers R ₄ and R ₅ or R ₆ and R _7. To the calculator 202.

Next, a case where calculation is performed in the bundle mode 2 will be described.
In the program sequencer 18, when an instruction code set to the bundle mode 2 is executed, bundle mode data indicating the bundle mode 2 is output to the data calculation unit 12. When the instruction code for setting the bundle number “0” is executed, “00000” is output to the data operation unit 12 as bundle index data.

In the data operation unit 12, when bundle mode data and bundle index data are given, since the lower 1 bit of the bundle index data is “0”, the selectors 230 and 232 generate and output “0xxxx” as register index data. . Then, based on the given register index data “0xxxx” by the selectors 224 and 226, the data of any one of the group registers R _{0 to} R ₃ is selected and output to the arithmetic unit 202.

In the program sequencer 18, when the instruction code for setting the bundle number “1” is executed, “00001” is output to the data operation unit 12 as bundle index data.
In the data operation unit 12, since the lower 1 bit of the bundle index data is “1”, “1xxxx” is generated and output as register index data by the selectors 230 and 232. Then, the selectors 224 and 226 select the data of any one of the group registers R _{4 to} R ₇ based on the given register index data “1xxx” and output the selected data to the arithmetic unit 202.

Next, a case where calculation is performed in the bundle mode 3 will be described.
In the program sequencer 18, when the instruction code set to the bundle mode 3 is executed, bundle mode data indicating the bundle mode 3 is output to the data calculation unit 12.
In the data operation unit 12, when bundle mode data is given, the selector 230 and 232 output the selected element index data as it is as register index data. Then, the selectors 224 and 226 select data of any one of the group registers R _{0 to} R ₇ based on the given register index data, and output the selected data to the arithmetic unit 202.

Next, a case where calculation is performed in the bundle mode 0 will be described.
In the program sequencer 18, when the instruction code to set the bundle mode 0 is executed, bundle mode data indicating the bundle mode 0 is output to the data calculation unit 12. When the instruction code for setting the bundle number “0” is executed, “00000” is output to the data operation unit 12 as bundle index data.

In the data operation unit 12, when bundle mode data and bundle index data are given, since the lower 3 bits of the bundle index data are “000”, the selectors 230 and 232 generate and output “000xx” as register index data. . Then, based on the given register index data “000xx” by the selectors 224 and 226, the data of any one register is selected from the group register R ₀ and output to the computing unit 202.

The same applies to the case where the instruction code for setting the bundle numbers “1” to “7” is executed, and any of the group registers R ₁ , R ₂ , R ₃ , R ₄ , R ₅ , R ₆ or R ₇ is selected. Data in one register is selected and output to the computing unit 202.
In this way, in this embodiment, when bundle index data specifying a register block is given, it is designated by the bundle index data based on the given bundle index data and the element index data of the index register. Selectors 230 and 232 for generating register index data indicating the register block to be processed and the position of data in the register block.

As a result, a plurality of register blocks can be selectively used according to the bundle index data, thereby improving the usability of the registers and facilitating the creation of a program.
Furthermore, in this embodiment, when the bundle mode data indicating the bundle mode is given, the selectors 230 and 232 select the register index data based on the given bundle mode data, bundle index data, and element index data. It is designed to generate.
Thereby, the logical structure of the register block can be changed by the bundle mode data, so that the usability of the register is further improved and the program can be more easily created.

In the second embodiment, the selectors 224 and 226 correspond to the selector described in claim 5, the selectors 230 and 232 correspond to the index data generation means described in claim 5 or 6, and the register index data is , Corresponding to the second element index data.
In the first embodiment, the group registers R ₀ and R ₁ are grouped as the register block A. However, the present invention is not limited to this, and two specific group registers may be grouped as the register block A. So it can be grouped in other combinations. The same applies to the register block B.

In the first embodiment, the index register file 208 is provided. However, the present invention is not limited to this, and only one index register may be provided. In this case, the selectors 210 and 212 are also unnecessary.
In the second embodiment, the index register file 228 is provided. However, the present invention is not limited to this, and only one index register may be provided. In this case, the selectors 230 and 232 need not have a selection function, but only a function for generating register index data.

In the second embodiment, the register block is configured using the eight group registers R _{0 to} R _7. However, the present invention is not limited to this, and the register block is configured using less than eight group registers. It is also possible to configure a register block using nine or more group registers. The number of bits of bundle index data and element index data is, for example, 3 bits each when a register block is configured using two group registers, and 4 bits when each register block is configured using four group registers. When a register block is configured by using 16 bits and 16 group registers, it is sufficient to have 5 bits each. In either case, the same procedure as in the second embodiment can be performed.

In the second embodiment, a register block is configured using eight group registers R _{0 to} R ₇ and four bundle modes are set. However, the present invention is not limited to this, and the number of bundle modes is less than four. May be set as In this case, the number of bits of the bundle index data is 4 bits when three bundle modes 0 to 2 are set, 3 bits when two bundle modes 0 and 1 are set, and only one bundle mode 0 is set. In this case, only 2 bits are required. This is the same even when the number of group registers used in the configuration of the register block is less than 8 and when it is 9 or more.

  In the first and second embodiments, the data calculation unit 12 is provided with one calculation unit 202. However, the present invention is not limited to this, and the data calculation unit 12 is provided with a plurality of calculation units 202. It can also be configured. In the case of the first embodiment, selectors 204, 206, 210, and 212 may be provided for each computing unit 202. In the case of the second embodiment, selectors 224, 226, 230, and 232 may be provided for each computing unit 202.

  In the first and second embodiments, the selectors 210 and 230 that output the element index data or the register index data to the selectors 204 and 224, and the element index data or the register index data are output to the selectors 206 and 226. However, the present invention is not limited to this, and the selectors 210 and 224 are not provided, and the selectors 204 and 224 can be selected from the register file 200 based on select data from the program sequencer 18. Alternatively, the data of one register can be selected. Also, the selectors 212 and 232 are not provided, and the selectors 206 and 226 can be configured to select data of any one register from the register file 200 based on the select data from the program sequencer 18. .

The operation of the latter configuration without the selectors 212 and 232 will be described with the aid of the correlation calculation process shown in the flowchart of FIG.
In step S100, when the instruction code for setting the data address of r [0] in the pointer register P0 is executed, the data address generator 14 stores the group address in the data address of r [0] in the pointer register P0. Is done.

  In step S102, when an instruction code for setting the data address of s [0] in the pointer register P1 is executed, the data address generator 14 stores the group address in the data address of s [0] in the pointer register P1. Is done. In the data operation unit 12, the lower 2 bits of the data address of s [0] are stored in the index register file 208. Since the lower 2 bits of the data address of s [0] are “00”, the most significant bit is “0” and 3-bit data “000” is stored as element index data s.

In step S104, when an instruction code for initializing the contents of the register A0 is executed, the data operation unit 12 sets “0” in the register A0.
In step S108, when the instruction code for reading the data of the group address indicated by the pointer register P1 into the group register _R0 is executed, the data operation unit 12 stores s [0] to s [3] from the data memory 10 into the group register. Read into _R0 .

In step S110, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, s [4] that is 4 bytes ahead is indicated.
In step S112, when the instruction code read data of the group address pointer register P1 pointed to the group registers R ₁ is executed, the data calculating unit 12, s [4] from the data memory 10 ~s [7] is Group Register It is loaded into R _1.

In step S114, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, s [8] that is 4 bytes ahead is indicated.
At step S116, the instruction code reads data group address pointer register P0 pointed to a group register R ₂ is executed, the data calculating unit 12, r [0] from the data memory 10 ~r [3] is Group Register It is loaded into R _2.
In step S118, when the instruction code for adding the pointer register P0 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P0. On the data memory 10, it points to r [4] 4 bytes ahead.

In step S 120, when the block operation instruction code is executed, the data operation unit 12 selects the element index data s “000” by the selector 210 based on the select data from the program sequencer 18 and outputs it to the selector 204. Then, the selector 204 selects the data s [0] of the register R ₀ [0] and outputs it to the computing unit 202. Further, based on the select data from the program sequencer 18, the selector 206 selects the data r [0] of the register R ₂ [0] and outputs it to the computing unit 202. Then, s [0] and r [0] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the first term of the above equation (1) is obtained. Further, “1” is added to the element index data s by the calculator 214 and stored in the index register file 208.

In step S122, when the block operation instruction code is further executed, the data operation unit 12 selects the element index data s “001” by the selector 210 based on the select data from the program sequencer 18 and selects the selector 204. The selector 204 selects the data s [1] of the register R ₀ [1] and outputs it to the computing unit 202. Further, based on the select data from the program sequencer 18, the selector 206 selects the data r [1] of the register R ₂ [1] and outputs it to the computing unit 202. The computing unit 202 multiplies s [1] and r [1], adds the multiplication result to the value of the register A0, and stores the result in the register A0. Thereby, the calculation results of the first term and the second term of the above formula (1) are obtained. Further, “1” is added to the element index data s by the calculator 214 and stored in the index register file 208.

At step S124, the further the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₀ [2], data of _{R 2 [2] s [2} ], r [2] is selected. Then, s [2] and r [2] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 3rd term of the above formula (1) is obtained.

In step S126, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₀ [3], the data s of _{R 2 [3] [3]} , Each r [3] is selected. Then, s [3] and r [3] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 4th term of the above formula (1) is obtained.

In step S128, when an instruction code for reading the data of the group address indicated by the pointer register P1 into the group register _R0 is executed, the data operation unit 12 stores s [8] to s [11] from the data memory 10 into the group register. Read into _R0 .
In step S130, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, s [12] that is 4 bytes ahead is indicated.

In step S132, when the instruction code read data group address pointer register P0 pointed to a group register R ₂ is executed, the data calculating unit 12, r [4] from the data memory 10 ~r [7] is Group Register It is loaded into R _2.
In step S134, when the instruction code for adding the pointer register P0 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P0. On the data memory 10, it points to r [7] 4 bytes ahead.

In step S136, when the block operation instruction code is executed, the data operation unit 12 similarly uses the selectors 204 and 206 to store the data s [4] and r [] in the registers R ₁ [0] and R ₂ [0]. 4] is selected respectively. Then, s [4] and r [4] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation results of the first to fifth terms of the above equation (1) are obtained.

In step S138, when the block operation instruction code is further executed, the data operation unit 12 similarly uses the selectors 204 and 206 to store the data s [5], Rs [1] and R2 [1] in the registers R ₁ [1] and R ₂ [1]. r [5] is selected. Then, s [5] and r [5] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 6th term of the above formula (1) is obtained.

In step S140, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₁ [2], data of _{R 2 [2] s [6} ], Each r [6] is selected. Then, s [6] and r [6] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 7th term of the above formula (1) is obtained.

In step S142, further, the block operation instruction code is executed, the data calculating unit 12, similarly, by the selector 204, the register R ₁ [3], the data s [7] of R ₂ [3], Each r [7] is selected. Then, s [7] and r [7] are multiplied by the arithmetic unit 202, and the multiplication result is added to the value of the register A0 and stored in the register A0. Thereby, the calculation result of the 1st term-the 8th term of the above formula (1) is obtained.

In step S144, when the instruction code read data of the group address pointer register P1 pointed to the group registers R ₁ is executed, the data calculating unit 12, s [12] from the data memory 10 ~s [15] is Group Register It is loaded into R _1.
In step S146, when the instruction code for adding the pointer register P1 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P1. On the data memory 10, it points to s [16] 4 bytes ahead.

In step S148, when the instruction code read data group address pointer register P0 pointed to a group register R ₂ is executed, the data calculating unit 12, r [8] from the data memory 10 ~r [11] is Group Register It is loaded into R _2.
In step S150, when the instruction code for adding the pointer register P0 is executed, the data operation unit 12 adds “1” to the group address of the pointer register P0. On the data memory 10, it points to r [12] 4 bytes ahead.

  In the first and second embodiments, the present invention is applied to the 32-bit RISC type digital signal processing apparatus 100. However, data access to the data memory 10 is performed in a unit larger than the minimum storage unit of the data memory 10. The present invention can be applied to any processor as long as it performs. For example, if the minimum storage unit of the data memory 10 is 1 byte, the access unit is a processor of 16 bits or more. If the minimum storage unit of the data memory 10 is 2 bytes, the processor is an access unit of 32 bits or more. is there.

  In the first embodiment, the case where the control program stored in advance in the program memory 16 is executed in the processes shown in the flowcharts of FIGS. 5 and 6 has been described. However, the program may be read from the storage medium storing the program showing these procedures into the program memory 16 and executed.

  Here, the storage medium is a semiconductor storage medium such as RAM or ROM, a magnetic storage type storage medium such as FD or HD, an optical reading type storage medium such as CD, CDV, LD, or DVD, or a magnetic storage type such as MO. / Optical reading type storage media, including any storage media that can be read by a computer regardless of electronic, magnetic, optical, or other reading methods.

  In the first and second embodiments, the data operation device according to the present invention is applied to the data operation unit 12 in the 32-bit RISC type digital signal processing device 100 that performs digital signal processing. However, the present invention can be applied to other cases without departing from the gist of the present invention.

2 is a block diagram showing a hardware configuration of a digital signal processing apparatus 100. FIG. It is a figure which shows the data structure of a data address. 2 is a block diagram illustrating a hardware configuration of a data calculation unit 12. FIG. It is a figure which shows the data structure of element index data. 3 is a flowchart showing processing executed by a program sequencer 18; 3 is a flowchart showing processing executed by a program sequencer 18; 2 is a block diagram illustrating a hardware configuration of a data calculation unit 12. FIG. It is a figure which shows the structure of a register block. It is a figure which shows the data structure of element index data. It is a figure which shows arrangement | positioning of the data on memory. It is a block diagram which shows the structure of the conventional digital signal processor. It is a figure for demonstrating operation | movement of the conventional digital signal processor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Digital signal processor 10 Data memory 12 Processor 14 Data address generation part 16 Program memory 18 Program sequencer 20 Bus 200 Register file 202 Calculator 204,206,210,212 Selector 208,228 Index register file 214,234 Calculator 216 Selector 224, 226, 230, 232 selector 236 selector

Claims (8)

Data that includes a register file composed of a plurality of registers and a computing unit that performs computation using the data of the registers, and performs data access between the register file and the outside in a group register unit composed of the plurality of registers An arithmetic unit,
An index register for storing index data;
A selector that selects data of one or a plurality of the registers from at least two of the registers of the register file based on the index data of the index register and outputs the selected data to the arithmetic unit; A data operation device characterized by the above. Data that includes a register file composed of a plurality of registers and a computing unit that performs computation using the data of the registers, and performs data access between the register file and the outside in a group register unit composed of the plurality of registers An arithmetic unit,
An index register for storing element index data for designating a position of data in the register block when grouping at least two of the group registers in the register file as a register block;
A data arithmetic device comprising: a selector that selects data of any one of the registers of the register block based on element index data of the index register and outputs the selected data to the arithmetic unit. In claim 2,
Furthermore, an index register file composed of a plurality of the index registers,
A data selector comprising: a second selector that selects element index data of any one of the index registers from the index register file based on given select data and outputs the selected element index data to the selector . In claim 3,
The data operation device further comprises index data updating means for updating the element index data output to the selector and storing it in the index register file. In any one of Claims 2 thru | or 4,
Furthermore, when bundle index data designating the register block is given, the register block designated by the bundle index data based on the given bundle index data and the element index data of the index register, and Index data generating means for generating second element index data indicating the position of data in the register block;
The selector selects data of any one of the registers from a plurality of registers of the register block based on the second element index data generated by the index data generating means, and outputs the selected data to the arithmetic unit. A data operation device characterized by that. In claim 5,
The index data generation means includes a first bundle mode for logically grouping two or more first predetermined number of the group registers as the register block, and a second predetermined number of the groups greater than the first predetermined number. When bundle mode data that designates one of the second bundle modes that logically group registers as the register block is given, the given bundle mode data, the bundle index data, and the element index data Based on this, the second element index data is generated. Data that includes a register file composed of a plurality of registers and a computing unit that performs operations using the data of the registers, and performs data access between the register file and the outside in a group register unit composed of the plurality of registers A data calculation method for performing calculation using an arithmetic device,
A data reading step of reading data from the outside to each group register of the register block when grouping at least two of the group registers of the registers of the register file as a register block;
An index data storage step of storing in the index register element index data specifying the position of data in the register block;
A data selection step of selecting data of any one of the registers from the registers of the register block based on element index data of the index register and outputting the selected data to the computing unit;
A data operation method comprising: an operation step of performing an operation by the operation unit. In claim 7,
The data calculation method further includes an iterative calculation step in which the index data storage step, the data selection step, and the calculation step are repeated.

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