JP2005539408A - 分散された多重化バスを用いる通信のための方法及び装置 - Google Patents

分散された多重化バスを用いる通信のための方法及び装置 Download PDF

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Publication number
JP2005539408A
JP2005539408A JP2003565048A JP2003565048A JP2005539408A JP 2005539408 A JP2005539408 A JP 2005539408A JP 2003565048 A JP2003565048 A JP 2003565048A JP 2003565048 A JP2003565048 A JP 2003565048A JP 2005539408 A JP2005539408 A JP 2005539408A
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Japan
Prior art keywords
bus
unit
input
side unit
coupled
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JP2003565048A
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Japanese (ja)
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JP2005539408A5 (enExample
Inventor
ジェフリー エイ エバート
ギアート ロッセル
マイケル ジェイ メイヤー
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ソニックス インコーポレイテッド
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Publication of JP2005539408A publication Critical patent/JP2005539408A/ja
Publication of JP2005539408A5 publication Critical patent/JP2005539408A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Logic Circuits (AREA)
  • Small-Scale Networks (AREA)
JP2003565048A 2002-01-29 2003-01-21 分散された多重化バスを用いる通信のための方法及び装置 Pending JP2005539408A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/060,735 US6683474B2 (en) 2002-01-29 2002-01-29 Method and apparatus for communication using a distributed multiplexed bus
PCT/US2003/001804 WO2003065581A1 (en) 2002-01-29 2003-01-21 Method and apparatus for communication using a distributed multiplexed bus

Publications (2)

Publication Number Publication Date
JP2005539408A true JP2005539408A (ja) 2005-12-22
JP2005539408A5 JP2005539408A5 (enExample) 2006-03-02

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ID=27610079

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JP2003565048A Pending JP2005539408A (ja) 2002-01-29 2003-01-21 分散された多重化バスを用いる通信のための方法及び装置

Country Status (4)

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US (1) US6683474B2 (enExample)
EP (1) EP1470643A4 (enExample)
JP (1) JP2005539408A (enExample)
WO (1) WO2003065581A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7356633B2 (en) * 2002-05-03 2008-04-08 Sonics, Inc. Composing on-chip interconnects with configurable interfaces
US7254603B2 (en) * 2002-05-03 2007-08-07 Sonics, Inc. On-chip inter-network performance optimization using configurable performance parameters
US7194566B2 (en) * 2002-05-03 2007-03-20 Sonics, Inc. Communication system and method with configurable posting points
US6880133B2 (en) * 2002-05-15 2005-04-12 Sonics, Inc. Method and apparatus for optimizing distributed multiplexed bus interconnects
US7736299B2 (en) * 2002-11-15 2010-06-15 Paracor Medical, Inc. Introducer for a cardiac harness delivery
US7603441B2 (en) 2002-12-27 2009-10-13 Sonics, Inc. Method and apparatus for automatic configuration of multiple on-chip interconnects
US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
US7694249B2 (en) * 2005-10-07 2010-04-06 Sonics, Inc. Various methods and apparatuses for estimating characteristics of an electronic system's design
US20080120082A1 (en) * 2006-11-20 2008-05-22 Herve Jacques Alexanian Transaction Co-Validation Across Abstraction Layers
US8020124B2 (en) * 2006-11-20 2011-09-13 Sonics, Inc. Various methods and apparatuses for cycle accurate C-models of components
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US7814243B2 (en) * 2007-06-01 2010-10-12 Sonics, Inc. Shared storage for multi-threaded ordered queues in an interconnect
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5847580A (en) 1996-10-10 1998-12-08 Xilinx, Inc. High speed bidirectional bus with multiplexers
US5936424A (en) * 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US5627480A (en) * 1996-02-08 1997-05-06 Xilinx, Inc. Tristatable bidirectional buffer for tristate bus lines

Also Published As

Publication number Publication date
US6683474B2 (en) 2004-01-27
EP1470643A4 (en) 2006-05-31
WO2003065581A1 (en) 2003-08-07
EP1470643A1 (en) 2004-10-27
US20030141904A1 (en) 2003-07-31

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