JP2005512367A - Reconfigurable input Galois extension field linear converter device - Google Patents

Abstract

  A reconfigurable input Galois field linear transformer device (10) includes a Galois field linear transformer (12) including a matrix of cells; and a plurality of storage surfaces (18, 18) for storing control patterns representing many different functions. 18 ′, 18 ″); a memory surface selection circuit (20) for selecting a memory surface (18, 18 ′, 18 ″) representing the function to enable use of the cells of the matrix defining the function; And a reconfigurable input circuit (14) for transmitting the input data to a cell enabled for application to the input data.

Description

  The present invention relates to a reconfigurable input Galois field linear transformer system.

Galois Extension Field Linear Transformer has recently been improved to apply historical logic to perform multi-cycle operations in one cycle using predictive logic (filed on January 18, 2002) Patent Document 1) to Stein et al. Entitled GALOIS FIELD LINEAR TRANSFORMER. In this approach, each cell of a Galois field linear transformer (GFLT) includes an AND gate, an exclusive OR gate, and a storage device. The pattern of enabled / disabled cells that define specific functions applied to input data, eg bit alignment, cyclic redundancy check (CRC), scrambling / descrambling, and convolutional coding. To do so, the storage device is used to enable or disable the associated cell. Typically, the entire matrix of cells that make up the GFLT is set to a pattern to perform a specific function even when only a portion of the matrix is required. This is not economical in terms of power or die size.
US patent application 10 / 051,533

  Accordingly, it is an object of the present invention to provide an improved reconfigurable input Galois extension field linear converter device.

  It is a further object of the present invention to provide such an improved reconfigurable input Galois extension linear converter device that is more economical in terms of power and die size.

  It is a further object of the present invention to provide such an improved reconfigurable input Galois extension linear converter device in which the same placement plane can be shared by different functions.

  A further object of the present invention is to provide such an improved reconfigurable input Galois extension that allows the converter to perform both memory bit manipulation and memory-less bit manipulation separately or simultaneously. It is to provide a body linear converter device.

  A further object of the present invention is to provide such an improved reconfigurable input Galois extension linear converter device that can select and combine any byte combination of current data and previous state inputs. There is.

  The present invention allows an improved Galois Extension Field Linear Transformer (GFLT) device with multiple storage surfaces to store control patterns representing many different bit manipulation functions can be easily reconfigured, one in terms of placement To reconfigure the input circuit that can perform more functions and send the input data to the enabled cells to enable the cells of the GFLT matrix and provide the functions to the input data In addition, it can be achieved by selecting a memory surface representing the selected function.

  The present invention features a reconfigurable input Galois extension linear converter apparatus including a Galois extension linear converter having a matrix of cells and a plurality of storage surfaces for storing control patterns representing many different functions. A memory plane selection circuit selects a memory plane representing a function in order to enable use of a matrix cell defining the function. A reconfigurable input circuit transmits input data to a cell that has been enabled to provide functionality to the input data.

  In a preferred embodiment, each cell can include an exclusive OR logic circuit, an AND logic circuit having an output connected to the exclusive OR logic circuit, and an input for receiving input data bits. Each storage surface can include a storage device associated with each cell. Each storage device can include a plurality of storage units arranged with associated cells, one storage unit corresponding to each storage surface. Each storage device can include a multi-stage register arranged with associated cells, one stage corresponding to each storage surface. The storage surface selection circuit can include a surface selection register. The reconfigurable input circuit can include at least a first input register and a switching device that transmits input data from the first input register to the usable cell. The switching device can include a plurality of switching circuits, one associated with each byte of input data in the first input register. A second input register can be included, and the switching device can selectively transmit input data from the first and second input registers to the usable cell. The storage device can be programmable.

  Other objects, features, and advantages will be found to those skilled in the art from the following description of the preferred embodiment and the accompanying drawings.

FIG. 1 shows a reconstruction including a Galois extension field linear converter 12, a reconfigurable input circuit 14, an output circuit 16, and a plurality of storage surfaces 18, 18 ′, 18 ″ that can be selected separately by a storage surface selection circuit 20. A configurable input Galois extension linear converter device 10 is shown. The control patterns included in each of the storage surfaces 18, 18 ', 18 "can be all or only part of a complete Galois extension linear converter. Can be used. For example, the storage surface 18 representing the function f ₁ utilizes the entire array of cells in the Galois field linear transformer 12, while the function f ₂ whose control pattern is included in the storage surface 18 'is the global (GFLT) 12 Only require one-fourth 119. Similarly, function _{f 3,} represented by the control pattern on the storage surface 18 ", requires only a quarter 21 of the total array of cells in (GFLT) 12. These smaller pieces 19 and 21, Although shown neatly arranged in the corner of (GFLT) 12, the cell can be programmed to use any part of the (GFLT) 12 matrix of cells, and is not a necessary restriction.

Galois Extension Field Linear Transformer (GFLT) 12 comprises 32 bit matrix cells (1024 cell matrix), 64 bit matrix cells (4096 cell matrix), or any other desired size smaller or larger be able to. Continuing with the present invention, each cell storage surface 18, 18 ', 18 are associated with ", each storage surface a specific function _{f 1,} f 2, _{f 3} to be performed by (GFLT) 12 represents and stores the setting of the pattern of the individual cells. for example, the storage surface 18 may include a control pattern for executing reordering of the input to the output. function 2, f ₂ of the storage surfaces 18 ', the input to the output A control pattern can be included that exchanges the order of the functions f ₁ , f ₂ , f ₃ , or the control pattern by alternately selecting one of the storage surfaces 18, 18 ′, 18 ″. (GFLT) 12 can be used to perform any other function stored in the plane. For example, when the storage surface selecting circuit 20 selects the storage surface 18, the function f ₁ may be performed as shown in FIG. 2, the cell 12 here 32-bit matrix as circle shaded, using Represents a possible cell, cell 22. The input register 24 representing the ordered form of bits 1-32 has bits rearranged according to the cell enablement pattern depicted in FIG. For example, the data at bit position 1 in input register 24 is provided to bit position 16 in output register 26. The data at bit position 2 of input register 24 is provided to bit position 29 of output register 26, and so on. Exclude storage surface 18, by selecting a storage surface 18 'representing a control pattern for function f _2, the pattern of enablement of cells depicted in Figure 3 occurs. Here, the smaller subsection 19, ie the 16-bit portion of the matrix containing 256 bits, is manipulated by part 28 of the input register 24, changing the order of the bits located in bit positions 0-7, The order of the bits in bit positions 8-15 as given to the corresponding part 30 is switched separately. Thus, for example, bits at input register bit positions 0-7 appear at bit positions 7-0 of part 30 of output register 26, and data at bit positions 8-15 of part 28 of input register 24 are Appears at positions 15-8 of a portion 30 of the output register 26.

In one embodiment, the reconfigurable input circuit 14a of FIG. 4 includes more than one input register, namely register 40 and input register 42, each with 4 bytes in byte sections 44-50 and 52-58. Can be held. The reconfigurable input circuit 14a also includes multiplexers 60, 62, 64, and 66, one associated with each byte section of the input registers 40 and 42. There is one multiplexer 60-66 for each byte section, each of which is connected to the byte section in each of the two registers as shown. (GFLT) 12a is again designated as 32 by the cells of the 32-bit array, and the column length has been shortened for convenience of explanation. Each of multiplexers 60, 62, 64, and 66 can provide 8 bit bytes from one multiplexer, and two associated registers can be used for 8 columns of cells. For example, multiplexer 60 can send either the bits from byte section 44 or the bits from byte section 52 to any of the cells in the associated eight cell column 68. Multiplexers 62, 64, and 66 can be similarly implemented for the associated columns 70, 72, and 74, and multiplexers 60-66 can operate in any combination. For example, multiplexers 62 and 64 select byte sections 46 and 48 from register 40, while multiplexer 60 can select byte section 52 from register 42, and multiplexer 66 can select byte section 58 from register 42, for example. You can choose. Thus, the data in registers 40 and 42 can be assigned to cells in any predetermined pattern. In this way, selective data is transmitted to a cell in the (GFLT) converter 12a in combination with the ability to select a specific memory plane representing a specific function, so that the memory plane is selected and stored in the memory plane. Depending on the function and the selective transmission of data from the reconfigurable input circuit 14a, the same Galois extension field linear converter 12a can perform many different functions. This not only saves device die size, but is also economical in terms of power. In addition, using two or more input registers, such as input registers 40 and 42, achieve both memory bit operations and memoryless bit operations, and predictive Galois extension field transformations separately or simultaneously. Can do. Thus, there is no longer any need to move data from register to register, and the data in registers 40 and 42 are simultaneously byte-selected, combined and loaded into (GFLT) 12a via multiplexers 60-66 in one cycle. Can be done. As a result, as shown in FIG. 5, in the multi-cycle Galois field predictive transformation, a linear converter output (previous state) can be selected as one of the inputs. Features (GFLT) 12a in the portion 21a _{f 3} is, Galois whole filed January 18, 2002 which is incorporated herein by reference the FIELD LINEAR TRANSFORMER U.S. patent application for Stein et al titled 10 / 051,533 ( Perform a predictive multi-cycle Galois extension field transformation as taught in AD-239J)). US patent application Ser. No. 10 / 060,699, filed Jan. 30, 2002, to Stein et al. Entitled GALOIS FIELD MULTIPLIER SYSTEM, is also incorporated herein by reference in its entirety. The state prior to the conversion performed in the part 21a is passed from the corresponding part of the output register 16a and loaded into the byte section 50 of the register 40, so that both inputs are sent to the part 21a of the GFLT 12a at the same time. The byte section 56 of the register 42 is loaded. Portion 21a is utilized to perform as described in U.S. Patent Application 10 / 051,533 for Stein et al entitled Galois the FIELD LINEAR TRANSFORMER, filed January 18, 2002, for example, the function _{f 3} A storage surface 18 ″ control pattern.

Each cell 100 of (GFLT) 12a of FIG. 6 includes an AND gate 102 whose output is connected to an exclusive OR gate 104, which is the output from the previous cell on line 106. And provides output to the next cell on line 108. The AND gate 102 is made to enable or disable the exclusive OR gate 104 by an input on line 110 from the storage device 112, which in this case is a simple flip-flop. Under certain conditions, the storage device 112 enables the AND gate 102 to use the exclusive OR gate 104 and thus enables the cell 100. In other states, the cell 100 is not enabled without being enabled. The state of storage device 112 is controlled by a signal on line 114. The storage device 112 need not be implemented by flip-flops, and any other storage device can be used. 8 and 9, each of the cells 100a and 100b requires a logical product function and an exclusive logical sum function, which are Boolean meanings such as an exclusive logical sum gate and a logical product gate (Boolean It can be implemented in many different ways without the need for a specific exclusive or gate, as long as the logic circuit that functions in sense). For example, the AND function can be achieved without a specific AND gate having the 2: 1 input multiplexer 120 of FIG. 8A. The storage device 112 ″ is imagined as part of the storage surface and is set on the control line 114 according to, for example, the control pattern of the enabled cell required to perform function f ₁ or the storage device 112. There when tied with the storage surface 18 'is set according to the function f _2.

The memory plane selection circuit 20 and the reconfigurable input circuit 14 of FIG. 1 are 16 bits for operating the configuration register 120 of FIG. Controlled by a 32-bit register that fills 16 bits to operate unit 124. For example, a 16-bit input 124 section labeled 0-15 requires only four bits to operate four multiplexers 60-66, one bit / multiplexer as shown in this example: “0” to select a byte from register 40 and “1” to select from register 42. However, if 8 of the bits are used, 8 multiplexers can be used to serve a 64 bit matrix. If 16 bits are used, 16 multiplexers can be used for a 128 bit matrix. Similarly, the 16 bits available from positions 16-31 of the surface 122 of the configuration register 120 are used to select a large number of different storage surfaces including control patterns representing a very large number of different functions. Can do. Control bits loaded into the configuration register 120 select the storage plane and input so that the input data is sent to the enabled cell to apply the function represented by the enabled cell to the input data. Reconfigure the circuit appropriately. This information comes from a configuration command 126 from a microprocessor or any suitable hierarchical controller. The storage device 112 'typically has a number of individual storage units 112a, 112b, 112c, 112d, 112. . . including. Each of these storage units can here be a simple flip-flop, and each flip-flop constitutes a part of a different storage surface. Alternatively, the storage device 112 ″ of FIG. 9 includes a selector 118 that receives 2 ⁿ data bits at many stages 112a ′, 112b ′, 112c ′, 112d ′, 112e ′, 112f ′, 112g ′, 112h ′. Multi-stage registers 116 may be included, where each stage executes a storage unit and is associated with a different storage surface.

  Certain features of the invention are illustrated in some drawings and not described elsewhere, but this is for convenience because each feature may be combined with some or all of the other features according to the invention. Only. As used herein, the terms “comprising”, “having”, and “comprising” are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the present application should not be construed as merely possible embodiments.

  Other embodiments will be found to those skilled in the art and are within the scope of the claims.

  This application claims the priority of US Provisional Application 60 / 341,737 to Stein et al., Entitled PROGRAMMABLE GF2-ALU LINEAR FEEDBACK SHIFT REGISTER-INCOMING DATA SELECTION, filed December 18, 2001.

1 is a simplified schematic block diagram of a reconfigurable input Galois extension field linear transformer (GFLT) device according to the present invention. FIG. FIG. 2 is a simplified schematic diagram illustrating a pattern of usable cells in a GFLT for performing the function f ₁ represented by the storage surface of FIG. FIG. ₂ is a simplified schematic diagram illustrating a pattern of usable cells in a GFLT for performing the function f2 represented by the storage surface of FIG. 2 is a more detailed schematic diagram of the GFLT device of FIG. 1 showing a reconfigurable input circuit according to the present invention. FIG. 1 is a functional diagram of a GFLT device that performs many functions, one being a predictive multi-cycle Galois extension field transformation and the second being a memoryless bit operation. FIG. 2 is a more detailed diagram showing one cell of a GFLT. FIG. 6 is a schematic diagram illustrating a placement command and configuration register for selecting a storage surface and reconfiguring an input circuit. It is a more detailed view of a cell showing one configuration of a storage device using a plurality of storage units. FIG. 10 is a schematic diagram showing an alternative storage device that performs a logical AND function without using a specific AND gate; It is a more detailed view of a cell showing another configuration of a storage device using a multistage register.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Reconfigurable input Galois extension field linear converter apparatus 12 Galois extension field linear converter 14 Reconfigurable input circuit 16 Output circuit 18, 18 ', 18 "Memory surface 20 Memory surface selection circuit 112 Memory devices 112a, 112b, 112c , 112d Storage unit 116 Multistage register

Claims (10)

A Galois extension field linear transformer containing a matrix of cells;
Multiple memory surfaces that store control patterns representing many different functions;
A memory surface selection circuit for selecting the memory surface representing the function in order to enable the cells of the matrix defining the function;
A reconfigurable input circuit for sending input data to a cell enabled to assign said function to input data;
A reconfigurable input Galois extension field linear converter device comprising: The reconfigurable input Galois extension field linear converter device according to claim 1,
Each of the cells includes an exclusive OR logic circuit, an AND logic circuit having an output connected to the exclusive OR logic circuit, and an input for receiving an input data bit. Possible input Galois extension field linear converter device. The reconfigurable input Galois extension field linear converter device according to claim 1,
A reconfigurable input Galois extension linear converter device, wherein each storage surface includes a storage device associated with each cell. The reconfigurable input Galois extension field linear converter device according to claim 3,
Each of the storage devices includes a plurality of storage units arranged with associated cells, one storage unit corresponding to each of the storage surfaces. A reconfigurable input Galois extension linear converter device. The reconfigurable input Galois extension field linear converter device according to claim 3,
A reconfigurable input Galois extension linear converter device, wherein each storage device includes a multi-stage register arranged with an associated cell, one stage corresponding to each storage surface. The reconfigurable input Galois extension field linear converter device according to claim 1,
The reconfigurable input Galois extension field linear converter device, wherein the memory plane selection circuit includes a plane selection register. The reconfigurable input Galois extension field linear converter device according to claim 1,
The reconfigurable input circuit includes at least a first input register and a switching device for transmitting input data from the first input register to the enabled cell. Enlarged body linear converter device. The reconfigurable input Galois extension field linear converter device according to claim 7,
The reconfigurable input Galois extension linear converter device, wherein the switching device includes a plurality of switching circuits, one associated with each byte of input data in the first input register. The reconfigurable input Galois extension field linear converter device according to claim 7,
A second input register;
The reconfigurable input Galois extension linear converter device, wherein the switching device selectively transmits input data from the first and second input registers to the enabled cell. The reconfigurable input Galois extension field linear converter device according to claim 3,
A reconfigurable input Galois extension field linear converter device, wherein the storage device is programmable.

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