WO2003048947A1 - Reconfigurable input galois field linear transformer system - Google Patents

Reconfigurable input galois field linear transformer system Download PDF

Info

Publication number
WO2003048947A1
WO2003048947A1 PCT/US2002/038370 US0238370W WO03048947A1 WO 2003048947 A1 WO2003048947 A1 WO 2003048947A1 US 0238370 W US0238370 W US 0238370W WO 03048947 A1 WO03048947 A1 WO 03048947A1
Authority
WO
WIPO (PCT)
Prior art keywords
input
galois field
linear transformer
field linear
storage
Prior art date
Application number
PCT/US2002/038370
Other languages
French (fr)
Inventor
Yosef Stein
Haim Primo
Yaniv Sapir
Original Assignee
Analog Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US33466201P priority Critical
Priority to US33451001P priority
Priority to US60/334,510 priority
Priority to US60/334,662 priority
Priority to US60/341,737 priority
Priority to US34173701P priority
Priority to US10/051,533 priority patent/US6587864B2/en
Priority to US10/051,533 priority
Priority to US10/060,699 priority patent/US6766345B2/en
Priority to US10/060,699 priority
Priority to US10/136,170 priority patent/US7269615B2/en
Priority to US10/136,170 priority
Application filed by Analog Devices, Inc. filed Critical Analog Devices, Inc.
Publication of WO2003048947A1 publication Critical patent/WO2003048947A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724Finite field arithmetic

Abstract

A reconfigurable input Galois field linear transformer system (10) includes a Galois field linear transformer (12) including a matrix of cells; a plurality of storage planes (18, 18', 18'') for storing control patterns representing a number of different functions; a storage plane selector circuit (20) for selecting a storage plane (18, 18', 18'') representing a function for enabling the cells of the matrix which defines that function; and a reconfigurable input circuit (14) for delivering input data to the enabled cells to apply that function to the input data.

Description

RECONFIGURABLE INPUT GALOIS FIELD LINEAR TRANSFORMER SYSTEM

FIELD OF THE INVENTION This invention relates to a reconfigurable input Galois field linear transformer system.

RELATED APPLICATIONS This application claims priority of U.S. Provisional application 60/341,737 to Stein et al. filed December 18, 2001 entitled PROGRAMMABLE GF2-ALU LINEAR FEEDBACK SHIFT REGISTER - INCOMING DATA SELECTION.

BACKGROUND OF THE INVENTION Galois field linear transformers have recently been improved (U.S. Patent application 10/051,533 to Stein et al., filed January 18, 2002 entitled GALOIS FIELD LINEAR TRANSFORMER) so that they can perform historically multicycle operations in one cycle using predictive logic. In that approach each cell of the Galois field linear transformer (GFLT) includes an AND gate, an Exclusive OR gate and a storage device. The storage device is used to enable or disable its associated cell in order to implement a pattern of enabled/disabled cells that define a particular function that will be applied to the input data e.g. bit permutation, cyclic redundancy checking (CRC), scrambling/descrambling and convolutional coding. Typically, the entire matrix of cells making up the GFLT is set to a pattern to perform a particular function even when only a portion of the matrix is required. This is not economical of power or die size.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide an improved reconfigurable input Galois field linear transformer system.

It is a further object of this invention to provide such an improved reconfigurable input Galois field linear transformer system which is more economical of power and die size.

It is a further object of this invention to provide such an improved reconfigurable input Galois field linear transformer system in which the same configuration plane can be shared by different functions.

It is a further object of this invention to provide such an improved reconfigurable input Galois field linear transformer system that enables the transformer to perform both memory and memory-less bit manipulation separately or simultaneously.

It is a further object of this invention to provide such an improved reconfigurable input Galois field linear transformer system which can select and combine any byte combination of the present data and previous state inputs.

The invention results from the realization that an improved Galois field linear transformer (GFLT) system with a plurality of storage planes for storing control patterns representing a number of different bit manipulation functions can be easily reconfigured and can perform more than one function in a configuration plane can be achieved by selecting a storage plane representing a chosen function for enabling the cells of the GFLT matrix and reconfiguring the input circuit to deliver the input data to the enabled cells to apply that function to the input data.

This invention features a reconfigurable input Galois field linear transformer system including a Galois field linear transformer having a matrix of cells and a plurality of storage planes for storing control patterns representing a number of different functions. A storage

plane selector circuit selects a storage plane representing a function for enabling the cells of the matrix which defines that function. A reconfigurable input circuit delivers input data to the enabled cells to apply that function to the input data.

In a preferred embodiment, each cell may include an exclusive OR logic circuit, an AND logic circuit having an output connected to the exclusive OR logic circuit, and an input for receiving an input data bit. Each storage plane may include a storage device associated with each cell. Each storage device may include a plurality of storage units disposed with the associated cell, one storage unit corresponding to each storage plane. Each storage device may include a multistage register disposed with the associated cell, one stage corresponding to each storage plane. The storage plane selector circuit may include a plane selection register. The reconfigurable input circuit may include at least a first input register and a switching system for directing the input data from the first input register to the enabled cells. The switching system may include a plurality of switching circuits, one associated with each byte of input data in the first input register. There may be a second input register and the switching system may direct the input data selectively from the first and second input registers to the enable cells. The storage device may be programmable. BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:

Fig. 1 is a simplified schematic block diagram of a reconfigurable input Galois field linear transformer (GFLT) system according to this invention;

Fig. 2 is a simplified schematic diagram illustrating a pattern of enable cells in a GFLT for executing the function fi represented by a storage plane of Fig. 1;

Fig. 3 is a simplified schematic diagram illustrating a pattern of enable cells in a GFLT for executing the function f2 represented by a storage plane of Fig. 1 ;

Fig. 4 is a more detailed schematic diagram of the GFLT system of Fig. 1 showing a reconfigurable input circuit according to this invention;

Fig. 5 is a functional diagram of a GFLT system for effecting a number of functions one of which is a predictive, multi cycle Galois field transformation, the second a memory-less bit manipulation ;

Fig. 6 is a more detailed view of one cell of the GFLT;

Fig. 7 is a schematic illustration of the configuration command and configuration register which select the storage plane and reconfigure the input circuit;

Fig. 8 is a more detailed view of a cell showing one construction of a storage device using a plurality of storage units;

Fig. 8 A is a schematic diagram of an alternative storage device which performs logical AND functions without a specific AND gate; and

Fig. 9 is a more detailed view of a cell showing another construction of a storage device using a multistage register.

PREFERRED EMBODIMENT

There is shown in Fig. 1 a reconfigurable input Galois field linear transformer system 10 including Galois field linear transformer 12, reconfigurable input circuit 14, output circuit 16 and a plurality of storage planes 18, 18', 18" which are individually selectable by storage plane selector circuit 20. The control pattern contained in each of the storage planes 18, 18', 18" may employ all or only a part of the full Galois field linear transformer. For example, while storage plane 18 representing function fi employs the entire array of cells in Galois field linear transformer 12, the function f2, whose control pattern is contained on storage plane 18', requires only a quarter 19 of the entire (GFLT) 12. Similarly, function f3, represented by the control pattern on storage plane 18" requires only a quarter 21 of the entire array of cells in (GFLT) 12. While these smaller portions 19 and 21 are shown neatly disposed in the comers of the (GFLT) 12, this is not a necessary limitation as the cells may be programmed to use any part of the (GFLT) 12 matrix of cells.

Galois field linear transformer (GFLT) 12 may be made up by a thirty-two bit matrix of cells (1024 cell matrix), a sixty-four bit matrix of cells (4096 cell matrix), or any other desired size whether smaller or larger. Keeping with this invention, each cell has associated with it a storage plane 18, 18', 18" each of which stores a pattern of settings of the individual cells that represents a particular function fi, f2, f3 to be performed by (GFLT) 12. For example, storage plane 18 may contain a control pattern for implementing a permutation of the input to the output. Function 2, f2, of storage plane 18' may contain a control pattern for swapping the order of the input with respect to the output. By alternately selecting one of storage planes 18, 18', 18" one can utilize (GFLT) 12 to perform function fi, function f2, function f or any other function for which the control pattern has been stored in a storage plane. For example if storage plane selector circuit 20 selects storage plane 18, then function fi will be implemented as shown in Fig. 2 where the thirty-two bit matrix of cells 12 displays as a shaded circle those cells which are enabled, cell 22. Input register 24 which presents the bits 1-32 in an ordered fashion has those bits permutated in accordance with the pattern of cell enablement depicted in Fig. 2 so that they are permutated in output register 26. For example, the data in bit position one in input register 24 are presented at bit position sixteen in output register 26. The data in bit position two of input register 24 is presented at bit position twenty-nine in output register 26 and so on. By deselecting storage plane 18 and selecting storage plane 18', which represents the control pattern for function f2, the pattern of cell enablement depicted in Fig. 3 will occur. Here the smaller subsection 19, a sixteen bit portion of the matrix containing 256 bits is, operated by a portion 28 of input register 24 to reverse the order of the bits located in bit positions 0-7 and separately reverse the order of the bits in bit positions 8-15 as presented at the corresponding portion 30 of output register 26. Thus, for example the bits at the input register bit positions 0-7 will appear at the bit positions 7-0 of the portion 30 of output register 26 and the data at bit positions at 8-15 of portion 28 of input register 24 will appear at positions 15-8 of portion 30 of output register 26.

In one embodiment, reconfigurable input circuit 14a, Fig. 4, includes more than one input register, register 40 and input register 42, each of which can hold four bytes in its byte sections 44-50 and 52-58. Also included in reconfigurable input circuit 14a are multiplexors 60, 62, 64, and 66, one associated with each byte section of input registers 40 and 42. There is one multiplexor 60-66 for each byte section and each of those multiplexors is connected to a byte section in each of the two registers as shown. (GFLT) 12a is again shown as a thirty-two by thirty-two bit array of cells the length of the columns having been foreshortened for convenience of presentation. Each of the multiplexors 60, 62, 64, and 66 can provide the eight bit byte from one its two associated registers to the eight columns of cells which it serves. For example, multiplexor 60 may deliver either the bits from byte section 44 or the bits from byte section 52 to any of the cells in the eight cell columns 68 with which it is associated. Multiplexors 62, 64 and 66 can perform similarly with respect to their associated columns 70, 72 and 74 and multiplexors 60-66 can be operated in any combination. For example, multiplexor 60 could choose byte section fifty-two from register 42 while multiplexors 62 and 64 choose byte sections 46 and 48 from register 40 and multiplexor 60 may choose byte section 58 from register 42 for example. Thus, the data residing in registers 40 and 42 can be applied to the cells in any given pattern. This selective delivery of the data to the cells in (GFLT) transformer 12a in combination with the ability to select a particular storage plane representing a particular function enables the same Galois field linear transformer 12a to perform a number of different functions depending upon the selection of the storage plane and the functions stored therein and the selective delivery of the data from reconfigurable input circuit 14a. This not only saves on the die size for the system but is also economical of power. Further, with the use of two or more input registers, for example input registers 40 and 42, both memory and memory less bit manipulation and predictive Galois filed transformation can be accomplished separately or simultaneously. Thus, it is no longer necessary to shift the data from register to register: the data in registers 40 and 42 can simultaneously, in one cycle, be byte selected combined and loaded into (GFLT) 12a through multiplexors 60-66. This also permits, in a multi cycle Galois field predictive transformation, the selection of the linear transformer output (previous state) as one of the inputs, as shown in Fig. 5. There the function f in portion 21a, of (GFLT) 12a implements a predictive multi cycle Galois field transformation as taught in U.S. Patent application 10/051,533 to Stein et al., filed January 18, 2002 entitled GALOIS FIELD LINEAR TRANSFORMER (AD-239J) incorporated herein in its entirety by reference. Also incorporated herein in its entirety by reference is U.S. patent application no. 10/060,699 to Stein et al., filed January 30, 2002, entitled GALOIS FIELD MULTIPLIER SYSTEM (AD-240J). There the previous state of the transform performed in portion 21a is delivered from the corresponding portion of output register 16a and loaded in byte section 50 of register 40 and the input is loaded in byte section 56 of register 42 so that both can be simultaneously delivered to portion 21a of GFLT 12a which has had the control pattern of, for example, storage plane 18" applied to it to implement function f as explained in U.S. Patent application 10/051,533 to Stein et al., filed January 18, 2002 entitled GALOIS FIELD LINEAR TRANSFORMER.

Each cell 100, Fig. 6 of (GFLT) 12a includes an AND gate 102 whose output is connected to an exclusive OR gate 104 which receives output from the previous cell on line 106 and provides outputs to the next cell on line 108. AND gate 102 is caused to enable or disable exclusive OR gate 104 by means of its input on line 110 from storage device 112 which in this case is a simple flip-flop. In one state storage device 112 causes AND gate 102 to enable exclusive OR gate 104 and thus enables cell 100; in the other state it does not, and cell 100 is not enabled. The condition of storage device 112 is controlled by a signal on line 114. The storage device 112 need not be implemented by a flip-flop, any other storage device could be used. In Figs. 8 and 9 cells 100a and 100b respectively need AND functions and exclusive OR functions, but these may be performed in a number of different ways not requiring a specific XOR gate or AND gate as long as these are logic circuits that function in a Boolean sense like an XOR gate and AND gate. For example, the AND function can be achieved without a specific AND gate using a 2:1 input multiplexor 120, Fig. 8 A which performs the AND function. Storage device 112" is envisioned as a part of a storage plane and will have been set on its control line 114 in accordance with the control pattern of enabled cells required to implement for example function fi, or if storage device 112 is associated with storage plane 18' then in accordance with the function f2.

Storage plane selector circuit 20 and reconfigurable input circuit 14, Fig. 1 are controlled by configuration register 120, Fig. 7, a thirty-two bit register which devotes sixteen bits to operate storage plane selector circuit 20, plane section 122 and sixteen bits to operate the reconfigurable input circuit 14, input section 124. For example, the input 124 section of sixteen bits denominated 0-15 requires only four bits to operate the four multiplexors 60-66 one bit/multiplexor "0" for selecting the byte from register 40 and "1" for selecting from register 42 as shown in this example. However, if eight of the bits are used eight multiplexors could be used to serve a 64 bit matrix. If sixteen bits are used sixteen multiplexors could be used for 128 bit matrix. In a similar fashion, the sixteen bits available from positions 16-31 of plane section 122 of configuration register 120 can be used to select a large number of different storage planes containing control patterns representing a very large number of different functions. The control bits which are loaded in configuration register 120 to select the storage plane and reconfigure the input circuit appropriately so that the input data is delivered to the enabled cells to apply to the input data the function that the enabled cells represent. This information comes from a configuration command 126 from a microprocessor or any suitable hierarchical controller. Storage device 112' normally includes a number of individual storage units, 112a, 112b, 112c, 112d, 112...as shown in Fig. 8 wherein each of those storage units may be a simple flip-flop and each one constitutes a part of a different storage plane. Alternatively, storage device 112", Fig. 9 may include a multistage register 116 including selector 118 which receives 2n data bits in a number of stages 112a', 112b', 112c', 112d\ 112e', 112f , 112g', 112h' where each stage implements a storage unit and each stage is associated with a different storage plane.

Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words "including", "comprising", "having", and "with" as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments.

Other embodiments will occur to those skilled in the art and are within the following claims:

What is claimed is:

Claims

1. A reconfigurable input Galois field linear transformer system comprising: a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector circuit for selecting a said storage plane representing a said function for enabling the cells of said matrix which define that function; and a reconfigurable input circuit for delivering input data to said enabled cells to apply that function to the input data.
2. The reconfigurable input Galois field linear transformer system of claim 1 in which each said cell includes an exclusive OR logic circuit, an AND logic circuit having an output connected to said exclusive OR logic circuit, and an input for receiving an input data bit.
3. The reconfigurable input Galois field linear transformer system of claim 1 in which each said storage plane includes a storage device associated with each said cell.
4. The reconfigurable input Galois field linear transformer system of claim 3 in which each said storage device includes a plurality of storage units disposed with the associated cell, one storage unit corresponding to each said storage plane.
5. The reconfigurable input Galois field linear transformer system of claim 3 in which each said storage device includes a multistage register disposed with the associated cell, one stage corresponding to each said storage plane.
6. The reconfigurable input Galois field linear transformer system of claim 1 in which said storage plane selector circuit includes a plane selection register.
7. The reconfigurable input Galois field linear transformer system of claim 1 in which said reconfigurable input circuit includes at least a first input register and a switching system for directing the input data from said first input register to said enabled cells.
8. The reconfigurable input Galois field linear transformer system of claim 7 in which said switching system includes a plurality of switching circuits one associated with each byte of input data in said first input register.
9. The reconfigurable input Galois field linear transformer system of claim 7 in which there is a second input register and said switching system directs input data selectively from said first and second input registers to said enabled cells.
10. The reconfigurable input Galois field linear transformer system of claim 3 in which said storage device is programmable.
11. The reconfigurable input Galois field linear transformer system of claim 8 in which said switching circuits includes a multiplexor for presenting inputs from said input registers.
PCT/US2002/038370 2001-11-30 2002-11-29 Reconfigurable input galois field linear transformer system WO2003048947A1 (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
US33466201P true 2001-11-30 2001-11-30
US33451001P true 2001-11-30 2001-11-30
US60/334,510 2001-11-30
US60/334,662 2001-11-30
US34173701P true 2001-12-18 2001-12-18
US60/341,737 2001-12-18
US10/051,533 US6587864B2 (en) 2001-11-30 2002-01-18 Galois field linear transformer
US10/051,533 2002-01-18
US10/060,699 US6766345B2 (en) 2001-11-30 2002-01-30 Galois field multiplier system
US10/060,699 2002-01-30
US10/136,170 2002-05-01
US10/136,170 US7269615B2 (en) 2001-12-18 2002-05-01 Reconfigurable input Galois field linear transformer system

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02791352A EP1459188A4 (en) 2001-11-30 2002-11-29 Reconfigurable input galois field linear transformer system
JP2003550072A JP3962022B2 (en) 2001-11-30 2002-11-29 Reconfigurable input Galois field linear transformer device
AU2002365807A AU2002365807A1 (en) 2001-11-30 2002-11-29 Reconfigurable input galois field linear transformer system

Publications (1)

Publication Number Publication Date
WO2003048947A1 true WO2003048947A1 (en) 2003-06-12

Family

ID=27556635

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/038370 WO2003048947A1 (en) 2001-11-30 2002-11-29 Reconfigurable input galois field linear transformer system

Country Status (5)

Country Link
EP (1) EP1459188A4 (en)
JP (1) JP3962022B2 (en)
CN (1) CN1316383C (en)
AU (1) AU2002365807A1 (en)
WO (1) WO2003048947A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
US5095525A (en) * 1989-06-26 1992-03-10 Rockwell International Corporation Memory transformation apparatus and method
US5153302A (en) 1990-10-29 1992-10-06 Diafoil Company, Limited Polyester film for capacitor
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
US5446850A (en) * 1991-01-15 1995-08-29 International Business Machines Corporation Cross-cache-line compounding algorithm for scism processors
US6246768B1 (en) * 1998-05-06 2001-06-12 Penta Security Systems, Inc. Data encryption system for encrypting plaintext data

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2583539B1 (en) * 1984-12-31 1991-05-24 Lehmann Jean Philippe Method for construction of simultaneous activation devices command trains and applications memoirs.
FR2605769B1 (en) * 1986-10-22 1988-12-09 Thomson Csf Operators polynomial in the Galois field and digital signal processor comprising such operator
US5680070A (en) * 1996-02-05 1997-10-21 Motorola, Inc. Programmable analog array and method for configuring the same
US5768168A (en) * 1996-05-30 1998-06-16 Lg Semicon Co., Ltd. Universal galois field multiplier
US6057703A (en) * 1997-08-22 2000-05-02 Holoplex Inc. Reconfigurable programmable logic devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
US5095525A (en) * 1989-06-26 1992-03-10 Rockwell International Corporation Memory transformation apparatus and method
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
US5153302A (en) 1990-10-29 1992-10-06 Diafoil Company, Limited Polyester film for capacitor
US5446850A (en) * 1991-01-15 1995-08-29 International Business Machines Corporation Cross-cache-line compounding algorithm for scism processors
US6246768B1 (en) * 1998-05-06 2001-06-12 Penta Security Systems, Inc. Data encryption system for encrypting plaintext data

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1459188A4 *

Also Published As

Publication number Publication date
JP3962022B2 (en) 2007-08-22
EP1459188A1 (en) 2004-09-22
CN1316383C (en) 2007-05-16
EP1459188A4 (en) 2007-03-07
CN1608251A (en) 2005-04-20
JP2005512367A (en) 2005-04-28
AU2002365807A1 (en) 2003-06-17

Similar Documents

Publication Publication Date Title
US6362650B1 (en) Method and apparatus for incorporating a multiplier into an FPGA
US5598573A (en) Multiple chip processor architecture with reset intercept circuit
JP3488258B2 (en) Programmable logic array integrated circuits
US4845664A (en) On-chip bit reordering structure
CA1205207A (en) Bidirectional data byte aligner
KR960016397B1 (en) File storaging apparatus and information processing apparatus using the same
EP1512223B1 (en) Programmable logic device having heterogeneous programmable logic blocks
EP0047440B1 (en) Shift circuit
US5237218A (en) Structure and method for multiplexing pins for in-system programming
US6986004B1 (en) FIFO memory with programmable data port widths
US5563529A (en) High speed product term allocation structure supporting logic iteration after committing device pin locations
JP3743487B2 (en) Programmable logic device, an information processing system, reconstruction method of the circuit to the programmable logic device, a method of compressing circuit information for the programmable logic device
US5218562A (en) Hamming data correlator having selectable word-length
US6567969B1 (en) Configurable logic array including lookup table means for generating functions of different numbers of input terms
US8358150B1 (en) Programmable microcontroller architecture(mixed analog/digital)
JP3210660B2 (en) Logical block for a programmable logic device
US6519673B1 (en) Multi-bank, fault-tolerant, high-performance memory addressing system and method
US4727474A (en) Staging memory for massively parallel processor
EP0510830A2 (en) Registered logic macrocell with product term allocation and adjacent product term stealing
US7218143B1 (en) Integrated circuit having fast interconnect paths between memory elements and carry logic
JP4410853B2 (en) fpga architecture with a ram block having a programmable word length and width and dedicated address and data lines
US4280176A (en) Memory configuration, address interleaving, relocation and access control system
US4654781A (en) Byte addressable memory for variable length instructions and data
US6438569B1 (en) Sums of production datapath
US20060155947A1 (en) Selectable block protection for non-volatile memory

Legal Events

Date Code Title Description
AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2002791352

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2003550072

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2002826083X

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2002791352

Country of ref document: EP