JP2005323399A - Programmable logic circuit apparatus, information processing system, reconstruction method of circuit to programmable logic circuit apparatus, and compression method of circuit information for programmable logic circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology equivalent to a multi-context technology without using a configuration memory to store a plurality of circuit information which incurs the deterioration of circuit performance, an increase in power consumption, an increase in the number of manufacturing processes, an increase in manufacturing cost or the like. <P>SOLUTION: A programmable logic circuit apparatus is provided with a circuit information storage means 102 separate from a configuration memory, and a circuit information editing means 103 for generating the circuit information of a designated circuit by using the circuit information stored in the storage means 102. A plurality of pieces of the circuit information are stored in a compressed state in the storage means 102. When the designated circuit information of the circuit to be reconstituted is inputted to a programmable logic circuit portion 104, the circuit is reconstructed by reading necessary circuit information from the storage means 102 in the editing means 103 by depressing compression by the generation of the circuit information designated by designated information, and by transferring the generated circuit information to the configuration memory 106. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a programmable logic circuit device suitable for a case where a plurality of circuits are sequentially reconfigured in order to share a part of processing by an application program, for example. In particular, it relates to a method for reducing the reconfiguration time of a programmable logic circuit device.

  In the field of digital circuit devices, programmable logic circuit devices such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) can be used as prototype devices before creating application specific integrated circuits (ASICs) or for several weeks. It has been used as an ASIC replacement device that requires a long production period of several months. Recently, a programmable logic circuit device has been used to change specifications or modify a circuit after the circuit device is created.

  The structure of a general programmable logic circuit device is shown in FIG. The programmable logic circuit device 1 includes a circuit information input control unit 2 that reads circuit information from the outside, and a programmable logic circuit unit 3 that realizes a circuit function according to the read circuit information.

  Further, the detailed structure of the programmable logic circuit section 3 is composed of a circuit element 4 and a configuration memory 5 connected to the circuit element 4 as shown in FIG. The circuit element 4 includes an input / output unit, a logic circuit cell, and a wiring unit. Depending on the connection form of the circuit element 4, the programmable logic circuit device is divided into an FPGA type and a CPLD type.

  In the FPGA type programmable logic circuit section 3A, as shown in FIG. 24A, logic circuit cells 6A arranged in a two-dimensional lattice are connected to each other by a wiring section 7A. Further, signals are input / output to / from the outside via the input / output units 8A connected to the four sides of the rectangular wiring unit 7A as a whole.

  In the CPLD type programmable logic circuit section 3B, as shown in FIG. 24B, the input / output section 8B and the logic circuit cell 6B are connected to the wiring section 7B in a tree structure.

  In any structure, circuit information read into the programmable logic circuit device 1 is written into the configuration memory 5 by the circuit information input control unit 2. According to the circuit information written in the configuration memory 5, the function and connection state of the circuit elements are determined. This operation is called reconfiguration or configuration of the programmable logic circuit device.

[Explanation of Reconfigurable Computing Technology]
By the way, recently, in the field of reconfigurable computing, which realizes faster processing than software processing using a general-purpose processor by hardware processing using a dedicated processing circuit adapted to application processing. Logic circuit devices are beginning to be used.

  In reconfigurable computing, circuit information of a plurality of processing circuits required for application processing is stored in advance in an external storage device, and circuit information read from the external storage device is stored in programmable logic as necessary. By writing to the configuration memory in the circuit device, a necessary circuit is realized on the programmable logic circuit device.

  This technology is called cache logic technology from the viewpoint of saving necessary circuit information outside the programmable logic circuit device, or by rewriting circuit information, the circuit of the actual programmable logic circuit section It is called virtual logic technology from the viewpoint of realizing a circuit with a scale larger than the scale. In the following description, for simplicity, these technologies are collectively referred to as a cache logic technology.

  The cache logic technique is a time-division driving technique in which different circuits are configured as necessary on the same programmable logic circuit device. As a result, a circuit larger than the circuit scale can be realized using a programmable logic circuit device having a small circuit scale, and the circuit device can be reduced in size and cost.

  However, depending on the scale of the circuit information to be written to the configuration memory of the programmable logic circuit device, it takes a long time to write the circuit information from the external storage device to the configuration memory of the programmable logic circuit device, and a dedicated hardware processing circuit is used. Even if high-speed processing is realized, there is a problem that the entire processing time including the circuit reconfiguration time becomes longer than the software processing time.

  One solution to this problem is device technology called multi-context technology. That is, in the multi-context technology, a plurality of configuration memories are provided so that a plurality of pieces of circuit information can be stored in the programmable logic circuit device, and the configuration memories are switched as necessary. By reconfiguring the circuit in the circuit device, the circuit reconfiguration time is greatly reduced.

[Description of programmable logic circuit device by multi-context technology]
The structure of the programmable logic circuit device based on the multi-context technology is shown in FIG. The programmable logic circuit device 10 based on the multi-context technology is selected by a circuit information input control unit 11 that reads a plurality of circuit information from the outside, a circuit information selection control unit 12 that selects necessary circuit information from the plurality of circuit information, and It is comprised from the programmable logic circuit part 13 which implement | achieves a circuit function according to circuit information.

  The detailed structure of the programmable logic circuit unit 13 based on this multi-context technology is as shown in FIG. The configuration memory 15 includes a circuit element 14 and a configuration memory 15 connected to the circuit element 14. The configuration memory 15 in the case of the programmable logic circuit unit 13 based on the multi-context technology is configured by a plurality of memory planes. The

  In the case of the programmable logic circuit unit 13 based on the multi-context technology, a plurality of pieces of circuit information read from the outside into the programmable logic circuit device 10 in both the FPGA type and the CPLD type (see FIG. 24). Is written in a state where one circuit information is written to each memory plane of the configuration memory 15 by the circuit information input control unit 11.

  The function of the circuit element 14 is determined according to the circuit information of the memory plane selected by the selection signal from the circuit information selection control unit 12 among the plurality of circuit information written in the plurality of memory planes of the configuration memory 15. The connection state is determined, and the circuit is reconfigured in the programmable logic circuit device 10.

  By the way, the circuit information format used in the programmable logic circuit device includes a serial format and a parallel format, and the configuration operation differs depending on these two circuit information formats. Therefore, the configuration operation in the case of each circuit information format in the programmable logic circuit device 1 in FIG. 22 and the programmable logic circuit device 10 using the multi-context technique in FIG. 25 will be described below.

[Structure of circuit information; (I) Circuit information in serial format]
FIG. 27 shows the structure of serial circuit information used in a conventional programmable logic circuit device. As shown in FIG. 27A, the circuit information includes a header part HDs, a data part DTs, and a footer part FTs. In the programmable logic circuit device, serial-format circuit information is handled as serial data, but parallel transmission and parallel memory access can be performed by dividing the information into appropriate units (for example, 8 bits).

  The header part HDs includes a preamble code indicating the start of circuit information, a length count indicating the data amount of the circuit information, and a delimiter code indicating the end of the header part HDs.

  The data part DTs consists of a plurality of frames. Here, a frame is a lump of data obtained by dividing data stored in the configuration memory by a certain amount (usually about 100 to 1000 bits). The size of this frame is determined in consideration of the ease of reconfiguration of the circuit into the programmable logic circuit portion. For example, the size of the frame corresponds to the logic circuit for one column in the vertical direction in the case of the FPGA type in FIG. Circuit information is used.

  As shown in FIG. 27B, each frame includes start field bit data STB representing the start of the frame, configuration data CFGD stored in the configuration memory, and stop field bit data ENB representing the end of the frame. Consists of.

  The footer part FTs is composed of a postamble code indicating the end of one circuit information.

[Configuration of Conventional Programmable Logic Circuit Device 1 Based on Serial Circuit Information]
FIG. 28 is a functional block diagram for explaining a configuration operation by serial circuit information to the conventional programmable logic circuit device 1 shown in FIG. The storage of circuit information in the configuration memory will be described with reference to the block diagram shown in FIG.

  The circuit information input control unit 2 shown in FIG. 22 includes the configuration controller 2a, length count register 2b, selector 2c, and a plurality of shift registers 2d shown in FIG.

  The programmable logic circuit unit 3 shown in FIG. 22 includes the circuit element 4 and the configuration memory 5 as described above. In FIG. 28, for example, an FPGA type as shown in FIG. If so, for example, a plurality of logic circuit cells in one vertical column can be divided into a set of configuration memory 5s and circuit elements 4s for a plurality of columns.

  The registers at each stage of each shift register 2d are connected to each memory cell of the configuration memory 5s in each column. Therefore, each shift register 2d is configured to have, for example, an FPGA type as shown in FIG. 24A, the number of stages corresponding to circuit information to the number of logic circuit cells in a vertical column. One shift register is allocated to a plurality of logic circuit cells in one vertical column, and the shift registers 2d are provided by the number of logic circuit cells in the horizontal direction.

  When the number of logic circuit cells is large, one shift register 2d is provided for a plurality of columns of about several to several tens, and one shift register 2d is commonly used for the plurality of columns. May be configured.

  The size of one frame of the circuit information is, for example, the data amount for one shift register 2d.

  In the configuration of FIG. 28, when circuit information is read from the external storage device 9, the configuration controller 2a detects the preamble code in the header portion of the circuit information and starts configuration processing.

  The length count following the preamble code is stored in the length count register 2b. The value of the length count register 2b is decremented by 1 for each data shift of the shift register 2d described later, and the shift register 2d operates until the value of the length count register 2b becomes 0. As a result, all data is sent to the shift register 2d.

  The data part following the delimiter code is sent to the selector 2c. In the initial state, the selector 2c sends the configuration data to the shift register 2d in the first column. The shift register 2d sequentially shifts the data sent from the selector 2c. When the data is shifted to the end of the shift register 2d, the selector 2c switches the data output to the shift register 2d in the next column.

  By repeating the above operation, the shift register 2d operates until the value of the length counter 2b described above becomes 0, whereby all data is stored in the shift register 2d.

  When the shift register 2d is filled with configuration data, the data is transferred to all of the configuration memories 5s in parallel and reconfiguration of the programmable logic circuit unit 3 is performed. That is, for example, as shown in FIG. 29, the latch 5L of each memory cell of the configuration memory 5s is connected to each register of the shift register 2d, and by sending a latch clock LCLK to the latch 5L, the shift register 2d To the configuration memory 5s at the same time in parallel.

  Then, when the configuration controller 2a detects the postamble code in the footer part following the data part, the configuration process is terminated.

[Configuration of Programmable Logic Circuit Device 10 Using Conventional Multicontext Technology Based on Serial Circuit Information]
FIG. 31 is a functional block diagram for explaining a configuration operation by serial circuit information to the programmable logic circuit device 10 by the multi-context technique shown in FIG. With reference to the block diagram shown in FIG. 31, the storage of circuit information in the configuration memory in the case of the conventional multi-context technique will be described.

  The circuit information input control unit 11 shown in FIG. 25 includes the configuration controller 11a, length count register 11b, selector 11c, and a plurality of shift registers 11d shown in FIG.

  In addition, the programmable logic circuit section shown in FIG. 25 is, for example, an FPGA type as shown in FIG. The configuration memory 15s for a plurality of columns and the circuit element 14s are divided into sets. In this example, each of the configuration memories 15s for each column is represented by a broken line in FIG. Provide a plane.

  The registers at each stage of each shift register 11d are connected to each memory cell in each plane of the configuration memory 15s in each column. Further, the selection of the configuration memory plane by the circuit information selection control unit 12 shown in FIG. 25 is performed by using the word lines W1, W2,..., WN of the memory plane of the configuration memory 15s in each column shown in FIG. Corresponds to the selection.

  FIG. 30 shows the connection between the shift register 11d and the configuration memory 15s. Each register of the shift register 11d is connected to memory cells 15s1, 15s2,..., 15sN of each configuration memory plane via switches SW1, SW2,. By selectively controlling the word lines W1, W2,..., WN, the switches SW1, SW2,. Then, by opening / closing the switches SW1, SW2,..., SWN, it is possible to select and control which circuit element 14 is configured based on the circuit information of which configuration memory plane.

  Also in this case, each shift register 11d is configured to have, for example, an FPGA type as shown in FIG. 24A, the number of stages corresponding to circuit information to the number of logical cells in one vertical column. One shift register is assigned to a plurality of logic circuit cells in one vertical column, and the shift registers 11d are provided by the number of logic cells in the horizontal direction.

  When the number of logic cells is large, one shift register 11d is provided for a plurality of columns of several columns to several tens of columns, and one shift register 11d is commonly used for the plurality of columns. Sometimes it is done.

  The size of one frame of the circuit information is, for example, the data amount for one shift register 11d.

  In the configuration of FIG. 31, the external storage device 9 stores, for example, circuit information of a plurality of processing circuits necessary for an application program, that is, a plurality of circuit information to be stored in a plurality of configuration memory planes. ing. When the first circuit information is read from the external storage device 9, the configuration controller 11a detects the preamble code in the header portion of the circuit information and starts the configuration process.

  The length count following the preamble code is stored in the length count register 11b. The value of the length count register 11b is decremented by 1 for each data shift of the shift register described below, and the shift register 11d operates until the value of the length count register 11b becomes 0. As a result, all data is sent to the shift register 11d.

  Data following the delimiter code is sent to the selector 11c. In the initial state, the selector 11c sends the data to the shift register 11d in the first column. The shift register 11d that has received the data sequentially shifts the data sent from the selector 11c. When the data is shifted to the end of the shift register 11d, the selector 11c switches the sending of data to the shift register 11d in the next column. The above operation is repeated, and the shift register 11d operates until the length counter value described above becomes 0, whereby the configuration data of the first circuit information is stored in the shift register 11d.

  When the shift register 11d is filled with data, the word line W1 shown in FIG. 29 is selected, and the first circuit information is transferred simultaneously and in parallel from the shift register 11d to the memory cell 15s1 of the first configuration memory plane. The

  When the configuration controller 11a detects the postamble code of the footer part FTs following the data part DTs, the configuration process of the first circuit information is completed.

  Subsequently, the second circuit information is read, and the shift register 11d is filled with data in the same procedure as the reading of the first circuit information, the word line W2 shown in FIG. 29 is selected, and the second configuration is selected from the shift register 11d. The second circuit information is transferred simultaneously and in parallel to the memory cell 2 of the memory plane.

  Thereafter, the same procedure is sequentially repeated to store each of the N pieces of circuit information in independent memory planes of the configuration memory 15.

  When reconfiguration is performed, the word line corresponding to the selected circuit information is selected, and then the latch clock LCLK is sent to the latch 15L, so that the configuration data can be simultaneously and parallelly transmitted from the memory cells of the selected memory plane. Is transferred for reconfiguration.

[Structure of circuit information; (II) Circuit information in parallel format]
FIG. 32 shows a structure of circuit information in a parallel format used in a conventional programmable logic circuit device. As illustrated, the circuit information includes a header part HDp, a data part DTp, and a footer part FTp. Within a programmable logic circuit device, circuit information in a certain bit width, for example, 32-bit parallel format, is serially transferred outside the programmable logic circuit device by dividing it in appropriate units, for example, 1 bit, 64 bits, etc. Parallel transmission of bus width and parallel memory access can be performed.

  The header part HDp includes a preamble code indicating the start of circuit information, an option code for setting a configuration parameter such as an input clock speed of the circuit information, a switch command for executing the set option and starting reading of data. Consists of.

  The data part DTp is composed of a plurality of frames as in the case of the serial format. The contents of each frame include a frame address FADR indicating a frame position in the configuration memory in which the configuration data CFGD is written, a data-in command DIN instructing writing of the configuration data CFGD, and the number of words read from the configuration data CFGD. It consists of an instructed word count WCNT and configuration data CFGD. The footer part FTp is composed of a postamble code that indicates the end of circuit information.

  All of the serial circuit information described above is handled as data, and the circuit information is passively read into the entire configuration memory by operating the shift register for the number of clocks specified by the length count. On the other hand, the circuit information in the parallel format is handled as data and commands, and the configuration data CFGD is partially written to the configuration memory portion indicated by the frame address FADR by the activation of the data-in command DIN. It is a feature.

[Configuration of Conventional Programmable Logic Circuit Device 1 Based on Parallel Circuit Information]
FIG. 33 is a functional block diagram for explaining a configuration operation by parallel circuit information to the conventional programmable logic circuit device 1 shown in FIG. The storage of circuit information in the configuration memory will be described with reference to a block diagram of a part of the configuration memory of the conventional programmable logic circuit device shown in FIGS.

  The circuit information input control unit 2 shown in FIG. 22 includes the configuration controller 2e, address generator 2f, and selector 2g shown in FIG. Further, in FIG. 33, the programmable logic circuit unit 3 shown in FIG. 22 is, for example, an FPGA type shown in FIG. The configuration memory 5s and the circuit element 4s are divided into groups.

  The circuit information frame is configured to include configuration data for a plurality of logic circuit cells for one column, as in the serial format.

  Then, as shown in FIG. 34, the bit lines of the configuration memory 5s in each column are connected to the selector 2g. The word line of the configuration memory 5s is connected to the address generator 2f.

  In the configuration of FIG. 33, when circuit information is read from the external storage device 9, the configuration controller 2e detects the preamble code of the header part HDp of the circuit information and starts the configuration process.

  Then, parameters for configuration are set by an option code following the preamble code. The next switch command executes the set option and starts reading data.

  First, the frame address FADR of a frame is read into the address generator 2f, and a bit line and a word line corresponding to the configuration memory 5s to which data is written are selected. Next, the data-in command DIN is activated, the number of data indicated by the word count WCNT is read from the configuration data CFGD, and the read data is written to the configuration memory 5s via the selector 2g. . This procedure is repeated for all frames.

  When the configuration controller 2e detects the postamble code of the footer part FTp following the data part DTp, the configuration process ends.

[Configuration of Programmable Logic Circuit Device 10 Using Conventional Multi-context Technology Based on Parallel Circuit Information]
FIG. 36 is a functional block diagram for explaining a configuration operation by parallel circuit information to the programmable logic circuit device 10 by the multi-context technique shown in FIG. The storage of circuit information in the configuration memory will be described with reference to a block diagram of a part of the configuration memory of the programmable logic circuit device according to the conventional multi-context technique shown in FIGS.

  The circuit information input control unit 11 shown in FIG. 25 includes the configuration controller 11e, address generator 11f, and selector 11g shown in FIG. The programmable logic circuit unit 13 shown in FIG. 25 includes the configuration memory 15s and the circuit element 14s shown in FIG.

  As in the case of FIG. 31 described above, the set of the configuration memory 15s and the circuit element 14s is divided into a plurality of columns. The configuration memory 15s in each column includes a plurality of memory planes as indicated by broken lines in FIG.

  In this example, the frame of the circuit information is configured to include configuration data for one column of the memory cell array for one plane, as in the serial format.

  As shown in FIG. 35, the bit lines of the configuration memory 15s (consisting of a plurality of memory planes (memory cell array)) in each column are connected to the selector 11g. In this case, the bit lines of the memory cell arrays of the plurality of memory planes are commonly connected to the selector 11g. The word line of the configuration memory 15s is common to the memory cell arrays of a plurality of memory planes, and is connected to the address generator 11f.

  The circuit information selection control unit 12 shown in FIG. 25 corresponds to the context selection of the configuration memory 15s shown in FIG.

  In the configuration of FIG. 36, when the first circuit information is read from the external storage device 9, the configuration controller 11e detects the preamble code of the header part HDp of the circuit information and starts the configuration process.

  Configuration parameters are set by an option code following the preamble code. Next, the set option is executed by the switch command, and reading of data is started.

  Then, the frame address FADR of the frame is read into the address generator 11f, and a bit line and a word line corresponding to the configuration memory 15s to which data is written are selected. At this time, as shown in FIG. 35, since a plurality of memory cell arrays are arranged for one column, for example, for the first circuit information, the bit line of the first memory cell array 15s1 is connected to the selector 11g. Selected by.

  Next, the data-in command DIN is activated, data corresponding to the number indicated by the word count WCNT is read from the configuration data CFGD, and written to the configuration memory 15s via the selector 11g. This procedure is repeated for all frames.

  When the configuration controller 11e detects the postamble code of the footer part FTp following the data part DTp, the configuration process of the first circuit information is completed.

  Subsequently, the second circuit information is read, and the circuit information is stored in the second memory cell array 15s2 selected by the selector 11g in the same procedure as the reading of the first circuit information. Thereafter, the same procedure is sequentially repeated, and N pieces of circuit information are stored in the configuration memory 15.

  When reconfiguration is performed, a context selection line corresponding to the selected circuit information is selected, and the circuit element 14s is configured.

[Processing by reconfigurable circuit using conventional multi-context technology]
Next, a procedure for reconfiguring circuit information to the programmable logic circuit device when performing one process using a plurality of circuits using the programmable logic circuit device according to the conventional multi-context technology as described above. This will be further described with reference to the explanatory diagram of FIG. 37 and the flowchart of FIG.

  As described above, the circuit information is usually configured in units called frames. However, in the example shown in FIG. 37, one circuit information is composed of five frames, and one process includes circuit information 1 and circuit information. This is a case where information 2 and circuit information 3 are used.

  That is, the three pieces of circuit information (circuit information 1, circuit information 2, and circuit information 3) are stored in the configuration memory 15 via the circuit information input control unit 11. For example, one circuit information is selected from three pieces of circuit information stored in the configuration memory 15 by the circuit information selection control unit 12 according to a selection signal generated by an application program, and the programmable logic circuit device 10 is selected according to the circuit information. Reconfigured.

  This reconfiguration procedure will be described with reference to the flowchart of FIG. 38 and the timing chart of FIG. In the timing chart of FIG. 39, it is assumed that the programmable logic circuit device is reconfigured in the order of circuit information 1, circuit information 2, and circuit information 3, and the processing ends.

  First, the circuit information input control unit 11 reads circuit information stored in an external storage device (not shown) or the like one by one and stores it in the configuration memory 15 (step S101). At this time, each time the circuit information is read, the remaining capacity of the configuration memory 15 is checked (steps S102 and S103). If the configuration memory 15 becomes full before reading all the circuit information, an error is indicated. The operation is detected and the operation is terminated (step S104).

  When the circuit information input control unit 11 stores all three pieces of circuit information in the configuration memory 15, the circuit information selection control unit 12 monitors the selection signal (step S105). When the circuit information selection control unit 12 detects that the selection signal has been switched in accordance with, for example, the application program, it determines which of the three pieces of circuit information has been selected (step S106), and determines the switched selection signal. Corresponding circuit information is read from the configuration memory 15, and a programmable logic circuit unit (not shown) is reconfigured according to the circuit information (step S107 or step S108 or step S109).

  Thereafter, as long as the processing by the programmable logic circuit device 10 continues, the circuit information selection control unit 12 continues to monitor the selection signal, and the circuit information is switched every time the selection signal is switched. When the process by the programmable logic circuit device 10 is finished, the above-described reconfiguration procedure is finished regardless of the selection signal.

  When the processing by the programmable logic circuit device 10 ends, generally, the programmable logic circuit device is reconfigured with the circuit information selected last unless the power supply to the programmable logic circuit device 10 is cut off. The state is maintained.

  The above processing will be further described with reference to the timing chart of FIG. That is, when the processing is in the execution state, first, the three pieces of circuit information 1, 2, and 3 are read into the configuration memory 15. When reading is completed and a circuit information selection instruction is issued, the configuration memory plane in which the circuit information instructed to be selected is stored is switched and the circuit information is read and read. The programmable logic circuit unit is reconfigured based on the circuit information.

  In FIG. 39, the circuit information 3 continues to be configured even after the completion of execution, as described above, generally, as long as the power supply is not cut off when the processing is completed, the programmable logic circuit device is generally used. This is because the state reconstructed with the circuit information selected last is held.

[Specific examples of multi-context technology]
As one of the multi-context technologies as described above, there is an example of “multi-function programmable logic device” disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2-130023). This will be described as Conventional Example 1 with reference to FIG.

  FIG. 40 shows a configuration diagram of a multi-function programmable logic device. This device includes a programmable logic array 21, a switch setting PROM 22 composed of SRAM, and a selection circuit 23.

  The switch setting PROM 22 can store M sets of N-bit circuit information corresponding to the circuits configured in the programmable logic array 21. The circuit configuration of the programmable logic array 21 is determined by a set of circuit information selected by the selection circuit 23 among the M sets of circuit information stored in the switch setting PROM 22. That is, by switching the circuit information selected by the selection circuit 23, the circuit configuration of the programmable logic array 21 can be reconfigured.

  As another example of the multi-context technology, there is an example of Non-Patent Document 1 ("A Time-Multiplexed FPGA" published in FCCM'97 (FPGAs for Custom Computing Machines 1997)). This will be described as Conventional Example 2 with reference to FIG.

  FIG. 41 shows the configuration of the announced time division drive FPGA. This time-sharing drive FPGA is an improvement of the Xilinx XC4000E in the United States, and includes eight sets of configuration memory 25 composed of SRAM that determines logic cells and internal wiring of the circuit element 24. Yes. Circuit information corresponding to different circuit configurations is stored in each of the configuration memories 25. By switching these configuration memories 25, the circuit configuration of the FPGA can be reconfigured in a time division manner.

  As shown in the conventional example 1 and the conventional example 2 described above, the multi-context technique stores a plurality of pieces of circuit information in the configuration memory in advance, so that the circuit reconfiguration time can be shortened. To do.

  However, since a plurality of planes or a plurality of configuration memories are required in the programmable logic circuit device to store circuit information, the circuit scale of the programmable logic circuit unit is increased. When the circuit scale is increased, the load capacity of the circuit element is increased, thereby causing problems that the circuit performance is lowered and the power consumption is increased. Further, when the circuit scale is increased, there is a problem that the manufacturing cost of the programmable logic circuit device is increased.

  Since a programmable logic circuit device is usually manufactured by a CMOS process, an SRAM that can be manufactured by the same CMOS process is used as a configuration memory. In Conventional Example 1 and Conventional Example 2, SRAM is used as a configuration memory. Since SRAM requires six transistors to store one bit, if the number of pieces of circuit information that can be stored in the programmable logic circuit device is increased, the circuit scale of the programmable logic circuit section is significantly increased.

  The problem of such a large circuit scale is disclosed in Non-Patent Document 2 (“A First Generation DPGA Implementation”, published in FPD '95 (Third Canadian Works of Programmable Devices 1995)). This is somewhat mitigated by using a DRAM consisting of three transistors per bit as a configuration memory. This will be described as Conventional Example 3 with reference to FIG.

  FIG. 42 shows the logic cell structure of the announced DPGA. The logic cell includes a 4 × 32-bit DRAM 31 that can store four sets of configurations, four 8-input multiplexers 32-35, a 4-input lookup table 36, a flip-flop 37, and a selector 38 that switches the output.

  Of the outputs of the 32-bit DRAM 31, 12 bits determine the state of the four 8-input multiplexers 32 to 35, 16 bits determine the state of the 4-input lookup table 36, 1 bit determines the state of the selector 38, and the remaining 3 Bit is reserved. The four sets of DRAMs 31 store different circuit information, and different circuits can be configured by switching the memory output.

  As described above, since the DRAM 31 is composed of three transistors per bit, the conventional example 3 can alleviate the problem of an increase in circuit scale in the multi-context technology.

  Furthermore, recent advances in semiconductor device fabrication technology have made it possible to fabricate a DRAM composed of a CMOS circuit and one transistor per bit on a single device. This semiconductor fabrication technique is called a DRAM mixed process. In order to store one bit, an SRAM composed of CMOS requires six transistors, and a DRAM composed of CMOS requires three transistors, whereas a DRAM based on a DRAM mixed process requires 1 transistor. Only a single transistor is required.

  Therefore, the disadvantage of the multi-context technology described above that an extra configuration memory area is required to store circuit information can be further improved by using a one-transistor DRAM by a DRAM mixed process as the configuration memory. it can.

  As an example of this, there is an example shown in Non-Patent Document 3 (“An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration” published in Symposium on VLSI Circuit 1997). This will be described as Conventional Example 4 with reference to FIG.

  FIG. 43 shows the announced DRAM-FPGA logic element and the structure of the DRAM element. The DRAM element 41 composed of 256 × 256 cells is surrounded by four logic elements 42 to 45. Yes. One logic element is reconstructed with 64-bit circuit information. 64 bits of bit lines drawn out by 128 bits to the left and right via sense amplifiers are connected to the logic elements 42 to 45, respectively.

  The circuit information output to the left and right bit lines is switched by selecting word lines drawn 128 bits up and down via a word driver. That is, the DRAM-FPGA can store 256 sets of circuit configurations by using the DRAM element 41 as a memory circuit.

  As shown in the above-described conventional example 4, by using a DRAM mixed process, a memory circuit is manufactured with a one-transistor DRAM, so that an extra configuration memory circuit area is required to store circuit information. It is possible to greatly alleviate the shortcomings of the context technology.

  However, since the gate oxide film of the transistor used in the DRAM circuit portion needs to be thicker than the gate oxide film of the transistor used in the CMOS circuit portion, it must be formed separately. For this reason, a manufacturing process increases, and the new manufacturing cost of a programmable logic circuit device becomes high, or a manufacturing yield falls. Further, in order not to increase the number of manufacturing steps, when a thick oxide film is used in common with the manufacturing steps, another problem that the performance of the CMOS circuit portion deteriorates is caused.

The above prior art documents are as follows.
JP-A-2-130023 "A Time-Multiplexed FPGA" announced at FCCM '97 (FPGAs for Custom Computing Machines 1997) “A First Generation DPGA Implementation” announced at FPD '95 (Third Canadian Works of Field Programmable Devices 1995) “An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration” presented at Symposium on VLSI Circuit 1997

  As described above, in an information processing system using reconfigurable computing technology that uses a cache logic technology to process a part of processing by an application program with a circuit configured by a programmable logic circuit device, the circuit is reconfigured. The hardware processing by the programmable logic circuit device, which originally has a faster processing speed than the software processing, takes more time than the software processing when compared with the total processing time including the circuit reconfiguration time. There is a problem that there is.

  Multi-context technology, which is one means to solve this problem, can reduce the reconfiguration time of the circuit, but requires an extra configuration memory area for storing multiple circuit information. There is a drawback that the circuit scale of the programmable logic circuit section is increased.

  When the circuit scale is increased, the load capacity of the circuit element is increased, thereby causing problems that the circuit performance is deteriorated and the power consumption is increased. Further, when the circuit scale is increased, there is a problem that the manufacturing cost of the programmable logic circuit device is increased.

  In order to reduce the configuration memory area, a one-transistor DRAM circuit manufactured by a DARM mixed process is used as the memory circuit instead of an SRAM circuit generated by a CMOS process. As described above, the number of manufacturing processes increases, which causes a new problem that the manufacturing cost of the programmable logic circuit device increases and the manufacturing yield decreases. Further, if the manufacturing process is made common and the thick oxide film of the DRAM part is used for the CMOS circuit part in order not to increase the manufacturing process, another problem such as deterioration of the performance of the CMOS circuit part is caused.

  In view of the above, the present invention provides a high-speed circuit without using a configuration memory that stores a plurality of circuit information that causes a decrease in circuit performance, an increase in power consumption, an increase in manufacturing processes, an increase in manufacturing cost, and the like. It is an object of the present invention to provide a programmable logic circuit device that can be reconfigured.

In order to solve the above problem, in a programmable logic circuit device according to the invention of claim 1,
A programmable logic circuit unit comprising a circuit element and a configuration memory connected to the circuit element, the circuit being configured based on circuit information written in the configuration memory;
A plurality of circuit information for sequentially configuring a plurality of circuits in the programmable logic circuit section, and circuit information storage means different from the configuration memory;
Circuit information writing means for writing the plurality of circuit information to the circuit information storage means;
The circuit information of one circuit to be generated in the programmable logic circuit unit designated by the designation information is one or a plurality of circuit information among a plurality of circuit information stored in the circuit information storage means. Circuit information editing means to generate using
Control means for writing circuit information of the one circuit generated by the circuit information editing means to the configuration memory;
It is characterized by providing.

The invention according to claim 2 is the programmable logic circuit device according to claim 1,
The circuit information storage means and the circuit information editing means are provided separately from the programmable logic circuit section.

According to a third aspect of the present invention, in the programmable logic circuit device according to the first aspect,
The circuit information storage means and the circuit information editing means read circuit information for this purpose into a part of the configuration memory, thereby generating a part of the circuit elements of the programmable logic circuit section.

Moreover, invention of Claim 4 is the programmable logic circuit apparatus in any one of Claims 1-3,
The circuit information stored in the circuit information storage means is compressed, and the circuit information editing means decompresses the compression to generate circuit information designated by the designation information.

  In the invention of claim 1 having the above-described configuration, the plurality of pieces of circuit information are temporarily stored in the circuit information storage means rather than being stored in the configuration memory as in the multi-context technique. Then, circuit information to be reconfigured is read from the circuit information storage means, edited into circuit information in a format to be written in the configuration memory by the circuit information editing means, and transferred to the configuration memory.

  Therefore, according to the first aspect of the present invention, the configuration memory area only needs to be provided with a memory area that can store one circuit information as in the conventional general programmable logic circuit device. In this case, it is possible to avoid the disadvantage that the circuit scale of the programmable logic circuit section becomes large.

  Instead, circuit information storage means is required. In the invention of claim 1, the circuit information stored in the circuit information storage means is edited by the circuit information editing means and then transferred to the configuration memory. Therefore, the circuit information stored in the circuit information storage means does not need to be stored in the configuration memory directly, and can have a small amount of data.

  For example, as in the invention of claim 4, by compressing the circuit information and decompressing the compressed information by the circuit information editing means, the memory capacity of the circuit information storage means can be further reduced. Is.

  The circuit information storage means and the circuit information editing means can be configured outside the programmable logic circuit section as in the invention of claim 2, or within the programmable logic circuit section as in the invention of claim 3. It can also be configured by reading the circuit information.

  Particularly, in the case of claim 3, there is an effect that the programmable logic circuit device according to the present invention can be realized by using a conventional programmable logic circuit device.

  According to the present invention, it is possible to realize a technique equivalent to a multi-context technique using a programmable logic circuit unit that does not require an extra configuration memory for storing a plurality of circuit information as in the conventional multi-context technique. This can be used to reduce the reconfiguration time of the programmable logic circuit device, and even when compared with the total processing time including the circuit reconfiguration time, it is possible to realize hardware processing with a shorter processing time than software processing. As a result, it is possible to realize a high-speed and downsized information processing system using reconfigurable computing based on cache logic technology.

  In addition, unlike the conventional multi-context technology, an extra configuration memory is not required in the programmable logic circuit section, so that the circuit performance is deteriorated due to an increase in wiring load capacity caused by arranging the extra configuration memory. A programmable logic circuit device equivalent to that based on the multi-context technology can be realized without increasing the power consumption.

  In the present invention, since the compressed circuit information is stored in the circuit information storage unit, the same circuit information is stored in the programmable logic circuit device with a smaller memory capacity than the conventional multi-context technology. As a result, a technology equivalent to the multi-context technology can be realized with a smaller circuit scale than a pro-programmable logic circuit device based on the conventional multi-context technology without using DRAM technology which causes an increase in manufacturing process and a decrease in circuit performance. be able to.

  In addition, the programmable logic circuit device according to the present invention can use the programmable logic circuit portion having the same structure as the conventional ordinary programmable logic circuit device, and therefore can be easily realized by using the design of the conventional programmable logic circuit device. Can do.

  In addition, the circuit information storage unit and the circuit information editing unit of the programmable logic circuit device according to the present invention are configured in the conventional programmable logic circuit device by reading the circuit information, so that a conventional circuit device is not newly manufactured. There is also an advantage that the programmable logic circuit device of the present invention can be realized by using the programmable logic circuit device.

  Hereinafter, several embodiments of a programmable logic circuit device according to the present invention will be described with reference to the drawings while comparing with a programmable logic circuit device based on the conventional multi-context technique described above.

  In the embodiments described below, in the information processing system using the above-described reconfigurable computing technology, a plurality of circuits for executing part or all of the processing by the application program are programmable logic circuit devices. It is an example in the case of comprising.

  That is, circuit information of a plurality of processing circuits required by an application program is stored in an external storage device in advance, and the plurality of circuit information read from the external storage device is stored in the programmable logic circuit device as necessary. The necessary circuits are sequentially reconfigured in the programmable logic circuit device, and the necessary processing is executed.

[First Embodiment]
[First Structure of Programmable Logic Circuit Device According to the Invention]
The programmable logic circuit device according to the first embodiment includes the first structure of the programmable logic circuit device according to the present invention. FIG. 1 shows a configuration of a programmable logic circuit device 100 according to the present invention having the first structure. A circuit information input control unit 101 for reading a plurality of circuit information from, for example, an external storage device (not shown). A circuit information storage unit 102 that temporarily stores a plurality of read circuit information, a circuit information editing unit 103 that selects and edits necessary circuit information from the plurality of circuit information, and a circuit information input control unit 101 And a programmable logic circuit unit 104 that realizes a circuit function in accordance with the edited circuit information read through the interface.

  In the programmable logic circuit device 100 having the first structure, the circuit information input control unit 101 also has a function of circuit information writing means for writing a plurality of circuit information in the circuit information storage unit 102. The circuit information input control unit 101 also serves as a control unit that writes circuit information of one circuit generated by the circuit information editing unit into the configuration memory of the programmable logic circuit unit 104.

  That is, the programmable logic circuit device 100 having the first structure includes a circuit information input control unit 101 and a programmable circuit similar to the circuit information input control unit 2 and the programmable logic circuit 3 of the conventional programmable logic circuit device 1 shown in FIG. In addition to the logic circuit unit 104, a circuit information storage unit 102 and a circuit information editing unit 103 are provided therein.

  The detailed structure of the programmable logic circuit unit 104 is the same as that of the programmable logic circuit unit of the conventional programmable logic circuit device shown in FIG. 22, and is the same as that shown in FIGS. That is, in the programmable logic circuit unit 104, the configuration memory does not include a plurality of memory planes, unlike the programmable logic circuit unit 15 based on the conventional multi-context technique shown in FIG.

  That is, the programmable logic circuit unit 104 is connected to the circuit element 105 including the input / output unit, the logic circuit cell, and the wiring unit as shown in FIGS. And a configuration memory 106 for storing one piece of circuit information.

  Since the configuration memory built in the programmable logic circuit unit 104 does not have a plurality of configuration memories or a plurality of memory planes, the programmable logic circuit device 100 of this embodiment is shown in FIG. The circuit information selection control unit 12 like the conventional programmable logic circuit device 10 based on the multi-context technique is not provided.

  And the programmable logic circuit device 100 in the case of this embodiment is also as shown in FIG. 24 (A) by the connection form of the circuit element 105 of the programmable logic circuit part 104 like the conventional programmable logic circuit device 1. An FPGA type and a CPLD type as shown in FIG.

  In any structure, in the programmable logic circuit device 100 according to the first embodiment, when a plurality of pieces of circuit information are read into the programmable logic circuit device 100, the plurality of pieces of circuit information are stored in the circuit information storage unit 102, After being edited by the information editing unit 103, the information is written in the configuration memory 106 by the circuit information input control unit 101. Then, according to the circuit information written in the configuration memory 106, the function and connection state of the circuit element 105 are determined.

[Configuration in the first embodiment]
Next, the configuration method in the first embodiment will be described in comparison with the case of a programmable logic circuit device based on a conventional multi-context technique. In the first embodiment, the configuration is performed using serial circuit information.

  FIG. 2 is a diagram for explaining circuit information and its editing operation in the case of the first embodiment. The operation of the programmable logic circuit device 100 according to the first embodiment will be described with reference to FIG. In the example of FIG. 2, three circuits based on the same three pieces of circuit information 1, 2, and 3 shown in FIG. 37 described in the configuration of the programmable logic circuit device 10 according to the conventional multi-context technique described above are reproduced. It is an example of the procedure to comprise.

  FIG. 2A shows a frame configuration of the three circuit information 1, 2, and 3 of the conventional example shown in FIG. As shown in FIG. 2 (A), the circuit information 1, 2, and 3 are each composed of 5 frames. When the frame structure of the circuit information is examined in more detail, the following configuration is obtained. It has become.

  The circuit information report 1 includes two types of frames, a frame (1-A) and a frame (1-B). One of the frames (1-A) and four of the frames (1-B) are included. It consists of a total of 5 frames.

  The circuit information 2 is composed of four types of frames (1-A, 2-A, 2-B, 2-C), and the frame (1-A) is a frame constituting the circuit information 1 Same as (1-A). The circuit information 2 is composed of two frames (1-A) and other frames, each of which is a total of five frames.

  The circuit information 3 is composed of three types of frames (2-A, 2-B, 3-A), of which the frame (2-A) and the frame (2-B) constitute circuit information 2. It is the same as the frame to be played. The circuit information 3 is composed of three frames (2-A) and one frame (2-B) and one frame (3-A).

  In the first embodiment, three pieces of circuit information 1, 2, and 3 for reconfiguring the same circuit as shown in FIG. 37 are considered in consideration of frame repetition and frame reference of other circuit information. Thus, it is compressed so as to be composed of a smaller number of frames.

  That is, the circuit information 1 is composed of two frames, a frame (1-A) and a frame (1-B), as shown in FIG. At this time, reference information that the frame is repeated three times is added to the frame (1-B) of the circuit information 1. Such a frame including repeated reference information is referred to as a repeat frame in this specification.

  As shown in FIG. 2B, the circuit information 2 is composed of four frames: a frame (2-A), a frame (1-A), a frame (2-B), and a frame (2-C). At this time, reference information that the frame data is the same as the frame (1-A) of the circuit information 1 is added to the frame (1-A) of the circuit information 2. A frame including reference information of another circuit information frame is referred to as a reference frame in this specification.

  As shown in FIG. 2B, the circuit information 3 includes three frames of a frame (2-A), a frame (2-B), and a frame (3-A). At this time, the frame data (2-A) and the frame (2-B) of the circuit information 3 are the same as the frames (2-A) and (2-B) of the circuit information 2, respectively. The reference frame is added with the reference information. Further, the frame (2-A) of the circuit information 3 has a repeat frame configuration to which reference information is added that the frame is repeated three times.

[Specific Example of Circuit Information in Serial Format According to the Present Invention]
FIG. 3 shows an example of the structure of serial circuit information according to the present invention. Like the conventional serial format circuit information shown in FIG. 27, the serial format circuit information of this example is also composed of a header portion HDs, a data portion DTs, and a footer portion FTs as shown in FIG. Is done. As described above, in the programmable logic circuit device 100, serial-format circuit information is handled as serial data, but parallel transmission and parallel memory access are performed by dividing the serial information into appropriate units (for example, 8 bits). be able to.

  As shown in FIG. 3A, the header portion HDs includes a preamble code indicating the start of circuit information, a length count indicating the data amount of the circuit information, and a delimiter code indicating the end of the header portion. The footer FTs is composed of a postamble code indicating the end of the circuit information, as in the conventional case of FIG.

  The length count is used as information for transfer to the shift register as in the case of the conventional programmable logic circuit device 1, and in this embodiment, the length count is edited by the circuit information editing unit 103. Also used as instruction information.

  In the case of this embodiment, the data part DTs is composed of a plurality of frames. However, the data portion DTs is different from the conventional case of FIG. There are three types of frames constituting the data part: a normal frame having the same structure as the conventional example, the repeat frame described above, and the reference frame described above.

  That is, as shown in FIG. 3B, the normal frame is the same as the frame used in the conventional circuit information, and the start field bit data STB indicating the start of the frame and the configuration stored in the configuration memory. It consists of data CFGD and stop field bit data ENB indicating the end of the frame.

  As shown in FIG. 3C, the repeat frame includes start field repeat data STrp indicating the start of the repeat frame, configuration data CFGD stored in the configuration memory, and a reference count indicating the number of repetitions of the same frame data. It consists of RCNT and stop field bit data ENB indicating the end of the frame. The start field repeat data STrp includes identification information indicating that it is a repeat frame. The number of normal frames indicated by the reference count RCNT is generated from this repeat frame by the procedure described later.

  As shown in FIG. 3D, the reference frame includes start field reference data STref indicating the start of the frame, a reference address RADR indicating the address of another frame to be referenced in the circuit information storage unit 102, and a reference frame. It consists of a reference count RCNT indicating the number of repetitions, a reference offset ROFS indicating a relative address from which data is read in another reference destination frame, and stop field bit data ENB indicating the end of the frame. The start field reference data STref includes identification information indicating that it is a reference frame.

  A normal frame having configuration data stored in the circuit information storage unit 102 calculated from the reference address RADR and the offset address ROFS from this reference frame by the procedure described later is indicated by the reference count RCNT. Are generated.

  In addition to the normal frame, having two types of frames, a repeat frame and a reference frame, is a feature of the circuit information in the serial format used in this embodiment. These three types of frames are recognized by the circuit information editing unit 103 by having different start field codes as described above.

  As described above, one feature of the present invention is that the data size of circuit information (the number of frames constituting the circuit information) is small even when the circuit information reconfigures the same circuit. This circuit information having a small data size is referred to as compressed circuit information.

  In the example shown in FIG. 37 described above, one circuit information is composed of 5 frames (normal frame), and 3 circuit information (circuit information 1, circuit information 2, circuit information 3) is provided via the circuit information input control unit 2. Is stored in the configuration memory 15. Therefore, the configuration memory 15 of the programmable logic circuit device 10 according to the conventional multi-context technique shown in FIG. 25 must have a capacity capable of storing at least 15 frames in this example.

  That is, in general, the configuration memory of the programmable logic circuit device using the multi-context technology is different from the configuration memory of the conventional conventional programmable logic circuit device as shown in FIG. "Requires twice as much storage capacity.

  On the other hand, in the first embodiment, for example, a plurality of circuit information read from an external storage device is temporarily stored in the circuit information storage unit 102. Then, the circuit information editing unit 103 extracts the compressed circuit information from the circuit information storage unit 102 in accordance with the circuit information selection signal, and the extracted circuit information is stored in a configuration similar to the conventional one having a capacity for storing one circuit information. The circuit information stored in the storage memory 106 is edited.

  Next, the circuit information input control unit 101 stores the edited circuit information in the configuration memory 106, and the circuit selected as the circuit element 105 is reconfigured according to the circuit information.

  Another feature of the present invention is that the capacity of the configuration memory 106 of the programmable logic circuit unit 104 is the same as that of the conventional programmable logic circuit device regardless of the number of pieces of circuit information stored in the programmable logic circuit device 100. It is. In the case of the above-described example in which the circuit information in the normal frame format is composed of 5 frames, the configuration memory 106 only needs to have a capacity capable of storing 5 frames corresponding to 1 circuit information.

  Therefore, the circuit capacity of the configuration element of the programmable logic circuit device according to the conventional multi-context technology is large, and the load capacity of the circuit element is increased, so that the circuit performance is reduced and the power consumption is increased. The problem is solved by this first embodiment.

  In the first embodiment, since the circuit information is compressed as shown in FIG. 2B as described above, the circuit information storage unit 102 is necessary for the normal frame structure. A plurality of necessary circuit information can be stored with a capacity smaller than the capacity. Incidentally, in the case of the above example, when storing in the normal frame format, the circuit information storage unit 102 requires a capacity of 15 frames, as shown in FIG. A capacity for storing nine frames is sufficient.

[Configuration of Programmable Logic Circuit Device 100 of First Embodiment Based on Serial Circuit Information]
FIG. 4 is a functional block diagram for explaining a configuration operation by serial circuit information to the programmable logic circuit device of the first embodiment shown in FIG. The storage of the circuit information in this case in the configuration memory will be described with reference to the block diagram shown in FIG.

  In FIG. 4, the circuit information input control unit 101 shown in FIG. 1 includes a configuration controller 101a, a length count register 101b, a selector 101c, and a plurality of shift registers 101d.

  Further, in FIG. 4, the circuit element 105 and the configuration memory 106 of the programmable logic circuit unit 104 shown in FIG. 1 are, for example, an FPGA type as shown in FIG. These logic circuit cells are divided into a plurality of columns.

  That is, it is configured by a plurality of columns as a set of a configuration memory 106 s having a capacity capable of storing circuit information for a plurality of logic circuit cells in one vertical column and circuit elements 105 s connected thereto. In this case, the circuit information of one normal frame is the size of the circuit information for a plurality of logic circuit cells in one vertical column.

  The registers at each stage of each shift register 101d are connected to each memory cell of the configuration memory 106s in each column. Accordingly, each shift register 101d is configured to have, for example, an FPGA type as shown in FIG. 24A, the number of stages of circuit information corresponding to the number of logic circuit cells in one vertical column. One shift register is assigned to a plurality of logic circuit cells in one vertical column, and shift registers 101d are provided by the number of logic circuit cells in the horizontal direction.

  When the number of logic circuit cells is large, one shift register 101d is provided for a plurality of columns of about several to tens of columns, and one shift register 101d is commonly used for the plurality of columns. May be configured. Note that the size of the normal frame of the circuit information is the data amount for one shift register 101d.

  The circuit information storage unit 102 shown in FIG. 1 corresponds to the configuration cache memory 102M, and the function of the circuit information editing unit 103 is incorporated in the configuration controller 101a.

  In the configuration of FIG. 4, when circuit information is read from the external storage device 9, it is stored in the configuration cache memory 102M via the configuration controller 101a.

  When the configuration controller 101a receives a context selection instruction, circuit information corresponding to the instruction is read from the configuration cache memory 102M to the configuration controller 101a. The configuration controller 101a detects the preamble code of the header part HDs of the read circuit information and starts circuit information editing processing.

  The length count following the preamble code is stored in the length count register 101b. The value of the length count register 101b is decremented by 1 every data shift of the shift register 101d described below, and the shift register 101d operates until the value of the length count register 101b becomes 0. As a result, all data is sent to the shift register 101d.

  The data part DTs following the delimiter code is converted from a frame compressed as a repeat frame or a reference frame into a normal frame in a decompressed state according to a procedure described later, and is sent to the selector 101c.

  In the initial state, the selector 101c sends data to the shift register 101d in the first column. The shift register 101d sequentially shifts data sent from the selector 101c. When the data is shifted to the end of the shift register 101d, the selector 101c switches the data transmission to the shift register 101d in the next column. The shift register 101d operates until the length counter value described above becomes 0, whereby all data is stored in the shift register 101d.

  When the shift register 101d is filled with data, the data is transferred to the configuration memory 106s simultaneously and in parallel, and the programmable logic circuit unit 104 is reconfigured. In this case, for example, as shown in FIG. 29 described above, the latch of each memory cell of the configuration memory 106s is connected to each register of the shift register, and the latch clock LCLK is sent to the latch from the shift register. Data is transferred to the configuration memory in parallel.

  When the configuration controller 101a detects the postamble code of the footer part FTs following the data part DTs, the configuration process ends.

  As in the case of the above-described example, the reconfiguration procedure described above is performed when the processing instructed by the application program is performed by three pieces of circuit information of circuit information 1, circuit information 2, and circuit information 3, as shown in FIG. This will be described with reference to the flowcharts of FIGS. 7 and 8 and the timing chart of FIG. In the timing chart of FIG. 6, it is assumed that the programmable logic circuit device is reconfigured in the order of the circuit information 1, the circuit information 2, and the circuit information 3, and the processing is completed.

  First, the circuit information input control unit 101 reads circuit information stored in an external storage device (not shown in FIG. 1) or the like one by one and stores it in the circuit information storage unit 102 (step S201). . At this time, every time circuit information is read, the remaining capacity of the circuit information storage unit 102 (configuration cache memory 102M) is checked (steps S202 and 203), and the circuit information storage unit 102 is full before reading all circuit information. When the error has occurred, an error is detected and the operation is terminated (step S204).

  When the circuit information input control unit 101 stores all circuit information in the circuit information storage unit 102, the circuit information editing unit 103 (a part of the configuration controller 101a) monitors the selection signal (step S205). When the circuit information editing unit 103 detects that the selection signal has been switched by, for example, a user's selection operation, the circuit information editing unit 103 determines which of the three pieces of circuit information has been selected (step S206), and has been switched. Circuit information corresponding to the selection signal is read from the circuit information storage unit 102 (step S207, step S208, or step S209).

  Next, it is determined from the read circuit information whether there is a repetition of a frame (repeat frame) or a frame reference (reference frame) of other circuit information, and it is determined that the read circuit information includes the repeat frame or reference frame. In some cases, these repeat frames and reference frames are resolved as shown in the flowcharts of FIGS. 7 and 8 to be described later, thereby solving the compressed state of the circuit information and configuring the circuit information after the compressed state is solved. Transfer to the storage memory 106 (step S210).

  For example, as illustrated in FIG. 2D, the circuit information editing unit 103 may repeat the same frame data after the frame (1-B) when the frame (1-B) is repeated four times as in the circuit information 1. Is added three times. When the frame (1-A) of the circuit information 1 is referred to by the second frame as in the circuit information 2, the circuit information editing unit 103 sends the frame of the circuit information 1 from the circuit information storage unit 102. The data (1-A) is taken out and inserted into the second frame of the circuit information 2. Further, when the frame (2-A) and the frame (2-B) of the circuit information 2 are referred to by the first, second, third, and fourth frames as in the circuit information 3, The circuit information editing unit 103 extracts the data of the frame (2-A) and the frame (2-B) of the circuit information 2 from the circuit information storage unit 102, and the first, second, and third frames of the circuit information 3 And inserted into the fourth frame.

  As described above, when all the frame data that has been released from the compressed state and converted into circuit information including normal frames is transferred to the configuration memory 106 and stored, it is designated to the programmable logic circuit unit 104. Circuit reconfiguration is complete. When the read circuit information does not include a repeat frame or a reference frame, the circuit information is sequentially transferred to the configuration memory 106 as it is, and the reconfiguration of the designated circuit is completed.

  Thereafter, as long as the process by the programmable logic circuit device 100 continues, the circuit information editing unit 103 continues to monitor the selection signal (the processes after Step S211 and Step S205). When the process by the programmable logic circuit device 100 ends (step S211), the reconfiguration procedure ends regardless of the selection signal.

  When the processing by the programmable logic circuit device 100 is completed, generally, the state reconfigured with the circuit information selected last is held unless the power supply to the programmable logic circuit device 100 is cut off. .

  The above processing will be further described with reference to the timing chart of FIG. That is, when the process is in an execution state, first, the three pieces of circuit information 1, 2, and 3 are read into the circuit information storage unit 102. When reading is completed and a circuit information selection instruction is issued, the circuit information instructed to be selected is transferred from the circuit information storage unit 102 to the circuit information editing unit 103, and necessary editing is performed. Then, the edited circuit information is stored in the configuration memory 106, and the programmable logic circuit unit 104 is reconfigured based on the circuit information.

  In FIG. 6, the circuit information 3 continues to be configured even after the execution is completed. As described above, when the processing is completed, generally, the programmable logic circuit device is used unless the power supply is cut off. This is because the state reconstructed with the circuit information selected last is held.

  Note that if the shift register 101d is present in all the pairs of the configuration memory 106s and the circuit element 105s, the edited circuit information is written in the shift register 101d, so that the configuration memory 106 Stored.

  However, when the shift register 101d is common to a plurality of columns (plural sets) of configuration memories 106s and circuit elements 105s, the circuit information editing unit 103 needs to include a memory unit that holds the editing result. There is.

[Repeat Frame and Reference Frame Cancellation Processing in Circuit Information Editing Unit 103]
With reference to FIGS. 7 and 8, the editing process including the repeat frame and reference frame cancellation process in step S210 of FIG. 5 and the transfer process to the configuration memory 106 will be described.

  First, the circuit information editing unit 103 reads the first frame (step S301), and determines the type of the frame by the start field of the frame (step S302). That is, when the start field is the start field bit data STB, it is determined that the frame is a normal frame. When the start field is the start field repeat data STrp, it is determined that the frame is a repeat frame, and the start reference data STref. Sometimes it is determined that it is a reference frame.

  If the result of determination of the frame type in step S302 is that the read frame is a normal frame, the frame data is sent out as it is (step S303).

  As a result of determining the type of frame in step S302, if the read frame is a repeat frame, the reference count RCNT is read (step S304). Next, since the output is sent as normal frame data, start field bit data STB, configuration data CFGD, and stop field bit data ENB are sent out (steps S305, S306, S307), and 1 is subtracted from the reference count RCNT (step S305). Step S308).

  Then, it is determined whether or not the value of the reference count RCNT has become 0 (step S309). If not 0, the procedure from step S305 to step S308 is repeated. When the reference count RCNT becomes 0, it is determined whether or not all the processes have been completed (step S310). If not completed, the process returns to step S301 and the above steps are repeated. When all the processes are finished, this processing routine is finished.

  As described above, the procedure from step S305 to step S308 is repeated until the reference count RCNT becomes 0, so that the number of normal frames indicated by the reference count RCNT is generated from the compressed repeat frame.

  As a result of determining the type of frame in step S302, when the read frame is a reference frame, the reference count RCNT, the reference address RADR, and the reference offset ROFS are read (steps S311, S312 and S313 in FIG. 8).

  Next, the reference address RADR indicating the position of the reference destination frame in the circuit information storage unit 102 is added to the reference offset ROFS indicating the relative position of the configuration data CFGD to be referred to in the reference destination frame for reference. The absolute address of the circuit information storage unit 102 of the configuration data is calculated (step S314).

  Next, the configuration data located at the absolute address is read from the circuit information storage unit 102 and temporarily stored in the circuit information editing unit 103 (step S315).

  Next, as in the case of the repeat frame, since the output is sent as normal frame data, start field bit data STB, configuration data CFGD, and stop field bit data ENB are sent out sequentially (steps S316, S317, S318), 1 is subtracted from the reference count RCNT (step S319). Then, the procedure from step S316 to step S319 is repeated until the reference count RCNT becomes 0 (step S320).

  When the reference count RCNT becomes 0, it is determined whether or not all the processes have been completed (step S310). If not completed, the process returns to step S301 and the above steps are repeated. When all the processes are finished, this processing routine is finished.

  As described above, the procedure from step S316 to step S319 is repeated until the reference count RCNT becomes 0, so that the normal frame having the referenced configuration data is the reference count RCNT from the compressed reference frame. Only the number indicated is generated.

  By performing the above procedure for all frames, circuit information (circuit information consisting only of normal frames) that has been decompressed is generated from circuit information compressed by repeat frames and reference frames.

  Then, the circuit information that has been uncompressed as described above is sent from the circuit information editing unit 103 to the circuit information input control unit 101, and in the same procedure as the configuration of the conventional programmable logic circuit device, The circuit unit 104 is configured.

[Second Embodiment]
Next, a programmable logic circuit device according to a second embodiment of the present invention will be described in comparison with the first embodiment.

  As the programmable logic circuit device of the second embodiment, the programmable logic circuit device 100 having the first structure shown in FIG. 1 is used. As the circuit information, the same serial format circuit information as shown in FIG. 3 is used. The second embodiment differs from the first embodiment in the configuration method.

  FIG. 9 is a diagram for explaining circuit information and its editing operation in the case of the second embodiment. Similarly to the case of the first embodiment of FIG. 2, the example of FIG. 9 has the same three as those shown in FIG. 37 described in the configuration of the programmable logic circuit device according to the conventional multi-context technique described above. It is an example of a procedure for reconfiguring three circuits based on circuit information 1, 2, and 3.

  Also in FIG. 9, the frame structure of the circuit information is the same as that shown in FIG. That is, FIGS. 9A to 9C are exactly the same as FIGS. 2A to 2C.

  In the second embodiment, it is assumed that the circuit information 1, the circuit information 2, and the circuit information 3 are reconfigured in the order as in the timing chart shown in FIG.

  In the second embodiment, when reconstructing with the circuit information 3 after reconstructing with the circuit information 2, the frame data of the first frame and the fourth frame of the circuit information 3 are the first of the circuit information 2. The circuit information editing unit 103 detects that the frame data is the same as the frame data of the fourth frame.

  In different circuit information, the same frame data at the same position means that the function and connection state of the circuit elements corresponding to the frame are the same in the programmable logic circuit unit 104 even if the circuit information is different. Means that. In other words, when reconfiguration is performed according to the circuit information 3 after being reconfigured according to the circuit information 2, it is understood that the circuit information corresponding to the first frame and the fourth frame need not be stored in the configuration memory 106 again. .

  Therefore, in the second embodiment, the circuit information editing unit 103, when the circuit information generated by editing includes the same frame data at the same frame position as the circuit information of the previously generated circuit. The data of the frame is not transferred to the circuit information input control unit 101.

  The editing process in the circuit information editing unit 103 and the transfer process to the configuration memory 106 in the second embodiment will be described with reference to the flowcharts of FIGS. 10 and 11 and the timing chart of FIG. . In the timing chart of FIG. 6, the programmable logic circuit device is reconfigured in the order of circuit information 1, circuit information 2, and circuit information 3, and the process ends.

  Since most of the flowcharts of FIGS. 10 and 11 are the same as the corresponding flowcharts of FIGS. 7 and 8 in the first embodiment, the same step numbers as those of the flowcharts of FIGS. Will be attached.

  The differences between FIGS. 10 and 11 and FIGS. 7 and 8 of the first embodiment are as follows. That is, as a result of determining the type of frame in step S302, when it is determined that the read frame is a reference frame, as shown in FIG. 11, the frame is reconstructed immediately before that. It is determined whether or not the frame is identical to the frame at the same position in the circuit information (step S330). If not identical, the procedure from step S311 is executed in the same manner as described above.

On the other hand, if it is determined in step S330 that the frame is the same as the frame at the same position in the circuit information of the circuit reconfigured immediately before that, the configuration memory 106 of the circuit information of the frame is determined. Is skipped (step S331), and 1 is subtracted from the reference count RCNT (step S332).

  Then, it is determined whether or not the value of the reference count RCNT has become 0 (step S333). If not 0, the process returns to step S330 and the above-described operation is repeated. When it is determined in step S333 that the reference count RCNT has become 0, it is determined whether or not all the processes have been completed (step S310). If not completed, the process returns to step S301, and the above steps are performed. repeat. When all the processes are finished, this processing routine is finished.

  The procedures of the other steps are exactly the same as those described with reference to FIGS. That is, in FIG. 11, an underlined step is added to the flowcharts of FIGS. 7 and 8 in the second embodiment.

  As shown in FIG. 9D, in this example, the frame (2-A) of the circuit information 2 is referred to by the first, second, and third frames of the circuit information 3, and The frame (2-B) of the circuit information 2 is referred to as the fourth frame of the circuit information 3. Among the frames that are referred to, the frame data of the first frame and the fourth frame are the same in the circuit information 2 and the circuit information 3. Therefore, in the case of the second embodiment, in the circuit information 3, the frame data of the first frame and the fourth frame are stored in the configuration memory 106 as indicated by blanks in FIG. Not transferred.

  However, since each frame data of the circuit information 2 is already transferred and stored in the corresponding frame portion of the configuration memory 106, the frame data necessary for the circuit information 3 is stored.

  As described above, in the second embodiment, unnecessary transfer of frame data can be avoided by effectively using the circuit information already existing in the configuration memory 106. The configuration of circuit information can be further increased.

[Third Embodiment]
[Second Structure of Programmable Logic Circuit Device According to the Invention]
The programmable logic circuit device according to the third embodiment includes the second structure of the programmable logic circuit device according to the present invention. FIG. 12 shows the configuration of the programmable logic circuit device 200 according to the present invention having the second structure. The circuit information input control unit 201 reads circuit information from the outside, and the circuit function according to the read circuit information. It is comprised from the programmable logic circuit part 202 implement | achieved.

  The programmable logic circuit unit 202 is provided with a circuit element 2021 for reconfiguring the circuit and a configuration memory 2022 for storing circuit information for reconfiguring the circuit in the circuit element 2021. Further, in this second structure, the programmable logic circuit unit 202 has a circuit information storage unit 2023 for temporarily storing a plurality of circuit information necessary for processing, and a plurality of these. A circuit information editing unit 2024 that selects and edits necessary circuit information from the circuit information is reconfigured.

  That is, the first structure described above includes a circuit information storage unit and a circuit information editing unit in addition to the circuit information input control unit and the programmable logic circuit unit, which are components of a conventional programmable logic circuit device having a normal configuration. The configuration of the programmable logic circuit device according to the present invention is a configuration which is newly provided and cannot be used as it is, but the second structure of the embodiment of the programmable logic circuit device according to the present invention is a conventional configuration. A programmable logic circuit device having a conventional normal configuration is obtained by reconfiguring the circuit information storage unit 2023 and the circuit information editing unit 2024 in the programmable logic circuit unit 202 of the programmable logic circuit device having a normal configuration. This is a case where it can be used as it is.

  Also in the second structure, as in the first structure, a plurality of pieces of circuit information read into the programmable logic circuit device 200 are stored in the circuit information storage unit 2023 of the programmable logic circuit unit 202, and circuit information editing is performed. After being edited by the unit 2024, it is written into the configuration memory 2022 by the circuit information input control unit 201. The function and connection state of the circuit element 2021 are determined according to the circuit information written in the configuration memory 2022.

  The first difference between the second structure and the first structure is that, first, one piece of circuit information is read as the programmable logic circuit device 200, and the circuit information storage unit 2023 and the programmable logic circuit unit 202 are read. The purpose is to reconfigure a circuit portion having the function of the circuit information editing unit 2024. The circuit information at this time is stored in the configuration memory 2022 via the circuit information input control unit 201.

  The second difference between the second structure and the first structure is that, for example, when a plurality of circuit information is read from an external storage device and stored in the circuit information storage unit 2023, the circuit information input control unit 201 is changed. Instead, a plurality of pieces of circuit information is read into the circuit information storage unit 2023 via the input / output unit of the programmable logic circuit unit 202. Therefore, in this second structure, the input / output unit of the programmable logic circuit unit 202 constitutes circuit information writing means to the circuit information storage unit 2023.

  The third difference between the second structure and the first structure is that the circuit information edited by the circuit information editing unit 2024 is transmitted to the programmable logic circuit device 200 via the input / output unit of the programmable logic circuit unit 202. Is input to the circuit information input control unit 201 again. The circuit information input control unit 201 transfers the circuit information to the configuration memory 2022 and executes the configuration as in the conventional case.

  The second and third differences are that the conventional programmable logic circuit device cannot read a plurality of circuit information, and the circuit configured in the programmable logic circuit unit inputs and outputs data via the input / output unit. Caused by what must be.

[Configuration in the third embodiment]
In the third embodiment, except that the programmable logic circuit device 200 has the above-described second structure, circuit information is configured in a serial format, and the circuit information is 3 as shown in FIG. Since the frame structure can be taken, it is compressed in the same manner as described above, as in the case of the first and second embodiments described above.

  In the following, focusing on the circuit information input control unit 201, the circuit information storage unit 2023, the circuit information editing unit 2024, and the configuration memory 2022 among the components of the programmable logic circuit device 200 of the third embodiment, FIG. The operation of the programmable logic circuit device 200 according to the third embodiment will be described with reference to FIG.

  In the example shown in FIG. 13, the configuration memory 2022 of the programmable logic circuit device 200 can store circuit information for five frames. In the programmable logic circuit device 200, the circuit information storage unit 2023 and the circuit information editing unit 2024 are reconfigured in the programmable logic circuit unit 202 in the first frame (first frame), and the remaining four frames ( In the second frame to the fifth frame), three types of processing circuits are reconfigured.

  Actually, as shown in FIG. 13, circuit information 0 of only the first frame for reconfiguring the circuit information storage unit 2023 and the circuit information editing unit 2024 is prepared as the first circuit information. Then, the circuit information storage unit 2023 and the circuit information editing unit 2024 are reconfigured in the programmable logic circuit unit 202 based on the circuit information 0. As shown in FIG. 13, the circuit information 1, 2, and 3 required for processing is composed of four frames in which the first frame portion is blank so that the first frame portion is not reconstructed.

  In the example of FIG. 13, finally, as in the above-described embodiment, the three pieces of circuit information 1, 2, and 3 are configured with a smaller number of frames by compressing the circuit information as described above. The

  That is, the circuit information 1 is composed of two frames, a frame (1-A) and a frame (1-B). The frame (1-B) has a repeat frame configuration, and in this example, reference information that the frame is repeated three times is added.

  The circuit information 2 is composed of three frames: a frame (2-A), a frame (1-A), and a frame (2-B). The frame (1-A) of the circuit information 2 is a reference frame, and reference information that is the same as the frame (1-A) of the circuit information 1 is added to the frame data. The reference information that is repeated once is added.

  The circuit information 3 is composed of two frames, a frame (2-A) and a frame (2-B). In the frame (2-A) and the frame (2-B) of the circuit information 3, reference information that the frame data is the same as the frame (2-A) and the frame (2-B) of the circuit information 2, respectively. In addition, reference information that the frame is repeated three times is added to the frame (2-A).

  As described above, the circuit information of the third embodiment is also compressed in the same manner as in the first embodiment. Therefore, the number of frames stored in the circuit information storage unit 2023 may be as small as 7 frames, while 12 frames are required when there is no compression.

  In the third embodiment, the functions of the circuit information storage unit 2023 and the circuit information editing unit 2024 are the same as those of the above-described embodiment, and a plurality of circuit information read from the outside, in this example, The circuit information 1, 2, and 3 are temporarily stored in the circuit information storage unit 2023. Then, the circuit information editing unit 2024 takes out the compressed circuit information from the circuit information storage unit 2023 in accordance with a selection signal according to the user's selection instruction, and uses the taken out circuit information as a configuration memory of a conventional programmable logic circuit device. The circuit information is edited to be the same as the circuit information stored in. Next, the circuit information input control unit 201 stores the circuit information from the circuit information editing unit 2024 in the configuration memory 2022, and the programmable logic circuit device 200 is reconfigured according to the circuit information.

  This reconstruction procedure will be described with reference to the flowchart of FIG. 15 and the timing chart of FIG. In the timing chart of FIG. 16, the circuit necessary for processing is reconfigured in the programmable logic circuit device 200 in the order of circuit information 1, circuit information 2, and circuit information 3, and the processing ends.

  The flowchart of FIG. 15 differs from the flowchart of FIG. 5 of the first embodiment and the second embodiment described above only in that step S400 is inserted first, and the subsequent steps are as follows. Is exactly the same. Therefore, also in the flowchart of FIG. 15, the same step numbers are assigned to the same steps as those in the flowchart of FIG. 5.

  First, the circuit information input control unit 201 reads circuit information 0 for reconfiguring the circuit information storage unit 2023 and the circuit information editing unit 2024 into the programmable logic circuit unit 202. As illustrated in FIG. 13, the circuit information 0 includes circuit information for reconfiguring the circuit information storage unit 2023 and the circuit information editing unit 2024 in the first frame 0. The second to fifth frames are empty frames in order to reconfigure the processing circuit later. This procedure is the same as that realized by the conventional programmable logic circuit device.

  Thereafter, the steps S201 to S211 described above are executed, and the circuit information 1, 2, and 3 are sequentially stored in the configuration memory 2022 while being decompressed and processed in the programmable logic circuit device 200. The necessary circuits are sequentially reconfigured.

  That is, a plurality of circuit information 1, 2, and 3 stored in an external storage device (not shown) or the like is read one by one through the input / output unit of the programmable logic circuit unit 202, and the circuit information storage unit 2023 (step S201). Unlike the case of the above-described embodiment, in the case of the second embodiment, reading is not performed via the circuit information input control unit, but is read via the input / output unit of the programmable logic circuit unit 202.

  At this time, each time one piece of circuit information is read, the remaining capacity of the circuit information storage unit 2023 is checked. If the circuit information storage unit 2023 becomes full before reading all the circuit information, an error is detected. The operation is terminated (steps S202, S203, 204).

  As shown in FIG. 13, the first frame of the circuit information 1, 2, and 3 to be read is already stored in the configuration memory 2022 and reconfigured in the programmable logic circuit unit 202. It is an empty frame so as not to interfere with the circuit information editing unit 2024, that is, in the programmable logic circuit unit 202, so that the circuit configurations of the circuit information storage unit 2023 and the circuit information editing unit 2024 are not destroyed.

  When all circuit information is stored in the circuit information storage unit 2023 (step S202), the circuit information editing unit 2024 monitors the selection signal (steps S205 and S206). When the circuit information editing unit 2024 detects that the selection signal has been switched, it extracts necessary circuit information from the circuit information storage unit 2023 according to the switched circuit information (steps S207 to S209).

  Next, from the extracted circuit information, frame repetition (repeat frame) and other circuit information frame references (reference frames) are checked, and the circuit information is compressed by eliminating those repeat frames and reference frames. The state is solved (step S210).

  In the circuit information editing process in step S210, as shown in FIG. 14, when the frame (1-B) is repeated three times as in the circuit information 1, the same frame data 2 is added after the frame (1-B). Append times.

  When the frame (1-A) of the circuit information 1 is referred to by the third frame like the circuit information 2, the circuit information editing unit 2024 sends the frame (1) of the circuit information 1 from the circuit information storage unit 2023. The data of -A) is taken out and inserted into the third frame of the circuit information 2.

  Furthermore, when the frame (2-A) and the frame (2-B) of the circuit information 2 are referred to by the second, third, fourth, and fifth frames as in the circuit information 3 The circuit information editing unit 2024 extracts the data of the frame (2-A) and the frame (2-B) of the circuit information 2 from the circuit information storage unit 2023, and the second, third, and fourth frames of the circuit information 3 Insert into the fifth frame.

  The circuit information that has been uncompressed is sent to the circuit information input control unit 201 and is stored in the configuration memory 2022 as in the conventional programmable logic circuit device, and the reconfiguration is completed (step S211).

  Thereafter, as long as the processing by the programmable logic circuit device continues, the selection signal is continuously monitored by the circuit information editing unit. When the process by the programmable logic circuit device ends, the reconfiguration procedure ends regardless of the selection signal.

  FIG. 16 is a timing chart of the above circuit information reading and circuit information reconfiguration operation. Prior to reading the circuit information 1, 2, and 3, the circuit information storage unit 2023 and the circuit information editing unit 2024 are preconfigured in the programmable logic circuit unit 202, so that the circuit information 0 is read. This is different from the timing chart of FIG. 6 in the case of the second embodiment.

[Fourth Embodiment]
In the fourth embodiment, as in the second embodiment described above, in the third embodiment, a circuit that has been reconfigured in the programmable logic circuit unit 202 immediately before is effectively used. This is the case.

  That is, in the fourth embodiment, the circuit information editing unit 2024 edits the circuit information read from the circuit information storage unit 2023, and the circuit information is stored in the configuration memory 2022 through the circuit information input control unit 201. When transferring, when the circuit information of the circuit reconfigured and generated immediately before that by the programmable logic circuit unit 202 includes the same frame data at the same frame position, the data of the frame is the circuit information input control. The data is not transferred to the configuration memory 2022 through the unit 201.

  For example, taking the case where three circuits are sequentially reconfigured and generated in the programmable logic circuit device 200 using the same three circuit information 1, 2, and 3 as described above, as shown in FIG. After reconfiguring the programmable logic circuit unit 202 with the information 2, when reconfiguring the programmable logic circuit unit 202 with the circuit information 3, the frame data of the second frame and the fifth frame of the circuit information 3 The circuit information editing unit 2024 detects that the data is the same as the frame data at the same position.

  As described above, the same frame data at the same position in the circuit information means that the function and connection state of the circuit element corresponding to the frame are the same. In the case of reconfiguration according to 3, it is not necessary to store circuit information corresponding to the second frame and the fifth frame again in the configuration memory, and exactly the same as in the case shown in FIGS. The data part is skipped and the frame data is not transferred to the circuit information input control unit 201.

[Fifth Embodiment]
In all of the first to fourth embodiments described above, the circuit information is in the serial format, but the present invention is naturally applicable to the case of the parallel format circuit information. The fifth embodiment is a case of circuit information in a parallel format.

  In the fifth embodiment, a specific structure of circuit information in parallel format is shown, and a circuit information editing unit 103 (in the case of the first and second embodiments) and a circuit information editing unit 2024 (third). Next, the elimination of the repeat frame and the reference frame of the circuit information performed in the case of the fourth embodiment) will be described.

[Parallel circuit information according to the present invention]
FIG. 18 shows the structure of parallel circuit information used in the fifth embodiment. As in the case of the conventional parallel format circuit information shown in FIG. 32, the parallel format circuit information in this case also includes a header portion HDp, a data portion DTp, and a footer portion FTp, as shown in FIG. Is done.

  Within the programmable logic circuit device 100 or 200, circuit information in a parallel format having a certain bit width (for example, 32 bits) is divided by an appropriate unit (for example, 1 bit, 64 bits), thereby enabling the programmable logic circuit device 100 or 200. Outside, serial transfer, parallel transmission with different bus widths and parallel memory access can be performed.

  The header part HDp includes a preamble code indicating the start of circuit information, an option code for setting a configuration parameter such as an input clock speed of the circuit information, a switch command for executing the set option and starting reading of data. Consists of. This switch command also serves as editing instruction information to the circuit information editing unit of each embodiment of the present invention.

  The data part DTp is composed of a plurality of three types of frames as in the serial format. The footer part FTp is composed of a postamble code indicating the end of the circuit information.

  There are three types of frames constituting the data portion DTp: a normal frame, a repeat frame, and a reference frame even in this parallel format.

  As shown in FIG. 18B, the normal frame has the same structure as the frame used in the conventional parallel circuit information, and includes a frame address FADR indicating the frame position in the configuration memory in which data is written, It consists of a data-in command DIN for instructing writing, a word count WCNT for instructing the number of words read from the configuration data CFGD, and configuration data CFGD.

  As shown in FIG. 18C, the repeat frame includes a frame address FADR indicating a frame position in the configuration memory in which data is written, a repeat command REPT instructing data repetition, and the number of words read from the configuration data CFGD. It consists of an instructed word count WCNT, a reference count RCNT instructing the number of repetitions, and configuration data CFGD. In the procedure described later, the number of normal frames indicated by the reference count RCNT is generated from the compressed repeat frames.

  As shown in FIG. 18D, the reference frame indicates a frame address FADR indicating a frame position in the configuration memory to which data is written, a reference command REFC for instructing data reference, and the number of words read from the configuration data CFGD. A word count WCNT to instruct, a reference count RCNT to instruct the number of repetitions, a reference offset ROFS indicating a relative address for reading data in the reference destination frame, and a reference indicating an address of the reference destination frame in the circuit information storage unit 102 or 2023 It consists of the address RADR. The normal frame having the configuration data stored in the circuit information storage unit 102 or 2023 calculated from the reference address RADR and the offset address ROFS from the compressed reference frame in the procedure described later is the reference count RCNT. Only the indicated number is generated.

  In addition to the normal frame, having two types of frames, a repeat frame and a reference frame, is a feature of the parallel circuit information in this example. These three types of frames have different commands (data-in command DIN, repeat command REPT, reference command REFC) and are recognized and distinguished by the circuit information editing unit 103 or 2024.

[Configuration of Programmable Logic Circuit Device 100 of First Structure Based on Circuit Information in Parallel Format]
FIG. 19 is a functional block diagram for explaining a configuration operation based on circuit information in parallel format for the programmable logic circuit device having the first structure shown in FIG. The storage of circuit information in this case in the configuration memory will be described with reference to the block diagram shown in FIG.

  The circuit information input control unit 101 shown in FIG. 1 includes a configuration controller 101e, an address generator 101f, and a selector 101g in FIG.

  Further, in FIG. 19, for example, the circuit element 105 and the configuration memory 106 of the programmable logic circuit unit 104 shown in FIG. 1 are, for example, an FPGA type as shown in FIG. These logic circuit cells are divided into a plurality of columns.

  That is, it is configured by a plurality of columns as a set including a configuration memory 106s having a capacity capable of storing circuit information of a plurality of logic circuit portions in one vertical column and circuit elements 105s connected thereto. In this case, the circuit information of one normal frame is the size of the circuit information of a plurality of logic circuit portions in a vertical row.

  In the same manner as shown in FIG. 34, the bit lines of the configuration memory 106s in each column are connected to the selector 101g. The word line of the configuration memory 106s is connected to the address generator 101f.

  The circuit information storage unit 102 shown in FIG. 1 corresponds to the configuration cache memory 102M in FIG. 19, and the function of the circuit information editing unit 103 is incorporated in the configuration controller 101e.

  In the configuration of FIG. 19, when circuit information is read from the external storage device 9, it is stored in the configuration cache memory 102M via the configuration controller 101e.

  When the configuration controller 101e receives a context selection instruction, circuit information corresponding to the instruction is read from the configuration cache memory 102M to the configuration controller 101e. Then, the configuration controller 101e detects the preamble code in the header part HDp of the circuit information and starts circuit information editing processing.

  First, a configuration parameter is set by an option code following the preamble code. Then, the set option is executed by the next switch command, and reading of the data DTp is started.

  The frame data of the data portion DTp is converted from a frame compressed by a repeat frame or a reference frame into a normal frame that has been uncompressed by a procedure described later. Then, the frame address FADR of each frame is read into the address generator 102f, and a bit line and a word line corresponding to the configuration memory 106s to which data is written are selected. Next, the data-in command DIN is activated, data corresponding to the number indicated by the word count WCNT is read from the configuration data CFGD, and written into the configuration memory 106s via the selector 101g. This procedure is repeated for all frames.

  When the configuration controller 101e detects the postamble code of the footer part FTp following the data part DTp, the configuration process ends. The above processing is exactly the same as the procedure shown in the flowchart of FIG. 5, except that the compression / decompression processing in the circuit information editing unit 103 in step S210 is as shown in FIG. 20 and FIG. This is different from the case of the serial format circuit information (FIGS. 7 and 8).

[Processing in the circuit information editor]
With reference to FIG. 20 and FIG. 21, the process of canceling the repeat frame and the reference frame in the embodiment in the case of the circuit information in the parallel format will be described.

  First, the circuit information editing unit 103 reads the first frame, and determines the type by a command following the frame address FADR of each frame. When it is determined that the read frame is a normal frame, the data of the frame is sent as it is (step S503).

  When it is determined that the read frame is a repeat frame, the reference count RCNT is read. Next, the frame address FADR, the data-in command DIN, the word count WCNT, and the configuration data CFGD are sequentially sent out (steps S504 to S508), and 1 is subtracted from the reference count RCNT (step S509). By repeating this procedure until the reference count reaches 0 (step S510), the number of normal frames indicated by the reference count RCNT is generated from the compressed repeat frames.

  When it is determined that the read frame is the reference frame, the reference count RCNT, the reference address RADR, and the reference offset ROFS are read (steps S511 to S513 in FIG. 21). Next, the reference address RADR indicating the position of the reference destination frame in the circuit information storage unit 102 is added to the reference offset ROFS indicating the relative position of the configuration data CFGD to be referred to in the reference destination frame for reference. The absolute address of the configuration data CFGD is calculated (step S514).

  Next, the configuration data CFGD located at the absolute address is read out and temporarily stored in the circuit information editing unit 103 (step S515). Next, as in the case of the above-described repeat frame, the frame address FADR, the data-in command DIN, the word count WCNT, and the configuration data CFGD are sent out until the reference count RCNT becomes 0 (steps S516 to S521). From the compressed reference frame, the normal frame having the referenced configuration data CFGD is generated in the number indicated by the reference count RCNT.

  By performing this procedure for all the frames (step S522), circuit information including only the normal frame that has been decompressed is generated from the circuit information compressed by the repeat frame and the reference frame.

  By sending the circuit information that has been decompressed to the circuit information input control unit 101, the circuit information is configured in the same procedure as the configuration of the conventional programmable logic circuit device.

  The fifth embodiment described above is a case where circuit information in the parallel format is used for the configuration of the programmable logic circuit device 100 having the first structure, but the programmable logic circuit device having the second structure. In the case of 200, the present invention can be applied in the same manner, and also in the case of effectively using a circuit already generated in the programmable logic circuit unit as in the case of the second embodiment or the fourth embodiment, It can be applied in the same manner as described above.

  The circuit information compression method described above is merely an example, and any circuit information compression method may be used. The circuit information editing unit 103 is configured to have a function of performing an editing process corresponding to the circuit information compression method.

1 is a block diagram illustrating a first structure of an embodiment of a programmable logic circuit device according to the present invention. FIG. 1 is a diagram for explaining a first embodiment of a programmable logic circuit device according to the present invention; FIG. It is a figure explaining the example of the circuit information of the serial format used by embodiment of this invention. It is a block diagram explaining the programmable logic circuit device of an embodiment which performs configuration using circuit information of serial form. It is a flowchart for demonstrating operation | movement of the programmable logic circuit apparatus of 1st Embodiment. It is a timing chart for demonstrating operation | movement of the programmable logic circuit apparatus of 1st and 2nd embodiment. It is a part of flowchart for demonstrating edit of the circuit information of the serial format in the programmable logic circuit apparatus of 1st and 3rd embodiment. It is the remainder of the flowchart for demonstrating edit of the circuit information of the serial format in the programmable logic circuit apparatus of 1st and 3rd embodiment. It is a figure explaining 2nd Embodiment of the programmable logic circuit device by this invention. It is a part of flowchart for demonstrating edit of the circuit information of the serial format in the programmable logic circuit apparatus of 2nd and 4th embodiment. It is the remainder of the flowchart for demonstrating the edit of the circuit information of the serial format in the programmable logic circuit apparatus of 2nd and 4th embodiment. It is a block diagram explaining the 2nd structure of embodiment of the programmable logic circuit apparatus by this invention. It is a figure for demonstrating 3rd Embodiment of the programmable logic circuit apparatus by this invention. It is a figure for demonstrating the edit operation | movement in 3rd Embodiment of the programmable logic circuit apparatus by this invention. It is a flowchart for demonstrating operation | movement of the programmable logic circuit apparatus of 3rd Embodiment. It is a timing chart for demonstrating operation | movement of the programmable logic circuit apparatus of 3rd and 4th Embodiment. It is a figure for demonstrating the edit operation | movement in the programmable logic circuit apparatus of 4th Embodiment by this invention. It is a figure explaining the example of the circuit information of the parallel format used by embodiment of this invention. It is a block diagram explaining the programmable logic circuit device of an embodiment which performs composition using circuit information of parallel form. FIG. 5 is a part of a flowchart for explaining an editing operation when parallel circuit information is used in the embodiment of the present invention. FIG. In the embodiment of the present invention, the remainder of the flowchart for explaining the editing operation in the case of using parallel circuit information. It is a block diagram explaining the structure of the conventional programmable logic circuit apparatus. It is a block diagram explaining the structure of the programmable logic circuit part of the conventional programmable logic circuit apparatus. It is a figure which shows the specific structural example of a programmable logic circuit part of FPGA type and CPLD type. It is a block diagram explaining the structure of the programmable logic circuit apparatus by the conventional multi-context technique. It is a block diagram explaining the structure of the programmable logic circuit part of the programmable logic circuit apparatus by the conventional multi-context technique. It is a figure explaining the circuit information of the conventional serial format. It is a block diagram explaining the conventional programmable logic circuit apparatus using the circuit information of a serial format. It is a block diagram explaining a part of programmable logic circuit part of the programmable logic circuit device using the circuit information of a serial form. It is a block diagram explaining the structure of a part of programmable logic circuit part of the programmable logic circuit apparatus by the multi-context technique using the circuit information of a serial format. It is a block diagram explaining the programmable logic circuit device by the multicontext technique using the circuit information of a serial format. It is a figure explaining the circuit information of the conventional parallel format. It is a block diagram explaining the conventional programmable logic circuit apparatus using the circuit information of a parallel format. It is a figure explaining the structure of a part of programmable logic circuit part of the conventional programmable logic circuit device using the circuit information of a parallel format. It is a figure explaining the structure of a part of programmable logic circuit part of the programmable logic circuit apparatus by the multi-context technique using the circuit information of a parallel format. It is a block diagram explaining the programmable logic circuit device by the multi-context technique using the circuit information of a parallel format. It is a figure for demonstrating operation | movement of the programmable logic circuit apparatus by the conventional multi-context technique. It is a flowchart explaining operation | movement of the programmable logic circuit apparatus by the conventional multi-context technique. It is a timing chart explaining operation | movement of the programmable logic circuit apparatus by the conventional multi-context technique. It is a block diagram explaining Example 1 of the programmable logic circuit device by the conventional multi-context technique. It is a block diagram explaining Example 2 of the programmable logic circuit device by the conventional multi-context technique. It is a block diagram explaining Example 3 of the programmable logic circuit device by the conventional multi-context technique. It is a block diagram explaining Example 4 of the programmable logic circuit device by the conventional multi-context technique.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Programmable logic circuit apparatus of 1st structure 101 Circuit information input control part 102 Circuit information memory | storage part 103 Circuit information edit part 104 Programmable logic circuit part 105 Circuit element 106 Configuration memory 200 Programmable logic circuit apparatus 201 of 2nd structure Information input control unit 202 Programmable logic circuit unit 2021 Circuit element 2022 Configuration memory 2023 Circuit information storage unit 2024 Circuit information editing unit

Claims (29)

A programmable logic circuit unit comprising a circuit element and a configuration memory connected to the circuit element, the circuit being configured based on circuit information written in the configuration memory;
A plurality of circuit information for sequentially configuring a plurality of circuits in the programmable logic circuit section, and circuit information storage means different from the configuration memory;
Circuit information writing means for writing the plurality of circuit information to the circuit information storage means;
The circuit information of one circuit to be generated in the programmable logic circuit unit designated by the designation information is one or a plurality of circuit information among a plurality of circuit information stored in the circuit information storage means. Circuit information editing means to generate using
Control means for writing circuit information of the one circuit generated by the circuit information editing means to the configuration memory;
A programmable logic circuit device comprising:   The programmable logic circuit device according to claim 1, wherein the circuit information storage unit and the circuit information editing unit are provided separately from the programmable logic circuit unit.   The circuit information storage means and the circuit information editing means generate circuit information for that purpose into a part of the circuit elements of the programmable logic circuit section by reading the circuit information into a part of the configuration memory. Item 12. The programmable logic circuit device according to Item 1.   The circuit information stored in the circuit information storage means is compressed, and the circuit information editing means decompresses the compression to generate circuit information designated by the designation information. The programmable logic circuit device in any one of Claims 1-3. The programmable logic circuit device according to any one of claims 1 to 3,
The circuit information stored in the circuit information storage means includes reference information for reading out the other circuit information from the circuit information storage means when part or all of the circuit information is composed of other circuit information. It is prepared
The circuit information editing means obtains circuit information of one circuit designated by the designation information, the circuit information designated by the designation information from the circuit information storage means, and the circuit information includes the reference information. If it is, the programmable logic circuit device is characterized in that the other circuit information is obtained and generated based on the reference information. The programmable logic circuit device according to any one of claims 1 to 3,
The circuit information stored in the circuit information storage means refers to the other part of the circuit information when the part of the circuit information is composed of the other part of the circuit information. With reference information for
The circuit information editing means obtains the circuit information of the circuit designated by the designation information, and obtains the designated circuit information from the circuit information storage means. A programmable logic circuit device characterized in that it is also generated using information. The programmable logic circuit device according to any one of claims 1 to 3,
Each of the plurality of circuit information stored in the circuit information storage means includes a circuit data portion and an additional information portion thereof,
The additional information portion includes a description for instructing the circuit information editing means to edit the circuit data portion,
The circuit data part is a data part for constituting a circuit in the programmable logic circuit part, and when part or all of the circuit data part is constituted by a circuit data part of other circuit information, the part or All the circuit data portions describe reference information for referring to the other circuit information with respect to the circuit information storage means,
The circuit information editing means obtains circuit information designated by the designation information from the circuit information storage means and a circuit data portion of the designated circuit information and other circuit information referenced by the reference information. A programmable logic circuit device characterized by the above. The programmable logic circuit device according to any one of claims 1 to 3,
Each of the plurality of circuit information stored in the circuit information storage means includes a circuit data portion and an additional information portion thereof,
The additional information portion includes a description for instructing the circuit information editing means to edit the circuit data portion,
The circuit data part is a data part for configuring a circuit in the programmable logic circuit part, and when the part is composed of another circuit data part of its own circuit information, the other circuit data It is described using reference information for referring to the part,
The circuit information editing means obtains the circuit information designated by the designation information, the designated circuit information from the circuit information storage means, and if the reference information is included, also uses the reference information A programmable logic circuit device characterized by the above. The programmable logic circuit device according to claim 7 or 8,
The circuit data portion of the circuit information stored in the circuit information storage means is described by one to a plurality of frames corresponding to data divided into a predetermined amount of data stored in the configuration memory,
When some or all of the one or more frames are composed of other circuit information frames, the reference information refers to the frame of the other circuit information in the circuit information. A programmable logic circuit device characterized by being described as circuit data of a frame to be performed. The programmable logic circuit device according to claim 7 or 8,
The circuit data portion of the circuit information stored in the circuit information storage means is described by one to a plurality of frames corresponding to data divided into a predetermined amount of data stored in the configuration memory,
When a part of the one or more frames is composed of another frame of its own circuit information, the reference information should refer to the frame of its own circuit information in the circuit information. A programmable logic circuit device characterized by being described as circuit data of a frame. The programmable logic circuit device according to claim 9 or 10,
The programmable logic circuit device, wherein the reference information is a memory address of the circuit information storage means in which a frame of the other circuit information to be referred to or a frame of its own circuit information to be referenced is stored. The programmable logic circuit device according to claim 11, wherein
The circuit information editing means is stored in a memory address of the circuit information storage means indicated by the reference information in a frame in which the reference information is described as circuit data of circuit information of the circuit specified by the specification information. A programmable logic circuit device characterized by inserting a frame. The programmable logic circuit device according to claim 9 or 10,
The programmable information circuit, wherein the reference information is a memory address of the circuit information storage means in which a frame of the other circuit information to be referred to or a frame of its own circuit information to be referenced is stored, and a reference count apparatus. The programmable logic circuit device according to claim 13,
The circuit information editing means is stored in a memory address of the circuit information storage means indicated by the reference information in a frame in which the reference information is described as circuit data of circuit information of the circuit specified by the specification information. A programmable logic circuit device, wherein frames are inserted for the number of times of reference indicated by the reference information. The programmable logic circuit device according to claim 9, wherein
In the case where the reference information is described in the circuit information frame of the circuit to be generated, the circuit information editing means is configured such that the data at the frame position where the reference information is described immediately before the programmable logic circuit When it is determined that the frame information is the same as the frame data at the same position in the circuit information generated by the circuit, the frame data is not transferred to the configuration memory via the control means. A programmable logic circuit device. An information processing system for processing at least a part of processing by an application program with a programmable logic circuit device,
An information processing system using the programmable logic circuit device according to claim 1 for the programmable logic circuit device. A programmable logic circuit device comprising a programmable logic circuit unit comprising a circuit element and a configuration memory connected to the circuit element, and comprising a programmable logic circuit unit configured based on circuit information written in the configuration memory. Stores a plurality of circuit information for sequentially configuring a plurality of circuits in the logic circuit section, and is stored in the circuit information storage means different from the configuration memory and in the circuit information storage means Circuit information editing means for generating circuit information of the specified circuit is provided using the circuit information,
The circuit information storage means stores the circuit information of the plurality of circuits in a compressed state,
When the designation information of the circuit information of the circuit to be reconfigured is input to the programmable logic circuit unit, the circuit information editing unit reads the necessary circuit information from the circuit information storage unit, decompresses the compression, A circuit reconfiguration method for a programmable logic circuit device, comprising generating circuit information specified by the specification information, transferring the generated circuit information to the configuration memory, and reconfiguring the circuit. The circuit information stored in the circuit information storage means includes reference information for reading out the other circuit information from the circuit information storage means when part or all of the circuit information is composed of other circuit information. It is compressed by describing,
When the circuit information editing means reads the designated circuit information from the circuit information storage means, and the reference information is included in the circuit information, the circuit information editing means, based on the reference information, The necessary circuit information is obtained from the circuit information storage means. The method of reconfiguring a circuit into the programmable logic circuit device according to claim 17. The circuit information stored in the circuit information storage means refers to the other part of the circuit information when the part of the circuit information is composed of the other part of the circuit information. It is compressed by describing the reference information of
When the circuit information editing means reads the designated circuit information from the circuit information storage means, and the reference information is included in the circuit information, the circuit information editing means, based on the reference information, The necessary circuit information is generated by using the read circuit information. The method of reconfiguring a circuit into the programmable logic circuit device according to claim 17. A method for reconfiguring a circuit into a programmable logic circuit device according to claim 18 or claim 19,
Each of the plurality of circuit information stored in the circuit information storage means includes a circuit data portion and an additional information portion thereof,
The additional information portion includes a description for instructing the circuit information editing means to edit the circuit data portion,
The circuit data portion is compressed using the reference information. A method of reconfiguring a circuit into a programmable logic circuit device. A method for reconfiguring a circuit into a programmable logic circuit device according to claim 18 or claim 19,
The circuit data portion is described by 1 to a plurality of frames corresponding to a predetermined amount of data stored in the configuration memory,
When some or all of the one or more frames are composed of other circuit information frames, the reference information refers to the frame of the other circuit information in the circuit information. It is described as circuit data of a frame to be performed. A method for reconfiguring a circuit into a programmable logic circuit device. A method for reconfiguring a circuit into a programmable logic circuit device according to claim 18 or claim 19,
The circuit data portion is described by 1 to a plurality of frames corresponding to a predetermined amount of data stored in the configuration memory,
When a part of the one or more frames is composed of another frame of its own circuit information, the reference information should refer to the frame of its own circuit information in the circuit information. A circuit reconfiguration method for a programmable logic circuit device, characterized in that the circuit data is described as frame circuit data. A method for reconfiguring a circuit into a programmable logic circuit device according to claim 21 or claim 22,
The circuit to the programmable logic circuit device, wherein the reference information is a memory address of the circuit information storage means in which a frame of the other circuit information to be referred to or a frame of the circuit information to be referred to is stored. Reconfiguration method. The method of reconfiguring a circuit into a programmable logic circuit device according to claim 23,
The circuit information editing means is stored in a memory address of the circuit information storage means indicated by the reference information in a frame in which the reference information is described as circuit data of circuit information of the circuit specified by the specification information. A method for reconfiguring a circuit into a programmable logic circuit device, comprising inserting a frame. A method for reconfiguring a circuit into a programmable logic circuit device according to claim 21 or claim 22,
The programmable information circuit, wherein the reference information is a memory address of the circuit information storage means in which a frame of the other circuit information to be referred to or a frame of its own circuit information to be referenced is stored, and a reference count A method for reconfiguring a circuit into a device. The method of reconfiguring a circuit into a programmable logic circuit device according to claim 25,
The circuit information editing means is stored in a memory address of the circuit information storage means indicated by the reference information in a frame in which the reference information is described as circuit data of circuit information of the circuit specified by the specification information. A method of reconfiguring a circuit into a programmable logic circuit device, wherein frames are inserted for the number of times of reference indicated by the reference information. The method of reconfiguring a circuit into a programmable logic circuit device according to claim 21,
In the case where the reference information is described in the circuit information frame of the circuit to be generated, the circuit information editing means is configured such that the data at the frame position where the reference information is described immediately before the programmable logic circuit When it is determined that the frame information is the same as the frame data at the same position in the circuit information generated by the circuit, the frame data is not transferred to the configuration memory via the control means. A method for reconfiguring a circuit into a programmable logic circuit device. A method for managing a plurality of circuit information for sequentially configuring a plurality of circuits in a programmable logic circuit device,
Each of the circuit information is described by 1 to a plurality of frames corresponding to data stored in the configuration memory of the programmable logic circuit device divided by a certain amount,
When a part or all of the circuit information is composed of other circuit information or another part of its own circuit information, the reference information is the other circuit information or its own circuit information. A circuit information management method characterized in that it is described as circuit data of a frame to be referred to. A circuit data portion of circuit information constituting the circuit in the programmable logic circuit device is described by a set of frames corresponding to data stored in the configuration memory of the programmable logic circuit device divided by a certain amount,
When a part or all of the circuit information is composed of other circuit information or another part of its own circuit information, the reference information is the other circuit information or its own circuit information. A method of compressing circuit information, characterized by compressing the amount of circuit information data by describing it as circuit data of a frame to be referred to.

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