JP2005505888A - Semiconductor memory device in which magnetoresistive memory cell is arranged at intersection of word line and bit line - Google Patents

Abstract

In the memory cell array of the semiconductor memory device (2), the memory element, more precisely, the memory cell (1) having a magnetoresistive effect is characterized by the weak magnetization of the hard magnetic memory layer (10) and the soft magnetic detection layer (11). The axis (30/31) intersects. The magnetization axis (30) of the hard magnetic layer (10) is parallel to the line connected to this layer (for example, the bit line (9)). The magnetization axis (31) is parallel to a line (for example, the word line (8)) connected to the soft magnetic layer. Each axis having parallel lines is preferably substantially perpendicular to each other. A voltage signal or current signal is passed through each selected line (eg, word line (8)) via an AC voltage source (51) or AC current source (50). Thereby, the magnetization direction (21) of the soft magnetic layer (11) shifts from the weak magnetization axis (31) to a sine wave shape. As a result, the magnetoresistance of the memory cell changes with the supplied signal. Depending on the magnetization direction (20) of the hard magnetic layer (10), this signal is adjusted in phase or in phase by a variable resistor. As a result, for example, a DC voltage and a first harmonic with a sign can be detected as the constituent components of the generated measurement signal. This code transmits and receives stored information.

Description

[0001]
The present invention relates to a semiconductor memory device in which magnetoresistive memory cells are arranged at intersections of word lines and bit lines, and a method and circuit structure for evaluating information contents of the memory cells. The magnetoresistive memory cell includes at least one first magnetic layer (ersten magnetischen Schicht) having one first magnetization axis, one insulating layer, and one second magnetic layer having one second magnetization axis. Consisting of
[0002]
Nonvolatile memory cells (also referred to as MRAM memory cells) having magnetoresistance typically comprise a stack of combinations of ferromagnetic materials and insulating layers located therebetween. This insulating layer is also called a tunnel dielectric. In this case, the memory effect is present in the electrical resistance of the memory cell or cells that can change the magnetization, ie the memory cell.
[0003]
Each layer of these ferromagnetic materials has one magnetization axis, and these magnetization axes are arranged in parallel to each other, so that each layer can set two magnetization directions. That is, the magnetization direction of the magnetic layer can be parallel or antiparallel depending on the magnetization state of the memory cell. Depending on these directions, the electrical resistance of the memory cell varies. In this case, if the magnetization direction is parallel, the electrical resistance of the memory cell is low, and if the magnetization direction is antiparallel, the resistance is high.
[0004]
Normally, the formation of these layers changes the magnetization state of only one of the two ferromagnetic layers due to the influence of the induced magnetic field, while the state of the other layer does not change over time (i.e. Function as the reference magnetization direction of the cell).
[0005]
The insulating layer may have a thickness of about 1 to 3 nm, for example. The conductivity of this layer system is mainly defined by the insulating layer tunneling effect of this layer system. As the thickness of the tunnel insulating layer changes, the conductivity changes significantly. This is because the thickness of the insulating layer affects the tunnel current almost exponentially.
[0006]
Writing to such a memory cell is performed using a current. For this purpose, the memory cell is formed so as to have two crossed conductors. These conductors are hereinafter referred to as word lines or bit lines. One of the above-mentioned stacks of magnetic layers and tunnel dielectric layers is provided at each conductor intersection. A current flows through both of these conductors, and this current forms one magnetic field in the stack. A magnetic field generated by overlapping these plural magnetic fields affects each magnetic layer. When the strength of each magnetic field is sufficiently large, the magnetizations of these magnetic layers exposed to the magnetic field are reversed.
[0007]
In addition, a plurality of reading methods for evaluating the contents of the memory cell can be considered. For example, the cell resistance can be directly evaluated (direkte Bewertung) and possibly followed by comparison with, for example, the reference resistance of another cell. In this case, however, a parameter variation is caused in which a difference in measured values of magnetoresistance is 10 to 20% or more depending on the thickness of the tunnel oxide of the adjacent cell.
[0008]
Alternatively, the direct reading can be switched. In this case, during current measurement to determine the memory cell resistance, this memory cell resistance is increased to perform magnetization reversal (that is, reprogramming) of the cell contents. In this case, when the magnetization state of the cell is known, if the current intensity is changed in order to change the resistance, the magnetization state is known until the current flows. The same is true when the current strength is not changed. However, when the voltage is low, a high cell resistance has the disadvantage that the expected change in current occurs only to a thousandth (ie, difficult to detect). However, this reading method is destructive in the first place. That is, if the resistance is changed, it is necessary to restore the memory cell contents before the read process.
[0009]
Another method (Moeglichkeit) is disclosed in DE 199 47 118 A1. In sequence, two voltages are each stored in the capacitor. These voltage values depend on the resistance of the memory cell before and after attempting programming or switching. These voltages can be compared, for example, in a differential amplifier, by defining them with specific other resistors, respectively. Only if the programming attempt is successful will the different voltages stored in the capacitors be obtained. In principle, however, there are also disadvantages here. That is, since it is a destructive reading method, it is necessary to rewrite the contents of the original storage device, and since re-reading is complicated, time and energy are wasted. In addition, this solution can reduce the parasitic effect due to the current through the unselected word and bit lines, but this inevitably limits the size of the cell array. Have
[0010]
Based on the above prior art, an object of the present invention is to provide a semiconductor memory device including a magnetoresistive memory cell and a driving method thereof. By using this method, the above inconvenience can be avoided. In particular, a memory cell or memory cell array can be evaluated so as to be fast, accurate and reliable while avoiding parasitic effects.
[0011]
This object is solved by a semiconductor memory device in which magnetoresistive memory cells are arranged at the intersections of word lines and bit lines. In the magnetoresistive memory cell, each of the magnetoresistive memory cells includes one first magnetic layer having one first magnetization axis, one second magnetic layer having one second magnetization axis, and And at least one insulating layer disposed between the layers. The magnetoresistive memory cell is characterized in that the first magnetic layer is made of a hard ferromagnetic material, the second magnetic layer is made of a soft ferromagnetic material, and the first magnetization axis and the second magnetization axis. Means that they intersect when projected onto the spreading surface of the word lines and bit lines. This object is solved by a method for driving a semiconductor memory device.
[0012]
Other aspects of the invention are indicated in the dependent claims.
[0013]
These magnetoresistive memory cells are a TMR (tunnel magnetoresistive) element, a GMR (giant magnetoresistive) element, or these arranged at the intersection of the word line and the bit line of the memory cell array, respectively. And similar storage elements. In accordance with the present invention, these elements include a hard magnetic layer and a soft magnetic layer separated from the hard magnetic layer by a thin tunnel oxide barrier, eg, an insulating layer. The characteristic of the hard ferromagnetic layer (hartmagnetische ferromagnetische Schicht) is that when the externally supplied magnetic field is turned off, there is residual magnetization (so-called residual magnetization), that is, there is magnetic hysteresis. In the point.
[0014]
Also, a soft ferromagnetic layer is defined by a small hysteresis curve (ie, only a small remanence and a corresponding small coercive field strength. Therefore, this layer is a hard magnetic layer in the present invention). It does not function as a storage layer that can be turned on and off by supplying a magnetic field (for example, passing a current through a word line and / or a bit line), and reads information stored in a hard magnetic layer (that is, this Function as a sensing layer for directing (residual) magnetization in the layer, very little remanent magnetization in the soft magnetic layer does not affect the read result, thus the external Stoerfelder Even if the magnetization of the soft magnetic layer is changed via the gap, it is preferable that it is not at all important (kaum eine Rolle spielen).
[0015]
These magnetic layers have uniaxial anisotropy (that is, their weak magnetization axes). In these layers, the actual magnetization direction shows the same direction as the axis along the axis, or the direction completely opposite to the axis. In accordance with the present invention, both axes of both layers intersect in a plane defined by the bit and word lines and are not parallel to each other as is conventional. These axes are preferably located perpendicular to each other. The magnetization axis of the soft magnetic layer is oriented so that the magnetization direction of this layer can be influenced, for example, by an external magnetic field induced by the current flow of the word line. Due to this influence, the magnetization direction of the soft magnetic layer stably disposed along the magnetization axis is shifted (that is, rotated). At this time, the magnetization direction forms an angle with the soft or hard magnetization axis indicating the unstable position (Konfiguration) of the magnetization.
[0016]
Therefore, in an effective form of the present invention, the magnetization axis of the soft magnetic layer is arranged substantially parallel to the connected word lines. An inclined arrangement is also possible. Only when the magnetization axis is arranged substantially perpendicular to the word line can the actual magnetization be prevented from shifting in the (zu) angle direction of the strong magnetization axis.
[0017]
It can be logically understood that the present invention functions even if the above-described bit line and word line functions are exchanged. This case is also included in the present invention.
[0018]
Uniaxial anisotropy of the storage layer is defined by the deposition / heat treatment in the magnetic field of the storage element and / or the shape of the storage element. In particular, no antiferromagnet (so-called pinning layer) is required.
[0019]
The effect of the present invention is based on the detection of various resistances of the memory element. This detection is performed when information content is read according to the magnetization direction of the hard magnetic layer when a change in the magnetic field that directly affects the magnetization direction of the soft magnetic layer occurs. This shifts the magnetization direction of the soft magnetic layer. To be precise, the magnetization direction of the soft magnetic layer is shifted in the parallel or antiparallel direction in accordance with the magnetization direction of the hard magnetic layer. In accordance with these mutual directions, the magnetoresistance of the element detected by current measurement or voltage measurement is changed.
[0020]
In another particularly advantageous form of the invention, the current flowing through the word line is varied with time, preferably as an alternating current having a sinusoidal shape. This current forms an alternating magnetic field (magnetisches Wechselfeld) parallel to the strong magnetization direction of the detection layer. As a result, the magnetization of the soft magnetic layer is shifted from the weak magnetization direction to the same phase as the magnetic field. The angle at this time may be 90 ° at the maximum when the magnetization axes of the soft magnetic layer and the word line are arranged in parallel.
[0021]
Since magnetization changes linearly with a strong magnetization direction and this change is not hysteresis, the magnetization of the soft magnetic layer and the external magnetic field are in phase. Similarly, the magnetization of the soft magnetic layer is less than the saturation magnetic field strength (coercive force, anisotropic magnetic field strength) and changes in the shape of a sine wave so as to oscillate, but the magnetic field exceeds this coercive force. When the amplitude is generated, it becomes saturated (see FIG. 3). As a result, a magnetized shape having a rectangular shape is generated. In addition, a signal curve with a rectangular shape can also be evaluated according to the invention, but the amplitude of the measured current or voltage signal can no longer be increased when a field amplitude above this coercivity occurs.
[0022]
Therefore, the magnetoresistance _RMR also changes depending on the frequency of the alternating current.
[0023]
R _MR = R ₀ + (1/2) ΔR (1 ± cos α) = R ₀ + (1/2) ΔR (1 ± sin φ)
The symbols + and-are two possible states of the magnetization direction of the hard magnetic layer. α is an angle between the magnetization direction of the hard magnetic layer and the magnetization direction of the soft magnetic layer. φ = (n / 2) −α is the phase angle of the external magnetic field. ΔR is the magnetization shows a difference in magnetic resistance in the direction as parallel direction state and antiparallel, the value is usually 10% to 30% of R _MR.
[0024]
If the magnetic field amplitude of the alternating magnetic field (Wechselfeldes) is less than the coercivity of this layer, the stored information in the hard magnetic layer is reliably retained. The coercive force of the hard magnetic layer is much larger than that of the soft magnetic layer (in this case, it is preferable to select the magnetic field amplitude), and in the reading method of the present invention, the magnetic field affects the storage element. This condition can be easily realized.
[0025]
For reading, a varying voltage or a varying current is applied to, for example, the actually selected word line and the ground potential is selected using another resistance that is well selected and much lower than the magnetoresistance of the storage cell. Connect to (verbunden). The semiconductor memory device further includes an AC voltage source or an AC current source. By selecting other resistors, the voltage drop or current flow reaction at the storage element can be reliably reduced as much as possible with respect to the signal in the word line and storage element (auf).
[0026]
When the relational expression U _MR = I _MR · R _MR is valid, the voltage U _MR between the word line and the bit line measured by the voltage measuring device in the semiconductor memory device or applied to the memory element The voltage changes. This change is accompanied by a change in the current I _MR through the storage element and a change in the magnetoresistance R _MR of the selected storage element. However, these changes change in phase or in phase exactly depending on the parallel or antiparallel direction of magnetization. Thus, different voltage signals are generated for each of the two directions. Further, a relational expression similar to this is effective when a current passing through the memory element of the magnetoresistive memory cell is measured using a current measuring device (for example, along the bit line).
[0027]
The present invention will be described in detail according to embodiments with reference to the drawings. FIG. 1 is a diagram showing an embodiment according to the present invention of a memory cell array. FIG. 2A is a plan view of the memory cell showing the directions of the magnetization axis and the magnetic field. FIG. 2B is a perspective view showing the possibility of setting (how the magnetization direction can be set) and the magnetization shift of the soft magnetic layer of the present invention. FIG. 3 is a graph showing a diagram (Abbildung) of a changing external magnetic field with respect to the magnetization of the soft magnetic layer. FIG. 4A is a circuit diagram showing an embodiment of the present invention using an alternating current supplied to a word line. FIG. 4B is a circuit diagram showing an embodiment of the present invention using an alternating voltage applied to a word line. FIG. 5 is an illustrative graph showing the alternating voltage measured at the storage element resulting from the alternating current supplied to the word line in accordance with the present invention to change the two directions of magnetization of the hard magnetic layer. .
[0028]
The structure of the present invention of the memory cell 1 disposed between the word line 8 and the bit line 9 in the semiconductor memory device 2 is shown in FIG. The memory cell 1 or a memory element (TMR element) having a tunnel magnetoresistance includes a hard ferromagnetic layer 10, an insulating layer 12 (that is, a tunnel oxide), and a soft ferromagnetic layer 11. The magnetization directions 20 and 21 are parallel to the word lines or bit lines connected to the layers, respectively, in the absence of an influencing magnetic field. The word line 8 is arranged perpendicular to the bit line 9. Therefore, the weak magnetization axes 30 and 31 of the hard ferromagnetic layer 10 and the soft ferromagnetic layer 11 along the actual direction of magnetization are also perpendicular to each other.
[0029]
Information is stored by the magnetization direction of the hard ferromagnetic layer 10. For example, in FIG. 2b, the logical value “1” corresponds to the leftward direction, and the logical value “0” corresponds to the rightward direction. The originally weak magnetization direction 21 in the soft ferromagnetic layer 11 is accidental when no current is flowing and has no effect on the stored information for the time being.
[0030]
The plan view of FIG. 2 a shows the effect of the alternating current I _Y flowing from the alternating current source 50 to the word line 8 for reading the stored contents for one of the memory cells 1. In this embodiment, the direction of the word line 8 is the Y coordinate. The current flow I _Y generates a magnetic field H (vector) particularly in the soft ferromagnetic layer 11 disposed below the word line 8 in the plan view. Since the weak magnetization axis 31 of the soft magnetic layer 11 is parallel to the word line 8, the direction of the magnetic field is perpendicular to the weak magnetization axis. Due to the external magnetic field H (vector), the magnetization direction 21 of the soft magnetic layer is shifted from the position of the weak magnetization axis 31 to the angle φ. This is illustrated in the schematic tilt diagram on the right side of FIG.
[0031]
3, the strong soft magnetic layer functioning as a detection layer magnetization component M _X, the relationship of the AC magnetic field H in the form of a sine wave (vector) are shown for the two sides. In the first aspect (thick sine wave curve), the magnetic field amplitude H _X0 is less than or equal to the coercivity of the soft magnetic layer (H _X0 ≦ H _CW ). That is, in the case of uniaxial anisotropy, the strength of the anisotropic magnetic field is the same. Also, the strength of the magnetization shift has a sine wave shape.
[0032]
In the second side surface (sinusoidal curve shown by a thin line), H _X0 > H _CW and as a result of the magnetization reaching a saturation state, a magnetized shape having a rectangular shape is generated.
[0033]
FIG. 4a shows a schematic circuit diagram of a part of the TMR cell array of the embodiment. In order to write the information in the storage device, a DC current pulse of sufficient magnitude and in a certain direction is passed through the intersecting wires in the selected element, as in the prior art. In order to write, the generated magnetic field needs to exceed the switching threshold of the hard magnetic layer.
[0034]
The information content of the selected memory cell is read through the word line 8 and the alternating current I _Y = I _Y0 · sin ωt having a constant amplitude I _Y0.
Further, the analysis is performed by analyzing the voltage between the word line 8 and the bit line 9 that intersect in the selected memory cell. The unselected lines are insulated from the alternating current source 50 and the reading electronics including the voltage measuring device.
[0035]
As a result of adjusting the magnetization direction 21 of the soft magnetic layer 11 by the current I _Y , similarly, the angle between the magnetization direction 20 of the soft magnetic layer 11 and the magnetization direction 21 of the hard magnetic layer 10 is changed, so that the magnetic The resistance _RMR changes to a sine wave shape. For example, when the other resistance of the circuit shown in the lower end of FIG. 4a is of an appropriate magnitude, the current I _MR that actually flows through the memory element has a certain relationship with the supplied current I _Y. Therefore, the voltage dropped at the storage element is
U _MR = c · I _Y · R _MR
It is. Here, C≈R _L / R ₀ , and examples of these values are the wiring resistance R _L ≈1 kΩ and the average value of magnetic resistance R ₀ ≈100 kΩ.
[0036]
By the above equation,
U _MR = c · I _Y0 · sin ωt · (R ₀ + (1/2) ΔR (1 ± sin ωt))
U _MR = cI _Y0 R ₀ sin ωt + (1/2) cI _Y0 ΔR sin ωt ± (1/2) cI _Y0 ΔRsin ² ωt
U _MR = U ₁ + U ₂ + U ₃
It becomes. The following three voltage components are added to this equation.
[0037]
U ₁ = ± (c / 4) · I _Y0 · ΔR
U ₂ = c · I _Y0 (R ₀ + (1/2) ΔR) sin ωt
U ₃ = ± (c / 4) · I _Y0 · ΔR · cos 2ωt
These are the constant voltage contribution U ₁ , the fundamental wave U ₂ , and the first harmonic U ₃ . A rectifying effect is generated from a magnetic resistance that is not linear. Due to this rectification effect, a DC voltage component U ₁ is generated. The sign (Vorzeichen) of the DC voltage component changes according to the magnetization direction 20 of the hard magnetic storage layer 10 and the stored information. FIG. 5 shows the relationship between time and phase in an appropriate and appropriate size when H _XO ≦ H _CW .
[0038]
The amplitude of the applied voltage U _MR in the storage element, a first half period (Halbperiode, half-cycles) and the second half period are different. At this time, the sign of the generated DC voltage component is determined by the magnetization direction 20 of the hard magnetic storage layer 10. This is apparent from the thick or thin curve in FIG.
[0039]
When a larger magnetic field H _X (H _CH > H _X0 > H _CW ) (H _CH is the coercive force of the hard magnetic layer 10) is supplied, the magnetization component M _{X in} the magnetization direction 21 of the soft magnetic layer 11 becomes X It becomes saturated in the direction (that is, the direction of the bit line 9). Next, as described above, the curve of the magnetization component M _X and reluctance R _MR is in the shape of a rectangle. In this case, the signal can be zerlegened into more harmonics. However, according to the invention, this rectangular shaped curve or any other alternating signal appearing periodically can also be evaluated.
[0040]
Moreover, by determining the sign of U _1, it is effective to be deduced the information content of the cell. It is not necessary to accurately recognize the average cell resistance R ₀ and the magnetoresistive effect ΔR. In this embodiment, the voltage measuring device shown in FIG. 4a is used for detection.
[0041]
Further, the voltage component U ₂ does not include information regarding the storage contents of the memory cell 1.
[0042]
On the other hand, the first harmonic U ₃ having two (doppelten) frequencies compared to the fundamental wave similarly includes a code along the magnetization direction 20 of the hard magnetic layer 10. Further, like U ₁ , it is not necessary to accurately recognize the average cell resistance R ₀ and the magnetoresistance effect ΔR. In accordance with the present invention, it is sufficient to define a sign or phase angle with respect to I _Y.
[0043]
An AC current in the form of a sine wave supplied with an amplitude I _Y0 = 1 mA and a ratio (Verhaeltnis) ΔR / R ₀ = 20% causes the following voltage component drop.
[0044]
U ₁ = 50 mV
U ₂ = 1.1V
U ₃ = 50 mV
Therefore, the detected signal is 5% of the fundamental wave. Therefore, such a measurement can be technically easily performed.
[0045]
A DC voltage some of the components U ₁ a (Anteil), by integrating (Integration) that during the measuring time of one or few amplitudes periods, separated from the AC voltage component U _2. Alternatively, a part (Anteil) of the DC voltage component U ₁ is derived from the general signal (Gesamtsignal) U _MR . At an alternating current frequency of 100 Mhz, the measurement time for this example is 10 nanoseconds. The measurement time can be further shortened by minimizing the RC wiring. On the other hand, by increasing the integration time, the signal-to-noise ratio, that is, the read reliability can be increased. Furthermore, it is useful for this purpose to use low-pass filters, amplifiers and / or comparators in the voltage measuring device for reading the information content.
[0046]
The first harmonic U ₃ can be detected by phase selective amplification (eg, so-called Lock-in-Technik). This technique can also increase the signal-to-noise ratio.
[0047]
FIG. 4b shows a schematic circuit diagram of the semiconductor memory device while the current measuring device 61 is measuring the current through the memory cell for another embodiment similar to that described above. In this circuit diagram, the voltage source 51 applies an alternating voltage to the word line 8. Similar to the case of the voltage signal, a current term (Stromterme) including a direct current, a fundamental wave, and a harmonic is generated for the current signal to be measured as shown in FIG. The direct current term or the harmonic term is labeled according to the magnetization direction 20 of the hard magnetic layer 10 (vorzeichenbehaftet), and this term is read in this embodiment in the same manner as in the previous embodiment. Then, for example, integrated from overall signal U _MR (Integration), a low-pass filter, derived by such comparators evaluate.
[0048]
Another advantage of the present invention is that it prevents parasitic effects in a wide range by connecting (in) storage elements 1 in the resistance matrix of the storage cell array. The current through the shunt resistor (Nebenschlusswiderstaende) is significantly reduced by the high resistance of the TMR element.
[0049]
In summary, the following applies to the present invention. That is, in the memory cell array of the semiconductor memory device 2, the memory element 1, that is, the memory cell 1 having the magnetoresistive effect is characterized by the hard magnetic memory layer 10 and the soft magnetic sensing layer 11 where the weak magnetization axes 30 and 31 intersect is there. The magnetization axis 30 of the hard magnetic layer 10 is parallel to the wiring (for example, the bit line 9) connected to this layer. The magnetization axis 31 of the soft magnetic layer is parallel to the wiring (for example, the word line 8) connected to this layer. These axes, each having parallel wiring, are preferably substantially perpendicular to each other.
[0050]
A voltage signal or a current signal is supplied to each selected wiring (for example, word line 8) via the AC voltage source 51 or the AC current source 50. Thereby, the magnetization direction 21 of the soft magnetic layer 11 is deviated from the weak magnetization axis 31 in the shape of a sine wave. As a result, the magnetoresistance of the memory cell changes with the supplied signal. Depending on the magnetization direction 20 of the hard magnetic layer 10, in-phase or anti-phase overlap of the signal and resistance occurs. Thereby, for example, a signed DC voltage and a first harmonic can be detected as components from the signal. This code provides stored information.
[Brief description of the drawings]
[0051]
FIG. 1 is a diagram showing an embodiment of a memory cell array according to the present invention.
FIG. 2A is a plan view of a memory cell showing directions of a magnetization axis and a magnetic field, and FIG. 2B is a perspective view showing a setting possibility and magnetization deviation of a soft magnetic layer of the present invention. is there.
FIG. 3 is a graph showing a diagram (Abbildung) of an external magnetic field that changes with respect to the magnetization of a soft magnetic layer.
4A is a circuit diagram showing an embodiment of the present invention using an alternating current supplied to a word line, and FIG. 4B is a circuit diagram illustrating an embodiment of the present invention using an alternating voltage applied to a word line. It is a circuit diagram which shows the Example of.
FIG. 5 is an illustrative graph showing the alternating voltage measured at a storage element resulting from an alternating current applied to a word line in accordance with the present invention to provide two different orientations of the magnetization of a hard magnetic layer. It is.
[Explanation of symbols]
[0052]
DESCRIPTION OF SYMBOLS 1 Memory cell, Memory element 2 Semiconductor memory device 8 Word line 9 Bit line 10 Hard magnetic layer 11 Soft magnetic layer 12 Insulating layer, tunnel oxide 20 Magnetization direction 21 of hard magnetic layer Magnetization direction 30 of soft magnetic layer Magnetization axis 31 Magnetization axis of soft magnetic layer 50 AC source 51 AC voltage source 60 Voltage measuring device 61 Current measuring device

Claims (23)

A magnetoresistive memory cell (1) is a semiconductor memory device (2) arranged at an intersection of a word line (8) and a bit line (9), and the magnetoresistive memory cell has a first magnetization axis ( 30) at least one first magnetic layer (10), a second magnetic layer (11) having a second magnetization axis (31), and an insulating layer (12) disposed between these layers. In the semiconductor memory device (2) included,
A first magnetic layer (10) formed of a hard ferromagnetic material;
A second magnetic layer (11) formed of a soft ferromagnetic material;
The semiconductor memory device (2), wherein the first magnetization axis (30) and the second magnetization axis (31) intersect each other when projected onto the spreading surface of the word line (8) and the bit line (9). ). The semiconductor memory device (2) according to claim 1, characterized in that the magnetoresistance is based on a tunnel magnetoresistance (TMR) effect combining layer materials. The semiconductor memory device according to claim 1, wherein the magnetoresistance is based on a giant magnetoresistance (GMR) effect obtained by combining layer materials. The second magnetization axis (31) of the second magnetic layer (11) is arranged substantially parallel to the first line of the word line (8) or the bit line (9). The semiconductor memory device (2) according to any one of claims 1 to 3. 5. The semiconductor memory device according to claim 4, wherein the first magnetization axis (30) of the first magnetic layer (10) is arranged substantially perpendicular to the second magnetization axis (31). . In the semiconductor memory device (2) according to any one of claims 1 to 5,
A circuit structure for evaluating the information content of at least one of the magnetoresistive memory cells (1),
An alternating current source (50) connected to the memory cell (1) via a word line (8);
A voltage measuring device (60) connected to the word line (8) and to the memory cell (1) via the bit line (9) for voltage measurement;
A semiconductor memory device, wherein a memory cell (1) having a magnetic resistance is connected between a word line (8) and a bit line (9). The word line (8) connected to the alternating current source (50) is connected to the ground potential via another resistor,
The semiconductor memory device (2) according to claim 6, wherein the resistance of the magnetoresistive memory cell is larger than that of other resistors. The word line (8) has a wiring resistance,
8. The semiconductor memory device (2) according to claim 7, wherein a value of the other resistor is a value equal to or greater than a wiring resistance. 9. The semiconductor memory device (2) according to any one of claims 6 to 8, wherein the voltage measuring device (60) includes a device for detecting a DC voltage component. The device for detecting a DC voltage component comprises at least one member of a group consisting of a low pass filter, an amplifier, a comparator, and an integrated device. Semiconductor memory device (2). 11. The semiconductor memory device (1) according to any one of claims 6 to 10, characterized in that the voltage measuring device (60) includes a device for phase-selectively measuring voltage harmonics. 2). In the semiconductor memory device (2) according to any one of claims 1 to 5,
A circuit structure for evaluating the information content of at least one of the magnetoresistive memory cells (1),
An alternating voltage source (51) connected to the memory cell (1) via the word line (8);
A current measuring device (61) connected between the bit line (9) and the ground potential for measuring the current flow;
A semiconductor memory device (2), wherein a memory cell (1) having a magnetic resistance is connected between a word line (8) and a bit line (9). The word line (8) connected to the AC voltage source (51) is connected to the ground potential via another resistor,
13. The semiconductor memory device (2) according to claim 12, wherein the magnetic resistance of the memory cell is larger than that of other resistances. The word line (8) has a wiring resistance,
14. The semiconductor memory device (2) according to claim 13, wherein the other resistance is equal to or greater than a wiring resistance value. 15. The semiconductor memory device (2) according to any one of claims 12 to 14, wherein the current measuring device (61) includes a device for detecting a direct current component. 16. The apparatus of claim 15, wherein the apparatus for detecting a direct current component includes at least one of a group of elements consisting of a low pass filter, an amplifier, a comparator, and an integrated device. Semiconductor memory device (2). 17. The semiconductor memory device according to claim 12, wherein the current measuring device (61) includes a device for measuring current flow harmonics in a phase selective manner. 18. The method of driving a semiconductor memory device (2) according to any one of claims 1 to 17, for evaluating the information content of at least one of the magnetoresistive memory cells (1),
Supplying an alternating current or alternating voltage having a constant frequency and amplitude to a word line (8) connected to the storage cell (1) to be evaluated;
a) From the strength of the current flow through the stack (10, 11, 12) of the memory cells (1) having magnetoresistance, the current measuring device (61) is used.
b) Or, from the voltage between the bit line (9) and the word line (8), using the voltage measuring device (60),
Measuring the derived signal during a measurement time;
Evaluating the information content of the memory cell (1) as a function of the signal curve during the measurement time. The method of claim 18, wherein
The signal derived by the measurement using the current measuring device (61) or the voltage measuring device (60) includes a DC current component or a DC voltage component of the measured AC current curve or AC voltage curve,
The evaluation is performed according to the sign of the DC current component or DC voltage component. The method according to claim 18 or 19, wherein
AC current in which the signal derived from the measurement using the current measuring device (61) or the voltage measuring device (60) has a frequency that is twice the supplied AC current frequency or AC voltage frequency (mit dem Zweifachen) Including the first harmonic of the curve or AC voltage curve,
In the case of a predetermined phase, the evaluation is performed according to the sign of the harmonic. The method according to claim 20, characterized in that a phase selective lock-in technique is used. The method according to any one of claims 18 to 21, characterized in that the measurement time is shorter than 20 nanoseconds. The method according to any one of claims 18 to 22, characterized in that the alternating current frequency or alternating voltage frequency is higher than 100 megahertz.

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