JP2005354855A - Rush current suppressing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a rush current suppressing circuit that can suppress a rush current that occurs to a load circuit by a simple circuit structure when a power supply source is turned on. <P>SOLUTION: This circuit is constituted of a transistor 4 whose emitter and collector are connected between the output side of the power supply source 2 and the input side of a load circuit 5, an operation circuit 6 that supplies a base current to the transistor 4 between the output side of the power supply source 2 and the base of the transistor 4 by turning on the power supply source 2 to operate the transistor 4, and a base current control circuit 7 that controls the base current at the base of the transistor 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inrush current suppression circuit provided in, for example, a control device of a power system.

  Inrush current at power-on becomes a serious problem when a load circuit such as a print card is a capacitive load. In order to cope with this problem, in the conventional inrush current suppression circuit, an integration circuit that charges the input voltage, an input voltage detection circuit that detects a change in the input voltage during charging, and an output voltage supplied to the load circuit. An output voltage detection circuit that detects a change, a differential amplification circuit that inputs a signal from the input and output voltage detection circuit, amplifies a voltage corresponding to a difference between input and output voltages, and a change in the output voltage of the differential amplification circuit Switching means consisting of a transistor that changes the mutual inductance according to the current, and by gradually increasing the drive voltage of the transistor that is the switching means while monitoring the output voltage supplied to the load circuit, the inrush current is completely suppressed Like to do. (For example, see Patent Document 1)

Japanese Patent Laid-Open No. 10-327057 (page 4, FIG. 1)

  Since the conventional inrush current suppression circuit is configured by combining a plurality of circuits as described above, the circuit configuration becomes complicated and large, and there are problems in terms of circuit arrangement space, reliability, and cost.

  In addition, the inrush current suppression circuit used for the control device of the power system has a complicated structure as described above with respect to the inrush current generated in the load circuit when the power supply of the control device is turned on several times a year due to maintenance. A circuit configuration that does not completely suppress the inrush current using the circuit configuration, but can suppress the inrush current to a magnitude that does not affect the operation of the load circuit even if an inrush current occurs. There was also a request that it should be realized easily.

  The present invention has been made to solve the above-described problems, and is to obtain an inrush current suppression circuit capable of suppressing the occurrence of an inrush current that affects the operation of the load circuit as a simple circuit configuration. It is the purpose.

  The inrush current suppressing circuit according to the present invention includes a transistor having an emitter and a collector connected between the output side of the supply power source and the input side of the load circuit, and the supply power source between the output side of the supply power source and the base of the transistor. Is turned on to supply a base current to the transistor to operate the transistor, and a base current control circuit for controlling the base current is provided at the base of the transistor.

  According to the present invention, the inrush current suppression circuit has a simple circuit configuration, and the inrush current generated when the power supply is turned on is suppressed to a size that does not affect the load circuit. This has the effect of improving reliability and reducing costs.

Embodiment 1 FIG.
FIG. 1 is a circuit configuration diagram of an inrush current suppression circuit 1 according to the present invention. In FIG. 1, the output of the power supply 2 is input to the inrush current suppression circuit 1 surrounded by the alternate long and short dash line through terminals 3a and 3b. This inrush current suppression circuit 1 is connected in parallel between the base and emitter of the transistor 4 in order to operate the PNP type transistor 4 connected to the terminal 3a and the transistor 4 when the power supply 2 is turned on. The start resistor 6 that is an operating circuit and the base current control circuit that is connected to the base side of the transistor 4 and controls the base current in order to suppress the inrush current that flows when the power supply 2 is turned on. The resistor 7 is used. The inrush current prevention circuit 1 suppresses an inrush current generated when the power supply 2 is turned on, and is input to the load circuit 5 via the terminals 3c and 3d.

  FIG. 2 is an operation state diagram of the inrush current suppression circuit 1. In FIG. 2, the horizontal axis represents elapsed time, and the vertical axis represents current or voltage. Time t1 is when the power supply 2 is turned on. From this time, the power supply 2 shows a constant supply power voltage 2a. At the same time, a base current 4a and a collector current 4b indicated by chain lines respectively flow in the transistor 4. The collector current 4b rises steeply at time t1, and then, for a predetermined time, a region in which the magnitude of the collector current 4b is limited based on the product relationship between the transistor 4 and its current amplification factor (hereinafter referred to as collector current 4b). After passing through a current limiting region (4c), a region (hereinafter referred to as a collector) showing a decreasing tendency based on the time constant determined from the resistance of the transistor 4 and the capacitance of the load circuit 5 when the transistor 4 is activated. After passing through 4d (referred to as a current attenuation region), the load circuit 5 gradually approaches the steady load current 5a included in the load circuit 5 indicated by a one-dot chain line.

  Next, the operation of the first embodiment will be described with reference to FIGS.

  When the power supply 2 is turned on at time t1 and the power supply voltage 2a is supplied to the inrush current suppression circuit 1, the base current 4a flows to the limiting resistor 7 via the starting resistor 6 and the transistor 4 is activated. The base current 4a during the operation of the transistor 4 includes the base-emitter voltage of the current control transistor 4 as VBE, the resistance value of the starting resistor 6 as R6, the resistance value of the limiting resistor 7 as R7, and the supply power voltage 2a. Is VS and the base current 4a is IB, the following equation (1) is established, and the base current 4a (IB) is limited by the starting resistor 6 (R6) and the limiting resistor 7 (R7). Become.

IB = [(VS−VBE) / R7] − (VBE / R6) (1)

  Further, the load current 5a flowing through the load circuit 5 is equivalent to the collector current 4b of the transistor 4. When the current amplification factor of the transistor 4 is hFE, the load current 5a is IL, and the collector current 4b is IC, the following ( 2), and the base current IB of the transistor 4 is limited by the formula (1). As a result, the load current 5a (IL) flowing through the load circuit 5 is limited.

IC = IL = hFE × IB (2)

  From the above, when the power supply 2 is first turned on, an inrush current flows through the inrush current suppression circuit 1 based on the capacitive load of the load circuit 5, and this inrush current is shown in the collector current limiting region 4c. In other words, it is limited by the product value of the base current 4a of the transistor 4 limited by the starting resistor 6 and the limiting resistor 7 and the current amplification factor hFE. Thereafter, the collector current 4b gradually approaches the steady load current 5a that can be consumed steadily by the load circuit 5 through the collector current drop region 4d.

  In the steady state, it is necessary to supply a sufficient load current to the load circuit 5 from the transistor 4. Therefore, the limiting resistor 7 is set so that the collector current supplied from the power supply 2 to the load circuit 5 is larger than the maximum load current of the load circuit 5 in consideration of the steady load current of the load circuit 5. ing.

  According to the present embodiment, the inrush current suppression circuit has a simple configuration as compared with the conventional case, and a transient inrush current that causes malfunction or failure to the load circuit 5 of the control device when the power supply 2 is turned on is provided. As a result, it is possible to reduce the size, improve the reliability and reduce the cost.

Embodiment 2
In the first embodiment, when the power supply 2 is turned on, the collector current 4b changes abruptly. Therefore, the load circuit 5 may be affected by the change in the abrupt collector current 4b. In the circuit configuration diagram of FIG. 3, in order to alleviate this steep change in the collector current 4b, a start-up relaxation capacitor 10 is provided in parallel with the start-up resistor 6 as an operation circuit to configure a first-order lag circuit.

  FIG. 4 is an operation state diagram of the second embodiment. After the power supply 2 is turned on at time t1, a region in which the base current 4a tends to gradually increase based on a time constant determined by the product of the starting resistor 6 and the starting relaxation capacitor 10 (hereinafter referred to as a base current gradually increasing region). 4e and a region (hereinafter referred to as a collector current relaxation region) 4f in which rising of the collector current 4b is relaxed corresponding to the base current gradually increasing region 4e appear. 3 and FIG. 4, the description of the same reference numerals as those described in Embodiment 1 is omitted.

  Next, with respect to the operation of the second embodiment, portions different from the first embodiment will be described with reference to FIGS.

  When the power supply 2 is turned on at time t1 and the voltage of the power supply voltage 2a is supplied to the inrush current suppression circuit 1, the start resistor 6 and the start relaxation capacitor 10 are connected in parallel. The charging current flows through the activation relaxation capacitor 10 until the voltage applied to both ends of the activation relaxation capacitor 10 reaches the rising voltage between the base and the emitter of the current control transistor 4. The change in the base current 4a when the supply power source 2 is turned on is assumed to be a state in which the activation relaxation capacitor 10 is discharged when the supply power source 2 is turned on. The impedance Z is excessive, the resistance value of the starting resistor 6 is R6, the capacitance of the starting relaxation capacitor 10 is C10, and t is the time elapsed from the time t1 when the power supply 2 is turned on. Is represented by the following equation (3).

Z = (1-exp (−t / (C10 · R6))) · R6 (3)

  Since this impedance Z corresponds to R6 in the equation (1) which is the calculation formula of the base current 4a, the base current 4a is VS for the power supply voltage 2a, IB for the base current 4a, and the limiting resistor 7 When the resistance value of R7 is R7 and the base-emitter voltage of the transistor 4 is VBE, the following equation (4) is obtained.

IB = ((VS-VBE) / R7)-(VBE / (1-exp (-t / C10.R6) .R6)] (4)

  From the above, when the power supply 2 is turned on, the term (VBE / (1-exp (−t / C8 · R6) · R6)] shown in the equation (4) becomes a large value. Then, the value of the base current 4a decreases, and then gradually increases as shown in the base current gradually increasing region 4e.

  Further, the collector current 4b equivalent to the load current 5a flowing through the load circuit 5 is limited by the product of the base current 4a and its current amplification factor as shown in the above equation (2). Reflecting the gradual increase state of the base current 4a when is turned on, its rise becomes gradual as shown in the collector current relaxation region 4f.

  According to the present embodiment, the load is applied to the load circuit 5 when the power supply 2 is turned on by providing the start-up relaxation capacitor 10 in parallel with the start-up resistor 6 in the configuration of the first embodiment to configure the first-order lag circuit. By slowing the rise of the current, compared to the effect of the first embodiment, there is an effect that the reliability can be further improved by preventing malfunction and failure of the control device due to the inrush current.

Embodiment 3
In the first embodiment, for example, when the supply power supply voltage 2a from the supply power supply 2 is increased, the base current 4a of the transistor 4 is increased, so that the inrush current when the supply power supply 2 is turned on is more than necessary. Can be large. In FIG. 5, in order to prevent this, the constant current diode 11 is used as a base current control circuit instead of the limiting resistor 7 shown in the first embodiment. In this case, assuming that the constant current flowing through the constant current diode 11 is ID, the voltage VS of the supply power supply voltage 2a is related to ((VS−VBE) / R7) in the equation (1) which is the calculation formula of the base current 4a. ) Is replaced by the constant current ID of the constant current diode 20, and is expressed by the following equation (5), and is not affected by the voltage VS of the supply power supply voltage 2a. In FIG. 5, the description of the same reference numerals as those described in Embodiment 1 is omitted.

IB = ID-VBE / R6 (5)

  According to the present embodiment, since the constant current diode 11 is used in place of the limiting resistor 7 shown in the first embodiment, the transistor 4 is not affected regardless of the fluctuation of the power supply voltage 2a of the power supply 2. Since the base current 4a can be kept constant, there is an effect that the inrush current can be stably suppressed.

  In addition, although this Embodiment showed what was applied with respect to Embodiment 1, it cannot be overemphasized that it is applicable similarly to Embodiment 2. FIG.

Embodiment 4
In the first or second embodiment, the PNP type transistor 4 is used. However, since this PNP type transistor generally has a base-emitter voltage as small as about 0.6 V, it is difficult to construct an operation circuit of a time constant circuit having a long time. In order to cope with this, FIG. 6 uses an NPN type transistor 15, a charging capacitor 16 for setting a first-order lag, and a Zener diode 17 connected to the collector side of the transistor 15 as a base current control circuit. It is configured.

  FIG. 7 is an operation state diagram of the fourth embodiment. After the power supply 2 is turned on at time t1, the base current 4a is a region where the base current 4a does not flow because the voltage applied to the charging capacitor 16 is lower than the rising voltage between the base and the emitter of the transistor 15 (hereinafter referred to as no base 4g, the voltage related to the charging capacitor 16 and the rising voltage between the base and emitter of the transistor 15 are equal, and the time t2 when the base current 4a begins to flow, A constant current is obtained after a constant region 4e where the base current 4a gradually increases (hereinafter referred to as a base current gradually increasing region) 4e. The collector current 4b is a region (hereinafter referred to as a collector current relaxation region) 4h in which the rising of the collector current 4b is suppressed by suppressing the base current 4a for a predetermined time from the time t1, the transistor 15 and its current amplification. After passing through a region (hereinafter referred to as a collector current limiting region) 4c limited based on the product of the rates, the operating resistance of the Zener diode 17, the resistance of the transistor 15 when the transistor 15 is activated, and the load circuit The steady load current 5a of the load circuit 5 indicated by the alternate long and short dash line passes through a region 4j that shows a decreasing tendency based on a time constant determined by the capacitance of the capacitor 5 (hereinafter referred to as a collector current attenuation region) 4j. Asymptotically. 6 and 7, the description of the same reference numerals as those described in the first or second embodiment will be omitted.

  Next, the operation of the fourth embodiment will be described with reference to FIGS.

  When the power supply 2 is turned on at time t 1 and the power supply voltage 2 a is supplied to the inrush current suppression circuit 1, a charging current flows through the charging capacitor 16 via the starting resistor 6. At this time, the voltage related to the charging capacitor 16 is V16, the power supply voltage 2a is VS, the resistance value of the starting resistor 6 is R6, the capacitance of the charging capacitor 16 is C16, and the power supply 2 is turned on. Assuming that the time has elapsed since time t1, the following equation (6) is obtained.

V16 = [1-exp (-t / R6.C16)]. VS (6)

  Here, since the value of the starting resistor 6 can be increased by the Zener voltage of the Zener diode 17, the time constant determined by the resistance value of the starting resistor 6 and the electrostatic capacitance of the charging capacitor 16 can be increased. The rise of the voltage related to the charging capacitor 16 can be moderated.

  As a result, for the base current 4a, the base current 4a does not flow through the transistor 15 until the voltage applied to the charging capacitor 16 reaches the rising voltage between the base and the emitter of the transistor 15. The base current region 4g in which the base current 4a does not flow is obtained from the time t1 when the transistor is turned on to the elapsed time t2 when the voltage related to the charging capacitor 16 and the rising voltage between the base and emitter of the current control transistor 15 become equal. . After the time t2 when the voltage applied to the charging capacitor 16 exceeds the rising voltage between the base and emitter of the transistor 15, the base current is applied to the base of the transistor 15 via the starting resistor 6 as shown in the base current gradually increasing region 4c. It flows while gradually increasing, and then reaches a steady value when the charging of the charging capacitor 16 is completed. The magnitude of the base current 4a at this time is as follows: IB is the base current 4a, VZ is the Zener voltage of the Zener diode, R6 is the resistance value of the starting resistor 6, VCE is the collector-emitter voltage of the current control transistor 15, Assuming that the voltage between the emitters is VBE, in a steady state, the base current 4a (IB) is equal to the current flowing through the starting resistor 6, and therefore, is expressed by the following equation (7).

IB = (VZ + VCE−VBE) / R6 (7)

  Further, the collector current 4b equivalent to the load current 5a flowing through the load circuit 5 is limited by the product of the base current 4a and its current amplification factor as shown in the above equation (2). Corresponding to the base current gradually increasing region 4e in which the base current 4a thereafter increases and the base current gradually increasing region 4e in which the subsequent base current 4a gradually increases, its rise becomes gentle as shown in the collector current relaxation region 4h. Thereafter, it gradually approaches the steady load current 5a of the load circuit 5 indicated by the alternate long and short dash line through the collector current limiting region 4c and the collector current attenuation region 4j.

  According to the present embodiment, in contrast to the configuration of the first embodiment, an NPN type transistor 15 instead of the PNP type transistor 4, a charging capacitor 16 instead of the limiting resistor 7 as a base current control circuit, and a transistor 15 The rise of the load current to the load circuit 5 when the supply power supply 2 is turned on is configured such that the value of the starting resistor 6 can be increased. By further reducing the speed, the reliability can be further improved by preventing malfunction and failure of the control device due to the inrush current.

  Further, in the present embodiment, the one using the Zener diode 16 is shown. However, since a constant voltage element can be used, the same effect can be obtained even if the diode is connected in the forward direction.

It is a circuit block diagram of the inrush current suppression circuit in Embodiment 1 of this invention. It is an operation state figure of the inrush current control circuit in Embodiment 1 of this invention. It is a circuit block diagram of the inrush current suppression circuit in Embodiment 2 of this invention. It is an operation state figure of the inrush current control circuit in Embodiment 2 of this invention. It is a circuit block diagram of the inrush current suppression circuit in Embodiment 3 of this invention. It is a circuit block diagram of the inrush current suppression circuit in Embodiment 4 of this invention. It is an operation state figure of the inrush current control circuit in Embodiment 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inrush current suppression circuit 2 Power supply 3a, 3b, 3c, 3d Terminal 4 PNP type transistor 5 Load circuit 6 Starting resistor 7 Limiting resistor 10 Starting relaxation capacitor 11 Constant current diode 15 NPN type transistor 16 Charging capacitor 17 Zener diode

Claims (6)

An inrush current suppression circuit that is provided between the output side of the power supply and the input side of the load circuit and suppresses an inrush current generated in the load circuit when the power supply is turned on;
A transistor having an emitter and a collector connected between the output side of the power supply and the input side of the load circuit, and is connected between the output side of the power supply and the base of the transistor. An operating circuit for supplying current and operating the transistor; a base current control circuit connected to the base for controlling the base current;
An inrush current suppression circuit comprising: The transistor is a PNP type transistor in which the emitter is connected to the output side of the supply power source and the collector is connected to the input side of the load circuit, and the operating circuit is a starting resistor that starts the transistor The inrush current suppression circuit according to claim 1, wherein the base current control circuit is a limiting resistor that limits the base current. The inrush current suppression circuit according to claim 2, wherein the operation circuit includes a start-up relaxation capacitor that is connected in parallel to the start-up resistor and gradually increases the base current. The inrush current suppression circuit according to claim 2, wherein the base current control circuit is a constant current diode. The transistor is an NPN type transistor in which the collector is connected to the output side of the supply power source and the emitter is connected to the input side of the load circuit, and the operating circuit is a starting resistor that starts the transistor The inrush current suppression circuit according to claim 1, wherein the base current control circuit is a charging capacitor. 6. The inrush current suppression circuit according to claim 5, wherein a Zener diode is provided between an output side of the supply power source and the collector.

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