JP2005354035A - Forming method of semiconductor device - Google Patents

Forming method of semiconductor device Download PDF

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JP2005354035A
JP2005354035A JP2005096593A JP2005096593A JP2005354035A JP 2005354035 A JP2005354035 A JP 2005354035A JP 2005096593 A JP2005096593 A JP 2005096593A JP 2005096593 A JP2005096593 A JP 2005096593A JP 2005354035 A JP2005354035 A JP 2005354035A
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forming
insulating film
semiconductor device
gate electrode
gate insulating
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Ryuichi Nakamura
隆一 中村
Ryohei Matsubara
亮平 松原
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Toppan Inc
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Toppan Printing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To avoid the use of an expensive process by using an inexpensive material, and to inexpensively provide a large amount of semiconductor devices of high performance. <P>SOLUTION: The semiconductor device is formed by a forming method comprising a process for forming a gate electrode 2 on at least a flexible insulating substrate 1; a process for forming a gate insulating film 4 on the gate electrode 2; a process for forming source/drain electrodes 5 on the gate insulating film; a process for polishing and removing a part of the source/drain electrodes 5 and the gate insulating film 4, and forming a channel between the source/drain electrodes; and a process for forming a semiconductor layer 6 between the channels. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、ICカード、電子ペーパー、RFIDタグ等に使用する半導体装置とその形成方法に関するものである。   The present invention relates to a semiconductor device used for an IC card, electronic paper, an RFID tag and the like and a method for forming the same.

近年、ICカードや電子ペーパー、RFIDタグ等が注目されている。これらには半導体装置が使用されている。半導体装置は年々多機能化が進んでいるが、逆に薄型化、軽量化が進行しており、それを実現するため限られたスペースへの集積化や素子の薄型化が求められている。
また、半導体装置に使用される基板を薄くして薄型化を計ろうとすると、素子が壊れ易くなる。例えば、ICカードはカードホルダや財布などに収納され持ち運ばれるが、ポケットやカバンなどの中で外部からの力により曲げ、捻りなどを加えられることも多く、フレキシブルで壊れにくいことが強く求められる。また、ワイヤボンディングなどで配線する必要があるため、曲げ、捻りなどで素子自身や配線などが壊れるなど信頼性を著しく低下させる問題がある。
しかも現在の半導体製造プロセスは、プラスチックフィルムが耐えられない高温プロセスを必要とする。
このため半導体装置を安価に大量に供給し、しかもフレキシブルな基材上に半導体装置を形成するためには、印刷法を用いて形成した半導体装置も出現している(例えば、特許文献1参照。)。
In recent years, IC cards, electronic paper, RFID tags, and the like have attracted attention. For these, semiconductor devices are used. Semiconductor devices are becoming more and more multifunctional year by year, but conversely, they are becoming thinner and lighter, and in order to realize them, integration in a limited space and thinning of elements are required.
In addition, if the substrate used in the semiconductor device is thinned to reduce the thickness, the element is easily broken. For example, IC cards are stored and carried in card holders, wallets, etc., but they are often required to be bent and twisted by external force in pockets and bags, and are strongly required to be flexible and not easily broken. . In addition, since it is necessary to perform wiring by wire bonding or the like, there is a problem that the reliability is remarkably lowered, for example, the element itself or wiring is broken by bending or twisting.
Moreover, current semiconductor manufacturing processes require high temperature processes that cannot be tolerated by plastic films.
For this reason, in order to supply a large amount of semiconductor devices at low cost and to form a semiconductor device on a flexible base material, a semiconductor device formed using a printing method has also appeared (for example, see Patent Document 1). ).

印刷法が注目されるのには、以下のような理由によっている。すなわち、
(1)低温での加工が可能であるので基材に可撓性の樹脂フィルムを使用することが可能となる、(2)このため、ロール状の樹脂フィルムを用いていわゆるロール・ツー・ロールプロセスで高速生産することが可能となる、(3)溶液状の半導体が利用できるので、印刷加工が容易である、等の理由が挙げられる。このような理由からフレキシブルな基材上に形成した半導体装置を大量にしかも安価に提供することが可能となる。
The printing method is attracting attention for the following reasons. That is,
(1) Since processing at low temperature is possible, it is possible to use a flexible resin film as a base material. (2) For this reason, a roll-shaped resin film is used so-called roll-to-roll. The reason is that high-speed production can be performed by the process, and (3) since a solution-like semiconductor can be used, printing processing is easy. For these reasons, a large amount of semiconductor devices formed on a flexible base material can be provided at low cost.

印刷法を用いた半導体装置の形成方法としては、例えばオフセット印刷法を使用してレジストインキや遮光性インキを塗布し半導体パターンや回路基板を形成する方法(例えば、特許文献2参照。)、あるいはインクジェットプリント法により導電性高分子溶液を用いて配線パターンを形成する方法(例えば、特許文献3参照。)等が知られている。
再公表特許WO98-29261号公報 特開平7-240523号公報 特開2003-123047号公報
As a method for forming a semiconductor device using a printing method, for example, a method of forming a semiconductor pattern or a circuit board by applying a resist ink or a light-shielding ink using an offset printing method (see, for example, Patent Document 2), or the like. A method of forming a wiring pattern using a conductive polymer solution by an inkjet printing method (for example, see Patent Document 3) is known.
Republished patent WO98-29261 JP-A-7-240523 Japanese Patent Laid-Open No. 2003-123047

実際に印刷法が適用可能な材料としては、電極材料については導電パターンを形成するためのポリマー厚膜ペーストが広く用いられており、金や銀などのナノサイズの金属粒子をインキ状に加工したものが市販されている。
また、半導体材料についてはポリチオフェン、ポリアリルアミンの誘導体、ペンタセン前駆体等がある。また、有機物に限らず溶液として調整可能であればセレン化カドミウム、シリコン、ゲルマニウム等の微粒子、あるいはこれらの金属有機化合物等も利用することができる。
また、プラスチックフィルムが使用可能な温度で製膜できる半導体材料としてInGaZnO系、InGaO系、ZnGaO系、InZnO系、ZnO、SnO2等の酸化物半導体も使用可能である。
さらに、絶縁膜材料としてはポリビニルフェノールやポリメチルメタアクリレート等の高分子材料が利用できるほか、コンデンサ用に用いられているチタン酸バリウム等の高誘電体を、所定の割合で適度な粘度の樹脂を練り合わせてペースト状にしたものが利用できる。
これらの材料を用いることで、印刷法による半導体装置が現実のものとなっており、その研究報告も数多く発表されている。
なお、ここで印刷法による半導体装置とは、半導体の構成要素である電極、絶縁膜、半導体の全てを印刷法により形成する場合に限らず、これらの一部の要素を印刷法により形成した場合も含めるものとする。
As a material to which the printing method can actually be applied, a polymer thick film paste for forming a conductive pattern is widely used as an electrode material, and nano-sized metal particles such as gold and silver are processed into ink. Things are commercially available.
Examples of semiconductor materials include polythiophene, polyallylamine derivatives, and pentacene precursors. Further, not only organic substances but also fine particles such as cadmium selenide, silicon, germanium, or these metal organic compounds can be used as long as they can be prepared as a solution.
In addition, oxide semiconductors such as InGaZnO-based, InGaO-based, ZnGaO-based, InZnO-based, ZnO, and SnO2 can also be used as semiconductor materials that can be formed at temperatures at which plastic films can be used.
In addition, polymer materials such as polyvinylphenol and polymethylmethacrylate can be used as the insulating film material, and high dielectrics such as barium titanate used for capacitors can be used as a resin with an appropriate viscosity at a predetermined ratio. Paste can be used.
By using these materials, semiconductor devices based on the printing method have become real, and many research reports have been published.
Here, the semiconductor device by the printing method is not limited to the case where all of the electrodes, the insulating film, and the semiconductor, which are the components of the semiconductor, are formed by the printing method, but when some of these elements are formed by the printing method. Shall also be included.

一般にICカード等で使用される半導体装置は、ゲート電極、ゲート絶縁膜、ソース・ドレイン電極及び半導体膜を積層した、いわゆるTFT( Thin Film Transistor )タイプの半導体装置である。この半導体装置においては、ゲート電極が薄いほど高速性の目安である遮断周波数が高くなり、素子の大きさが小さいほど寄生容量や回路抵抗が小さくなり、動作が速くなって高性能を発揮するとされている。
このような半導体装置を形成するには、(1)ゲート電極とソース・ドレイン電極の相対的な位置を正確に決め、(2)ソース・ドレイン電極間の距離(チャネル長)を正確に決める、という2つの課題がある。
従来のフォトプロセスを利用した半導体装置の形成方法では、各層の重ね合わせを光学的な位置読み取りで行い、機械的にフォトマスクの位置を合わせて露光することが行われている。
光学的な位置合わせは正確であるものの装置が高価であり、生産性も低いので製品コストの上昇は避けられない。
A semiconductor device generally used in an IC card or the like is a so-called TFT (Thin Film Transistor) type semiconductor device in which a gate electrode, a gate insulating film, source / drain electrodes, and a semiconductor film are stacked. In this semiconductor device, the thinner the gate electrode, the higher the cutoff frequency, which is a measure of high speed, and the smaller the element size, the smaller the parasitic capacitance and circuit resistance. ing.
In order to form such a semiconductor device, (1) the relative positions of the gate electrode and the source / drain electrodes are accurately determined, and (2) the distance (channel length) between the source / drain electrodes is accurately determined. There are two issues.
In a conventional method for forming a semiconductor device using a photo process, each layer is superposed by optical position reading, and exposure is performed by mechanically aligning a photo mask.
Although the optical alignment is accurate, the apparatus is expensive, and the productivity is low, so an increase in product cost is inevitable.

半導体装置のコスト低減のためには真空プロセスの使用を避け、ゲート電極も銅貼り基板や厚膜ペーストを使用するのが効果的であるが、正確な位置合わせを行うためには従来のものと同様高価な装置が必要である。このため自己整合的に位置合わせができることが望ましい。   In order to reduce the cost of semiconductor devices, it is effective to avoid the use of a vacuum process and to use a copper-clad substrate or thick film paste for the gate electrode. Similarly expensive equipment is required. For this reason, it is desirable that alignment can be performed in a self-aligning manner.

本発明は、上記課題を解決するためになされたものであって、安価な材料を使用して高価なプロセスの利用を避け、高性能な半導体装置を安価に大量に提供することを目的とする。   The present invention has been made to solve the above problems, and aims to provide a large amount of high-performance semiconductor devices at low cost by using inexpensive materials and avoiding the use of expensive processes. .

上記課題を解決するため本発明は、少なくとも、可撓性絶縁基板上にゲート電極を形成する工程と、該ゲート電極上にゲート絶縁膜を形成する工程と、該ゲート絶縁膜上にソース・ドレイン電極を形成する工程と、該ソース・ドレイン電極及びゲート絶縁膜の一部を研磨除去してソース・ドレイン電極間にチャネルを形成する工程と、該チャネル間に半導体層を形成する工程を含む半導体装置の形成方法を採用した。
このような方法を採用すれば、安価な材料を使用して、ゲート電極やソース・ドレイン電極の位置を正確に規定でき、チャネル長も一定となって性能の良い半導体装置を安価に大量に提供することが可能となる。
In order to solve the above problems, the present invention includes at least a step of forming a gate electrode on a flexible insulating substrate, a step of forming a gate insulating film on the gate electrode, and a source / drain on the gate insulating film. A semiconductor including a step of forming an electrode, a step of polishing and removing part of the source / drain electrode and the gate insulating film to form a channel between the source / drain electrode, and a step of forming a semiconductor layer between the channel The device forming method was adopted.
If such a method is adopted, the position of the gate electrode and the source / drain electrode can be accurately defined by using an inexpensive material, and a large number of semiconductor devices having good performance with a constant channel length can be provided at low cost. It becomes possible to do.

本発明においては、前記ゲート絶縁膜をスクリーン印刷法により形成することができる。
また、前記ゲート電極をスクリーン印刷法により形成することができる。
また、前記ゲート電極を銅貼り基板をエッチングして形成することもできる。
さらに、前記ソース・ドレイン電極及びゲート絶縁膜の一部を研磨除去する工程を湿式研磨法を使用して行うこともできる。
また、前記半導体層を、有機半導体溶液をインクジェット滴下した後加熱乾燥して形成することができる。
また、前記半導体層を酸化物半導体とすることができる。
さらに、前記可撓性絶縁基板としてポリエステル樹脂またはポリイミド樹脂を使用することが好ましい。
In the present invention, the gate insulating film can be formed by a screen printing method.
The gate electrode can be formed by a screen printing method.
The gate electrode can be formed by etching a copper-clad substrate.
Furthermore, the step of polishing and removing a part of the source / drain electrodes and the gate insulating film may be performed using a wet polishing method.
In addition, the semiconductor layer can be formed by dropping an organic semiconductor solution by inkjet and then drying by heating.
The semiconductor layer may be an oxide semiconductor.
Furthermore, it is preferable to use a polyester resin or a polyimide resin as the flexible insulating substrate.

本発明によれば、安価な材料を使用して高価なプロセスの利用を避け、高性能な半導体装置を安価に大量に提供することが可能となる。   According to the present invention, it is possible to provide a large amount of high-performance semiconductor devices at low cost by using an inexpensive material and avoiding an expensive process.

図1に本発明で形成する半導体装置の断面構造を示す。
本発明で形成する半導体装置10は、可撓性の絶縁体からなる基板1上にゲート電極2が形成されており、該ゲート電極2を含む基板1面はゲート絶縁膜4により覆われている。該ゲート絶縁膜4上にはゲート電極2で盛り上がった部分を挟んでソース電極5-1とドレイン電極5-2が一定の距離を保ってチャネルが形成されている。そしてソース電極5-1とドレイン電極5-2の上にはそれぞれの端部を連結した半導体層6が設けられている。このように構成された基板の表面のソース電極5-1とドレイン電極5-2上にボンディングパッド7を設けて、それ以外の部分を保護膜8で被覆して半導体装置10としている。
FIG. 1 shows a cross-sectional structure of a semiconductor device formed according to the present invention.
In a semiconductor device 10 formed according to the present invention, a gate electrode 2 is formed on a substrate 1 made of a flexible insulator, and the surface of the substrate 1 including the gate electrode 2 is covered with a gate insulating film 4. . On the gate insulating film 4, a channel is formed with a certain distance between the source electrode 5-1 and the drain electrode 5-2, with a portion raised by the gate electrode 2 interposed therebetween. A semiconductor layer 6 is provided on the source electrode 5-1 and the drain electrode 5-2. The bonding pad 7 is provided on the source electrode 5-1 and the drain electrode 5-2 on the surface of the substrate configured as described above, and the other part is covered with the protective film 8 to form the semiconductor device 10.

次に、本発明の半導体装置の形成方法につき図面を使用して説明する。なお、以下の図面においては説明を判りやすくするために、縮尺は必ずしも正確に描いてはいない。
図2及び図3は本発明の半導体装置の形成方法を説明する工程断面図である。
先ず、図2(a)に示すように、可撓性の絶縁体からなる基板1上にゲート電極2を形成する。
基板1としては、半導体素子を薄く小型に形成し、しかも折れ曲げに強い可撓性を持たせるために、ポリエステル樹脂フィルムやポリイミド樹脂フィルムを使用するのが好ましい。勿論用途によってはガラスやアルミナ等の無機絶縁基板も利用できる。
ゲート電極2は、例えば導電性の厚膜ペーストを所定の位置にスクリーン印刷等を利用して印刷した後焼成して形成しても良いし、あるいは銅箔を貼った銅貼り基板を使用して、所定の形状にパターニングして形成したものであっても良い。厚膜ペーストとしては、特に制限はないが、導電率が高く、適度の粘性を有していて印刷したときにムラ無く塗布できるものであればよい。例えば、銀(Ag)と炭素(C)の微粒子を有機ポリマー中に分散させて適当な粘度に調製したものが利用できる。ゲート電極2の厚さは、10〜20μmの範囲でなるべく薄くするのがよい。
Next, a method for forming a semiconductor device of the present invention will be described with reference to the drawings. In the following drawings, the scale is not necessarily drawn accurately for easy understanding.
2 and 3 are process cross-sectional views illustrating a method for forming a semiconductor device of the present invention.
First, as shown in FIG. 2A, a gate electrode 2 is formed on a substrate 1 made of a flexible insulator.
As the substrate 1, it is preferable to use a polyester resin film or a polyimide resin film in order to form a semiconductor element thin and small and to have flexibility to bend and bend. Of course, an inorganic insulating substrate such as glass or alumina can also be used depending on the application.
The gate electrode 2 may be formed by, for example, printing a conductive thick film paste at a predetermined position using screen printing or the like, followed by baking, or using a copper-clad substrate with a copper foil attached. Alternatively, it may be formed by patterning into a predetermined shape. The thick film paste is not particularly limited as long as it has high electrical conductivity, has an appropriate viscosity, and can be applied without unevenness when printed. For example, silver (Ag) and carbon (C) fine particles dispersed in an organic polymer and adjusted to an appropriate viscosity can be used. The thickness of the gate electrode 2 is preferably as thin as possible within the range of 10 to 20 μm.

次に、図2(b)に示すように、上記ゲート電極2を含む基板表面にゲート絶縁膜4を形成する。この時ゲート電極2は盛り上がっているので、通常のスピンコート法は均一な被膜が得にくいので好ましくない。ゲート絶縁膜の形成には、たとえばスクリーン印刷法等の印刷法を使用するのが好ましい。印刷法で形成できるゲート絶縁膜4の材質には、ソルダーレジストやチタン酸バリウムを有機溶媒中に分散させてペースト状にしたものが利用できる。ゲート絶縁膜4の厚さは10〜30μmとするのが適当である。   Next, as shown in FIG. 2B, a gate insulating film 4 is formed on the surface of the substrate including the gate electrode 2. At this time, since the gate electrode 2 is raised, a normal spin coating method is not preferable because it is difficult to obtain a uniform film. For forming the gate insulating film, it is preferable to use a printing method such as a screen printing method. As a material of the gate insulating film 4 that can be formed by a printing method, a paste obtained by dispersing solder resist or barium titanate in an organic solvent can be used. The thickness of the gate insulating film 4 is suitably 10 to 30 μm.

次いで、図2(c)に示すように、導電性の厚膜ペーストをゲート絶縁膜4の表面全域にスクリーン印刷等を利用して印刷した後焼成して導電膜5を形成する。厚膜ペーストはゲート電極を形成する際のものと同じものが利用できる。導電膜5の厚さは、10〜20μm程度が適当である。   Next, as shown in FIG. 2C, a conductive thick film paste is printed on the entire surface of the gate insulating film 4 using screen printing or the like and then baked to form the conductive film 5. The same thick paste as that used when forming the gate electrode can be used. The thickness of the conductive film 5 is suitably about 10 to 20 μm.

次いで、図3(d)に示すように、先の導電膜5のゲート電極で盛り上がっている部分を研磨して平坦にする。この際、導電膜5の平坦な部分の一部とゲート絶縁膜4の盛り上がった部分の一部も研磨する。
研磨方法は特に制限はなく、公知の方法が利用できる。例えば、半導体分野で広く用いられている化学的機械研磨(CMP)を使用して、研磨材とエッチング剤によるバフ研磨により研磨することができる。高速で能率良く研磨加工するには、耐水研磨紙を用いた後、バフ研磨する方法を採用するのがよい。研磨紙の砥粒粒度としては、例えば、#500,#1200,#2400,#4000を用いて研磨した後、バフ及びアルミナ懸濁研磨液やシリカ懸濁研磨液で研磨加工することにより、鏡面研磨することができる。
Next, as shown in FIG. 3D, the raised portion of the previous conductive film 5 at the gate electrode is polished and flattened. At this time, part of the flat part of the conductive film 5 and part of the raised part of the gate insulating film 4 are also polished.
There is no restriction | limiting in particular in the grinding | polishing method, A well-known method can be utilized. For example, chemical mechanical polishing (CMP) widely used in the semiconductor field can be used for polishing by buffing with an abrasive and an etching agent. In order to efficiently polish at high speed, it is preferable to employ a buffing method after using water-resistant abrasive paper. As the abrasive grain size of the abrasive paper, for example, after polishing with # 500, # 1200, # 2400, # 4000, polishing with a buff and alumina suspension polishing liquid or silica suspension polishing liquid, Can be polished.

次いで、図3(e)に示すように、ゲート電極2を挟んでソース・ドレイン電極5間に半導体層6を形成する。
半導体層6としては、ポリチオフェン誘導体、ポリフェニレンビニレン誘導体、ポリチエニレンビニレン誘導体、ポリアリルアミン誘導体、ポリアセチレン誘導体、アセン誘導体、オリゴチオフェン誘導体等、既知の有機半導体や、InGaZnO系、InGaO系、ZnGaO系、InZnO系、ZnO、SnO等の酸化物半導体が使用可能である。半導体層6はゲート電極2の大きさLよりもやや大きく形成する。
最後に半導体層6を含むソース・ドレイン電極5上にボンディングパッドを設け、ボンディングパッドを除く基板表面の全面を保護膜で覆って半導体装置とする。
Next, as shown in FIG. 3E, a semiconductor layer 6 is formed between the source / drain electrodes 5 with the gate electrode 2 interposed therebetween.
As the semiconductor layer 6, known organic semiconductors such as polythiophene derivatives, polyphenylene vinylene derivatives, polythienylene vinylene derivatives, polyallylamine derivatives, polyacetylene derivatives, acene derivatives, oligothiophene derivatives, InGaZnO-based, InGaO-based, ZnGaO-based, InZnO An oxide semiconductor such as ZnO or SnO 2 can be used. The semiconductor layer 6 is formed slightly larger than the size L of the gate electrode 2.
Finally, a bonding pad is provided on the source / drain electrode 5 including the semiconductor layer 6, and the entire surface of the substrate excluding the bonding pad is covered with a protective film to obtain a semiconductor device.

(実施例1)
厚さ100μmのポリエステルフィルム上に、銀及びカーボンを導電体としたポリマー厚膜ペーストをスクリーン印刷により印刷して、これを乾燥炉で150℃で30分間加熱硬化させて厚さ20μmのゲート電極とした。
しかる後、その表面にチタン酸バリウムペーストをスクリーン印刷して150℃加熱硬化させ、厚さ10μmのゲート絶縁膜を形成した。
(Example 1)
On a polyester film having a thickness of 100 μm, a polymer thick film paste made of silver and carbon as a conductor was printed by screen printing, and this was heat-cured at 150 ° C. for 30 minutes in a drying oven to obtain a gate electrode having a thickness of 20 μm. did.
Thereafter, a barium titanate paste was screen-printed on the surface and heated and cured at 150 ° C. to form a gate insulating film having a thickness of 10 μm.

その後、ゲート絶縁膜上にゲート電極形成に使用したものと同じポリマー厚膜ペーストをスクリーン印刷して、これを150℃で30分間加熱硬化させて厚さ15μmの導電膜とした。
その結果、はじめに形成されたゲート電極の厚さに追随してゲート絶縁膜と導電膜が積層されたため、ゲート電極上だけ高くなった。
Thereafter, the same polymer thick film paste as that used for forming the gate electrode was screen-printed on the gate insulating film, and this was heat-cured at 150 ° C. for 30 minutes to obtain a conductive film having a thickness of 15 μm.
As a result, the gate insulating film and the conductive film were laminated following the thickness of the gate electrode formed first, so that the height was increased only on the gate electrode.

その後、湿式研磨装置で表面を研磨した。研磨は#500,#1200,#2400,#4000の耐水研磨紙を用いて研磨した後、バフ及びアルミナ懸濁液とシリカ懸濁液で鏡面研磨し、表面を平坦化した。この結果、ゲート電極上に位置する導電膜及びゲート絶縁膜の大部分が除去されてチャネルが形成された。その結果、ゲート電極上のゲート絶縁膜の厚さは1μmとなり、2箇所に分離されてソース・ドレイン電極が形成された。   Thereafter, the surface was polished by a wet polishing apparatus. Polishing was performed using # 500, # 1200, # 2400, # 4000 water-resistant abrasive paper, and then mirror-polished with buff, alumina suspension and silica suspension to flatten the surface. As a result, most of the conductive film and the gate insulating film located on the gate electrode were removed to form a channel. As a result, the thickness of the gate insulating film on the gate electrode was 1 μm, and the source / drain electrodes were formed separated into two portions.

その後、ソース・ドレイン電極上にポリチオフェン誘導体のアニソール溶液をインクジェット装置のノズルより滴下させて、大気中で100℃で乾燥させて半導体層を形成した。   Thereafter, an anisole solution of a polythiophene derivative was dropped from a nozzle of an ink jet device on the source / drain electrodes and dried at 100 ° C. in the atmosphere to form a semiconductor layer.

最後にソース・ドレイン電極上にボンディングパッドを設け、ボンディングパッドを除く基板表面の全面を保護膜で覆って半導体装置を完成させた。
この半導体装置のドレイン電圧Vとドレイン電流Iの関係(V-I特性)を測定した結果を図4に示す。図において曲線(a)〜曲線(i)は、ゲート電圧をそれぞれ0V、10V,20V、30V,40V,50V、60V、70V,80V,90Vと、10V毎に変化させた場合に対応している。図4に示すとおりゲート電圧が0(ゼロ)Vの時にはほとんどドレイン電流は流れず、ゲート電圧が上昇するに従ってドレイン電流が流れるようになった。
Finally, bonding pads were provided on the source / drain electrodes, and the entire surface of the substrate except the bonding pads was covered with a protective film to complete the semiconductor device.
FIG. 4 shows the result of measuring the relationship (VI characteristic) between the drain voltage V and the drain current I of this semiconductor device. In the figure, curve (a) to curve (i) correspond to the case where the gate voltage is changed every 10V, such as 0V, 10V, 20V, 30V, 40V, 50V, 60V, 70V, 80V, 90V. . As shown in FIG. 4, almost no drain current flows when the gate voltage is 0 (zero) V, and the drain current flows as the gate voltage increases.

(実施例2)
ポリイミドフィルムに厚さ18μmの銅箔をラミネートした銅貼り基板を使用して、公知の方法により銅箔をエッチングしてゲート電極を形成した。
しかる後、その表面にソルダーレジストをスクリーン印刷で印刷して150℃加熱硬化させ、厚さ10μmのゲート絶縁膜を形成した。
(Example 2)
Using a copper-clad substrate obtained by laminating a 18 μm thick copper foil on a polyimide film, the copper foil was etched by a known method to form a gate electrode.
Thereafter, a solder resist was printed on the surface by screen printing and heated and cured at 150 ° C. to form a gate insulating film having a thickness of 10 μm.

その後、ゲート絶縁膜上に銀及びカーボンを導電体としたポリマー厚膜ペーストをスクリーン印刷して、これを150℃で30分間加熱硬化させて厚さ15μmの導電膜とした。
その結果、はじめに形成されたゲート電極の厚さに追随してゲート絶縁膜と導電膜が積層されたため、ゲート電極上だけ高くなった。
Thereafter, a polymer thick film paste using silver and carbon as conductors was screen-printed on the gate insulating film, and this was heat-cured at 150 ° C. for 30 minutes to obtain a conductive film having a thickness of 15 μm.
As a result, the gate insulating film and the conductive film were laminated following the thickness of the gate electrode formed first, so that the height was increased only on the gate electrode.

その後、湿式研磨装置で表面を研磨した。研磨は#500,#1200,#2400,#4000の耐水研磨紙を用いて研磨した後、バフ及びアルミナ懸濁液とシリカ懸濁液で鏡面研磨し、表面を平坦化した。この結果、ゲート電極上に位置する導電膜及びゲート絶縁膜の大部分が除去されてチャネルか形成された。その結果、ゲート電極上のゲート絶縁膜の厚さは1μmとなり、2箇所に分離されてソース・ドレイン電極が形成された。   Thereafter, the surface was polished by a wet polishing apparatus. Polishing was performed using # 500, # 1200, # 2400, # 4000 water-resistant abrasive paper, and then mirror-polished with buff, alumina suspension and silica suspension to flatten the surface. As a result, most of the conductive film and the gate insulating film located on the gate electrode were removed to form a channel. As a result, the thickness of the gate insulating film on the gate electrode was 1 μm, and the source / drain electrodes were formed separated into two portions.

その後、ソース・ドレイン電極上にポリチオフェン誘導体のアニソール溶液をインクジェット装置のノズルより滴下させて、大気中で100℃で乾燥させて半導体層を形成した。   Thereafter, an anisole solution of a polythiophene derivative was dropped from a nozzle of an ink jet device on the source / drain electrodes and dried at 100 ° C. in the atmosphere to form a semiconductor layer.

最後にソース・ドレイン電極上にボンディングパッドを設け、ボンディングパッドを除く基板表面の全面を保護膜で覆って半導体装置を完成させた。   Finally, bonding pads were provided on the source / drain electrodes, and the entire surface of the substrate except the bonding pads was covered with a protective film to complete the semiconductor device.

(実施例3)
実施例2と同様に銅貼り基板を使用して厚さ18μmのゲート電極を形成した。
しかる後、その表面にソルダーレジストをスクリーン印刷で印刷して150℃加熱硬化させ、厚さ10μmのゲート絶縁膜を形成した。
(Example 3)
Similarly to Example 2, a gate electrode having a thickness of 18 μm was formed using a copper-clad substrate.
Thereafter, a solder resist was printed on the surface by screen printing and heated and cured at 150 ° C. to form a gate insulating film having a thickness of 10 μm.

その後、ゲート絶縁膜上に銀及びカーボンを導電体としたポリマー厚膜ペーストをスクリーン印刷して、これを150℃で30分間加熱硬化させて厚さ15μmの導電膜とした。
その結果、はじめに形成されたゲート電極の厚さに追随してゲート絶縁膜と導電膜が積層されたため、ゲート電極上だけ高くなった。
Thereafter, a polymer thick film paste using silver and carbon as conductors was screen-printed on the gate insulating film, and this was heat-cured at 150 ° C. for 30 minutes to obtain a conductive film having a thickness of 15 μm.
As a result, the gate insulating film and the conductive film were laminated following the thickness of the gate electrode formed first, so that the height was increased only on the gate electrode.

その後、湿式研磨装置で表面を研磨した。研磨は#500,#1200,#2400,#4000の耐水研磨紙を用いて研磨した後、バフ及びアルミナ懸濁液とシリカ懸濁液で鏡面研磨し、表面を平坦化した。この結果、ゲート電極上に位置する導電膜及びゲート絶縁膜の大部分が除去されてチャネルか形成された。その結果、ゲート電極上のゲート絶縁膜の厚さは1μmとなり、2箇所に分離されてソース・ドレイン電極が形成された。   Thereafter, the surface was polished by a wet polishing apparatus. Polishing was performed using # 500, # 1200, # 2400, # 4000 water-resistant abrasive paper, and then mirror-polished with buff, alumina suspension and silica suspension to flatten the surface. As a result, most of the conductive film and the gate insulating film located on the gate electrode were removed to form a channel. As a result, the thickness of the gate insulating film on the gate electrode was 1 μm, and the source / drain electrodes were formed separated into two portions.

その後、ソース・ドレイン電極上にペンタセン前駆体をインクジェット装置のノズルより滴下させて、大気中で100℃で乾燥させて半導体層を形成した。
最後にソース・ドレイン電極上にボンディングパッドを設け、ボンディングパッドを除く基板表面の全面を保護膜で覆って半導体装置を完成させた。
Then, the pentacene precursor was dripped from the nozzle of the inkjet device on the source / drain electrodes, and dried at 100 ° C. in the atmosphere to form a semiconductor layer.
Finally, bonding pads were provided on the source / drain electrodes, and the entire surface of the substrate except the bonding pads was covered with a protective film to complete the semiconductor device.

(実施例4)
ポリイミドフィルムに厚さ18μmの銅箔をラミネートした銅貼り基板を使用して、公知の方法により銅箔をエッチングしてゲート電極を形成した。
しかる後、その表面にソルダーレジストをスクリーン印刷で印刷して150℃加熱硬化させ、厚さ10μmのゲート絶縁膜を形成した。
Example 4
Using a copper-clad substrate obtained by laminating a 18 μm thick copper foil on a polyimide film, the copper foil was etched by a known method to form a gate electrode.
Thereafter, a solder resist was printed on the surface by screen printing and heated and cured at 150 ° C. to form a gate insulating film having a thickness of 10 μm.

その後、ゲート絶縁膜上に銀及びカーボンを導電体としたポリマー厚膜ペーストをスクリーン印刷して、これを150℃で30分間加熱硬化させて厚さ15μmの導電膜とした。
その結果、はじめに形成されたゲート電極の厚さに追随してゲート絶縁膜と導電膜が積層されたため、ゲート電極上だけ高くなった。
Thereafter, a polymer thick film paste using silver and carbon as conductors was screen-printed on the gate insulating film, and this was heat-cured at 150 ° C. for 30 minutes to obtain a conductive film having a thickness of 15 μm.
As a result, the gate insulating film and the conductive film were laminated following the thickness of the gate electrode formed first, so that the height was increased only on the gate electrode.

その後、湿式研磨装置で表面を研磨した。研磨は#500,#1200,#2400,#4000の耐水研磨紙を用いて研磨した後、バフ及びアルミナ懸濁液とシリカ懸濁液で鏡面研磨し、表面を平坦化した。この結果、ゲート電極上に位置する導電膜及びゲート絶縁膜の大部分が除去されてチャネルが形成された。その結果、ゲート電極上のゲート絶縁膜の厚さは1μmとなり、2箇所に分離されてソース・ドレイン電極が形成された。   Thereafter, the surface was polished by a wet polishing apparatus. Polishing was performed using # 500, # 1200, # 2400, # 4000 water-resistant abrasive paper, and then mirror-polished with buff, alumina suspension and silica suspension to flatten the surface. As a result, most of the conductive film and the gate insulating film located on the gate electrode were removed to form a channel. As a result, the thickness of the gate insulating film on the gate electrode was 1 μm, and the source / drain electrodes were formed separated into two portions.

ソース・ドレイン電極を連結して半導体層としてRFマグネトロンスパッタ法によりAr+Oの混合ガスを用いてInGaZnOを室温成膜して半導体層を形成した。なお、ここでは製膜時にシャドウマスクをもちいて半導体層をパターニングした。 A source / drain electrode was connected, and a semiconductor layer was formed as a semiconductor layer by depositing InGaZnO 4 at room temperature using a mixed gas of Ar + O 2 by RF magnetron sputtering. Here, the semiconductor layer was patterned using a shadow mask during film formation.

最後にソース・ドレイン電極上にボンディングパッドを設け、ボンディングパッドを除く基板表面の全面を保護膜で覆って半導体装置を完成させた。   Finally, bonding pads were provided on the source / drain electrodes, and the entire surface of the substrate except the bonding pads was covered with a protective film to complete the semiconductor device.

本発明で形成する半導体装置の断面構造を示す図である。It is a figure which shows the cross-section of the semiconductor device formed by this invention. 本発明の半導体装置の製造工程を説明する断面工程図である。It is sectional process drawing explaining the manufacturing process of the semiconductor device of this invention. 図2に続く断面工程図である。FIG. 3 is a sectional process diagram subsequent to FIG. 2; V-I特性を示す図である。It is a figure which shows a VI characteristic.

符号の説明Explanation of symbols

1・・・・・基板、2・・・・・ゲート電極、4・・・・・ゲート絶縁膜、5・・・・
・ソース・ドレイン電極、6・・・・・半導体層、7・・・・・ボンディングパッド、8
・・・・・保護膜、10・・・・・半導体装置


1 ... substrate, 2 ... gate electrode, 4 ... gate insulating film, 5 ...
Source / drain electrodes, 6 ... semiconductor layer, 7 ... bonding pad, 8
... Protective film, 10 ... Semiconductor device


Claims (8)

少なくとも、可撓性絶縁基板上にゲート電極を形成する工程と、該ゲート電極上にゲート絶縁膜を形成する工程と、該ゲート絶縁膜上にソース・ドレイン電極を形成する工程と、該ソース・ドレイン電極及びゲート絶縁膜の一部を研磨除去してソース・ドレイン電極間にチャネルを形成する工程と、該チャネル間に半導体層を形成する工程を含むことを特徴とする半導体装置の形成方法。   Forming at least a gate electrode on a flexible insulating substrate; forming a gate insulating film on the gate electrode; forming a source / drain electrode on the gate insulating film; and A method for forming a semiconductor device, comprising: a step of polishing and removing part of a drain electrode and a gate insulating film to form a channel between the source and drain electrodes; and a step of forming a semiconductor layer between the channel. 前記ゲート絶縁膜をスクリーン印刷法により形成することを特徴とする請求項1に記載の半導体装置の形成方法。   2. The method of forming a semiconductor device according to claim 1, wherein the gate insulating film is formed by a screen printing method. 前記ゲート電極をスクリーン印刷法により形成することを特徴とする請求項1または請求項2に記載の半導体装置の形成方法。   The method for forming a semiconductor device according to claim 1, wherein the gate electrode is formed by a screen printing method. 前記ゲート電極を銅貼り基板をエッチングして形成することを特徴とする請求項1または請求項2に記載の半導体装置の形成方法。   The method of forming a semiconductor device according to claim 1, wherein the gate electrode is formed by etching a copper-clad substrate. 前記ソース・ドレイン電極及びゲート絶縁膜の一部を研磨除去する工程を湿式研磨を使用して行うことを特徴とする請求項1から請求項4のいずれか1項に記載の半導体装置の形成方法。   5. The method of forming a semiconductor device according to claim 1, wherein the step of polishing and removing a part of the source / drain electrodes and the gate insulating film is performed by using wet polishing. . 前記半導体層を、有機半導体溶液をインクジェット滴下した後加熱乾燥して形成することを特徴とする請求項1から請求項5のいずれか1項に記載の半導体装置の形成方法。   The method for forming a semiconductor device according to claim 1, wherein the semiconductor layer is formed by applying an organic semiconductor solution by ink-jet dropping and then drying by heating. 前記半導体層が酸化物半導体であること特徴とする請求項1から請求項5のいずれか1項に記載の半導体装置の形成方法。   The method for forming a semiconductor device according to claim 1, wherein the semiconductor layer is an oxide semiconductor. 前記可撓性絶縁基板がポリエステル樹脂またはポリイミド樹脂からなることを特徴とする請求項1から請求項7のいずれか1項に記載の半導体装置の形成方法。


The method for forming a semiconductor device according to claim 1, wherein the flexible insulating substrate is made of a polyester resin or a polyimide resin.


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