JP2005353981A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device which method enables the precise formation of a contact hole without using a high-performance lithography apparatus and miniaturization of the semiconductor device as a whole. <P>SOLUTION: The manufacturing method includes a process of forming a second insulating film covering a semiconductor board, which second insulating film includes a plurality of lined up element separation insulating films and a plurality of lined up gate electrodes that cross the element separation insulating films and have respective upper layers of first insulating films; a process of eliminating the second insulating film selectively so as to expose the board surface and the element separation insulating films, and to leave the part of the second insulating film that covers the side faces of the gate electrodes, while protecting the gate electrodes with the first insulating films; a process of growing a silicon layer upward from exposed parts of the board by an anisotropic selective epitaxial growth method; a process of forming an interlayer insulating film that so covers the silicon layer as to expose a part thereof; and a process of forming a first opening by etching back the silicon layer selectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which conductive plugs are formed in a self-aligned manner on a substrate.

  With the recent high integration of semiconductor devices, the design dimensions have become finer. Especially for contact processing on underlying semiconductor elements and wiring, in addition to forming fine holes, alignment with the underlying There is no margin, and the quality of these processes greatly affects the quality and manufacturing yield of semiconductor products, and is one of the most important steps in the semiconductor manufacturing process.

  Therefore, in a fine semiconductor device, a manufacturing process capable of forming a contact by self-alignment with a lower semiconductor layer is usually used.

  As a method for forming such a self-aligned contact, conventionally, for example, as disclosed in Patent Document 1 as a prior art, first, a sidewall is formed on a side wall of a gate electrode formed on a substrate, and an etching stopper is formed. After forming a silicon nitride film functioning as an interlayer insulating film made of a silicon oxide film and performing planarization, a contact mask is formed using a resist by a photolithography technique. Then, the interlayer insulating film is etched using this contact mask. If this etching is performed under a condition having a sufficient selection ratio with respect to the silicon nitride film, the silicon nitride film is hardly etched. Therefore, even if there is a slight misalignment during the formation of the contact mask, the gate electrode is not exposed and is self-exposed. A contact hole can be opened by alignment. A substrate used in this method usually has a plurality of element isolation insulating films arranged in parallel so as to be orthogonal to the gate electrode.

  In this technology, when the misalignment during the formation of the contact mask increases, the bottom of the contact hole rides on the side wall, the element isolation insulating film, etc. Will increase. It is possible to cope with this problem by increasing the diameter of the contact hole. However, if this diameter is too large, the contact holes adjacent to each other across the element isolation insulating film may come into contact. Occur.

  For this reason, a technique for forming a contact using a selective epitaxial growth technique has been proposed. For example, Patent Document 2 discloses a technique in which a silicon layer is grown as a part of a contact by growing a silicon layer in a source / drain region of a MOS transistor.

  This prior art will be briefly described with reference to FIGS. FIGS. 11 to 15- (a) are cross-sectional views in the II direction in FIG. 10 of the plan view of the memory cell portion of the semiconductor device, and FIGS. 11 to 15- (b) are diagrams of the memory cell portion of the semiconductor device. It is sectional drawing of the II-II direction in FIG. 10 of a top view.

  First, as shown in FIG. 11, a gate insulating film 53, a gate electrode 54, and a silicon oxide film cap layer 55 are sequentially formed on a substrate 51, and then N-type impurities are introduced in a self-aligning manner with the gate electrode 54. , Source 56 / drain 57 are formed. Next, as shown in FIG. 12, an insulating film made of a silicon nitride film is deposited, the surface of the substrate 51 is exposed by etch back by anisotropic etching, and a side wall 58 is formed on the side wall.

  Then, using an anisotropic selective epitaxial growth technique, a columnar silicon layer 59 is deposited in the height direction on the element active region up to the top of the gate electrode 54 while introducing N-type impurities, Subsequently, isotropic selective epitaxial growth is performed, and when the silicon layer 60 is grown in the lateral direction so as to extend to the cap layer 55 above the gate electrode 54, the result is as shown in FIG. Next, as shown in FIG. 14, an interlayer insulating film 61 is deposited on the entire surface of the substrate, planarized by CMP or the like, and then an opening 62 that contacts the underlying silicon layer 60 is formed by a resist using a photolithography technique. Formation of the pattern 65 is performed using a dry etching technique. Then, a conductive film 63 is embedded in the opening 62 and a desired electrode 64 is connected to obtain a semiconductor device having a self-aligned contact as shown in FIG.

In this way, by making the upper surface of the silicon layer 60 function as a contact pad, the opening diameter 62 can be increased, and even if a slight misalignment occurs, there is no short circuit with the gate electrode 54 or the like. A semiconductor device with low resistance and leakage current can be obtained.
Japanese Patent Laid-Open No. 9-213949 JP-A-10-107219

  However, in the above method, in order to provide a margin for the alignment margin, the underlying silicon layer serving as the contact pad is grown laterally by isotropic growth. However, there is a risk that adjacent silicon layers may come into contact with each other. Is expensive.

  In addition, if the silicon layer itself is used as a conductive plug, there is a problem that the resistance becomes higher than that of a metal material.

  In addition, since the photolithographic technique is used to form the opening in the interlayer insulating film, when the interval between adjacent connection holes is narrowed, when the state of the exposure apparatus or the like changes, the openings contact each other, Miniaturization is difficult because it contacts the adjacent contact pad and causes leakage.

  Furthermore, especially in memory products such as flash memory, the memory cell pattern that occupies the majority is often designed with a narrow line width processing pitch because the cell size affects the memory capacity. Considering the rules, whether or not fine processing is possible is highly dependent on the technology relating to the lithography apparatus, and it can be said that it is difficult to form a fine opening without an exposure apparatus having high resolution.

  If the above-described microfabrication relies solely on lithography apparatus technology, as the design rule becomes finer, the lithography apparatus becomes increasingly complex and expensive, and the apparatus must be sequentially introduced. In this way, there is a possibility that the processing method depending only on the lithography apparatus will eventually reach its limit.

  The present invention has been made in view of such circumstances, and provides a method of manufacturing a semiconductor device that can accurately form a contact hole without using a high-performance lithography apparatus and can reduce the size of the entire apparatus. Is.

  According to the method of manufacturing a semiconductor device of the present invention, a plurality of element isolation insulating films arranged in parallel and a plurality of gate electrodes arranged in parallel with the first insulating film as an upper layer intersecting with the element isolation insulating film are formed. Forming a second insulating film covering the surface of the semiconductor substrate, and a portion that exposes the substrate surface and the element isolation insulating film and covers the side surface of the gate electrode while protecting the gate electrode with the first insulating film A step of selectively removing the second insulating film so as to leave a layer, a step of growing the silicon layer in the height direction from the exposed portion of the substrate by anisotropic selective epitaxial growth, and a portion of the silicon layer exposed A step of forming an interlayer insulating film covering the silicon layer, a step of forming a first opening by selectively etching back the silicon layer, and a material containing at least a metal in the first opening Characterized by a step of forming a conductive plug is filled.

  In the present invention, first, an opening is formed in the second insulating film using photolithography, etching technique, etc., and the substrate surface and the element isolation insulating film are exposed. This opening can be formed in the shape of a groove, and etching is performed while protecting the gate electrode with the first insulating film, so the opening of the second insulating film uses a lithographic apparatus with relatively low accuracy. Can be formed.

  Next, a silicon layer extending upward from the exposed portion is grown. At this time, since the silicon layer does not grow from the exposed portion where the element isolation insulating film is formed, the silicon layer grows in a self-aligned manner from the exposed portion of the substrate. Next, after covering the silicon layer with an interlayer insulating film, the silicon layer is removed, thereby forming a contact hole in the interlayer insulating film. Therefore, according to the present invention, the contact hole is formed by removing the silicon layer grown in a self-aligned manner. Therefore, the contact hole can be formed without performing photolithography. Therefore, unlike the prior art, it is not necessary to form contact holes larger in consideration of misalignment during photolithography, or to increase the distance between contact holes. Therefore, according to the present invention, the semiconductor device can be miniaturized.

1. Manufacturing method of semiconductor device The manufacturing method of a semiconductor device according to the present invention includes a plurality of element isolation insulating films arranged in parallel and a plurality of gates parallel to the element isolation insulating film and having a first insulating film as an upper layer. Forming a second insulating film covering the surface of the semiconductor substrate on which the electrode is formed, and exposing the substrate surface and the element isolation insulating film while protecting the gate electrode with the first insulating film and the gate; A step of selectively removing the second insulating film so as to leave a portion covering the side surface of the electrode, a step of growing a silicon layer in the height direction from an exposed portion of the substrate by anisotropic selective epitaxial growth, and a silicon layer Forming an interlayer insulating film covering the silicon layer so that a part of the silicon layer is exposed; forming a first opening by selectively etching back the silicon layer; and Small And a step of filling a material containing a metal to form a conductive plug.

1-1. A semiconductor substrate on which a plurality of parallel element isolation insulating films and a plurality of gate electrodes parallel to each other and having a first insulating film as an upper layer are formed to cover the surface. Step of Forming Second Insulating Film The semiconductor substrate is made of a silicon substrate or the like. A plurality of element isolation insulating films arranged in parallel are formed on the semiconductor substrate. The element isolation insulating film is made of a silicon oxide film (material) or the like and can be formed by a method such as a CVD method. The element isolation insulating film is preferably elongated. The plurality of element isolation insulating films are preferably arranged substantially in parallel.

  In addition, the semiconductor substrate includes a plurality of gate electrodes that intersect with the element isolation insulating film and have a first insulating film in an upper layer and are arranged in parallel. The gate electrode is preferably substantially orthogonal to the element isolation insulating film. The plurality of gate electrodes are preferably arranged substantially in parallel. The gate electrode is usually formed on a semiconductor substrate via a gate insulating film. The gate insulating film is made of a silicon oxide film or the like. The gate electrode is made of a polysilicon film or the like. The gate electrode may be a laminated film of a polysilicon film and a refractory metal silicide film such as a tungsten silicide film.

The first insulating film protects the gate electrode when an opening is formed in the second insulating film in a later step.
Therefore, the first insulating film is preferably formed of a material that is difficult to be removed when the opening is formed in the second insulating film. The first insulating film is made of a silicon oxide film or the like.
The gate insulating film, the gate electrode, and the first insulating film can be patterned by, for example, forming a film with a material for forming them and sequentially performing etching.

The second insulating film preferably covers the entire surface of the semiconductor substrate. The second insulating film is made of a silicon nitride film or the like. Any combination of the first and second insulating films may be used as long as the first insulating film cannot be easily removed when the opening is formed in the second insulating film. The film may be a silicon nitride film and the second insulating film may be a silicon oxide film. At this time, the opening of the second insulating film can be formed under the condition of dry etching using C ₄ F ₈ gas after forming the resist pattern. The first and second insulating films can be formed by a CVD method or the like.

  Further, before the second insulating film is formed or after the opening is formed in the second insulating film, a step of performing ion implantation of reverse conductivity type impurities from above the substrate may be provided. At this time, the gate electrode or the second insulating film serves as a mask, and ion implantation is performed in a self-aligned manner. The “reverse conductivity type” means a conductivity type opposite to that of the substrate.

1-2. The step of selectively removing the second insulating film so as to expose the substrate surface and the element isolation insulating film while leaving the portion covering the side surface of the gate electrode while protecting the gate electrode with the first insulating film. For example, it can be performed by forming a photoresist layer having a groove-shaped opening between gate electrodes and anisotropically etching the second insulating film using this layer as a mask. Since the substrate regions and the element isolation insulating film regions are alternately arranged between the gate electrodes, the substrate surface and the element isolation insulating film are exposed by this etching. The groove-like opening in the photoresist layer is preferably formed wider than the width between the gate electrodes. In this case, the substrate can be reliably exposed even if an alignment shift occurs in a direction perpendicular to the groove.
In addition, when the groove-like opening of the photoresist layer is formed wide in this way, the second insulating film above the gate electrode is also etched, but the gate electrode is protected by the first insulating film, so that the gate The electrode is not damaged.

1-3. The process of growing the silicon layer in the height direction from the exposed portion of the substrate by anisotropic selective epitaxial growth Since the silicon layer does not grow from the portion exposed in the previous step, the portion where the element isolation insulating film is formed The silicon layer grows self-aligned from the exposed portion of the substrate. The silicon layer is usually formed such that its upper surface is higher than the upper surface of the first insulating film. For example, anisotropic selective epitaxial growth of a silicon layer is performed by using, for example, disilane (Si ₂ H ₆ ) as a source gas at a temperature of 600 to 800 ° C. and a pressure of 1 × 10 ^{−3 to} 5 × 10 ⁻² Pa. It can be performed by flowing in an H ₂ atmosphere. Since the silicon layer grows anisotropically, it grows so as not to run over the element isolation insulating film and the second insulating film. The silicon layer may have a grain on the surface or inside. Note that N ⁺ impurity gas may be introduced during the growth of the silicon layer or may be made conductive by using an ion implantation method. The “silicon layer” includes a silicon alloy layer such as silicon germanium.

1-4. The step of forming an interlayer insulating film that covers the silicon layer so that a part of the silicon layer is exposed. This can be done by exposing the layer surface. Further, the interlayer insulating film may be formed so that the upper surface of the interlayer insulating film is lower than the upper surface of the silicon layer. The interlayer insulating film is made of BPSG or the like and can be formed by, for example, a CVD method. Planarization can be performed by a CMP method.

1-5. The step of forming the first opening by selectively etching back the silicon layer The silicon layer is etched back under the condition that the silicon layer can be removed without removing the interlayer insulating film. , HBr gas or the like can be used. When the silicon layer is removed, a hole (contact hole) is formed in the interlayer insulating film. Since the silicon layer is grown from the substrate in a self-aligned manner, contact holes are also formed in a self-aligned manner. Therefore, unlike the prior art, it is not necessary to form contact holes larger in consideration of misalignment during photolithography, or to increase the distance between contact holes. Therefore, according to the present invention, the semiconductor device can be miniaturized.

1-6. The step of filling the first opening with a material containing at least a metal to form a conductive plug. This step is performed by, for example, embedding a conductive film such as W through a barrier metal layer such as TiN in the opening. It can be carried out.

1-7. Others The method may further include a step of forming the second opening in an arbitrary region other than the first opening.
The second opening is formed in the peripheral circuit in a semiconductor device having a memory cell and a peripheral circuit, for example. Peripheral circuits do not affect the chip area as much as memory cells, so there is often room for design rules. Can be formed. The second opening can be formed before or after forming the first opening.
Further, the method may further include a step of filling the second opening with a material containing at least a metal to form a conductive plug. This step can be performed, for example, by embedding a conductive film such as W through a barrier metal layer such as TiN in the opening. The formation of the conductive plug in the second opening may be performed before or after the formation of the conductive plug in the first opening, or at the same time.

2. Structure of Semiconductor Device A semiconductor device according to the present invention includes a plurality of element isolation insulating films arranged in parallel, a plurality of gate electrodes parallel to each other having a sidewall insulating film on a side surface and intersecting the element isolation insulating film, and an element isolation insulating film And an interlayer insulating film that covers the gate electrode and that has an adjacent element isolation insulating film and an opening that exposes a region surrounded by the side wall insulating film of the adjacent gate electrode on the substrate. The size of the opening is substantially equal to the size of the opening on the substrate surface.

  In the conventional semiconductor device, a part of the opening runs on the side wall insulating film or the element isolation insulating film. Therefore, the contact area between the bottom surface of the opening and the substrate is reduced, and the contact resistance is increased. According to the present invention, since the entire bottom surface of the opening is reliably in contact with the substrate, the conventional problems are solved. In addition, since the size of the opening of the semiconductor device of this embodiment is the minimum necessary size, the semiconductor device can be miniaturized according to this embodiment.

  The opening may be filled with a material containing a metal. When the contact is formed in this way, the contact resistance is reduced.

The gate electrode is preferably substantially orthogonal to the element isolation insulating film.
In addition, the description of the method for manufacturing a semiconductor device is applicable to the structure of the semiconductor device as long as it does not contradict the purpose.

  A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view showing the structure of the semiconductor device of the present invention. 2-9- (a) is a cross-sectional view in the II direction in FIG. 1, and FIGS. 2-9- (b) are cross-sectional views in the II-II direction in FIG.

  As shown in FIG. 2, the semiconductor device of the present embodiment is arranged in parallel with a plurality of element isolation insulating films 2 arranged in parallel and with a side wall insulating film 9 on a side surface substantially orthogonal to the element isolation insulating film 2. A plurality of gate electrodes G, and the element isolation insulating film 2 and the gate electrode G are provided, and an opening 13 is provided to expose a region surrounded by the adjacent element isolation insulating film 2 and the sidewall insulating film 9 of the adjacent gate electrode G An interlayer insulating film 12 is provided on the substrate 1, and the size of the opening 13 on the surface of the interlayer insulating film 12 is substantially equal to the size of the opening 13 on the substrate surface. In addition, the opening 13 is filled with a material containing metal to form a conductive plug 14. A source region 7 and a drain region 8 are formed on the substrate 1, and a first insulating film 6 is formed on the gate electrode G. A metal electrode 15 is connected to the conductive plug 14.

  In the conventional semiconductor device, a part of the opening 13 rides on the side wall insulating film 9 or the element isolation insulating film 2, so that the contact area between the bottom surface of the opening 13 and the substrate is reduced, and the contact resistance is increased. . According to this embodiment, since the size of the opening 13 on the surface of the interlayer insulating film 12 is substantially equal to the size of the opening 13 on the substrate surface, the conventional problems are solved. Further, since the size of the opening 13 of the semiconductor device of this embodiment is the minimum necessary size, the semiconductor device can be miniaturized according to this embodiment. In the semiconductor device of this embodiment, since the opening 13 is filled with a material containing metal to form a conductive plug, the resistance of the conductive plug 14 is small.

Hereinafter, a method of manufacturing the semiconductor device shown in FIG. 2 will be described using the cross-sectional views of FIGS.
First, a polysilicon film 4 having a thickness of 150 nm and a tungsten silicide film having a thickness of 100 nm, for example, are formed on a P-type semiconductor substrate 1 having an element isolation insulating film 2 having a trench depth of 250 nm via a gate insulating film 3 having a thickness of 10 nm. After the refractory metal silicide film 5 and a first insulating film 6 made of a silicon oxide film as a cap layer are laminated on the upper layer to a thickness of 100 nm, the first insulating film is perpendicular to the element isolation insulating layer (TR). 6, the refractory metal silicide film 5 and the polysilicon film 4 are selectively patterned by sequential etching to form the gate electrode G, thereby obtaining the structure shown in FIG.

Next, as shown in FIG. 4, N-type impurities made of, for example, arsenic are ion-implanted using the gate electrode G as a mask to form a source 7 / drain 8 diffusion layer of the transistor. The ion implantation is performed, for example, with arsenic at an energy of 10 to 30 KeV and a condition of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ (atm / cm ² ) perpendicular to the substrate. The ion implantation for forming the source 7 / drain 8 of the transistor may be performed after the step of forming the sidewall 9 on the side wall of the gate electrode G to be performed later.

  Next, as shown in FIG. 5, a second insulating film 9 made of a silicon nitride film is deposited to 100 nm on the entire surface by using LPCVD or the like.

  Next, as shown in FIG. 6, for example, after a photoresist 10 having an opening in the drain region 8 is formed, the second insulating film 9 is exposed until the first insulating film 6 is exposed (second insulating film). 9) The entire surface is etched back to open the second insulating film 9 in the drain formation region 8 so that only the surface of the semiconductor substrate 8 is exposed. Thus, the region other than the drain 8 is protected by the element isolation insulating film 2 or the insulating film of either the first insulating film 6 or the second insulating film 9. For example, the gate electrode G is protected by the first insulating film 6. Note that the photoresist 10 is formed not only on the drain 8 but also on a groove pattern with good controllability that opens continuously in the II-II direction so as to open an element isolation insulating film (TR) between them. This means that a pattern can be formed without performing photolithography using a relatively high-performance manufacturing apparatus. The method of this example is particularly characterized in that the misalignment in the II-II direction is not a problem at all. According to the method of this example, the distance between adjacent elements is reduced with the element isolation insulating film interposed therebetween. be able to.

Next, when the photoresist 10 is removed and the silicon layer 11 is selectively grown in the height direction in the drain region 8 by using a selective epitaxial growth method, the result is as shown in FIG. As conditions for selective epi growth, for example, disilane (Si ₂ H ₆ ) as a source gas in a H ₂ atmosphere at a temperature of 600 to 800 ° C. and a pressure of 1 × 10 ^{−3 to} 5 × 10 ⁻² Pa. By flowing, the silicon layer 11 is anisotropically grown in the height direction. At this time, since the silicon layer 11 grows anisotropically, it grows so as not to run over the element isolation insulating film 2 and the second insulating film 9. The silicon layer 11 is not limited to this, and may have grains on the surface or inside. The film thickness to be grown may be higher than the first insulating film 6 above the gate electrode G (450 nm). Note that, when the silicon layer 11 is grown, an N ⁺ impurity gas may be introduced or the conductive substrate may be formed using an ion implantation method.

  Next, as shown in FIG. 8, an interlayer insulating film 12 is formed on the entire surface of the substrate so that the surface of the silicon layer 11 is exposed. Specifically, for example, BPSG is deposited as the interlayer insulating film 12 by the CVD method, and the interlayer insulating film 12 is polished and planarized until the silicon layer 11 is exposed using the CMP method.

  Next, when only the silicon layer 11 is moved back in the direction of the substrate by etching back or the like using conditions such as HBr gas having an etching selectivity such that the interlayer insulating film 12 becomes a hard mask, the result is as shown in FIG. . As a result, a fine opening 13 having the same bottom surface as the region excluding the gate sidewall 9 of the drain region 8 is formed in the interlayer insulating film 12 without using a high-performance photolithography apparatus. In a semiconductor device having a memory cell and a peripheral circuit, the peripheral circuit does not affect the chip area as much as the memory cell. Alternatively, the opening may be opened using conventional photolithography and dry etching.

  Thereafter, as in the conventional manufacturing method, a conductive film 14 such as W is embedded in the opening 13 via a barrier metal layer such as TiN, and a desired electrode 15 such as Al is connected, as shown in FIG. A semiconductor device including a memory cell in which a conductive plug is formed by a self-alignment process is obtained. The present embodiment is not limited to this, and can be applied to a semiconductor device having a memory cell or an N-type or P-type MOS transistor.

  Further, a heat treatment process for controlling the concentration profile of the source 7 / drain 8 region and a process of siliciding the substrate with a refractory metal such as Co or Ni can be appropriately inserted into the above-described processes.

  According to the above manufacturing method, in the contact formation by the conventional photolithography method, it is not necessary to partially deform the gate electrode in order to ensure the distance between the gate electrode and the contact. Can be placed straight. For this reason, the dimensional stability of the gate electrode is improved.

It is a top view which shows the structure of the semiconductor device of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 1 of this invention. It is a top view which shows the structure of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

Explanation of symbols

G ... Gate electrode 1, 51 ... Semiconductor substrate 2, 52 ... Element isolation insulating film 3, 53 ... Gate insulating film 4, 54 ... Polysilicon film 5 ... refractory metal silicide film 6, 55 ... First insulating film (cap) layer)
7, 56 ... Source region 8, 57 ... Drain region 9, 58 ... Side wall (second insulating film)
DESCRIPTION OF SYMBOLS 10, 65 ... Photoresist 11, 59, 60 ... Silicon layer 12, 61 ... Interlayer insulation film 13, 62 ... Opening part 14, 63 ... Conductive plug 15, 64 ... Metal electrode

Claims (6)

A semiconductor substrate on which a plurality of parallel element isolation insulating films and a plurality of gate electrodes parallel to each other and having a first insulating film as an upper layer are formed to cover the surface. Forming a second insulating film;
Selectively removing the second insulating film so as to expose the substrate surface and the element isolation insulating film while leaving the portion covering the side surface of the gate electrode while protecting the gate electrode with the first insulating film;
A step of growing a silicon layer in a height direction from an exposed portion of the substrate by anisotropic selective epitaxial growth;
Forming an interlayer insulating film covering the silicon layer so that a part of the silicon layer is exposed;
Forming a first opening by selectively etching back the silicon layer;
And a step of filling the first opening with a material containing at least a metal to form a conductive plug.   2. The manufacturing method according to claim 1, wherein the step of forming the interlayer insulating film is a step of forming the interlayer insulating film so as to completely cover the silicon layer and exposing the surface of the silicon layer by planarizing the interlayer insulating film. Forming a second opening in any region other than the first opening;
The manufacturing method according to claim 1, further comprising a step of filling the second opening with a material containing at least a metal to form a conductive plug. A plurality of element isolation insulating films in parallel;
A plurality of gate electrodes that intersect with the element isolation insulating film and have side wall insulating films on the side surfaces in parallel;
The substrate is provided with an interlayer insulating film that covers the element isolation insulating film and the gate electrode, and has an opening that exposes a region surrounded by the adjacent element isolation insulating film and the side wall insulating film of the adjacent gate electrode,
The size of the opening on the surface of the interlayer insulating film is a semiconductor device that is substantially equal to the size of the opening on the surface of the substrate.   The semiconductor device according to claim 4, wherein the opening is filled with a material containing a metal.   The semiconductor device according to claim 4, wherein the gate electrode is substantially orthogonal to the element isolation insulating film.

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