JP2005353728A - High-frequency device - Google Patents

High-frequency device Download PDF

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JP2005353728A
JP2005353728A JP2004170964A JP2004170964A JP2005353728A JP 2005353728 A JP2005353728 A JP 2005353728A JP 2004170964 A JP2004170964 A JP 2004170964A JP 2004170964 A JP2004170964 A JP 2004170964A JP 2005353728 A JP2005353728 A JP 2005353728A
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wiring
frequency device
substrate
island
wire
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JP4800594B2 (en
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Akira Inoue
晃 井上
Takahide Ishikawa
高英 石川
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

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  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency device allowing a wide-range impedance adjustment without a wire attaching process, but suffering from but a low loss due to impedance mismatch. <P>SOLUTION: In the high-frequency device having a substrate with wires arranged thereon, the wires include a first wire and a second wire connected to the first wire but formed apart from the first wire, with the second wire formed by fusing nano-scale wiring metal particles having a diameter of ≤100 nm. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は主として８００ＭＨｚ以上の高周波帯にて用いられる高周波デバイスに関するものである。 The present invention mainly relates to a high frequency device used in a high frequency band of 800 MHz or higher.

従来の高周波デバイスは、例えば、図７に示すように、ＧａＡｓ等からなる半導体基板１に、電界効果トランジスタ２を含んで構成されている。この高周波デバイスでは、トランジスタのばらつきや半導体基板外部の回路要素のばらつきに起因したインピーダンス不整合によって特性がばらついたり、悪化したりするために、トランジスタとその外部回路要素との間のインピーダンスを整合させるように調整して最適なＲＦ性能を得るようにしている。
尚、電界効果トランジスタ２は、ゲート７、ドレイン８及びソースを有するが、図７に示す例では、電界効果トランジスタ２のソースはビアホール等により半導体基板裏面の接地電極に接続されている。
また、図７に示す構造では、Ａｕ等からなる分離された配線４間を例えば金からなるワイヤ３により接続することにより、配線長を変化させてインピーダンス整合を図っている（特許文献１の図５）。
特開平０８−２１３５５０号公報 For example, as shown in FIG. 7, a conventional high-frequency device includes a field effect transistor 2 on a semiconductor substrate 1 made of GaAs or the like. In this high-frequency device, the characteristics are varied or deteriorated due to impedance mismatch caused by variations in transistors or circuit elements outside the semiconductor substrate. Therefore, the impedance between the transistor and the external circuit elements is matched. Thus, the optimum RF performance is obtained by adjusting.
The field effect transistor 2 has a gate 7, a drain 8, and a source. In the example shown in FIG. 7, the source of the field effect transistor 2 is connected to a ground electrode on the back surface of the semiconductor substrate by a via hole or the like.
Further, in the structure shown in FIG. 7, impedance matching is achieved by changing the wiring length by connecting the separated wirings 4 made of Au or the like with, for example, a wire 3 made of gold (see FIG. 7). 5).
Japanese Patent Laid-Open No. 08-213550

しかしながら、予め半導体基板上に設けられている配線４をワイヤ３により結線したり、しなかったりして行う従来の調整方法では、予め設けた配線４の位置、長さは変更出来ないため、自由に調整することが出来ず、調整範囲が限定される問題があった。
また、ワイヤを張る時にワイヤ長を制御する必要があるがその長さの制御は困難な作業であり熟練が必要であるという問題があった。
また、配線は金の薄膜で形成されるためバルクの金に比べて抵抗が高く、整合部の損失が大きい問題があった。 However, in the conventional adjustment method in which the wiring 4 previously provided on the semiconductor substrate is connected or not connected by the wire 3, the position and length of the wiring 4 provided in advance cannot be changed. There is a problem that the adjustment range is limited.
Further, it is necessary to control the length of the wire when the wire is stretched, but there is a problem that control of the length is a difficult task and requires skill.
Further, since the wiring is formed of a gold thin film, there is a problem that the resistance is higher than that of bulk gold and the loss of the matching portion is large.

そこで、本発明は、上記のような問題点を解消するためになされたもので、ワイヤを張ることなく広い範囲でインピーダンスの調整ができ、インピーダンス不整合による損失の小さい高周波デバイスを得ることを目的とする。   Therefore, the present invention has been made to solve the above-described problems, and it is an object of the present invention to obtain a high-frequency device that can adjust impedance in a wide range without stretching a wire and has low loss due to impedance mismatch. And

以上の目的を達成するために、本発明に係る高周波デバイスは、基板上に配線が施されてなる高周波デバイスであって、上記配線は、第１配線と、その第１配線に接続されかつ上記第１配線とは別に形成された第２配線とを含んでなり、該第２配線は１００ｎｍ以下の配線用金属ナノ粒子が融着されてなることを特徴とする。   In order to achieve the above object, a high-frequency device according to the present invention is a high-frequency device in which wiring is provided on a substrate, wherein the wiring is connected to the first wiring, the first wiring, and the above-mentioned wiring The second wiring is formed separately from the first wiring, and the second wiring is formed by fusing metal nanoparticles for wiring of 100 nm or less.

以上のように構成された本発明に係る高周波デバイスは、ワイヤを張ることなく広い範囲でインピーダンスの調整ができ、インピーダンス不整合による損失の小さい高周波デバイスを得ることができる。   The high-frequency device according to the present invention configured as described above can adjust the impedance in a wide range without stretching a wire, and can obtain a high-frequency device with small loss due to impedance mismatch.

以下、図面を参照しながら、本発明に係る実施の形態について説明する。
実施の形態１．
本発明に係る実施の形態１の高周波デバイスは、従来例と同様、例えば、ＧａＡｓ等からなる半導体基板１に、電界効果トランジスタ２が形成されることにより構成されているが、以下の点で従来例とは異なる。 Embodiments according to the present invention will be described below with reference to the drawings.
Embodiment 1 FIG.
The high-frequency device according to the first embodiment of the present invention is configured by forming a field effect transistor 2 on a semiconductor substrate 1 made of, for example, GaAs, as in the conventional example. Different from the example.

（１）実施の形態１の高周波デバイスでは、インピーダンス整合をとるために、従来例の金ワイヤに代えて金属ナノ粒子が融着されてなる第２配線５を用いて分離された配線４間を接続することにより、オープンスタブの配線長を調整している。
（２）トランジスタ２のゲートを、抵抗体膜１０とＭＩＭキャパシタ１１を介して接地し、その抵抗体膜１０として１００ｎｍ以下の抵抗体ナノ粒子が融着されてなる抵抗体を用いている。
実施の形態１の高周波デバイスは、上述の（１）（２）以外の点については、図７に示す従来例と同様に構成されており、図１において図７と同様のものには同様の符号を付して示している。
尚、本明細書において、第１配線とは、最初にスバッタ、蒸着もしくはメッキ等により基板上に形成された電極をいい、第２配線は第１配線が形成された後に、形成される電極をいう。 (1) In the high frequency device according to the first embodiment, in order to achieve impedance matching, the wiring 4 separated by using the second wiring 5 in which metal nanoparticles are fused instead of the gold wire of the conventional example is used. By connecting, the wiring length of the open stub is adjusted.
(2) The gate of the transistor 2 is grounded via the resistor film 10 and the MIM capacitor 11, and a resistor formed by fusing resistor nanoparticles of 100 nm or less is used as the resistor film 10.
The high-frequency device according to the first embodiment is configured in the same manner as the conventional example shown in FIG. 7 except for the above (1) and (2). In FIG. A reference numeral is attached.
In this specification, the first wiring means an electrode formed on a substrate by sputtering, vapor deposition or plating first, and the second wiring is an electrode formed after the first wiring is formed. Say.

以下、本実施の形態１の高周波デバイスについて、詳細に説明する。
一般に高周波デバイスは、電界効果トランジスタ等の能動素子や外部回路における素子や配線のばらつき等によりインピーダンスの不整合が生じ、配線が施された後にインピーダンスを調整することや、例えばトランジスタのゲート端子の近くにＣＲによるゲート側安定化回路を挿入することが必要となる場合がある。 Hereinafter, the high-frequency device of the first embodiment will be described in detail.
In general, high-frequency devices have impedance mismatches due to variations in active elements such as field-effect transistors and elements and wiring in external circuits, etc., and impedance adjustment after wiring has been performed, for example, near the gate terminal of a transistor It may be necessary to insert a gate side stabilization circuit using CR.

そこで、本実施の形態１では、オープンスタブを構成するための第１配線を分離された複数の配線とし、その分離された部分を、金属ナノ粒子が融着されてなる第２配線５を用いて接続することによりオープンスタブの線路長を調整できるようにしている。これにより、例えばインピーダンス特性を測定しながら第１配線４の分離された部分のうちの必要な部分のみを第２配線５によって接続するようにして入力インピーダンスを調整できる。   Therefore, in the first embodiment, the first wiring for configuring the open stub is used as a plurality of separated wirings, and the separated wiring is used as the second wiring 5 in which metal nanoparticles are fused. The line length of the open stub can be adjusted by connecting them. Thereby, for example, the input impedance can be adjusted so that only the necessary part of the separated parts of the first wiring 4 is connected by the second wiring 5 while measuring the impedance characteristics.

また、本実施の形態１では、電界効果トランジスタ２のゲート７に接続される線路は、ゲート７のすぐ近くで抵抗体膜１０（ナノ粒子が融着されてなる抵抗体膜１０）と容量１１（ＭＩＭキャパシタ）を介して接地することができるようになっており、オープンスタブを接続することによって入力インピーダンスが調整できるようになっている。   In the first embodiment, the line connected to the gate 7 of the field effect transistor 2 has a resistor film 10 (resistor film 10 formed by fusing nanoparticles) and a capacitor 11 in the immediate vicinity of the gate 7. It can be grounded via (MIM capacitor), and the input impedance can be adjusted by connecting an open stub.

すなわち、一端が接地されたＭＩＭ容量１１の他端とゲートに接続される線路の間に抵抗体膜１０を後で形成することによって、必要な場合にゲート側安定化回路を挿入することができるようになっている。尚、ＭＩＭ容量１１の一端はビアホール９により接地されている。また、安定化回路を挿入すると例えば利得が低下する等の問題が生じる場合があるので、安定化回路は必要な場合にのみ接続すればよく、高周波デバイスの特性を測定してから安定化の必要がある場合だけ安定化をできるので利得を損なうことなく必要最小限の安定化が図れるという利点がある。   That is, by forming the resistor film 10 later between the other end of the MIM capacitor 11 whose one end is grounded and the line connected to the gate, the gate side stabilization circuit can be inserted when necessary. It is like that. Note that one end of the MIM capacitor 11 is grounded by a via hole 9. Inserting a stabilization circuit may cause problems such as a decrease in gain. For example, a stabilization circuit may be connected only when necessary. Stabilization is necessary after measuring the characteristics of a high-frequency device. Since the stabilization can be performed only when there is, there is an advantage that the minimum necessary stabilization can be achieved without losing the gain.

実施の形態１では、さらに、第２配線５は、粒径が１００ｎｍ以下、好ましくは粒径が１ｎｍ〜１００ｎｍの範囲の金属ナノ粒子を含む導電性インクをインクジェット方式により塗布し、例えば、２００℃以下の比較的低い温度で熱処理して金属ナノ粒子を融着させることにより形成している。
このようなサイズのナノ粒子は沈殿することなく溶剤と混合することが可能であり、インクジェット等の方法で容易にかつ均一に必要な部分のみに塗布することができる。
また、高周波デバイスの調整用の配線部分には１０〜８００μｍ程度の幅の線路が用いられ、ナノ粒子を分散させたインクを用いたインクジェット方式ではその程度の線幅の線路は容易に形成することができるが、本実施の形態１の高周波デバイスでは、さらに以下のようにして、精度よく第２導体５が形成できるようにしている。 In the first embodiment, the second wiring 5 is further coated with a conductive ink containing metal nanoparticles having a particle size of 100 nm or less, preferably in a range of 1 nm to 100 nm by an inkjet method, for example, 200 ° C. The metal nanoparticles are formed by heat treatment at the following relatively low temperature.
Nanoparticles of such a size can be mixed with a solvent without precipitation, and can be easily and uniformly applied only to necessary portions by a method such as inkjet.
In addition, a line having a width of about 10 to 800 μm is used for the wiring portion for adjustment of the high-frequency device, and a line having such a line width can be easily formed in an ink jet system using ink in which nanoparticles are dispersed. However, in the high frequency device of the first embodiment, the second conductor 5 can be formed with high accuracy as follows.

すなわち、本実施の形態１では、インクの塗布領域の外部の領域を、表面処理により撥水性とすることにより、インク塗布時にインクが外部領域に滲むことを防止し、インクを塗布する領域を表面処理等により親水性領域１４としている。
これにより、インク塗布時に、第２導体５を形成すべき親水性領域１４にインクが付着し易くでき、かつ塗布領域内に均一にインクを拡げることができる一方、他の部分を撥水性領域とすることにより、不要な部分にインクが付着することを防止できる。
従って、本実施の形態１の高周波デバイスでは、極めて精度よく第２導体５が形成できる。尚、半導体基板の表面を酸素プラズマ処理することにより容易に親水性とでき、半導体基板の表面をＣＦ６プラズマ処理することにより撥水性とできる。
尚、本明細書において親水処理とは、水に限らずインクの溶剤が濡れやすくすることをいい、撥水処理とはインクの溶剤が濡れにくくすることをいう。 That is, in the first embodiment, the area outside the ink application area is made water-repellent by surface treatment, so that the ink is prevented from spreading into the external area when the ink is applied, and the area where the ink is applied is the surface. The hydrophilic region 14 is formed by processing or the like.
Thereby, at the time of ink application, the ink can easily adhere to the hydrophilic region 14 where the second conductor 5 is to be formed, and the ink can be spread uniformly in the application region, while the other portion is defined as the water repellent region. By doing so, it is possible to prevent ink from adhering to unnecessary portions.
Therefore, in the high frequency device of the first embodiment, the second conductor 5 can be formed with extremely high accuracy. The surface of the semiconductor substrate can be easily made hydrophilic by oxygen plasma treatment, and the surface of the semiconductor substrate can be made water repellent by CF6 plasma treatment.
In the present specification, the hydrophilic treatment means that the ink solvent is easily wetted, not just water, and the water repellent treatment means that the ink solvent is hardly wetted.

また、このナノ粒子を含むインクジェット用の塗料は、例えば、トルエン等の分散剤にナノ粒子を混ぜ、常温では融着しないようにしておいて、塗料を塗布した後に加熱して分散剤を気化させたり化学的性質を変えたりしてナノ粒子同士が接触するようにして融着させるが、粒径が１００ｎｍ以下のナノ粒子は、表面エネルギーが極めて大きいため、２００℃以下の比較的低温で融着させることができる。   In addition, for example, an inkjet paint containing the nanoparticles may be mixed with a dispersant such as toluene so that the nanoparticles are not fused at room temperature. Or by changing the chemical properties so that the nanoparticles are brought into contact with each other, but the nanoparticles having a particle size of 100 nm or less have a very large surface energy, and therefore are fused at a relatively low temperature of 200 ° C. or less. Can be made.

一般の樹脂基板の製造工程では４００℃といった高熱の加熱工程でナノ粒子を互いに融着して配線することが可能であるが（特開２００３-３０９８６９）、化合物半導体（例えば、ＧａＡｓ等）からなる半導体基板を用いて構成される高周波デバイスでは、このような高温では、例えばＧａＡｓのＡｓが動いてしまう。
従って、本実施の形態１では、ナノ粒子を融着させる温度が、化合物半導体基板の最大保存温度である１５０℃〜１７５℃を超えると半導体の性質が変わってしまうので、化合物半導体基板の最大保存温度である１５０℃〜１７５℃以下の温度でナノ粒子を融着させる。 In a general resin substrate manufacturing process, the nanoparticles can be fused and wired in a high-temperature heating process such as 400 ° C. (Japanese Patent Laid-Open No. 2003-309869), but is made of a compound semiconductor (eg, GaAs). In a high-frequency device configured using a semiconductor substrate, for example, GaAs As moves at such a high temperature.
Therefore, in this Embodiment 1, since the property of a semiconductor will change if the temperature which fuse | melts a nanoparticle exceeds 150 to 175 degreeC which is the maximum storage temperature of a compound semiconductor substrate, the maximum storage of a compound semiconductor substrate is carried out. The nanoparticles are fused at a temperature of 150 ° C. to 175 ° C., which is a temperature.

また、インクジェット方式により塗料を塗布する場合、塗料が流れて広がらないようにするために基板を加熱することが好ましく、例えば、基板を８０℃以上に加熱しながら塗布を行うことにより、１０μｍといった微細な寸法の線路をよりいっそう精度良く描画することができる。   Further, in the case of applying a paint by an ink jet method, it is preferable to heat the substrate so that the paint does not flow and spread. For example, by applying the substrate while heating the substrate to 80 ° C. or higher, a fineness of 10 μm is applied. It is possible to draw a track with a more accurate dimension with higher accuracy.

本実施の形態１では、上述の融着後の抵抗及び線路の寸法精度を考慮して、半導体基板を８０℃〜１７５℃の範囲で加熱して、塗布、融着することになるが、融着により抵抗の低い導電膜を形成するためには、より高い温度で融着させることが好ましく、温度制御精度分のマージン１０℃を最大定格温度から引いた温度、すなわち最大定格１５０℃の半導体では、融着温度を１４０℃に設定し（半導体基板が加熱される温度範囲として１４０℃〜１５０℃、）、最大定格１７５℃の半導体では１６５℃に設定する（１６５℃〜１７５℃）ことが望ましい。   In the first embodiment, in consideration of the above-mentioned resistance after fusion and the dimensional accuracy of the line, the semiconductor substrate is heated in the range of 80 ° C. to 175 ° C. to be applied and fused. In order to form a conductive film having a low resistance by deposition, it is preferable to fuse at a higher temperature. For a semiconductor having a temperature control accuracy margin of 10 ° C. subtracted from the maximum rated temperature, that is, a semiconductor having a maximum rating of 150 ° C. It is desirable to set the fusing temperature to 140 ° C. (140 ° C. to 150 ° C. as the temperature range in which the semiconductor substrate is heated), and to 165 ° C. (165 ° C. to 175 ° C.) for a semiconductor with a maximum rating of 175 ° C. .

また、実施の形態１において、抵抗体膜１０は、配線用の金属ナノ粒子に代えて、配線用の金属ナノ粒子より抵抗率が高い抵抗体用のナノ粒子を含む抵抗体インクを用いて、第２配線と同様にして形成する。
このような方法によって、実施の形態１では、必要な箇所に選択的に、抵抗体用ナノ粒子が融着されてなる抵抗体膜１０を精度（寸法及び抵抗値について）よく形成することができる。 In the first embodiment, the resistor film 10 uses a resistor ink containing nanoparticles for a resistor having a higher resistivity than the metal nanoparticles for the wiring, instead of the metal nanoparticles for the wiring. It is formed in the same manner as the second wiring.
According to such a method, in the first embodiment, the resistor film 10 in which the resistor nanoparticles are fused selectively at a necessary portion can be formed with high accuracy (in terms of dimensions and resistance value). .

以上のように、本実施の形態１では、調整用の接続配線として、ナノ粒子が融着された第２導体を用いているので、その接続配線をバルクの金属抵抗に近い抵抗値とでき（蒸着配線やメッキ配線より遥かに抵抗値とできる）、かつ従来のように金属ワイヤによるインダクタンス成分を生じることがないので、良好なインピーダンス整合が可能となる。
また、抵抗体用のナノ粒子を含む抵抗体インクを用いてインクジェット方式により塗布して、抵抗体膜１０を形成しているので、抵抗体膜１０の抵抗値を精度よく管理できる。
このようにして実施の形態１では、金属ワイヤを用いることなくトランジスタ２とそれに接続される回路のインピーダンスを整合させることが可能になり、かつ必要な場合にトランジスタに近接した安定化回路を挿入することができ、トランジスタの安定化が図れ、高周波特性（ＲＦ）特性を最適化が可能になる。 As described above, in the first embodiment, since the second conductor in which the nanoparticles are fused is used as the adjustment connection wiring, the connection wiring can have a resistance value close to the bulk metal resistance. The resistance value is much higher than that of vapor-deposited wiring and plated wiring), and no inductance component due to metal wire is generated as in the prior art, so that good impedance matching is possible.
Further, since the resistor film 10 is formed by applying the resistor ink containing the nanoparticles for the resistor by the ink jet method, the resistance value of the resistor film 10 can be accurately managed.
Thus, in the first embodiment, it is possible to match the impedance of the transistor 2 and the circuit connected thereto without using a metal wire, and a stabilization circuit close to the transistor is inserted when necessary. Therefore, the transistor can be stabilized and the high frequency characteristics (RF) characteristics can be optimized.

尚、図１及び図２では、ゲートに接続される線路及びゲート側の安定化回路の例により説明したが、本発明はこれに限られるものではなく、トランジスタの他の端子に接続される線路や他の線路のインピーダンス調整、他の部分に接続される安定化回路について適用できることはいうまでもない。
また、本実施の形態１では、電界効果トランジスタを例に説明したが、ヘテロバイポーラトランジスタ等の他のトランジスタであってもよいし、また、基板もＳｉ等の他の半導体基板やアルミナ等の誘電体基板であっても良い。 In FIGS. 1 and 2, the line connected to the gate and the stabilization circuit on the gate side have been described as examples. However, the present invention is not limited to this, and the line connected to the other terminal of the transistor. Needless to say, the present invention can be applied to the impedance adjustment of other lines and a stabilization circuit connected to other parts.
In the first embodiment, the field effect transistor has been described as an example. However, the transistor may be another transistor such as a heterobipolar transistor, and the substrate may be another semiconductor substrate such as Si or a dielectric such as alumina. It may be a body substrate.

実施の形態２．
本発明に係る実施の形態２の高周波デバイスは、第２導体５の基板への付着強度を高めるために、第２導体５が形成される領域に島状配線１２を形成しておいて、その上に第２導体５を形成するようにした以外は、実施の形態１の高周波デバイスと同様に構成される。
図３Ａは、実施の形態２に係る高周波デバイスの一部を拡大して示す上面図であり、図３Ｂは第２導体５を形成する前の上面図である。
図３Ａ，図３Ｂ中において１２の符号を付して示すものは、島状に設けられた接着強化用の島状配線であり、導電性インクを塗布する領域（第２導体５を形成する領域）に設けてある。 Embodiment 2. FIG.
In the high-frequency device according to the second embodiment of the present invention, in order to increase the adhesion strength of the second conductor 5 to the substrate, the island-like wiring 12 is formed in the region where the second conductor 5 is formed. The configuration is the same as that of the high-frequency device of the first embodiment except that the second conductor 5 is formed thereon.
FIG. 3A is an enlarged top view showing a part of the high-frequency device according to Embodiment 2, and FIG. 3B is a top view before the second conductor 5 is formed.
In FIG. 3A and FIG. 3B, what is indicated by reference numeral 12 is an island-like wiring for adhesion strengthening provided in an island shape, and a region to which conductive ink is applied (a region where the second conductor 5 is formed). ).

この接着強化用の島状配線１２は、半導体基板との密着力を強くでき、かつ第２導体５との間の密着力を高くできる方法及び材料で形成されて、基板と第２導体５の間の接着力を強化するものであり、好ましくは、接着強化用の島状配線は、例えば、第１導体４と同一材料及び同一方法（例えばスバッタリング又は蒸着）で第１導体と同時に形成される。   The island-like wiring 12 for reinforcing adhesion is formed by a method and a material that can increase the adhesion with the semiconductor substrate and can increase the adhesion with the second conductor 5. The island-like wiring for reinforcing adhesion is preferably formed simultaneously with the first conductor by the same material and the same method (for example, sputtering or vapor deposition) as the first conductor 4. Is done.

すなわち、一般に導電性インクにより形成された膜の半導体基板への付着強度は弱いために、融着後の導体膜が剥がれてしまうおそれがあるが、本実施の形態２では、第２導体５の下部に予め付着強度の強い島状配線１２を設けておくことにより、融着後の第２導体５付着強度が、島状配線１２と基板間の強い付着強度及び島状配線１２と第２導体５との間の強い付着強度により強化され、第２配線５と基板との間のはがれを防止できる。   That is, generally, the adhesion strength of the film formed of the conductive ink to the semiconductor substrate is weak, so that the conductor film after the fusion may be peeled off. By providing the island-like wiring 12 having a strong adhesion strength in the lower portion in advance, the adhesion strength of the second conductor 5 after the fusion is strong and the adhesion strength between the island-like wiring 12 and the substrate and the island-like wiring 12 and the second conductor. The strong adhesion strength between the second wiring 5 and the substrate can be prevented.

ここで、島状配線１２の形状及び間隔は、少なくとも第２導体５が形成されていないときには、マイクロ波信号が伝送されないように設定する。すなわち、第２導体５が形成されていない場合には、島状配線１２が形成された領域は、高インピーダンスに見えるようにして、分離された配線４が回路特性に影響を与えることがないようにする。具体的には、配線４はインピーダンスの関係から基板厚の１／５〜５倍程度に設定されるので、島状配線１２の間隔は基板厚の１倍以下にすればよい。   Here, the shape and interval of the island-like wiring 12 are set so that the microwave signal is not transmitted at least when the second conductor 5 is not formed. That is, when the second conductor 5 is not formed, the region where the island-like wiring 12 is formed looks high impedance so that the separated wiring 4 does not affect the circuit characteristics. To. Specifically, since the wiring 4 is set to about 1/5 to 5 times the substrate thickness due to impedance, the interval between the island-like wirings 12 may be set to 1 time or less of the substrate thickness.

また、図中の１３はワイヤボンドを行うパッド領域を示しており、ワイヤを打つために特に強い付着強度が必要な領域である。従って、本実施の形態２では、パッド領域１３の下に、予め付着強度の強い配線を島状に設けておき、ワイヤを打った場合でも第２導体がはがれないようにしている。
なお、図３に示す例では、上側に３個、下側に３個の島状配線１２を設けたが、各々の個数は何個であっても良い。 Reference numeral 13 in the figure denotes a pad region where wire bonding is performed, which is a region that requires particularly strong adhesion strength in order to hit a wire. Therefore, in the second embodiment, wiring having high adhesion strength is provided in an island shape in advance under the pad region 13 so that the second conductor is not peeled even when a wire is struck.
In the example shown in FIG. 3, three island-like wirings 12 are provided on the upper side and three island-like wirings 12 are provided on the lower side. However, the number of each may be any number.

実施の形態３．
本発明に係る実施の形態３の高周波デバイスは、異なる要求特性に対応して回路構成を変更する必要がある部分を第２導体５で構成するようにしたことを特徴としている。
すなわち、本実施の形態１の高周波デバイスは、高周波回路が形成された後に、主として、回路特性を測定して調整又は接続が必要な部分に第２導体５を形成するようにしたが、本実施の形態３の高周波デバイスでは、調整等が必要な部分だけではなく、例えば、異なる周波数帯域や異なる高周波特性の要求に対応して回路構成を変更する必要がある部分も含めて第２導体５で構成するようにしている。 Embodiment 3 FIG.
The high-frequency device according to the third embodiment of the present invention is characterized in that the second conductor 5 constitutes a portion that needs to be changed in circuit configuration in response to different required characteristics.
That is, in the high-frequency device of the first embodiment, after the high-frequency circuit is formed, the second conductor 5 is mainly formed in a portion that needs to be adjusted or connected by measuring circuit characteristics. In the high-frequency device according to the third embodiment, not only the part that needs to be adjusted, but also the second conductor 5 including the part that needs to be changed in circuit configuration in response to requirements for different frequency bands and different high-frequency characteristics. I am trying to configure it.

図４は、本発明に係る実施の形態３の高周波デバイスの一例を示す上面図であり、本実施の形態３では、予め半導体基板１上に、回路における汎用的な部分を構成する電界効果トランジスタ（ＦＥＴ）２、第１配線４、ビアホール９、ＭＩＭ容量１１等を設けておき、後から導電性インクや抵抗体インクを用いて第２配線５及び抵抗体膜１０を描画している。   FIG. 4 is a top view showing an example of the high-frequency device according to the third embodiment of the present invention. In the third embodiment, a field effect transistor that constitutes a general-purpose part of a circuit on the semiconductor substrate 1 in advance. (FET) 2, first wiring 4, via hole 9, MIM capacitor 11 and the like are provided, and the second wiring 5 and the resistor film 10 are drawn later using conductive ink or resistor ink.

また、実施の形態１の高周波デバイスでは、第１配線４間の接続等用の比較的小さい領域に第２配線５を形成したが、本実施の形態３の高周波デバイスでは、比較的大きい領域又は長い距離を第２配線５によって配線することが必要になる。
そこで、実施の形態３では、第２配線５及び抵抗体膜１０が形成される部分に、図５に示すように島状に親水性領域１４を形成するようにし、その島状親水性領域１４以外の部分を撥水性領域６として高い寸法精度を確保している。 In the high frequency device of the first embodiment, the second wiring 5 is formed in a relatively small region for connection between the first wirings 4. However, in the high frequency device of the third embodiment, the relatively large region or A long distance needs to be wired by the second wiring 5.
Therefore, in the third embodiment, an island-like hydrophilic region 14 is formed in the portion where the second wiring 5 and the resistor film 10 are formed as shown in FIG. The portion other than is used as the water repellent region 6 to ensure high dimensional accuracy.

ここで、撥水性領域６は、基板表面をＣＦ６プラズマで処理することにより形成でき、その撥水性領域６に、島状の開口部を有するレジストを形成して、その開口部により露出された基板表面を酸素プラズマで処理することにより、島状親水性領域１４を形成することができる。   Here, the water-repellent region 6 can be formed by treating the substrate surface with CF6 plasma, and a resist having island-like openings is formed in the water-repellent region 6 and the substrate exposed through the openings. By treating the surface with oxygen plasma, the island-like hydrophilic region 14 can be formed.

本実施の形態３では、上述のようにして、撥水性領域６の中に、島状に島状親水性領域１４を形成した領域に、導電性インク５又は抵抗体インクをインクジェツト方式により描画することにより、パターン精度よく第２配線５及び抵抗体膜１０を形成することができる。すなわち、撥水領域だと付着し難いのが島状親水性領域１４に付着することにより基板に付着させることができ、同時に親水性領域だけだと導電性インクの端からインクが滲んでパターン描画し難いという問題を解決出来る。   In the third embodiment, as described above, the conductive ink 5 or the resistor ink is drawn by the inkjet method in the region where the island-like hydrophilic region 14 is formed in the island shape in the water-repellent region 6. By doing so, the second wiring 5 and the resistor film 10 can be formed with high pattern accuracy. That is, it is possible to attach to the substrate by adhering to the island-like hydrophilic region 14 that is difficult to adhere in the water-repellent region, and at the same time, in the case of only the hydrophilic region, the ink is smeared from the edge of the conductive ink to draw the pattern. It can solve the difficult problem.

以上の実施の形態３の高周波デバイスでは、例えば、異なる周波数帯域や異なるＲＦ特性が要求される回路を、導電性インクや抵抗体インクを用いて描画する第２配線５及び抵抗体膜１０を変更することによって実現出来るので、短期間に回路を作成できる利点がある。
また、多品種少量の製品であっても、同一半導体基板１上の配線のみを変えて対応可能であることから製品毎にマスクを形成する必要がなく、製造コストを低くできるという効果もある。 In the high frequency device of the third embodiment described above, for example, the second wiring 5 and the resistor film 10 for drawing a circuit that requires different frequency bands and different RF characteristics using conductive ink or resistor ink are changed. It is possible to create a circuit in a short time because it can be realized.
In addition, since even a small variety of products can be handled by changing only the wiring on the same semiconductor substrate 1, it is not necessary to form a mask for each product, and the manufacturing cost can be reduced.

また、一般に電界効果トランジスタ（ＦＥＴ）から最初のスタブまでの間をメッキや蒸着配線で形成した場合には、配線抵抗が大きいために、ＦＥＴ直近の多重反射が多くなる配線部での高周波損失が大きくなるという問題があるが、例えば、図４に示す実施の形態３の高周波デバイスでは、電界効果トランジスタ２のゲート７やドレイン８から最初のスタブまでの配線を配線用金属ナノ粒子が融着された第２配線５で形成したので、その配線の抵抗を小さくでき、高周波の損失を小さくできるという効果もある。   In general, when the area between the field effect transistor (FET) and the first stub is formed by plating or vapor-deposited wiring, the wiring resistance is large, so that there is a high frequency loss in the wiring section where multiple reflections near the FET increase. For example, in the high-frequency device according to the third embodiment shown in FIG. 4, the wiring metal nanoparticles are fused to the wiring from the gate 7 and the drain 8 of the field effect transistor 2 to the first stub. In addition, since the second wiring 5 is used, the resistance of the wiring can be reduced and the high-frequency loss can be reduced.

なお、本実施の形態３の高周波デバイスでは、電界効果トランジスタ２、配線４、ビアホール９、ＭＩＭ容量１１を基板１上に設けるようにして構成したが、抵抗、インダクタ、ダイオード等のほかの回路要素を設けてもよい。また、トランジスタは、電界効果トランジスタに限られるものではなく、バイポーラトランジスタ等の他のトランジスタであってもよい。   In the high-frequency device according to the third embodiment, the field effect transistor 2, the wiring 4, the via hole 9, and the MIM capacitor 11 are provided on the substrate 1. However, other circuit elements such as a resistor, an inductor, and a diode are used. May be provided. The transistor is not limited to a field effect transistor, and may be another transistor such as a bipolar transistor.

実施の形態４．
本発明に係る実施の形態４の高周波デバイスは、複数の基板間を金属ナノ粒子が融着されてなる第２配線５によって接続したものである。図６は、実施の形態４の高周波デバイスの構成を示す斜視図であり、本実施の形態４の例では、２枚の半導体基板１の基板間をエポキシ樹脂等の誘電体の充填物１５を用いて充填し、充填後にその充填物１５の上にインクジェット方式により導電性インク５を塗布して、金属ナノ粒子を融着させることにより結線している。 Embodiment 4 FIG.
In the high-frequency device according to the fourth embodiment of the present invention, a plurality of substrates are connected by a second wiring 5 formed by fusing metal nanoparticles. FIG. 6 is a perspective view showing the configuration of the high-frequency device of the fourth embodiment. In the example of the fourth embodiment, a dielectric filler 15 such as an epoxy resin is provided between two semiconductor substrates 1. After filling, the conductive ink 5 is applied onto the filling 15 by an ink jet method, and the metal nanoparticles are fused to form a connection.

従来のワイヤボンドによる基板間の結線では、ワイヤの高さや長さの制御が難しいことからインダクタンス成分がばらつくという問題があったが、本構成により平面的に接続することが可能となり、基板間の接続用の第２導体５の幅の制御も容易であることから、基板間の接続のばらつきによる高周波特性のばらつきを抑制できる効果がある。   In the conventional wire bonding between the substrates, there is a problem that the inductance component varies because it is difficult to control the height and length of the wires. Since it is easy to control the width of the second conductor 5 for connection, there is an effect of suppressing variation in high-frequency characteristics due to variation in connection between substrates.

更に、ワイヤボンディングのように、一定以上の高さが必要になることも無く、平面的な接続であることから、半導体基板上部の蓋までの距離を短く出来、高周波デバイスのパッケージ後の高さを低くでき、薄型化が可能となる。また、ワイヤに比較して幅広いパターンを形成することが出来るので基板間の抵抗を小さくできると共に、結線部のインピーダンスの制御が可能となるという効果もある。
なお、本例では半導体基板を結線したが、アルミナ等の誘電体基板やパッケージ、モジュール等の間の接続に金属ナノ粒子が融着されてなる第２導体を用いてもよい。 Furthermore, unlike wire bonding, it does not require a certain height, and it is a planar connection, so the distance to the lid on the top of the semiconductor substrate can be shortened, and the height after packaging of the high-frequency device The thickness can be reduced. In addition, since a wider pattern can be formed as compared with the wire, the resistance between the substrates can be reduced, and the impedance of the connection portion can be controlled.
In this example, the semiconductor substrate is connected, but a second conductor formed by fusing metal nanoparticles for connection between a dielectric substrate such as alumina, a package, a module, or the like may be used.

本発明に係る実施の形態１の高周波デバイスの構成を示す平面図である。It is a top view which shows the structure of the high frequency device of Embodiment 1 which concerns on this invention. 実施の形態１の高周波デバイスの回路構成を示す回路図である。FIG. 3 is a circuit diagram illustrating a circuit configuration of the high-frequency device according to the first embodiment. 本発明に係る実施の形態２の高周波デバイスの一部の構成を拡大して示す平面図である。It is a top view which expands and shows a part of structure of the high frequency device of Embodiment 2 which concerns on this invention. 図３Ａの実施の形態２の高周波デバイスの一部における第２導体を形成する前の平面図である。It is a top view before forming the 2nd conductor in a part of high frequency device of Embodiment 2 of FIG. 3A. 本発明に係る実施の形態３の高周波デバイスの構成を示す平面図である。It is a top view which shows the structure of the high frequency device of Embodiment 3 which concerns on this invention. 実施の形態３の高周波デバイスにおけるインクが塗布される領域の構成を示す平面図である。FIG. 10 is a plan view showing a configuration of a region where ink is applied in the high-frequency device according to the third embodiment. 本発明に係る実施の形態４の高周波デバイスの構成を示す斜視図である。It is a perspective view which shows the structure of the high frequency device of Embodiment 4 which concerns on this invention. 従来例の高周波デバイスの構成を示す平面図である。It is a top view which shows the structure of the high frequency device of a prior art example.

符号の説明Explanation of symbols

１ 半導体基板、２ 電界効果トランジスタ、４ 第１配線、５ 第２配線、６ 撥水性領域、７ ゲート、８ ドレイン、９ ビアホール、１０ 抵抗体膜、１１ ＭＩＭキャパシタ、１２ 島状配線、１３ パッド領域、１４ 親水性領域、１５ 充填物。
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Field effect transistor, 4 1st wiring, 5 2nd wiring, 6 Water-repellent region, 7 Gate, 8 Drain, 9 Via hole, 10 Resistor film, 11 MIM capacitor, 12 Island-like wiring, 13 Pad region , 14 hydrophilic region, 15 filling.

Claims (12)

基板上に配線が施されてなる高周波デバイスであって、
上記配線は、第１配線と、その第１配線に接続されかつ上記第１配線とは別に形成された第２配線とを含んでなり、該第２配線は１００ｎｍ以下の配線用金属ナノ粒子が融着されてなることを特徴とする高周波デバイス。 A high-frequency device in which wiring is applied on a substrate,
The wiring includes a first wiring and a second wiring connected to the first wiring and formed separately from the first wiring, and the second wiring includes metal nanoparticles for wiring of 100 nm or less. A high-frequency device characterized by being fused. 上記第１配線は、複数に分離されて形成されており、上記第２配線は上記分離された第１配線間を接続する請求項１記載の高周波デバイス。   The high-frequency device according to claim 1, wherein the first wiring is formed by being separated into a plurality of parts, and the second wiring connects the separated first wirings. 上記第２配線は、要求される高周波特性に応じて描画されてなる請求項１又は２に記載の高周波デバイス。   The high frequency device according to claim 1, wherein the second wiring is drawn according to required high frequency characteristics. 上記基板表面のうち、上記第２配線が形成される部分が親水処理された請求項１〜３のうちのいずれか１つに記載の高周波デバイス。   The high frequency device according to any one of claims 1 to 3, wherein a portion of the substrate surface on which the second wiring is formed is subjected to a hydrophilic treatment. 上記第２配線が形成される部分以外の他の部分が撥水処理されている請求項４記載の高周波デバイス。   The high frequency device according to claim 4, wherein a portion other than the portion where the second wiring is formed is subjected to water repellent treatment. 上記基板表面のうち上記第２配線が形成される部分に、島状に親水性を有する領域を設けた請求項４又は５に記載の高周波デバイス。   The high-frequency device according to claim 4 or 5, wherein a region having hydrophilicity in an island shape is provided in a portion of the substrate surface where the second wiring is formed. 上記分離された第１配線間を接続する抵抗体膜をさらに含み、該抵抗体膜は上記配線用金属ナノ粒子より抵抗率が高く１００ｎｍ以下の径の抵抗体ナノ粒子が融着されてなる請求項１〜６のうちのいずれか１つに記載の高周波デバイス。   A resistor film connecting the separated first wirings is further included, and the resistor film is formed by fusing resistor nanoparticles having a resistivity higher than that of the wiring metal nanoparticles and having a diameter of 100 nm or less. Item 7. The high-frequency device according to any one of Items 1 to 6. 上記第２配線と基板表面との間に、互いに分離された複数の接着強化用の島状配線が形成された請求項１〜７のうちのいずれか１つに記載の高周波デバイス。   The high frequency device according to any one of claims 1 to 7, wherein a plurality of island-like wirings for reinforcing adhesion separated from each other are formed between the second wiring and the substrate surface. 上記島状配線は、上記第１配線と同じ材料からなる請求項８記載の高周波デバイス。   The high-frequency device according to claim 8, wherein the island-shaped wiring is made of the same material as the first wiring. 上記島状配線の上に形成された上記第２配線の一部を、ワイヤボンディング用のパッドとした請求項８又は９に記載の高周波デバイス。   The high-frequency device according to claim 8 or 9, wherein a part of the second wiring formed on the island-shaped wiring is used as a wire bonding pad. 上記基板上にトランジスタが形成されており、そのトランジスタの少なくとも１つの端子は上記第２配線により結線されている請求項１〜１０のうちのいずれか１つに記載の高周波デバイス。   The high-frequency device according to claim 1, wherein a transistor is formed on the substrate, and at least one terminal of the transistor is connected by the second wiring. 請求項１〜１１のうちのいずれか１つに記載の第１の高周波デバイスと請求項１〜１２のうちのいずれか１つに記載の第２の高周波デバイスとを含み、第１の高周波デバイスの基板と第２の高周波デバイスの基板の間に絶縁物を充填し、その絶縁物の上に、１００ｎｍ以下の配線用金属ナノ粒子が融着されてなる第３配線を形成し、その第３配線により第１の高周波デバイスと第２の高周波デバイスとを接続したことを特徴とする高周波デバイス。
A first high-frequency device comprising: the first high-frequency device according to any one of claims 1 to 11; and the second high-frequency device according to any one of claims 1 to 12. An insulating material is filled between the substrate of the second high frequency device and the substrate of the second high-frequency device, and a third wiring is formed on the insulating material by fusing metal nanoparticles for wiring of 100 nm or less, and the third wiring is formed. A high-frequency device characterized in that a first high-frequency device and a second high-frequency device are connected by wiring.
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