JP2005353041A - データ処理システム内のバス・トランザクション管理 - Google Patents

データ処理システム内のバス・トランザクション管理 Download PDF

Info

Publication number
JP2005353041A
JP2005353041A JP2005128546A JP2005128546A JP2005353041A JP 2005353041 A JP2005353041 A JP 2005353041A JP 2005128546 A JP2005128546 A JP 2005128546A JP 2005128546 A JP2005128546 A JP 2005128546A JP 2005353041 A JP2005353041 A JP 2005353041A
Authority
JP
Japan
Prior art keywords
request
write
read
bus
requests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005128546A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005353041A5 (https=
Inventor
Peter Guy Middleton
ピーター・ガイ・ミドルトン
David John Gwilt
デヴィッド・ジョン・グウィルト
Ian Victor Devereux
イアン・ヴィクター・デュヴルー
Bruce James Mathewson
ブルース・ジェイムス・マシューソン
Antony John Harris
アントニー・ジョン・ハリス
Richard Roy Grisenthwaite
リチャード・ロイ・グリセンスウェイト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Publication of JP2005353041A publication Critical patent/JP2005353041A/ja
Publication of JP2005353041A5 publication Critical patent/JP2005353041A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
JP2005128546A 2004-06-08 2005-04-26 データ処理システム内のバス・トランザクション管理 Pending JP2005353041A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/862,884 US7213095B2 (en) 2004-06-08 2004-06-08 Bus transaction management within data processing systems

Publications (2)

Publication Number Publication Date
JP2005353041A true JP2005353041A (ja) 2005-12-22
JP2005353041A5 JP2005353041A5 (https=) 2007-04-19

Family

ID=34465816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005128546A Pending JP2005353041A (ja) 2004-06-08 2005-04-26 データ処理システム内のバス・トランザクション管理

Country Status (3)

Country Link
US (1) US7213095B2 (https=)
JP (1) JP2005353041A (https=)
GB (1) GB2415067B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010026577A (ja) * 2008-07-15 2010-02-04 Seiko Epson Corp マルチプロセッサシステム及びそれを搭載した流体吐出装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8244825B2 (en) * 2006-11-06 2012-08-14 Hewlett-Packard Development Company, L.P. Remote direct memory access (RDMA) completion
US8161222B1 (en) 2007-07-23 2012-04-17 Augmentix Corporation Method and system and apparatus for use in data storage
US7913025B1 (en) * 2007-07-23 2011-03-22 Augmentix Corporation Method and system for a storage device
US8145844B2 (en) * 2007-12-13 2012-03-27 Arm Limited Memory controller with write data cache and read data cache
JP4982354B2 (ja) * 2007-12-28 2012-07-25 パナソニック株式会社 情報処理装置
GB2478795B (en) * 2010-03-19 2013-03-13 Imagination Tech Ltd Requests and data handling in a bus architecture
US8392621B2 (en) 2010-06-22 2013-03-05 International Business Machines Corporation Managing dataflow in a temporary memory
US10254967B2 (en) 2016-01-13 2019-04-09 Sandisk Technologies Llc Data path control for non-volatile memory
US10528267B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Command queue for storage operations
US10528286B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Interface for non-volatile memory
US10528255B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Interface for non-volatile memory
US10114589B2 (en) * 2016-11-16 2018-10-30 Sandisk Technologies Llc Command control for multi-core non-volatile memory

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage
US5195089A (en) 1990-12-31 1993-03-16 Sun Microsystems, Inc. Apparatus and method for a synchronous, high speed, packet-switched bus
EP0543652B1 (en) 1991-11-19 1998-10-28 Fujitsu Limited Memory accessing device
US5668971A (en) * 1992-12-01 1997-09-16 Compaq Computer Corporation Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer
FR2717921B1 (fr) 1994-03-24 1996-06-21 Texas Instruments France Dispositif de gestion de conflit d'accès entre un CPU et des mémoires.
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US5925118A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and architectures for overlapped read and write operations
US6223301B1 (en) * 1997-09-30 2001-04-24 Compaq Computer Corporation Fault tolerant memory
US6279087B1 (en) * 1997-12-22 2001-08-21 Compaq Computer Corporation System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations
GB2341766A (en) 1998-09-18 2000-03-22 Pixelfusion Ltd Bus architecture
US6430649B1 (en) * 1999-06-07 2002-08-06 Sun Microsystems, Inc. Method and apparatus for enforcing memory reference dependencies through a load store unit
US6513089B1 (en) * 2000-05-18 2003-01-28 International Business Machines Corporation Dual burst latency timers for overlapped read and write data transfers
US6832279B1 (en) * 2001-05-17 2004-12-14 Cisco Systems, Inc. Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010026577A (ja) * 2008-07-15 2010-02-04 Seiko Epson Corp マルチプロセッサシステム及びそれを搭載した流体吐出装置

Also Published As

Publication number Publication date
GB2415067A (en) 2005-12-14
GB0504585D0 (en) 2005-04-13
US20050273543A1 (en) 2005-12-08
GB2415067B (en) 2008-04-09
US7213095B2 (en) 2007-05-01

Similar Documents

Publication Publication Date Title
US7315912B2 (en) Deadlock avoidance in a bus fabric
JP6141379B2 (ja) トランザクション属性を修正するためのメモリ領域オーダリング要求に関するコンプリータ知識の使用
US6243781B1 (en) Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe
JP4589384B2 (ja) 高速メモリモジュール
JP2002530744A (ja) 多重レベル接続識別を備えた通信のシステムおよび方法
CN1961302B (zh) 具有命令前瞻的存储器控制器
JP2005353041A (ja) データ処理システム内のバス・トランザクション管理
US20040010652A1 (en) System-on-chip (SOC) architecture with arbitrary pipeline depth
US7181561B2 (en) Ordering rule controlled command storage
US20020083256A1 (en) System and method for increasing the count of outstanding split transactions
TW484065B (en) Dynamic priority external transaction system
US8990456B2 (en) Method and apparatus for memory write performance optimization in architectures with out-of-order read/request-for-ownership response
US6275914B1 (en) Apparatus for preserving memory request ordering across multiple memory controllers
US6275913B1 (en) Method for preserving memory request ordering across multiple memory controllers
JP4198376B2 (ja) バスシステム及びバスシステムを含む情報処理システム
WO2004099995A2 (en) Hierarchical memory access via pipelining
US20080005484A1 (en) Cache coherency controller management
US6941407B2 (en) Method and apparatus for ordering interconnect transactions in a computer system
US7340553B2 (en) Data processing device and method for transferring data
US7613841B2 (en) Systems and methods for reducing data storage in devices using multi-phase data transactions
US6449678B1 (en) Method and system for multiple read/write transactions across a bridge system
TWI336439B (en) System and method to reduce memory latency in microprocessor systems connected with a bus
JP4928683B2 (ja) データ処理装置
CN114430819B (zh) 数据处理系统及其处理单元和处理方法
US7363412B1 (en) Interrupting a microprocessor after a data transmission is complete

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070302

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070302

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20070302

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20070501

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070612

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20071106