GB2415067B - Bus transaction management within data processing systems - Google Patents

Bus transaction management within data processing systems

Info

Publication number
GB2415067B
GB2415067B GB0504585A GB0504585A GB2415067B GB 2415067 B GB2415067 B GB 2415067B GB 0504585 A GB0504585 A GB 0504585A GB 0504585 A GB0504585 A GB 0504585A GB 2415067 B GB2415067 B GB 2415067B
Authority
GB
United Kingdom
Prior art keywords
data processing
processing systems
transaction management
bus transaction
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB0504585A
Other languages
English (en)
Other versions
GB2415067A (en
GB0504585D0 (en
Inventor
Peter Guy Middleton
David John Gwilt
Ian Victor Devereux
Bruce James Mathewson
Antony John Harris
Richard Roy Grisenthwaite
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Publication of GB0504585D0 publication Critical patent/GB0504585D0/en
Publication of GB2415067A publication Critical patent/GB2415067A/en
Application granted granted Critical
Publication of GB2415067B publication Critical patent/GB2415067B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
GB0504585A 2004-06-08 2005-03-04 Bus transaction management within data processing systems Expired - Lifetime GB2415067B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/862,884 US7213095B2 (en) 2004-06-08 2004-06-08 Bus transaction management within data processing systems

Publications (3)

Publication Number Publication Date
GB0504585D0 GB0504585D0 (en) 2005-04-13
GB2415067A GB2415067A (en) 2005-12-14
GB2415067B true GB2415067B (en) 2008-04-09

Family

ID=34465816

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0504585A Expired - Lifetime GB2415067B (en) 2004-06-08 2005-03-04 Bus transaction management within data processing systems

Country Status (3)

Country Link
US (1) US7213095B2 (https=)
JP (1) JP2005353041A (https=)
GB (1) GB2415067B (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8244825B2 (en) * 2006-11-06 2012-08-14 Hewlett-Packard Development Company, L.P. Remote direct memory access (RDMA) completion
US8161222B1 (en) 2007-07-23 2012-04-17 Augmentix Corporation Method and system and apparatus for use in data storage
US7913025B1 (en) * 2007-07-23 2011-03-22 Augmentix Corporation Method and system for a storage device
US8145844B2 (en) * 2007-12-13 2012-03-27 Arm Limited Memory controller with write data cache and read data cache
JP4982354B2 (ja) * 2007-12-28 2012-07-25 パナソニック株式会社 情報処理装置
JP5187038B2 (ja) * 2008-07-15 2013-04-24 セイコーエプソン株式会社 マルチプロセッサシステム及びそれを搭載した流体吐出装置
GB2478795B (en) * 2010-03-19 2013-03-13 Imagination Tech Ltd Requests and data handling in a bus architecture
US8392621B2 (en) 2010-06-22 2013-03-05 International Business Machines Corporation Managing dataflow in a temporary memory
US10254967B2 (en) 2016-01-13 2019-04-09 Sandisk Technologies Llc Data path control for non-volatile memory
US10528267B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Command queue for storage operations
US10528286B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Interface for non-volatile memory
US10528255B2 (en) 2016-11-11 2020-01-07 Sandisk Technologies Llc Interface for non-volatile memory
US10114589B2 (en) * 2016-11-16 2018-10-30 Sandisk Technologies Llc Command control for multi-core non-volatile memory

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage
EP0497054A2 (en) * 1990-12-31 1992-08-05 Sun Microsystems, Inc. Apparatus and method for a synchronous, high speed, packet-switched bus
EP0543652A1 (en) * 1991-11-19 1993-05-26 Fujitsu Limited Memory accessing device
EP0674258A1 (en) * 1994-03-24 1995-09-27 Texas Instruments France Device for managing access conflict between a CPU and memories
US5925118A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and architectures for overlapped read and write operations
GB2341766A (en) * 1998-09-18 2000-03-22 Pixelfusion Ltd Bus architecture
US6430649B1 (en) * 1999-06-07 2002-08-06 Sun Microsystems, Inc. Method and apparatus for enforcing memory reference dependencies through a load store unit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668971A (en) * 1992-12-01 1997-09-16 Compaq Computer Corporation Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US6223301B1 (en) * 1997-09-30 2001-04-24 Compaq Computer Corporation Fault tolerant memory
US6279087B1 (en) * 1997-12-22 2001-08-21 Compaq Computer Corporation System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations
US6513089B1 (en) * 2000-05-18 2003-01-28 International Business Machines Corporation Dual burst latency timers for overlapped read and write data transfers
US6832279B1 (en) * 2001-05-17 2004-12-14 Cisco Systems, Inc. Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage
EP0497054A2 (en) * 1990-12-31 1992-08-05 Sun Microsystems, Inc. Apparatus and method for a synchronous, high speed, packet-switched bus
EP0543652A1 (en) * 1991-11-19 1993-05-26 Fujitsu Limited Memory accessing device
EP0674258A1 (en) * 1994-03-24 1995-09-27 Texas Instruments France Device for managing access conflict between a CPU and memories
US5925118A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and architectures for overlapped read and write operations
GB2341766A (en) * 1998-09-18 2000-03-22 Pixelfusion Ltd Bus architecture
US6430649B1 (en) * 1999-06-07 2002-08-06 Sun Microsystems, Inc. Method and apparatus for enforcing memory reference dependencies through a load store unit

Also Published As

Publication number Publication date
GB2415067A (en) 2005-12-14
GB0504585D0 (en) 2005-04-13
US20050273543A1 (en) 2005-12-08
US7213095B2 (en) 2007-05-01
JP2005353041A (ja) 2005-12-22

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20250303