JP2005347758A - Cmos image sensor and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS image sensor and its manufacturing method, in which a shallow surface diffusion region is formed on the surface of a HAD region on an N-type photodiode. <P>SOLUTION: The CMOS image sensor comprises a first conductivity-type photodiode formed on a semiconductor substrate from the surface to a first depth, a second conductivity-type HAD region opposite to the first conductivity-type, formed on the photodiode from the surface of the semiconductor substrate to a second depth shallower than that of the first depth, and the first conductivity-type surface diffusion region formed on the HAD region from the surface of the semiconductor substrate to a third depth shallower than that of the second depth. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image sensor that converts an optical signal into an electrical signal and a manufacturing method thereof, and more particularly to a CMOS image sensor (hereinafter referred to as “CIS”) and a manufacturing method thereof.

  Recently, CIS and CCD (Charge Coupled Device) are mainly used in new technical fields such as mobile phones, PDAs (Personal Digital Assistants), and digital cameras. Among them, CIS is similar in principle to CCD in that light incident on a two-dimensionally arranged photodiode is converted into electric charges (electrons) and sequentially read out as a signal voltage according to a time axis. There is a difference from the CCD in the place to change to and the method of transmitting the signal to the output terminal. In the CIS, a charge is converted into a voltage in a plurality of unit pixels, and a signal is output by a signal line according to a switching operation.

  In the conventional CMOS image sensor, it has been pointed out as a big problem that noise or dark current causes a reduction in charge transfer efficiency and a decrease in charge storage capacity, thereby causing an image defect. Dark current means the charge accumulated in the image sensor's photosensitive element without light input, mainly due to various defects and silicon dangling bonds existing on the silicon substrate surface. It has been reported. Silicon dangling bonds on the surface of the silicon substrate are in a state in which electric charges are easily generated even if there is no input by light. Therefore, if a large amount of dangling bonds are present on the surface of the silicon substrate, even in a dark state, the image sensor exhibits a non-normal state representing a reaction as if light was incident. The dark current generated in the image sensor adversely affects the image quality of the image sensor.

  As described above, various techniques for reducing the dark current in the image sensor have been proposed (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3). However, the conventional techniques proposed so far have a limit in efficiently reducing the dark current generated by the defect at a specific position in the unit pixel.

In particular, in the configuration of a normal CMOS image sensor, various portions of a P ⁺ type HAD (Hole-Accumulation Diode) region formed on the N type photodiode from the photodiode region are adjacent to the surface of the silicon substrate. There are interface defects, for example, various impurities and defects such as silicon dangling bonds generated as a result of the substrate undergoing various processes. The charge generated by such defects flows into the N-type photodiode region through various paths, and moves to the floating diffusion region through the transfer gate region together with the electrons generated by the incident light in the photodiode, and is a source follower buffer amplifier Appears as output through. Since the output generated by such a defect appears in addition to the output from the incident light, it causes an image defect called a white spot on the screen.
US Pat. No. 6,730,899 US Pat. No. 6,714,241 US Pat. No. 6,649,950

  The present invention has been devised to solve the above problems, and the object of the present invention is to suppress the generation of dark current caused by interface defects of the silicon substrate in the photodiode region constituting the unit pixel. Thus, a CMOS image sensor capable of improving charge transfer characteristics is provided.

  Another object of the present invention is to provide a method of manufacturing a CMOS image sensor that can easily implement a configuration for suppressing generation of dark current caused by an interface defect of a silicon substrate in a photodiode region constituting a unit pixel. That is.

  In order to achieve the above object, a CMOS image sensor according to a first aspect of the present invention includes a first conductivity type photodiode formed on a semiconductor substrate from a surface thereof to a first depth, the photodiode on the photodiode, A second conductivity type HAD region opposite to the first conductivity type formed from the surface of the semiconductor substrate to a second depth shallower than the first depth; and on the HAD region, the second conductivity type HAD region from the surface of the semiconductor substrate. And a surface diffusion region of the first conductivity type formed to a third depth shallower than the depth. A transfer gate is formed in the vicinity of the photodiode, and a first channel region of the second conductivity type is formed under the transfer gate. A first conductive type floating diffusion region is formed so as to be spaced apart from the photodiode with the first channel region interposed therebetween. A second channel region of the first conductivity type is formed on the surface of the semiconductor substrate, isolated from the photodiode, and connected to the surface diffusion region and the floating diffusion region on the first channel region. ing. As an example, the surface diffusion region is formed to be the same as the second channel region or shallower than the second channel region.

In order to achieve the above object, a CMOS image sensor according to the second aspect of the present invention is formed on an N-type photodiode formed on a semiconductor substrate and on the surface of the semiconductor substrate on the N-type photodiode. A P ⁺ type region, and an N ⁻ type surface diffusion region formed on the surface of the semiconductor substrate on the P ⁺ type region. A transfer gate is formed in the vicinity of the N-type photodiode, and a P ⁻ type channel region is formed under the transfer gate. An N ⁺ type floating diffusion region is formed so as to be separated from the N type photodiode across the P ⁻ type channel region. The P ^- on type channel region, wherein the semiconductor substrate surface the N-type photodiode is isolated, the N ^- N as the mold surface diffusion region and the N ⁺ -type floating diffusion region is connected ^- -type channel region Is formed.

  In order to achieve the above object, a CMOS image sensor according to a third aspect of the present invention includes a CMOS control circuit, a transistor region including at least a floating diffusion region, a transfer transistor and a source follower buffer amplifier, and a photodiode region. Includes a plurality of active pixels. Each of the active pixels includes an N-type photodiode formed in the photodiode region, a P-type HAD region formed on the N-type photodiode, and a P-type first that constitutes the transfer transistor. An N-type second channel region formed on the surface of the transistor region on the first channel region so as to be isolated from the channel region and connected to the floating diffusion region; The semiconductor device includes an N-type surface diffusion region formed on the surface of the semiconductor substrate on the HAD region so as to be connected to the second channel region and completely isolated from other adjacent active pixels. .

  In the method of manufacturing a CMOS image sensor according to the first aspect of the present invention for achieving the other object, the first channel region of the first conductivity type is formed in the vicinity of the boundary between the photodiode region and the transistor region of the semiconductor substrate. . A second channel region of a second conductivity type opposite to the first conductivity type is formed on the surface of the semiconductor substrate on the first channel region. A first gate insulating layer and a transfer gate stacked thereon are formed on the second channel region. A first conductivity type HAD region is formed on the surface of the semiconductor substrate in the photodiode region. A second conductivity type photodiode isolated from the second channel region is formed in the photodiode region. A surface diffusion region of the second conductivity type is formed on the surface of the semiconductor substrate on the HAD region so as to be connected to the second channel region. A floating diffusion region of a second conductivity type separated from the photodiode with the second channel region interposed therebetween is formed on the semiconductor substrate so as to be connected to the second channel region.

In order to achieve the other object, in the method of manufacturing a CMOS image sensor according to the second aspect of the present invention, a P ^- type first channel region is formed in the vicinity of the boundary between the photodiode region and the transistor region of the semiconductor substrate. Form. An N ⁻ -type second channel region is formed on the surface of the semiconductor substrate on the first channel region. A first gate insulating layer and a transfer gate stacked thereon are formed on the second channel region. A P ⁺ type HAD region is formed on the surface of the semiconductor substrate in the photodiode region. In the photodiode region, an N-type photodiode is formed adjacent to the first channel region and isolated from the second channel region. An N ⁻ type surface diffusion region is formed on the surface of the semiconductor substrate on the HAD region so as to be connected to the second channel region. An N ⁺ type floating diffusion region connected to the second channel region is formed on the opposite side of the photodiode across the first channel region.

According to another aspect of the present invention, there is provided a method of manufacturing a CMOS image sensor according to the second aspect of the present invention. The CMOS image sensor includes a plurality of transistors each including at least a floating diffusion region, a transistor region including a transfer transistor and a source follower buffer amplifier, An image sensor with active pixels is manufactured. For this purpose, a P ⁺ type HAD region is first formed in the photodiode region. An N-type photodiode is formed below the HAD region in the photodiode region. An N ⁻ type surface diffusion region separated for each active pixel is formed on the surface of the semiconductor substrate on the HAD region.

The CMOS image sensor according to the present invention includes an N ⁻ type surface diffusion region formed shallowly from the surface of the semiconductor substrate on the HAD region in the photodiode region of the unit pixel. The N ⁻ type surface diffusion region is connected to the N ⁻ type channel region of the transfer transistor, and the charge generated by the interface defect in the photodiode region and in the vicinity thereof is transferred to the transfer gate region and the reset by the potential difference. Since the power supply terminal is passed through the gate region to the connected V _DD region, it is not output to the source follower buffer amplifier. Therefore, no image defect is caused. According to the present invention, it is possible to fundamentally eliminate the possibility of white spot generation due to an interface defect of a substrate.

The CMOS image sensor according to the present invention includes an N ⁻ type surface diffusion region formed shallowly from the surface of the semiconductor substrate on the HAD region in the photodiode region of the unit pixel. The N ⁻ type surface diffusion region is connected to the N ⁻ type channel region of the transfer transistor, and the charge generated by the interface defect in the photodiode region and in the vicinity thereof is transferred to the transfer gate region and the reset gate by the potential difference. By passing the power supply terminal to the V _DD region to which the power supply terminal is connected through the region, the signal is not output to the source follower buffer amplifier. Therefore, no image defect is caused. According to the present invention, it is possible to fundamentally remove the possibility of white spots due to interface defects on the substrate.

  The following exemplary embodiments can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the accompanying drawings, the size or thickness of a film or region is exaggerated for clarity.

FIG. 1 is a block diagram of a CIS according to the present invention.
Referring to FIG. 1, the CIS 10 includes an active pixel array region 20 and a CMOS control circuit 30 formed on a circuit board. The active pixel array region 20 includes a plurality of unit pixels 22 arranged in a matrix. The CMOS control circuit 30 positioned around the active pixel array region 20 includes a plurality of CMOS transistors (not shown), and provides a constant signal to each unit pixel 22 of the active pixel array region 20. On the other hand, the output signal is controlled.

FIG. 2 is an equivalent circuit diagram of the unit pixel 22 of FIG.
Referring to FIG. 2, the unit pixel 22 includes a photodiode PD that generates light charges when light is applied thereto, a transfer transistor Tx that transports charges generated by the photodiode PD to a floating diffusion region FD, A reset transistor Rx that periodically resets the charge stored in the floating diffusion region FD, and a drive transistor Dx that functions as a source follower buffer amplifier to buffer a signal due to the charge charged in the floating diffusion region FD. And a select transistor Sx that performs switching and addressing for selecting the unit pixel 22. In FIG. 2, “RS” is a signal applied to the gate of the reset transistor Rx, and “TG” is a signal applied to the gate of the transfer transistor Tx.

  FIG. 2 illustrates a circuit configuration of a unit pixel including one photodiode PD and four MOS transistors Tx, Rx, Dx, and Sx. However, the present invention is not limited to this, and any circuit may be used as long as it includes a unit pixel including at least three transistors and photodiodes each including at least a transfer transistor and a source follower buffer amplifier in a transistor region. It is also applicable to.

FIG. 3 is a cross-sectional view illustrating a main configuration of a CIS according to a preferred embodiment of the present invention. FIG. 3 is a cross-sectional view showing a partial configuration of the unit pixel 22 of FIG.
Referring to FIG. 3, the CIS according to the preferred embodiment of the present invention includes a semiconductor substrate 100 having a photodiode region and a transistor region. As a preferred example, the semiconductor substrate 100 is made of a silicon substrate. An N-type photodiode 142 is formed in the photodiode region of the semiconductor substrate 100. A P ⁺ -type HAD (Hole-Accumulation Diode) region 140 is formed on the N-type photodiode 142 in the vicinity of the surface of the semiconductor substrate 100. The HAD region 140 is formed to reduce the dark current on the surface of the silicon substrate where many dangling bonds exist in the photodiode region. That is, among the electron-hole pairs thermally generated by dangling bonds on the surface of the semiconductor substrate 100, the holes spread to the grounded substrate through the HAD region 140, and the electrons become holes in the process of spreading to the HAD region 140. And recombine and disappear. Accordingly, the dark current can be reduced by reducing the accumulation of thermally generated electrons in the N-type photodiode 142.

An N ⁻ type surface diffusion region 144 having a relatively shallow depth is formed on the surface of the semiconductor substrate 100 on the HAD region 140.
In the transistor region of the semiconductor substrate 100, a transfer transistor Tx for transferring charges generated by the N-type photodiode 142 to the N ⁺ -type floating diffusion region 152 is formed. A reset transistor Rx is formed adjacent to the transfer transistor Tx. A floating diffusion region 152 and a drain region 154 are formed on both sides of the reset gate 134 of the reset transistor Rx.

A P ^- type first channel region 112 is formed under the transfer gate 132 of the transfer transistor Tx. An N ⁻ -type second channel region 114 is formed on the surface of the semiconductor substrate 100 on the first channel region 112 at a depth shallower than the first channel region 112. The first channel region 112 is formed shallower than the N-type photodiode 142, and the second channel region 114 is formed shallower than the HAD region 140 and the floating diffusion region 152. The N ⁻ type surface diffusion region 144 formed in the photodiode region is the same as or shallower than the second channel region 114. In FIG. 3, the N ⁻ type surface diffusion region 144 is formed shallower than the second channel region 114. The N ⁻ type surface diffusion region 144 is connected to the second channel region 114, but is completely isolated from other adjacent active pixels.

The floating diffusion region 152 is separated from the N-type photodiode 142 with the first channel region 112 and the second channel region 114 interposed therebetween. Here, the second channel region 114 is completely isolated from the N-type photodiode 142 and is connected to the N ⁺ -type floating diffusion region 152. That is, between the N-type photodiode 142 and the N-type photodiode 152, a P-type ion implantation region, that is, the P ⁺ -type HAD region 140 and the P ⁻ -type first channel region 112. Accordingly, the second channel region 114 and the N-type photodiode 142 can be completely isolated from each other.

The operation of the CIS according to the present invention configured as described above will be described as follows.
First, when light is incident on the photodiode 142 as a light receiving unit from the outside, the photodiode 142 generates electrons proportional to the sensed light quantity. The electric charge generated by the photodiode 142 is constrained to the photodiode region by the gate barrier of the transfer transistor Tx. When the reset transistor Rx is turned off and the transfer transistor Tx is turned on, the signal charge accumulated in the photodiode 142 is transmitted to the floating diffusion region 152 in a higher potential state through the transfer gate, and thereafter the transfer gate. When is turned off and returned to a low potential state, the photodiode is depleted.

Thereafter, charges generated in the photodiode 142 due to light incident on the light receiving portion for a predetermined accumulation time are accumulated in a depletion region of the photodiode 142.
Thereafter, when the reset signal RS is applied to the reset gate 134 of the reset transistor Rx and the reset gate is turned on, the floating diffusion region 152 is charged to the V _DD level, the gate potential barrier of the reset transistor Rx is lowered, and the floating diffusion The charge charged in the region 152 is released to the outside. As a result, the floating diffusion region 152 is in a state where charge can be received. When the reset gate 134 is turned off, the gate potential barrier of the reset transistor Rx is restored to the original state. At this time, the output voltage OUT of the CIS is lowered by a predetermined value by feed-through and coupling, and the floating diffusion region 152 becomes a feedthrough level slightly lower than the normal _VDD level. At this time, the potential level of the floating diffusion region 152 is detected as a primary sampling voltage.

  Next, when the transfer signal TG is applied to the gate of the transfer transistor Tx, the potential barrier of the transfer gate 132 is lowered, and as a result, the charge generated in the photodiode 142 passes through the channel region under the transfer gate 132 to the floating diffusion region 152 side. Move to. As a result, electric charges are charged in the floating diffusion region 152, and the output voltage decreases. At this time, the potential level in the floating diffusion region 152 changed in proportion to the amount of charge transmitted to the floating diffusion region 152 is detected as a secondary sampling voltage. Here, the output signal of the CIS is defined by the difference between the primary sampling voltage and the secondary sampling voltage.

In the CIS according to the present invention shown in FIG. 3, the first channel region 112 formed below the transfer gate 132 is a potential barrier between the N-type photodiode 142 and the N ⁺ -type floating diffusion region 152. P-type impurities are ion-implanted to enable the role. When a high clock is applied to the transfer gate 132, the first channel region 112 has a low concentration of impurities in order to facilitate signal electron transmission from the N-type photodiode 142 to the floating diffusion region 152. Is formed by ion implantation. An N ⁻ -type second channel region 114 formed on the surface of the semiconductor substrate 100 below the transfer gate 132 is formed to be connected to the floating diffusion region 152. A potential gradient is formed in which the potential increases as it approaches the floating diffusion region 152, and as a result, electrons thermally generated on the surface of the semiconductor substrate 100 below the transfer gate 132 are drifted toward the floating diffusion region 152. sell. Further, an N ⁻ type surface diffusion region 144 formed on the surface of the semiconductor substrate 100 in the photodiode region is formed to be connected to the second channel region 114, whereby the semiconductor substrate 100 in the photodiode region is formed. As a result, a gradient is formed in which the potential increases as it approaches the transfer gate 132, and as a result, in the photodiode region, the charge generated by the interface defect is generated in the second channel region 114 even at a position relatively far from the transfer transistor Tx. Through the floating diffusion region 152.

The potential of the floating diffusion region 152 becomes V _DD while the reset transistor Rx is turned on. Therefore, during the reset operation, in the N ⁻ -type second channel region 114 formed shallowly on the surface of the semiconductor substrate 100 below the transfer gate 132, electrons are swept out to the floating diffusion region 152 by the potential of the floating diffusion region 152. To be fully depleted. Next, electrons generated by interface defects in the vicinity of the surface of the semiconductor substrate in the photodiode region and electrons generated thermally at the surface of the semiconductor substrate 100 below the transfer gate 132 are each changed to an arrow by the potential of the floating diffusion region 152. As indicated by “A”, “B”, and “C”, the surface diffusion region 144 and the second channel region 114 are swept to the floating diffusion region 152. At this time, since the P ⁻ type first channel region 112 is formed under the second channel region 114, a potential barrier due to the first channel region 112 exists on the N type photodiode 142 side. To do. Therefore, electrons in the surface diffusion region 144 and the second channel region 114 are not diffused into the N-type photodiode 142. The electrons swept into the floating diffusion region 152 are transferred to the V _DD region when the reset transistor Rx is on and are not output to the source follower buffer amplifier. Therefore, image defects caused by noise or dark current generated by electrons generated by interface defects on the surface of the semiconductor substrate 100 under the photodiode region and the transfer gate 132 can be efficiently suppressed.

4A is a diagram illustrating a potential profile in a channel region under the photodiode 142 and the transfer gate 132 in the CIS structure according to the present invention illustrated in FIG.
As shown in FIG. 4A, the potential profile in the channel region below the transfer gate 132 forms a potential gradient in which the potential increases as it approaches the floating diffusion region 152, and between the second channel region 114 and the photodiode 142. In this case, a potential barrier is formed. That is, by forming the second channel region 114 on the surface of the semiconductor substrate 100 below the transfer gate 132, electrons that are thermally generated on the surface of the semiconductor substrate 100 are generated by the potential of the floating diffusion region 152. The electrons generated by the P ⁻ type first channel region 112 and thermally generated in the second channel region 114 by the potential barrier are not diffused into the N type photodiode 142.

  FIG. 4B is a diagram showing a potential profile in the surface of the semiconductor substrate 100 in the photodiode region and the channel region below the transfer gate 132 in the CIS structure according to the present invention shown in FIG.

As shown in FIG. 4B, in the potential profile on the surface of the semiconductor substrate 100 in the photodiode region, a potential gradient is formed such that the potential increases as it approaches the transfer gate region. That is, by forming the N ⁻ -type surface diffusion region 144 on the surface of the semiconductor substrate 100 on the HAD region 140, electrons generated by interface defects on the surface of the semiconductor substrate 100 are generated by the potential of the floating diffusion region 152. It is swept out to the floating diffusion region 152 through the two-channel region 114. When the reset transistor Rx is turned on again, they move to the V _DD region and are not output to the source follower buffer amplifier.

FIG. 4C is a diagram showing a potential profile in the substrate surface of the photodiode region and the channel region under the transfer gate in the CIS according to the prior art as a control example. FIG. 4C is a diagram showing a potential profile in a CIS structure having the same configuration as FIG. 3 except that the N ⁻ type surface diffusion region 144 is not formed.
Referring to FIG. 4C, the potential profile at the surface of the semiconductor substrate 100 in the photodiode region is constant without changing over the entire photodiode region. Therefore, electrons generated due to interface defects on the substrate in the photodiode region tend to flow into the photodiode 142, and eventually cause image defects such as noise or dark current.

  5A to 5H are cross-sectional views illustrating a CIS manufacturing method according to a preferred embodiment of the present invention according to a process sequence. In this embodiment, a method for manufacturing a CIS as described with reference to FIG. 3 will be described as an example. 5A to 5H, the same reference numerals as those in FIG. 3 represent the same members.

  Referring to FIG. 5A, an element isolation film 102 is formed on a semiconductor substrate 100 by, for example, a trench element isolation method to define an active region of the semiconductor substrate 100, and then a P well for forming an NMOS transistor in the transistor region. (Not shown). In order to form the device isolation film 102, a LOCOS (local oxidation of silicon) method may be used.

Referring to FIG. 5B, after forming a first mask pattern 110 that exposes a first region 104 where a transfer transistor is to be formed in the transistor region of the semiconductor substrate 100, the first mask pattern 110 is used as an ion implantation mask. As a result, P ⁻ ions are implanted to form a first channel region 112 doped with P ⁻ ions in the semiconductor substrate 100. At this time, when boron (B) ions are used for the P ⁻ ion implantation, the implantation energy is, for example, about 30 keV, and the dose amount is about 1 × 10 ¹² / cm ² .

Referring to FIG. 5C, N ⁻ ions are implanted using the first mask pattern 110 as an ion implantation mask to form a second channel region 114 doped with N ⁻ ions in the semiconductor substrate 100. Here, it is illustrated and described that the first mask pattern 110 is used as an ion implantation mask when forming the second channel region 114, but the present invention is not limited thereto, and the first channel region 112 and the second channel region 114 are not limited thereto. Different ion implantation masks may be used when forming the channel region 114. At this time, when arsenic (As) ions are used for the N ⁻ ion implantation, the implantation energy is, for example, about 30 keV, the dose is about 5 × 10 ¹¹ / cm ^2, and the second channel region is formed. 114 is formed shallower than the first channel region 112 on the surface of the semiconductor substrate 100.

  Referring to FIG. 5D, after forming an insulating layer on the semiconductor substrate 100 and forming a conductive layer, for example, a doped polysilicon layer, patterning the conductive layer and the insulating layer, A gate electrode necessary for forming an image sensor is formed in the transistor region of the semiconductor substrate 100. In this example, only the transfer gate 132 formed on the first gate insulating film 122 and the reset gate 134 formed on the second gate insulating film 124 are illustrated. In this example, although not shown, a necessary gate electrode is formed on the semiconductor substrate 100 according to the type of CIS to be implemented. For example, when an image sensor having a unit pixel (see FIG. 2) composed of one photodiode PD and four MOS transistors Tx, Rx, Dx, Sx is to be formed, four MOS transistors Tx, Rx , Dx, and Sx are formed in any of the transistor regions.

Referring to FIG. 5E, a P ⁺ ion is implanted into the photodiode region using a mask pattern (not shown) that selectively exposes only the photodiode region of the semiconductor substrate 100 as an ion implantation mask. A HAD region 140 doped with P ⁺ ions is formed on the surface of the semiconductor substrate 100. Here, the HAD region 140 is formed deeper than the second channel region 114 from the surface of the semiconductor substrate 100. For this purpose, for example, when boron difluoride (BF ₂ ) is used for ion implantation for forming the HAD region 140, the implantation energy is, for example, about 50 keV, and the dose is about 5 ×. It can be 10 ¹³ / cm ² .

Referring to FIG. 5F, a mask pattern (not shown) that selectively exposes only the photodiode region of the semiconductor substrate 100 is used as an ion implantation mask, and N ions are implanted into the photodiode region. An N-type photodiode 142 positioned deeper than the HAD region 140 in the semiconductor substrate 100 is formed. At this time, a part of the N-type photodiode 142 can be overlapped with the transfer gate 132 in a region having a predetermined width W by using a tilted ion implantation method when implanting the N ions. Here, as an ion implantation mask used when forming the N type photodiode region 142, a mask pattern used as an ion implantation mask when forming the P ⁺ type HAD region 140 can be used. Use a mask pattern. When As ions are used for ion implantation for forming the photodiode region 142, the implantation energy is, for example, about 400 keV, and the dose amount is about 1.7 × 10 ¹² / cm ^2. it can.

Referring to FIG. 5G, N ⁻ ions are implanted into the photodiode region using a mask pattern (not shown) that selectively exposes only the photodiode region of the semiconductor substrate 100 as an ion implantation mask. An N ⁻ type surface diffusion region 144 is formed in the semiconductor substrate 100, which is shallower than the HAD region 140 and located near the surface of the semiconductor substrate 100. Here, the mask pattern used as the ion implantation mask when forming the P ⁺ type HAD region 140 and the N type photodiode region 142 can be used as the ion implantation mask used when forming the surface diffusion region 144. Preferably, it is desirable to use different mask patterns. When As ions are used for ion implantation for forming the surface diffusion region 144, the implantation energy may be about 20 keV and the dose may be about 3 × 10 ¹¹ / cm ² , for example. The surface diffusion region 144 is formed to be connected to the second channel region 114 while being isolated from other adjacent pixels by the device isolation layer 102.

Referring to FIG. 5H, an N ⁺ type impurity is ion-implanted into the active region of the transistor region using a predetermined ion implantation mask, and is floated in the active region between the transfer gate 132 and the reset gate 134. A diffusion region 152 is formed, and a drain region 154 is formed in an active region between the reset gate 134 and the gate (not shown) of the drive transistor Dx (see FIG. 1). The floating diffusion region 152 and the drain region 154 are formed deeper than the second channel region 114 from the surface of the semiconductor substrate 100.

When As ions are used for ion implantation for forming the floating diffusion region 152 and the drain region 154, the implantation energy is, for example, about 40 keV, and the dose amount is about 3 × 10 ¹⁵ / cm ² . can do.
After the floating diffusion region 152 is formed, the second channel region 114 is connected to the floating diffusion region 152.
Thereafter, necessary wiring formation steps are performed by a normal method to complete the CIS.

  Although the present invention has been described in detail based on the preferred embodiments, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made by those skilled in the art within the technical idea and scope of the present invention. .

  It can be applied not only to household products such as digital cameras and mobile phones, but also to image sensors in various fields, such as endoscopes used in hospitals and satellite telescopes.

It is a block diagram of CIS by this invention. FIG. 3 is an equivalent circuit diagram of a unit pixel of CIS according to the present invention. 1 is a cross-sectional view illustrating a configuration of main parts of a CIS according to a preferred embodiment of the present invention. 5 is a diagram illustrating a potential profile in a channel region under a photodiode and a transfer gate in the CIS according to the present invention. 6 is a diagram showing a potential profile in a channel region under a substrate surface of a photodiode region and a transfer gate under a CIS having a configuration in which an N ⁻ type surface diffusion region is formed in the photodiode region according to the present invention. FIG. 5 is a diagram showing a potential profile in a conventional technique of CIS in a substrate region of a photodiode region and a channel region under a transfer gate, in a case where there is no N ⁻ type surface diffusion region in the photodiode region. . FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a CIS according to a preferred embodiment of the present invention in order of processes.

Explanation of symbols

10 CIS
20 active pixel array region 22 unit pixel 30 CMOS control circuit

Claims (30)

A first conductivity type photodiode formed on a semiconductor substrate from its surface to a first depth;
A second conductivity type HAD (Hole-Accumulation Diode) region opposite to the first conductivity type formed on the photodiode from the surface of the semiconductor substrate to a second depth shallower than the first depth;
A surface diffusion region of the first conductivity type formed from the surface of the semiconductor substrate to a third depth shallower than the second depth on the HAD region;
A transfer gate formed in the vicinity of the photodiode;
A first channel region of the second conductivity type formed under the transfer gate;
A floating diffusion region of a first conductivity type separated from the photodiode across the first channel region;
A second channel region of the first conductivity type formed on the surface of the semiconductor substrate on the first channel region so as to be isolated from the photodiode and connected to the surface diffusion region and the floating diffusion region; A CMOS image sensor comprising:   2. The CMOS image sensor according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type.   The CMOS image sensor of claim 1, wherein the second channel region has a lower doping concentration than the floating diffusion region.   2. The CMOS image sensor according to claim 1, wherein the second channel region is formed shallower than the HAD region and the floating diffusion region.   2. The CMOS image sensor according to claim 1, wherein the surface diffusion region is formed to be the same as the second channel region or shallower than the second channel region.   The CMOS image sensor of claim 1, wherein the first channel region has a lower doping concentration than the HAD region.   The CMOS image sensor according to claim 1, wherein the first channel region is formed shallower than the photodiode. An N-type photodiode formed on a semiconductor substrate;
A P ⁺ type region formed on the surface of the semiconductor substrate on the N type photodiode;
An N ⁻ type surface diffusion region formed on the surface of the semiconductor substrate on the P ⁺ type region;
A transfer gate formed in the vicinity of the N-type photodiode;
A P ^- type channel region formed under the transfer gate;
An N ⁺ type floating diffusion region spaced from the N type photodiode across the P ⁻ type channel region;
Wherein the N-type photodiode is isolated, the N ^- type surface diffusion region and the N ⁺ -type floating the diffusion as the region is connected P ^- -type said upper channel region formed on a semiconductor substrate surface of N ^- A CMOS image sensor comprising: a mold channel region; 9. The CMOS image sensor according to claim 8, wherein the N ⁻ type channel region is formed shallower than the P ⁺ type region and the N ⁺ type floating diffusion region. The N ^- type surface diffusion region, said N ^- type channel region equal to or, the N ^- CMOS image sensor according to claim 8, characterized in that it is shallower than type channel region. 9. The CMOS image sensor according to claim 8, wherein the P ^- type channel region is formed shallower than the N-type photodiode. A CMOS control circuit;
A plurality of active pixels each having at least a floating diffusion region, a transistor region comprising a transfer transistor and a source follower buffer amplifier, and a photodiode region, each active pixel comprising:
An N-type photodiode formed in the photodiode region;
A P-type HAD region formed on the N-type photodiode;
A P-type first channel region constituting the transfer transistor;
An N-type second channel region formed on the surface of the transistor region on the first channel region so as to be isolated from the photodiode and connected to the floating diffusion region;
An N type surface diffusion region formed on the surface of the semiconductor substrate on the HAD region so as to be connected to the second channel region and completely isolated from other adjacent active pixels; A CMOS image sensor comprising:   The CMOS image sensor according to claim 12, wherein the second channel region and the photodiode are separated from each other with a P-type ion implantation region interposed therebetween.   The CMOS image sensor according to claim 12, wherein the N-type surface diffusion region is formed to be the same as or shallower than the second channel region.   The CMOS image sensor of claim 12, wherein each of the surface diffusion region and the second channel region has a lower doping concentration than the floating diffusion region.   The CMOS image sensor of claim 12, wherein the second channel region is formed shallower than the HAD region and the floating diffusion region.   The CMOS image sensor of claim 12, wherein the first channel region has a lower doping concentration than the HAD region.   The CMOS image sensor according to claim 1, wherein the first channel region is formed shallower than the photodiode. Forming a first channel region of a first conductivity type in the vicinity of a boundary between a photodiode region and a transistor region of a semiconductor substrate;
Forming a second channel region of a second conductivity type opposite to the first conductivity type on the surface of the semiconductor substrate on the first channel region;
Forming a first gate insulating layer and a transfer gate stacked thereon on the second channel region;
Forming a first conductivity type HAD region on the surface of the semiconductor substrate from the photodiode region;
Forming a second conductivity type photodiode isolated from the second channel region in the photodiode region;
Forming a surface diffusion region of the second conductivity type on the surface of the semiconductor substrate on the HAD region so as to be connected to the second channel region;
Forming a second conductive type floating diffusion region spaced apart from the photodiode across the second channel region on the semiconductor substrate so as to be connected to the second channel region. A manufacturing method of a CMOS image sensor.   The method of claim 19, wherein the first conductivity type is a P-type and the second conductivity type is an N-type.   20. The method of claim 19, wherein the surface diffusion region and the second channel region are formed to have a lower doping concentration than the floating diffusion region.   The method of claim 19, wherein the second channel region is formed shallower than the HAD region and the floating diffusion region.   20. The method of claim 19, wherein the surface diffusion region is formed to be the same as the second channel region or shallower than the second channel region.   The method of claim 19, wherein the first channel region has a lower doping concentration than the HAD region.   The method of claim 19, wherein the first channel region is formed shallower than the photodiode. Forming a P ^- type first channel region in the vicinity of the boundary between the photodiode region and the transistor region of the semiconductor substrate;
Forming an N ^- type second channel region on a surface of the semiconductor substrate on the first channel region;
Forming a first gate insulating layer and a transfer gate stacked thereon on the second channel region;
Forming a P ⁺ -type HAD region from the photodiode region to the surface of the semiconductor substrate;
Forming an N-type photodiode in the photodiode region adjacent to the first channel region and isolated from the second channel region;
Forming an N ⁻ type surface diffusion region on the surface of the semiconductor substrate on the HAD region so as to be connected to the second channel region;
Forming an N ⁺ -type floating diffusion region connected to the second channel region on the opposite side of the photodiode across the first channel region. .   27. The method of claim 26, wherein the first channel region is formed shallower than the photodiode.   27. The method of claim 26, wherein the second channel region is formed shallower than the HAD region.   27. The method of claim 26, wherein the surface diffusion region is formed to be the same as the second channel region or shallower than the second channel region. In a method of manufacturing an image sensor comprising at least a floating diffusion region, a transistor region including a transfer transistor and a source follower buffer amplifier, and a plurality of active pixels each having a photodiode,
Forming a P ⁺ type HAD region in the photodiode region;
Forming an N-type photodiode under the HAD region in the photodiode region;
Forming an N ^- type surface diffusion region separated for each active pixel on the surface of the semiconductor substrate on the HAD region.

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