JP2005333529A - Video signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an image which does not have any flicker and sticking at upper and lower ends of a video image, when the underscan display of the video image converted from an interlace scanning signal to a progressive scanning signal by the use of a video image in a field is performed on a liquid display panel. <P>SOLUTION: Two video image delay means and a control means are provided for generating write and read control signals corresponding to one line of desired upper and lower ends. An effective image corresponding to each one line of the upper and lower ends of a video image is held, and the video image is outputted at the same position after being delayed by one field. Moreover, only the upper and lower ends of the video image are switched over to video images delayed by one field and are outputted by a selection means. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video signal processing apparatus for converting interlaced scanning video signals into progressive scanning video signals.

  As a conventional video signal processing apparatus for converting an interlace signal into a progressive signal, for example, there is one as disclosed in Patent Document 1. FIG. 8 is a block diagram showing an example of a conventional video signal processing apparatus.

  In FIG. 8, an input terminal 801 is an input terminal for inputting an interlaced scanning video signal. The first field memory 802 and the second field memory 803 are field memories that delay interlaced video signals for one field period, and are connected in series. An interpolation circuit 804 is an interpolation circuit that generates an interpolation scanning line from pixels in the same field using the video signal output from the field memory 802.

  The intermediate value selection circuit 805 compares the level of the pixel of the video signal output from the field memory 803 with the level of the pixel of the video signal output from the interpolation circuit 804 and the level of the pixel of the video signal from the input terminal 801. It is a circuit that selects every pixel cycle. The double speed conversion units 806 and 807 are memories for storing the input video signal, and compressing the horizontal scanning period of the video signal to ½ and outputting the double rate storage content at the time of reading.

  The double speed conversion unit 806 converts the output of the intermediate value selection circuit 805, and the double speed conversion unit 807 converts the output of the field memory 802. The selection circuit 808 is a circuit that switches the outputs of the double speed conversion unit 806 and the double speed conversion unit 807 for each line cycle and generates a video signal for sequential scanning via the output terminal 809.

  The operation of the conventional video signal processing apparatus configured as described above will be described. In FIG. 8, when a video signal for interlaced scanning is input to the input terminal 801, the field memory 802 and the field memory 803 are respectively delayed by one field period. A video signal delayed by two fields, that is, one frame period is output from the field memory 803. The output of the field memory 802 is input to the interpolation circuit 804, where interpolation processing is performed from the pixels in the same field, and an interpolation scanning line is generated.

  The intra-field interpolation scanning line generated by the interpolation circuit 804, the output of the field memory 803 for inter-field interpolation, and the video signal at the input terminal 801 are input to the intermediate value selection circuit 805. The intermediate value selection circuit 805 selects an input pixel having an intermediate level pixel value from the three input pixels, and outputs the selected pixel as an interpolation scanning line pixel.

  The interpolation scanning line thus obtained by the intermediate value selection circuit 805 and the actual scanning line that is the output of the field memory 802 are input to the double speed conversion unit 806 and the double speed conversion unit 807, respectively. The double speed conversion unit 806 and the double speed conversion unit 807 read the pixel data of the scanning line written at a normal speed at a double speed. The selection circuit 808 alternately switches the outputs of the double speed conversion unit 806 and the double speed conversion unit 807 in one line cycle, and outputs the sequentially scanned video signal from the output terminal 809.

  In the configuration of the interpolation circuit 804 that generates the intra-field interpolation scanning line, for example, an interpolation scanning line having an average value of the upper and lower lines in the same field is output. The intermediate value selection circuit 805 compares the three input pixel values and outputs a signal that is an intermediate value.

  FIG. 9 shows how interpolation is performed when the intermediate value is output. FIG. 9A shows a case where the (N-1) field has an intermediate value, and the pixel value of the B pixel is interpolated at the interpolation point (black circle) of the N field. FIG. 9B shows a case where the N field has an intermediate value, and the average value of the E pixel and the F pixel is interpolated at the interpolation point (black circle) of the N field. Further, FIG. 9C shows a case where the (N + 1) field has an intermediate value, and the pixel value of the I pixel is interpolated at the interpolation point (black circle) of the N field.

As described above, by generating an interpolation scanning line by taking an intermediate value of three adjacent fields, it is possible to perform scanning line interpolation processing with a good image quality with a simple configuration regardless of a moving image / still image.
JP-A-9-224223

  However, in the configuration as described above, since the field for generating the current pixel and the interpolated pixel value uses N fields that are delayed by one field with respect to the current field (N + 1), the scanning lines are sequentially created. Since the video is delayed by one field with respect to the audio signal, the relationship between the audio and the video does not match in editing at the broadcasting station or the like, and the CRT display device for the broadcasting station that displays the interlaced signal itself has not received the video. The scene change (switching) differs by one field, which hinders video signal management.

  In consideration of this, when used in an application where delay is a problem, the user can select double-speed conversion display by writing twice in a field where no field delay occurs. However, in this case, there has been a problem that image sticking occurs at the flicker generation portions at the upper and lower ends of the image.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a video signal processing apparatus capable of performing scanning line interpolation processing with good image quality without causing image burn-in at the upper and lower ends of a video with a simple configuration.

  In addition, the present invention automatically detects the upper and lower end portions of an image when the image effective area is smaller than a predetermined width, so that the upper and lower end portions of the image are not always burned. An object of the present invention is to provide a video signal processing apparatus capable of performing scanning line interpolation.

  In order to achieve the above object, according to the present invention, when an interlaced scanning video signal is input, a double speed converting means for converting a video in a field into a sequentially scanned video, and one of outputs of the double speed converting means. First and second video delay means for holding and delaying video signals for lines; field discrimination means for discriminating a field of a video signal for interlace scanning from a horizontal synchronization signal and a vertical synchronization signal; Control signal generating means for outputting write and read control signals to the video delay means, and switching signal generating means for outputting a control signal for switching the video signal from the output of the field discriminating means and the output of the control signal generating means, Selecting means for selecting and outputting either the double speed conversion means or the first and second video delay means according to the output of the switching signal generating means; And it is characterized in that there was example.

  Further, in the present invention, the control signal generating means is set from the outside, a control signal output from the field discriminating means, a double horizontal synchronizing signal obtained by converting the inputted horizontal synchronizing signal to a double frequency, and the like. The video signal for one line at each of the upper and lower ends of the effective video area of the video signal converted into the progressive scan according to the set value is held in the first and second video delay means to delay the video by one field. A control signal is generated.

  The present invention also includes a double speed conversion means for converting a video in a field to a sequentially scanned video when an interlaced video signal is input, and holds the video signal for one line of the output of the double speed conversion means. First and second video delay means for delaying, field discrimination means for discriminating the field of the interlaced video signal from the horizontal synchronization signal and the vertical synchronization signal, and the upper and lower ends of the effective video area of the video signal, respectively From the image area discriminating means for detecting the position, the control signal generating means for outputting the write and read control signals to the first and second video delay means, the output of the field discriminating means and the output of the control signal generating means A switching signal generating means for outputting a control signal for switching the video signal; and the double speed converting means, the first and the second speed converting means by the output of the switching signal generating means. The selected selection means for outputting one of the second image delay means is characterized in that it comprises at least.

  Further, the present invention provides the control signal generating means, wherein the video region is based on a control signal output from the field discriminating means and a double horizontal sync signal obtained by converting the input horizontal sync signal into a double frequency. The position information output from the discriminator is compared with the set values for the upper and lower ends set from the outside, and a larger value is selected for the upper end and a smaller value is selected for the lower end, and converted to sequential scanning. A video signal for one line at each of the upper and lower ends of the effective video area of the generated video signal is held in the first and second video delay means, and a control signal for delaying the video by one field is generated. It is what.

  Further, according to the present invention, the video area determination means includes an output of the field determination means, a double horizontal synchronization signal obtained by converting the input horizontal synchronization signal into a double frequency, and an output of the double speed conversion means. In the video signal, the positions of the upper end and the lower end of the effective video area are detected.

  In the present invention, two video signal delay means for delaying the video 1 line at the upper and lower ends of the video signal delay each video signal at the upper end and the lower end by one field, and only the upper and lower end portions where the flicker is generated are always fielded. Interpolation does not cause burn-in, and it is possible to obtain good image quality. Furthermore, even when the effective image area in the vertical direction changes, the upper and lower edges are always detected automatically. It is possible to prevent the occurrence of flicker in the part.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
A video signal processing apparatus according to a specific embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a block diagram of a video signal processing apparatus according to Embodiment 1 of the present invention.

  The video signal processing apparatus shown in FIG. 1 includes an input terminal 101 to which an interlaced video signal is input, an input terminal 102 to which a horizontal synchronization signal is input, and an input terminal 103 to which a vertical synchronization signal is input. Double-speed conversion that generates a progressively-scanned video image that has been converted to a double frequency in the field from the video signal input to the input terminal 101 and the horizontal synchronization signal from the input terminal 102, and outputs a horizontal synchronization signal having a double frequency. Means 104, a horizontal sync signal from input terminal 102, a field discriminating means 105 for discriminating the field of the interlaced scanning signal from the vertical sync signal from input terminal 103, and a video signal output from double speed conversion means 104 From the video delay means 106, the video delay means 107, and the double speed conversion means 104 that hold one line and delay in line units. Write to the video delay means 106, the video delay means 107 and the switching control signal generation means from the double horizontal synchronizing signal output, the control signal output from the field discrimination means 105 and the control signal for determining the upper and lower end positions set from the outside. The control signal generating means 108 for outputting the read control signal, the switching control signal generating means 109 for outputting the switching control signal from the output of the field discriminating means 105 and the output of the control signal generating means 108, and the switching control signal generating means 109 The output unit 111 includes a selection unit 110 that switches and outputs the video of the double speed conversion unit 104 and the video delay units 106 and 107, and an output terminal 111 that outputs a video signal of progressive scanning.

  Next, the operation of the video signal processing apparatus of (Embodiment 1) configured as described above will be described.

  In FIG. 1, when a video signal for interlaced scanning is input to the input terminal 101, the double speed conversion means 104 performs double speed conversion in the field, and the same data is output every two lines (written twice in the field) sequentially. A scanning video signal is output. The relationship of the video signal at this time is as shown in FIG.

  As shown in FIG. 2, when double-speed conversion is performed within a field, a line in which only one field is present at the upper and lower ends of the first field and the second field is generated. When such an image is displayed as a 16: 9 image on a 5: 4 liquid crystal display panel as shown in FIG. 3A, the liquid crystal molecules are biased and shown in FIG. 3B. Thus, when switching to 4: 3 video, burn-in occurs at the upper and lower end portions at the time of 16: 9 display.

  To prevent this, the video for one line at point A in FIG. 4 is written to the video delay means 106, the video for one line at point B is written to the video delay means 107, and the video written at the same position after one field delay. Is output.

  In the selection means 110, the video signal of the double speed conversion means 104 is output to the output terminal 111 at times other than the points A and B in FIG. 4, and the output of the video output means 106 is output to the output terminal at the point A in FIG. In addition, the output of the video output means 107 is output to the output terminal 111 at the point B in FIG. As a result, the upper and lower end portions of the image are fitted between the fields, so that flicker does not occur and the liquid crystal molecules do not deviate, so that no burn-in occurs.

  The control signal generator 108 generates the write / read control signals for the video delay means 106 and the video delay means 107, and the selection means 110 is controlled by the switching signal generator 109.

  FIG. 5 is an operation waveform diagram for explaining this operation. FIG. 5A shows a vertical synchronization signal input to the input terminal 103, FIG. 5B shows a horizontal synchronization signal input to the input terminal 102, and FIG. FIG. 5C shows an example of a horizontal synchronizing signal output from the double speed conversion means 104 and having a frequency double that of the horizontal synchronizing signal from the input terminal 102. FIG. 5D shows an example of a video signal inputted from the input terminal 101. Is shown.

  FIG. 5E shows a field discrimination signal discriminated by the field discriminator 105 based on the synchronization signals input from the input terminal 102 and the input terminal 103, and FIG. 5F shows an example for writing the upper end of the video to the video delay unit 106. 5 (g) shows a control signal for reading the upper end of the video from the video delay means 106, FIG. 5 (h) shows a control signal for writing the lower end of the video to the video delay means 107, and FIG. (I) is a control signal for reading the lower end of the video from the video delay means 107, and FIG. 5 (j) is an output of the switching control signal generating means for generating a selection signal for selecting the video signal to be output to the output terminal 111. Show.

  Field discrimination is performed by the field discrimination means 105 based on the vertical sync signal shown in FIG. 5A and the horizontal sync signal shown in FIG. This field discrimination is performed, for example, when the horizontal sync signal shown in FIG. 5B is “High” or “Low” at the falling edge of the vertical sync signal shown in FIG. In the case of FIG. 5, when the horizontal synchronization signal is “Low” at the falling portion of the vertical synchronization signal, “High” is used as the field discrimination signal, and the horizontal synchronization signal is “High” at the falling portion of the vertical synchronization signal. If there is, a “Low” control signal is output from the field discrimination means 105 as a field discrimination signal.

  In the control signal generation means 108, a write control signal and a read control signal are sent to the video delay means 106 and the video delay means 107 from the control signal output from the field discrimination means 105 and the upper and lower end position data of the video set from the outside. Is output. In the case of FIG. 5, “9” is set as the upper end and “521” is set as the lower end, and the write control signal to the video delay means 106 for delaying the video signal at the upper end is shown in FIG. e) the field discrimination signal is “High”, and the horizontal synchronization signal that is twice that in FIG. 5C from the falling edge of the vertical synchronization signal in FIG. 5A is the ninth, and the “High” control signal is output. As for the read control signal, the field discrimination signal in FIG. 5E is “Low”, and the horizontal synchronization signal that is twice that in FIG. 5C from the falling edge of the vertical synchronization signal in FIG. ”Is output.

  The write control signal to the video delay means 106 for delaying the video signal at the lower end from the video signal at the lower end is “Low” in FIG. 5E and the vertical synchronization signal in FIG. The horizontal synchronization signal doubled from the falling edge in FIG. 5C is the 521st, and a “High” control signal is output, and the read control signal is “High” in the field discrimination signal in FIG. From the falling edge of the vertical synchronizing signal in (a), the horizontal synchronizing signal which is double that in FIG. 5C is the 521st and a “High” control signal is output. As a result, a video signal delayed by one field only at the upper and lower ends is output from the video delay means 106 and the video delay means 107.

  In the switching control signal generation means 109, a field determination signal (FIG. 5 (e)) output from the field determination means 105 and a read control signal (FIG. 5 (g), FIG. 5 (i) output from the control signal generation means 108. )), A switching control signal is output. When both FIG. 5 (g) and FIG. 5 (i) are “Low”, “1” is displayed. When FIG. 5 (g) is “High”, “2” is output. When (i) in FIG. 5 is “High”, “3” is output.

  In the selection circuit 110, the output of the double speed conversion means 104 and the video delay means 106 and 107 is selected by switching according to the control signal of the switching signal generation means 109 and output to the output terminal 111.

  As described above, according to the present embodiment, only the upper and lower end portions of the video signal are delayed by one field using the video delay means, so that the flicker and liquid crystal molecule bias generated in the upper and lower end portions due to the double speed conversion in the field. Therefore, even when the display size is changed from 16: 9 to 4: 3 or the like, image sticking does not occur in the upper and lower end portions, and good image quality can be obtained.

(Embodiment 2)
Next, a video signal processing apparatus according to another embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram of the video signal processing apparatus according to the present embodiment. Components corresponding to those of the video signal processing apparatus according to (Embodiment 1) shown in FIG. The description is omitted.

  In FIG. 6, reference numeral 601 denotes a video area discriminating means for detecting the upper and lower end positions of the video from the video signal converted at double speed and the field discrimination signal, and 602 obtains the positions of the upper and lower end portions from the video area discriminating means 601 and Control signal generating means for outputting a write control signal and a read control signal to the video delay means 106 and 107 in comparison with the set upper and lower end position information.

  The operation of the video signal processing apparatus according to this embodiment having the above-described configuration will be described.

  The video region discriminating means 601 receives the sequentially scanned video signal and the horizontal synchronizing signal of double frequency from the double speed converting means 104, and receives the field detection signal from the field discriminating means 105. Based on the video signal of the double speed conversion means 104 and the output of the field discrimination means 105, the video area discrimination means 601 detects the upper end position when the field discrimination is “High” and the lower end position when it is “Low”. Is output to the control signal generating means 602.

  The control signal generating means 602 compares the upper and lower end position information from the video area discriminating means 601 with the fixed upper and lower end position information set from outside, and the upper end position information from the video area discriminating means 601 in the case of the upper end. Only when the value is larger than the upper end position information set from the outside, a write control signal and a read control signal to the video delay means 106 are generated based on the value of the video area discrimination means. In the case of the lower end, only when the lower end position information from the video area discriminating means 601 is smaller than the lower end position information set from the outside, the write control signal and the read control to the video delay means 107 based on the value of the video area discriminating means. Generate a signal. In other cases, a write control signal and a read control signal are generated based on the upper and lower end position information set from the outside.

  FIG. 7 is a diagram showing this operation. In the case where “9” as the upper end and “521” as the lower end are set to the control signal generating means 602 as fixed values from the outside, the upper end image is a predetermined image. FIG. 7A shows a vertical synchronizing signal input to the input terminal 103, FIG. 7B shows a horizontal synchronizing signal input to the input terminal 102, and FIG. ) Shows a horizontal synchronizing signal having a double frequency output from the double speed conversion means 104, and FIG. 7D shows an example of a video signal inputted from the input terminal 101.

  FIG. 7E shows a field discrimination signal discriminated by the field discriminator 105 based on the synchronization signals inputted from the input terminal 102 and the input terminal 103, and FIG. 7 (g) shows a control signal for reading the upper end of the video from the video delay means 106, FIG. 7 (h) shows a control signal for writing the lower end of the video to the video delay means 107, and FIG. (I) is a control signal for reading the lower end of the video from the video delay means 107, and FIG. 7 (j) is an output of a switching control signal generating means for generating a selection signal for selecting a video signal to be output to the output terminal 111. Show.

  First, the video area discriminating means 601 detects the position of the upper end when the field discrimination output is “High” from the video area signal of FIG. 7D and the output of the field discriminating means 105 (FIG. 7E). When the field discrimination output is “Low”, the position of the lower end is detected and output to the control signal generating means 602. The control signal generation means 602 compares the upper and lower end position information from the video area determination means 601 with the upper and lower end position information set from the outside.

  In the case of FIG. 7, the upper end position information “11” detected by the control signal generating means 601 as the upper end is compared with “9” set from the outside, and in the case of the upper end, a large value “11” is selected. The At the lower end, the lower end position information “521” detected by the control signal generating means 601 is compared with “521” set from the outside, and in the case of the lower end, a small value is selected, but in the case of FIG. 521 ", a value set from the outside is selected.

  Based on the information on the upper and lower ends, the write control signal to the video delay means 106 for delaying the video signal at the upper end is “High” in the field discrimination signal in FIG. 7E and the vertical synchronization in FIG. The horizontal synchronizing signal that is twice as long as that in FIG. 7C from the falling edge of the signal is the 11th and the “High” control signal is output, and the read control signal is the field discrimination signal of “Low” in FIG. The horizontal synchronizing signal that is twice that of FIG. 7C from the falling edge of the vertical synchronizing signal in FIG. 7A is the eleventh, and a “High” control signal is output.

  The write control signal to the video delay means 107 that delays the video signal at the lower end is “Low” in FIG. 7E and the vertical synchronization signal falling in FIG. c) The horizontal synchronization signal that is twice the 521st and the “High” control signal is output, and the readout control signal is “High” as the field discrimination signal in FIG. 7E and the vertical synchronization signal in FIG. The horizontal synchronization signal that is twice that of FIG. 7C from the falling edge of the signal is the 521st, and a “High” control signal is output.

  Thereby, only the upper and lower ends of the video signal delayed by one field are output from the video delay means 106 and 107. In the switching control signal generation means 109, a field discrimination signal (FIG. 7 (e)) output from the field discrimination means and a read control signal (FIG. 7 (g), FIG. 7 (i)) output from the control signal generation means 602. Thus, a switching control signal is output, and when both FIG. 7 (g) and FIG. 7 (i) are “Low”, “1” is indicated, and when FIG. 7 (g) is “High”, “2” is indicated. When 7 (i) is “High”, “3” is output.

  Note that the upper and lower end position information set from the outside is determined from the video effective area defined by the standard, and therefore the upper end position information obtained by the video area discriminating means 601 is smaller than the upper end position information set from the outside. In addition, the lower end position information obtained by the video area discriminating means 601 is never larger than the lower end position information set from the outside.

  As described above, according to the present embodiment, when an input video is smaller than a predetermined size and an area different from the upper and lower end position information set from the outside is detected, the fitting process at the upper and lower end portions is performed. By doing so, even when the size temporarily changes, it is possible to prevent the upper and lower end portions from being burned and to obtain a better image.

  In the video signal processing apparatus according to the present invention, only the upper and lower end portions of the video signal are delayed by one field using the video delay means, thereby preventing flicker and liquid crystal molecules from being biased at the upper and lower end portions by double speed conversion in the field. Even when the display size is changed from 16: 9 to 4: 3, etc., it is possible to obtain good image quality without causing burn-in at the upper and lower end portions, and the input image becomes smaller than a predetermined size and set from the outside. If an area that is different from the upper and lower end position information is detected, the upper and lower end portions are subjected to an inlaying process, so that even if the size temporarily changes, the upper and lower end portions can be prevented from being burned. In the field interpolation mode that does not cause a delay when the field unit delay of the video is a problem, such as for business use that manages and edits video and audio. It is useful as use in when.

The block diagram which shows the structure of the video signal processing apparatus in embodiment of this invention The figure which showed the state which converts the video signal of the interlace scanning of the video signal processing apparatus into the video signal of the sequential scanning within the field The figure which showed the screen display state of the video signal processor The figure which showed the state which performs the conversion process in order to prevent the burn-in of the video signal processing apparatus The figure which shows the operation waveform of each structure of the video signal processor The block diagram of the video signal processor in other embodiments of the present invention The figure which shows the operation waveform of each structure of the video signal processor The block diagram which shows the structural example of the conventional video signal processing apparatus Pixel arrangement diagram explaining operation of interpolation value selection circuit of conventional video signal processing device

Explanation of symbols

101, 801 Video input terminal 102 Horizontal synchronization input terminal 103 Vertical synchronization input terminal 104 Double speed conversion means 105 Field discrimination means 106, 107 Video delay means 108, 602 Control signal generation means 109 Switching signal generation means 110 Selection circuit 111, 813 Output terminals 601 Video region discriminating means 802, 803 Field memory 804, 805 Interpolation circuit 806 Intermediate value comparison circuit 807 Filter circuit 808 Adder circuit 809 Interpolation value selection circuit 810, 811 Double speed conversion unit 812 selection circuit

Claims (5)

When a video signal for interlaced scanning is input, a double speed conversion means for converting the video in the field into a video for sequential scanning, and a first video for holding and delaying the video signal for one line of the output of the double speed conversion means A delay means, a second video delay means, a field discrimination means for discriminating a field of an interlaced video signal from a horizontal synchronization signal and a vertical synchronization signal, the first video delay means, and the second video delay means; Control signal generating means for outputting a write and read control signal to the display, switching signal generating means for outputting a control signal for switching a video signal from the output of the field discriminating means and the output of the control signal generating means, and the switching signal A selection for selecting one of the outputs of the double speed conversion means, the first video delay means or the second video delay means according to the output of the generation means. A video signal processing apparatus characterized by comprising a means. The control signal generating means sequentially converts to scanning by the control signal output from the field discriminating means, the double horizontal synchronizing signal obtained by converting the input horizontal synchronizing signal to a double frequency, and the set value set from the outside. The video signal for one line at each of the upper and lower ends of the effective video area of the recorded video signal is held in the first video delay means and the second video delay means, and a control signal for delaying the video by one field is generated. The video signal processing apparatus according to claim 1. When a video signal for interlaced scanning is input, a double speed conversion means for converting the video in the field into a video for sequential scanning, and a first video for holding and delaying the video signal for one line of the output of the double speed conversion means Delay means, second video delay means, field discriminating means for discriminating the field of the interlaced video signal from the horizontal sync signal and the vertical sync signal, and detecting the positions of the upper and lower ends of the effective video area of the video signal. Video region discriminating means, control signal generating means for outputting write and read control signals to the first video delay means and the second video delay means, output of the field discriminating means and output of the control signal generating means Switching signal generating means for outputting a control signal for switching the video signal from the video signal, and the double speed converting means by the output of the switching signal generating means, A video signal processing apparatus characterized by comprising a selection means for selecting either the output of the first image delay means or the second image delay means. The control signal generating means has upper and lower ends outputted from the video area discriminating means on the basis of the control signal output from the field discriminating means and the double horizontal synchronizing signal obtained by converting the input horizontal synchronizing signal into a double frequency. Is compared with the set values of the upper and lower ends set from outside, and a larger value is selected for the upper end and a smaller value is selected for the lower end, and the effective video area of the video signal converted to sequential scanning is selected. The video signal for one line at each of the upper and lower ends is held in the first video delay means and the second video delay means, and a control signal for delaying the video by one field is generated. 3. The video signal processing device according to 3. The video area discriminating means outputs the effective video area of the video signal from the output of the field discriminating means, the double horizontal synchronizing signal obtained by converting the input horizontal synchronizing signal to a double frequency, and the output of the double speed converting means. 4. The video signal processing apparatus according to claim 3, wherein the positions of the upper end and the lower end are detected.

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