JP2005333044A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
JP2005333044A
JP2005333044A JP2004151482A JP2004151482A JP2005333044A JP 2005333044 A JP2005333044 A JP 2005333044A JP 2004151482 A JP2004151482 A JP 2004151482A JP 2004151482 A JP2004151482 A JP 2004151482A JP 2005333044 A JP2005333044 A JP 2005333044A
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Prior art keywords
insulating material
groove
interposer
sealing
semiconductor device
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Masaji Funakoshi
正司 舩越
Naoto Ueda
直人 上田
Hiroharu Omori
弘治 大森
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2004151482A priority Critical patent/JP2005333044A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that reduces the bending of a batch sealed product, and contributes to cost reduction in manufacturing semiconductor devices. <P>SOLUTION: This semiconductor device manufacturing method comprises a process for mounting multiple semiconductor elements 1 in the interposer 2, a process for electrically connecting the electrode terminal of the above semiconductor element 1 to the terminal of the above interposer 2 by a wire 4, a process for batch sealing the area covering the above semiconductor elements 1 and the above wire 4 with an insulating material 5, a process for attaching a metal terminal 7 to the above interposer 2, and a process for dividing the semiconductor device into segments. Through these processes, a groove 6 is formed in the insulating material 5 of the above batch-sealed product. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子，インターポーザ，ワイヤ，絶縁材料および金属端子から構成される半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device including a semiconductor element, an interposer, a wire, an insulating material, and a metal terminal.

近年になり電子機器、特に携帯機器においては多機能化，高機能化，省スペース化および低コスト化の要望が高まっている。その動向に対応するために、チップサイズをシュリンクし、狭ピッチで配置された多ピンの構成の半導体素子が主流となってきた。そのためパッケージとして前記のような特徴を有する半導体素子をパッケージングし、セットの要望を満たしたパッケージを開発することが急務になってきている。   In recent years, there has been an increasing demand for electronic devices, particularly portable devices, to have multiple functions, high functionality, space saving, and cost reduction. In order to respond to this trend, semiconductor devices having a multi-pin configuration in which the chip size is shrunk and arranged at a narrow pitch have become mainstream. Therefore, it is an urgent task to develop a package that satisfies the requirements of a set by packaging the semiconductor element having the above-described characteristics as a package.

パッケージとしては、当初、ＱＦＰ（Quad Flat Package）の多ピン化により端子ピッチを狭ピッチ化することによって省スペース化にも貢献してきた。しかしながら、更なる省スペース化の要望に応えるため、端子配列をエリアアレイ化したＢＧＡ（Ball Grid Array）が開発され、ＢＧＡの需要が増大してきた。   As a package, it has contributed to space saving by reducing the terminal pitch by increasing the number of pins of QFP (Quad Flat Package). However, in order to meet the demand for further space saving, BGA (Ball Grid Array) in which the terminal array is made into an area array has been developed, and the demand for BGA has increased.

一方、ＢＧＡの需要が増大するに従い、低コスト化の要求は益々強まってきた。そこで低コスト化を図るための製造方法が主流となった。   On the other hand, as the demand for BGA increases, the demand for cost reduction has increased. Therefore, manufacturing methods for reducing costs have become mainstream.

具体的には、一枚のインターポーザに複数の半導体素子を搭載し、半導体素子の電極端子とインターポーザの端子を電気的に結線した後、複数の半導体素子を搭載したインターポーザの片面を絶縁材料で一括封止し、該一括封止品に、絶縁材料で封止されたインターポーザの反対面に金属端子を付設し、最後にダイシングにより一括封止品を分割して個片化する。   Specifically, a plurality of semiconductor elements are mounted on a single interposer, the electrode terminals of the semiconductor elements and the terminals of the interposer are electrically connected, and then one side of the interposer mounted with the plurality of semiconductor elements is collectively made of an insulating material. Then, a metal terminal is attached to the opposite surface of the interposer sealed with an insulating material, and finally the batch sealed product is divided into individual pieces by dicing.

前記のように複数の半導体素子を同時に一括封止するモールド工法と、個片化する方法としてダイシングを用いることは、従来のようにパッケージサイズ毎の封止金型、個片化するために必要な金型などの費用が削減可能であるため、従来と比較して低コスト化を図ることが可能となる。
特開２００１−４４２２６号公報 特開２００３−１３３５００号公報 As described above, the mold method for simultaneously sealing a plurality of semiconductor elements and the use of dicing as a method for dividing into pieces are necessary in order to separate the sealing mold for each package size as in the past. Since the cost of a simple mold or the like can be reduced, the cost can be reduced as compared with the conventional case.
JP 2001-44226 A JP 2003-133500 A

しかしながら、前記従来の技術では下記のような課題がある。すなわち、一枚のインターポーザに複数の半導体素子を搭載し一括封止をすることは、絶縁材料で封止する領域が広くなる。その結果、インターポーザと絶縁材料との線膨張係数の違いにより、一括封止品には反りが発生する。具体的には封止後にインターポーザよりも絶縁材料のほうが収縮率が大きく、絶縁材料の面積が広いほど、または厚みが厚いほど絶縁材料の収縮応力は増大する。その結果、インターポーザと絶縁材料との収縮率の差は大きくなり、一括封止品の反りは顕著になる。   However, the conventional techniques have the following problems. That is, when a plurality of semiconductor elements are mounted on one interposer and collectively sealed, a region to be sealed with an insulating material is widened. As a result, due to the difference in coefficient of linear expansion between the interposer and the insulating material, warpage occurs in the batch sealed product. Specifically, the shrinkage rate of the insulating material is larger than that of the interposer after sealing, and the shrinkage stress of the insulating material increases as the area of the insulating material increases or the thickness increases. As a result, the difference in shrinkage rate between the interposer and the insulating material becomes large, and the warpage of the collectively sealed product becomes remarkable.

そこで従来は、複数の半導体素子を搭載して一括封止する領域を一枚のインターポーザ内で数カ所に分割し、一括封止を行った領域間のインターポーザにスリットを設けることにより応力緩和を図る対策をとっている。具体的には、一括封止をする領域を分割することにより、絶縁材料で封止する面積を縮小化して絶縁材料自体の収縮応力を低減するようにし、かつインターポーザにスリットを設けることにより、絶縁材料の収縮にインターポーザの収縮が追随できるようにすることで反りを低減している。しかし、インターポーザにスリットを設けることによってインターポーザに占める封止有効面積が減り、パッケージ取れ数に大きく影響する。その結果、低コスト化の妨げになる。   Therefore, in the past, measures to reduce stress by mounting multiple semiconductor elements and dividing the area to be collectively sealed into several locations within a single interposer and providing slits in the interposer between the collectively sealed areas Have taken. Specifically, by dividing the area to be collectively sealed, the area to be sealed with the insulating material is reduced to reduce the shrinkage stress of the insulating material itself, and the interposer is provided with a slit to provide insulation. Warpage is reduced by allowing the interposer to follow the shrinkage of the material. However, providing a slit in the interposer reduces the effective sealing area occupied by the interposer, which greatly affects the number of packages that can be taken. As a result, the cost is hindered.

また、一括封止を行う場合に、封止金型を用いて絶縁材料にＶ溝を形成することにより、絶縁材料の小面積化およびＶ溝部分の薄膜化を図り、封止後の反りを低減する方法がある。しかし、形成したＶ溝にダイシングすると、ブレード側面がＶ溝の側面に接触することにより、ブレード側面が大きく磨耗し、ブレード交換時期の早期化およびコスト増を招く。   Also, when performing batch sealing, by forming a V-groove in the insulating material using a sealing mold, the insulating material can be reduced in area and the V-groove portion can be thinned, and warping after sealing can be achieved. There are ways to reduce it. However, when the dicing is performed on the formed V-groove, the blade side surface comes into contact with the side surface of the V-groove, so that the blade side surface is greatly worn, leading to earlier blade replacement time and cost increase.

本発明は、前記従来技術の課題を解決し、一括封止による反りを低減すると同時に、半導体装置の低コスト化に貢献することができる半導体装置の製造方法を提供することを目的とする。   An object of the present invention is to solve the above-described problems of the prior art and to provide a method for manufacturing a semiconductor device that can contribute to a reduction in cost of the semiconductor device while reducing warpage due to collective sealing.

前記目的を解決するため、本発明の半導体装置の製造方法は、インターポーザに複数の半導体素子を搭載する工程と、半導体素子の電極端子とインターポーザの端子を電気的にワイヤで結線する工程と、複数の半導体素子とワイヤの領域を絶縁材料により一括封止する工程と、絶縁材料で封止されたインターポーザの反対面に金属端子を付設する工程と、パッケージ毎に分割して個片化する工程から構成され、前記一括封止にする工程において絶縁材料に溝を形成する製造方法である。   In order to solve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention includes a step of mounting a plurality of semiconductor elements on an interposer, a step of electrically connecting electrode terminals of the semiconductor elements and terminals of the interposer with wires, A step of collectively sealing the semiconductor element and the wire region with an insulating material, a step of attaching a metal terminal to the opposite surface of the interposer sealed with the insulating material, and a step of dividing each package into individual pieces In the manufacturing method, the groove is formed in the insulating material in the step of forming the collective sealing.

このように絶縁材料に溝を形成することにより、溝以外の部分よりも溝の部分は絶縁材料の厚みは薄くなり、溝部分の絶縁材料による収縮応力が大きく低減する。また一括封止の後に複数の異なる箇所に溝を形成することにより、絶縁材料が見かけ上では分割され、その結果、封止領域が縮小したようになり、絶縁材料の収縮応力の低減が図れ、一括封止品の反りを抑えることができる。   By forming the groove in the insulating material in this way, the thickness of the insulating material is smaller in the groove portion than in the portion other than the groove, and the shrinkage stress due to the insulating material in the groove portion is greatly reduced. In addition, by forming grooves in a plurality of different locations after collective sealing, the insulating material is apparently divided, and as a result, the sealing region is reduced, and the shrinkage stress of the insulating material can be reduced. The warpage of the collectively sealed product can be suppressed.

また、一括封止後に溝を等間隔に形成することにより、見かけ上、封止領域は均等に分割され、一括封止品内で均一な反りに抑えることが可能となり、後工程のダイシングに必要な一括封止品のシート貼り付けが容易になる。   In addition, by forming grooves at regular intervals after batch sealing, the sealing area is apparently divided evenly, making it possible to suppress uniform warpage within the batch sealing product, which is necessary for dicing in subsequent processes. It is easy to attach a sheet of a batch sealed product.

また、一括封止の後に形成する溝には、溝以外の部分よりも樹脂厚を薄く絶縁材料を残す。このように溝に絶縁材料を残しておくことにより、絶縁材料に含まれているフィラーがダイシング工程のブレードをドレッシングする効果があり、ブレードの目づまりを防ぎ、切れ味を維持することができる。   Further, the insulating material is left in the groove formed after the collective sealing with a resin thickness smaller than that of the part other than the groove. By leaving the insulating material in the groove in this manner, the filler contained in the insulating material has an effect of dressing the blade in the dicing process, and the blade can be prevented from being clogged and maintained in sharpness.

また、一括封止品の平坦度を重視して極限まで一括封止品の反りを抑えたい場合は、一括封止の後に形成する溝の底部をインターポーザまで到達させ、局所的に絶縁材料を取り去ることが効果的である。   Also, if you want to suppress the warpage of the batch-sealed product to the limit with emphasis on the flatness of the batch-sealed product, let the bottom of the groove formed after the batch sealing reach the interposer and remove the insulating material locally It is effective.

更に一括封止後に形成する溝の底部は、平坦で、かつ溝の底部幅は後工程のダイシングに用いるブレード幅と同一寸法以上にする。このように溝の底部を平坦にすることにより、ブレードの偏り、あるいはブレを低減することができる。   Furthermore, the bottom of the groove formed after the batch sealing is flat, and the width of the bottom of the groove is equal to or larger than the width of the blade used for dicing in a subsequent process. By flattening the bottom of the groove in this way, it is possible to reduce blade bias or blurring.

また、溝底部の幅をブレード幅と同一寸法以上にすることにより、ブレード側面が溝側面に接触し磨耗することを防ぐ効果がある。   In addition, by making the width of the groove bottom portion equal to or larger than the blade width, there is an effect of preventing the blade side surface from coming into contact with the groove side surface and being worn.

一括封止後の溝を封止金型で形成することにより、溝部を形成する工程を追加する必要がないため工程数増加の抑制と、従来のようなスリットを入れる場合よりも封止領域を広くすることができるメリットがある。   By forming the groove after batch sealing with a sealing mold, there is no need to add a step for forming the groove, so the number of steps is suppressed, and the sealing region is larger than when a conventional slit is inserted. There is a merit that can be widened.

本発明の半導体装置の製造方法によれば、絶縁材料に溝を形成することにより一括封止後の反りを低減すると同時に、インターポーザ内の封止有効面積を拡大することによってパッケージ取れ数の増大と低コスト化に貢献することができる。   According to the method for manufacturing a semiconductor device of the present invention, the warpage after collective sealing is reduced by forming a groove in an insulating material, and at the same time, the number of packages that can be taken is increased by increasing the effective sealing area in the interposer. It can contribute to cost reduction.

また、封止後の絶縁材料に形成する溝がインターポーザまで達することにより、溝による反り低減効果は向上する。一方、封止後の絶縁材料に形成する溝に絶縁材料を残すことにより、残した絶縁材料のフィラーによりダイシングで用いるブレードのドレッシング効果が期待できる。   Moreover, the warp reduction effect by a groove | channel improves because the groove | channel formed in the insulating material after sealing reaches an interposer. On the other hand, by leaving the insulating material in the groove formed in the insulating material after sealing, the dressing effect of the blade used in dicing can be expected with the filler of the remaining insulating material.

また、封止後の絶縁材料に形成する溝の底部を、平坦にかつ底部の幅をブレード幅と同一寸法以上にすることにより、絶縁材料がブレード側面に接触し、ブレード側面が大きく磨耗することを防ぐ効果がある。   Also, when the bottom of the groove formed in the insulating material after sealing is flat and the width of the bottom is equal to or larger than the blade width, the insulating material comes into contact with the blade side surface and the blade side surface is greatly worn. There is an effect to prevent.

以下、本発明の実施形態について図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１（ａ）〜（ｆ）は本発明の実施形態１を説明するための半導体装置の製造方法の工程を示す説明図であって、複数の半導体素子１を接着剤３を用いてインターポーザ２に搭載する工程（図１（ａ））と、半導体素子１とインターポーザ２を電気的にワイヤ４で結線する工程（図１（ｂ））と、複数の半導体素子１とワイヤ４を包含する領域を絶縁材料５によって一括封止する工程（図１（ｃ））と、絶縁材料５で封止されたインターポーザ２の反対面に金属端子７を付設する工程（図１（ｄ））と、ダイシングブレード８を用いパッケージ毎に分割し（図１（ｅ））、個片化する工程（図１（ｆ））とから構成されている。   FIGS. 1A to 1F are explanatory views showing the steps of a method of manufacturing a semiconductor device for explaining the first embodiment of the present invention, wherein a plurality of semiconductor elements 1 are bonded to an interposer 2 using an adhesive 3. Mounting step (FIG. 1A), step of electrically connecting the semiconductor element 1 and the interposer 2 with wires 4 (FIG. 1B), and a region including the plurality of semiconductor elements 1 and the wires 4 A step (FIG. 1 (c)), a step of attaching a metal terminal 7 to the opposite surface of the interposer 2 sealed with the insulating material 5 (FIG. 1 (d)), a dicing process The blade 8 is divided into packages (FIG. 1 (e)) and separated into individual pieces (FIG. 1 (f)).

実施形態１では、図１（ｃ）に示すように、一括封止の後に、絶縁材料５に溝６を形成することによって反りの低減化を図る。絶縁材料５に溝６を形成することにより絶縁材料５の収縮応力が低減され一括封止品の反りが抑えられる。   In the first embodiment, as shown in FIG. 1C, the warpage is reduced by forming the groove 6 in the insulating material 5 after the collective sealing. By forming the groove 6 in the insulating material 5, the shrinkage stress of the insulating material 5 is reduced, and the warpage of the collectively sealed product is suppressed.

また、絶縁材料５に等間隔で溝６を形成することにより、絶縁材料５は見かけ上で均等に分割され、一括封止品内で均一な反りに抑えることが可能となり、後工程のダイシングに必要な一括封止品のシート貼り付けが容易になる。   In addition, by forming the grooves 6 in the insulating material 5 at equal intervals, the insulating material 5 is apparently divided evenly, and it is possible to suppress uniform warpage within the batch sealed product, which can be used for dicing in subsequent processes. It is easy to attach the necessary batch sealed product.

さらに、一括封止の後に形成する溝６に、溝６以外の部分よりも樹脂厚を薄く絶縁材料５を残す。溝６に絶縁材料５を残しておくことにより、絶縁材料５に含まれているフィラーが後工程のダイシングブレード８をドレッシングする効果があり、ダイシングブレード８の目づまりを防ぎ、切れ味を維持することができる。   Further, the insulating material 5 is left in the groove 6 formed after the collective sealing with a thinner resin thickness than the portion other than the groove 6. By leaving the insulating material 5 in the groove 6, the filler contained in the insulating material 5 has an effect of dressing the dicing blade 8 in the subsequent process, preventing clogging of the dicing blade 8 and maintaining sharpness. it can.

また、一括封止品の平坦度を重視して極限まで反りを抑えたい場合は、図２に示す本発明の実施形態２のように、一括封止の後に形成する溝６の底部９を、インターポーザ２まで到達させ局所的に絶縁材料５を取り去ることが効果的である。   In addition, when emphasizing the flatness of the batch-sealed product and suppressing warping to the limit, the bottom portion 9 of the groove 6 formed after the batch sealing, as in Embodiment 2 of the present invention shown in FIG. It is effective to reach the interposer 2 and remove the insulating material 5 locally.

一括封止後に形成する溝６の底部９は、平坦でかつ後工程のダイシングに用いるブレード幅と同一寸法以上にする。溝６の底部９を平坦にすることにより、ダイシングブレード８の偏り、あるいはブレを低減することができる。また、溝６の底部９の幅をダイシングブレード８と同一寸法以上にすることにより、ダイシングブレード８の側面が溝６の側面に接触して磨耗することを防ぐ効果がある。   The bottom 9 of the groove 6 to be formed after collective sealing is flat and has the same dimension as the blade width used for dicing in a subsequent process. By making the bottom portion 9 of the groove 6 flat, it is possible to reduce the deviation or blurring of the dicing blade 8. Further, by making the width of the bottom portion 9 of the groove 6 equal to or larger than that of the dicing blade 8, there is an effect of preventing the side surface of the dicing blade 8 from coming into contact with the side surface of the groove 6 and being worn.

一括封止後の溝を封止金型で形成することにより、溝部を形成する工程を追加する必要がないため工程数増加の抑制と、従来のようなスリットを入れる場合よりも封止領域を広くすることができるメリットがある。   By forming the groove after batch sealing with a sealing mold, there is no need to add a step for forming the groove, so the number of steps is suppressed, and the sealing region is larger than when a conventional slit is inserted. There is a merit that can be widened.

本発明の半導体装置の製造方法は、大面積を封止するときの反りを低減することが可能なことから、封止１回におけるパッケージ取れ数を増加させることができるため、多ピンで低コストな携帯電子機器向けの半導体素子を搭載する半導体装置に有用である。   Since the method for manufacturing a semiconductor device of the present invention can reduce the warpage when sealing a large area, the number of packages that can be obtained in one sealing can be increased. This is useful for a semiconductor device in which a semiconductor element for a portable electronic device is mounted.

（ａ）〜（ｆ）は本発明の実施形態１を説明するための半導体装置の製造方法の工程を示す説明図(A)-(f) is explanatory drawing which shows the process of the manufacturing method of the semiconductor device for describing Embodiment 1 of this invention. 本発明の実施形態２を説明するための半導体装置の製造方法の一工程を示す説明図Explanatory drawing which shows 1 process of the manufacturing method of the semiconductor device for describing Embodiment 2 of this invention

符号の説明Explanation of symbols

１ 半導体素子
２ インターポーザ
３ 接着剤
４ ワイヤ
５ 絶縁材料
６ 溝
７ 金属端子
８ ダイシングブレード
９ 溝の底部 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Interposer 3 Adhesive 4 Wire 5 Insulating material 6 Groove 7 Metal terminal 8 Dicing blade 9 Bottom of groove

Claims (6)

複数の半導体素子を１枚のインターポーザの上面に導電性材料を介して搭載する工程と、前記半導体素子と前記インターポーザをワイヤにて電気的に結線するワイヤボンド工程と、複数の前記半導体素子と前記ワイヤを包含する領域を絶縁材料で一括に封止する封止工程と、前記インターポーザの下面に金属端子を付設する工程と、前記半導体素子毎に分離して個片にするパッケージダイシング工程から構成されており、前記封止工程において、前記絶縁材料に溝を形成することを特徴とする半導体装置の製造方法。   A step of mounting a plurality of semiconductor elements on the upper surface of one interposer via a conductive material; a wire bonding step of electrically connecting the semiconductor elements and the interposer with wires; a plurality of the semiconductor elements; It consists of a sealing step for collectively sealing a region including a wire with an insulating material, a step for attaching a metal terminal to the lower surface of the interposer, and a package dicing step for separating each semiconductor element into individual pieces. And forming a groove in the insulating material in the sealing step. 前記封止工程において、前記絶縁材料に前記溝を等間隔に形成することを特徴とする請求項１記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein in the sealing step, the grooves are formed at equal intervals in the insulating material. 前記封止工程において、前記溝における前記絶縁材料を、前記溝以外の箇所より厚さを薄くして残すことを特徴とする請求項１または２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein, in the sealing step, the insulating material in the groove is left with a thickness thinner than a portion other than the groove. 前記封止工程において、前記溝の底部がインターポーザに達するように形成することを特徴とする請求項１または２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the sealing step, the groove is formed so that a bottom of the groove reaches the interposer. 前記封止工程において、前記溝の底部を平坦で、かつ該底部の幅をダイシングに用いるブレード幅と同一寸法以上にすることを特徴とする請求項１〜４いずれか１項記載の半導体装置の製造方法。   5. The semiconductor device according to claim 1, wherein, in the sealing step, a bottom portion of the groove is flat and a width of the bottom portion is equal to or larger than a blade width used for dicing. Production method. 前記封止工程において、前記絶縁材料に前記溝を形成する際に封止金型を用いることを特徴とする請求項１〜５いずれか１項記載の半導体装置の製造方法。   6. The method for manufacturing a semiconductor device according to claim 1, wherein a sealing mold is used when forming the groove in the insulating material in the sealing step.
JP2004151482A 2004-05-21 2004-05-21 Semiconductor device manufacturing method Pending JP2005333044A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010141261A (en) * 2008-12-15 2010-06-24 Elpida Memory Inc Intermediate structure for semiconductor device and method for manufacturing intermediate structure
JP2016072257A (en) * 2014-09-26 2016-05-09 三菱電機株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010141261A (en) * 2008-12-15 2010-06-24 Elpida Memory Inc Intermediate structure for semiconductor device and method for manufacturing intermediate structure
JP2016072257A (en) * 2014-09-26 2016-05-09 三菱電機株式会社 Semiconductor device

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