JP2005332983A - Optical semiconductor package and manufacturing method thereof - Google Patents

Optical semiconductor package and manufacturing method thereof Download PDF

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JP2005332983A
JP2005332983A JP2004150089A JP2004150089A JP2005332983A JP 2005332983 A JP2005332983 A JP 2005332983A JP 2004150089 A JP2004150089 A JP 2004150089A JP 2004150089 A JP2004150089 A JP 2004150089A JP 2005332983 A JP2005332983 A JP 2005332983A
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circuit board
optical semiconductor
electrode pattern
hole
collective
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Koichi Haneda
浩一 羽田
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Citizen Electronics Co Ltd
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Citizen Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Led Device Packages (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical semiconductor package wherein an optical semiconductor chip and other electronic components can be mounted on a sheet of circuit board hierarchically and efficiently and it has an electrode structure capable of dealing with its surface mounting. <P>SOLUTION: The optical semiconductor package has a circuit board 14 and a base board 15. The circuit board 14 has on its surface a first electrode pattern having an optical semiconductor chip mounted thereon, and has on its backside a second electrode pattern 22 having other electronic components 13 mounted thereon, and further, has on its side surfaces first through holes 23. The base board 15 so has a recess 18 for storing therein the electronic components 13 mounted on the second electrode pattern 22 and so has second through holes 24 brought into continuities with the first through holes 23 as to join it to the backside of the circuit board 14 in a body. Further, external connection electrodes 17 are provided on the backside of the base board 15, and the first electrode pattern and the second electrode pattern 22 are brought into continuities with the electrodes 17 via the second through holes 24. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、光半導体チップを中心に他の電子部品が混在した光半導体パッケージに係り、特に前記光半導体チップやその他の電子部品の実装効率を高めて小型化を実現する光半導体パッケージ及びその製造方法に関するものである。   The present invention relates to an optical semiconductor package in which other electronic components are mixed mainly in an optical semiconductor chip, and in particular, an optical semiconductor package that realizes miniaturization by increasing the mounting efficiency of the optical semiconductor chip and other electronic components, and the manufacturing thereof. It is about the method.

従来の光伝送デバイスやＯＥＩＣ（光電子集積回路）等の光半導体パッケージ１は、図１６に示すように、ＬＥＤや半導体レーザ等の光半導体チップ２を中心に、コンデンサや抵抗等の電子部品３から構成されており、これらの光半導体チップ２や電子部品３を回路基板４の表面側に実装している。ところで、近年の装置の小型化及び高機能化に伴って、実装する回路基板においても小型化が要求されるようになってきている。この要求に応えるため、電極ピッチ間を狭めるなどして光半導体チップや電子部品の実装密度を高めるようにしていたが、従来のような回路基板の表面側のみへの実装には限界があった。   A conventional optical semiconductor package 1 such as an optical transmission device or an OEIC (opto-electronic integrated circuit) is composed of an electronic component 3 such as a capacitor or a resistor, centering on an optical semiconductor chip 2 such as an LED or a semiconductor laser, as shown in FIG. The optical semiconductor chip 2 and the electronic component 3 are mounted on the surface side of the circuit board 4. By the way, with recent miniaturization and higher functionality of devices, miniaturization of circuit boards to be mounted has been required. To meet this requirement, the mounting density of optical semiconductor chips and electronic components was increased by narrowing the electrode pitch, but there was a limit to mounting only on the surface side of circuit boards as in the past. .

このような問題点を解消するために、本件出願人は特許文献１に、回路基板の表裏両面を使用して光半導体チップや電子部品を実装する光伝送デバイスを開示した。この光伝送デバイスは、装置への実装スペースを抑えるために、回路基板の表面に光デバイス部、裏面にその他の周辺電子部品を実装する構造となっている。
特開２００３−３０４００４号公報 In order to solve such problems, the present applicant disclosed in Patent Document 1 an optical transmission device that mounts an optical semiconductor chip or an electronic component using both the front and back surfaces of a circuit board. This optical transmission device has a structure in which an optical device portion is mounted on the front surface of the circuit board and other peripheral electronic components are mounted on the back surface in order to reduce the mounting space in the apparatus.
JP 2003-304004 A

上記従来の光伝送デバイスをマザーボード等の装置内の基板に表面実装する場合は、前記電子部品の封止樹脂面が装置基板に載置されることとなるが、この封止樹脂面にはスルーホール電極を形成することが容易でない。このため、前記封止樹脂面の側面に回路基板から装置基板に繋がる電極パターンを蒸着等によって形成する必要がある。   When the conventional optical transmission device is surface-mounted on a substrate in a device such as a mother board, the sealing resin surface of the electronic component is placed on the device substrate. It is not easy to form a hole electrode. For this reason, it is necessary to form an electrode pattern connected to the device substrate from the circuit board on the side surface of the sealing resin surface by vapor deposition or the like.

また、前記回路基板の両面に電子部品類を実装するため、回路基板を厚いガラスエポキシやＢＴレジン等で形成する必要があった。   In addition, in order to mount electronic components on both sides of the circuit board, it is necessary to form the circuit board with a thick glass epoxy, BT resin, or the like.

そこで、本発明の目的は、光半導体チップやその他の電子部品を一枚の回路基板上に階層的に効率よく実装可能とすると共に、表面実装に対応可能な電極構造を備えた光半導体パッケージ及びその製造方法を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to provide an optical semiconductor package having an electrode structure capable of hierarchically and efficiently mounting an optical semiconductor chip and other electronic components on a single circuit board and capable of supporting surface mounting. The manufacturing method is provided.

上記課題を解決するために、本発明の光半導体パッケージは、表面に光半導体チップを実装する第１の電極パターン、裏面に他の電子部品を実装する第２の電極パターン、側面に第１のスルーホールを有する回路基板と、前記第２の電極パターン上に実装される電子部品を収容する凹部または窓孔、前記第１のスルーホールと導通する第２のスルーホールを有して前記回路基板の裏面に一体に接合されるベース基板とを備え、前記ベース基板の裏面に外部接続電極を設けると共に、前記第１の電極パターン及び前記第２の電極パターンを前記第２のスルーホールを介して導通させたことを特徴とする。   In order to solve the above problems, an optical semiconductor package of the present invention includes a first electrode pattern for mounting an optical semiconductor chip on the front surface, a second electrode pattern for mounting other electronic components on the back surface, and a first electrode pattern on the side surface. The circuit board having a circuit board having a through hole, a recess or window hole for accommodating an electronic component mounted on the second electrode pattern, and a second through hole electrically connected to the first through hole A base substrate integrally bonded to the back surface of the base substrate, and external connection electrodes are provided on the back surface of the base substrate, and the first electrode pattern and the second electrode pattern are connected to each other through the second through hole. It is characterized by being conducted.

この発明によれば、光半導体チップや周辺の電子部品類を回路基板の表裏両面に実装可能としたことによって、回路基板の平面サイズを小さく抑えることができる。特に、前記光半導体チップを回路基板の表面に実装し、他のコンデンサや抵抗といった周辺の電子部品類を回路基板の裏面に実装することによって、光半導体チップへの透光性を確保することができる。また、前記回路基板と一体となるベース基板を設けたことで、前記回路基板の裏面に実装した電子部品の突出部分を収容すると共に、マザーボード等に表面実装する際の安定した支持ベースとなる。また、前記電子部品を収容する部分が窓孔に形成された場合にあっては、マザーボードに表面実装することで電子部品が密閉された状態となるので、別途樹脂封止する必要がなくなる。   According to the present invention, since the optical semiconductor chip and peripheral electronic components can be mounted on both the front and back surfaces of the circuit board, the planar size of the circuit board can be reduced. In particular, it is possible to ensure translucency to the optical semiconductor chip by mounting the optical semiconductor chip on the surface of the circuit board and mounting peripheral electronic components such as other capacitors and resistors on the back surface of the circuit board. it can. Further, by providing the base substrate integrated with the circuit board, the protruding part of the electronic component mounted on the back surface of the circuit board is accommodated, and a stable support base for surface mounting on the motherboard or the like is provided. Further, when the part for accommodating the electronic component is formed in the window hole, the electronic component is hermetically sealed by being surface-mounted on the mother board, so that it is not necessary to separately seal the resin.

また、前記回路基板の第１のスルーホールと導通する第２のスルーホールがベース基板に形成されているため、このベース基板を直接マザーボード等の実装基板に表面実装することができる。   In addition, since the second through hole that is electrically connected to the first through hole of the circuit board is formed in the base board, the base board can be directly surface mounted on a mounting board such as a mother board.

また、前記回路基板とベース基板との接合がペースト状またはフィルム状の異方性導電部材を介して行われることで、前記第１のスルーホールと第２のスルーホールとの導電性を損なうことなく、両者を安定した状態で接合することができる。   Further, the bonding between the circuit board and the base substrate is performed via a paste-like or film-like anisotropic conductive member, thereby impairing the conductivity between the first through hole and the second through hole. The two can be joined in a stable state.

また、本発明の光半導体パッケージの製造方法は、光半導体チップを実装する第１の電極パターンを集合回路基板の表面に、他の電子部品を実装する第２の電極パターンを集合回路基板の裏面に複数形成し、側面に第１のスルーホールを設ける集合回路基板形成工程と、側面に前記第１のスルーホールと導通する第２のスルーホール、裏面に外部接続電極を設けると共に、前記第２の電極パターン上に実装される電子部品を収容する凹部または窓孔を形成する集合ベース基板形成工程と、前記第２の電極パターン上にペースト状またはフィルム状の異方性導電部材を介して電子部品を実装した後、前記集合回路基板の裏面に前記集合ベース基板を前記異方性導電部材によって接合する基板接合工程と、前記第１の電極パターン上に光半導体チップを実装した後、集合回路基板の表面を樹脂で封止する樹脂封止工程と、前記集合ベース基板と一体になった集合回路基板を個々の光半導体チップに分断するチップ分割工程とを備えたことを特徴とする。   In the method of manufacturing an optical semiconductor package of the present invention, the first electrode pattern for mounting the optical semiconductor chip is provided on the surface of the collective circuit board, and the second electrode pattern for mounting other electronic components is provided on the back surface of the collective circuit board. Forming a plurality of the first through holes on the side surface, forming a second through hole in conduction with the first through hole on the side surface, providing an external connection electrode on the back surface, and the second An assembly base substrate forming step for forming a recess or a window hole for accommodating an electronic component mounted on the electrode pattern; and an electron via a paste-like or film-like anisotropic conductive member on the second electrode pattern After mounting the components, a substrate bonding step of bonding the collective base substrate to the back surface of the collective circuit substrate by the anisotropic conductive member, and an optical semiconductor chip on the first electrode pattern A resin sealing step for sealing the surface of the collective circuit board with a resin after mounting the chip, and a chip dividing step for dividing the collective circuit board integrated with the collective base substrate into individual optical semiconductor chips. It is characterized by that.

この発明によれば、複数の光半導体チップ及び電子部品を一括して集合回路基板の表面及び裏面に実装することで、工程の短縮を図ることができる。また、前記集合ベース基板と前記集合回路基板とが別体で製造されるため、製造工程及び製造条件の自由度が増し、前記集合回路基板に実装される電子部品に対応した凹部または窓孔や、スルーホールに合わせた集合ベース基板を適宜組み合わせて接合形成することができる。さらに、前記光半導体チップやその他の電子部品を実装した集合回路基板を集合ベース基板ごとダイシングすることによって、個々の光半導体チップに一括して分けることができる。このため、同一仕様の光半導体チップを安価に大量生産することができる。   According to this invention, a plurality of optical semiconductor chips and electronic components are collectively mounted on the front surface and the back surface of the collective circuit board, so that the process can be shortened. In addition, since the collective base board and the collective circuit board are manufactured separately, the degree of freedom in the manufacturing process and manufacturing conditions is increased, and a recess or a window hole corresponding to an electronic component mounted on the collective circuit board is provided. The assembly base substrates matched to the through holes can be appropriately combined and formed. Further, by dicing the collective circuit board on which the optical semiconductor chip and other electronic components are mounted together with the collective base board, it can be divided into individual optical semiconductor chips. For this reason, optical semiconductor chips of the same specification can be mass-produced at low cost.

本発明に係る光半導体パッケージによれば、発光ダイオードや半導体レーザのような光半導体チップと、その周辺に実装される電子部品とが混在した光半導体パッケージの小型化が図られる。このため、光半導体チップが搭載される光ピックアップ等のモジュールやこのモジュールが組み込まれる光ディスク装置の小型化が可能となる。   According to the optical semiconductor package of the present invention, it is possible to reduce the size of the optical semiconductor package in which an optical semiconductor chip such as a light emitting diode or a semiconductor laser and electronic components mounted around the optical semiconductor chip are mixed. For this reason, it is possible to reduce the size of a module such as an optical pickup on which an optical semiconductor chip is mounted and an optical disk apparatus in which this module is incorporated.

また、本発明の光半導体パッケージの製造方法によれば、集合回路基板や集合ベース基板を用いて複数の光半導体パッケージを一括して製造することができるため、品質が一定の製品を大量且つ安価に製造することができる。   In addition, according to the method for manufacturing an optical semiconductor package of the present invention, a plurality of optical semiconductor packages can be manufactured collectively using an aggregate circuit board and an aggregate base board, so that products with a constant quality can be manufactured in large quantities and at low cost. Can be manufactured.

以下、添付図面に基づいて本発明に係る光半導体パッケージの実施形態を詳細に説明する。図１は本発明の一実施形態に係る光半導体パッケージを表側から見た斜視図、図２は前記光半導体パッケージを裏側から見た斜視図、図３は前記光半導体パッケージの断面図である。   Embodiments of an optical semiconductor package according to the present invention will be described below in detail with reference to the accompanying drawings. 1 is a perspective view of an optical semiconductor package according to an embodiment of the present invention as viewed from the front side, FIG. 2 is a perspective view of the optical semiconductor package as viewed from the back side, and FIG. 3 is a cross-sectional view of the optical semiconductor package.

図１乃至図３に示すように、本発明の光半導体パッケージ１１は、表面にＬＥＤや半導体レーザ等の光半導体チップ１２、裏面にコンデンサや抵抗といった電子部品１３を実装するための回路基板１４と、この回路基板１４の裏面に一体に形成されるベース基板１５と、前記光半導体チップ１２の実装面を封止する透光性の樹脂体１６とを備えている。   As shown in FIGS. 1 to 3, an optical semiconductor package 11 of the present invention includes an optical semiconductor chip 12 such as an LED or a semiconductor laser on the front surface, and a circuit board 14 for mounting an electronic component 13 such as a capacitor or a resistor on the back surface. A base substrate 15 formed integrally with the back surface of the circuit board 14 and a translucent resin body 16 for sealing the mounting surface of the optical semiconductor chip 12 are provided.

前記回路基板１４は、厚さが０．１〜０．２ｍｍ程度のポリイミド、ガラスエポキシあるいはＢＴレジン等の樹脂材で形成され、表面に第１の電極パターン２１、裏面に第２の電極パターン２２がそれぞれ形成されている。前記第１の電極パターン２１と第２の電極パターン２２は、前記回路基板１４の側面に形成された第１のスルーホール２３によって導通される。   The circuit board 14 is formed of a resin material such as polyimide, glass epoxy, or BT resin having a thickness of about 0.1 to 0.2 mm, and has a first electrode pattern 21 on the front surface and a second electrode pattern 22 on the back surface. Are formed respectively. The first electrode pattern 21 and the second electrode pattern 22 are electrically connected by a first through hole 23 formed on a side surface of the circuit board 14.

前記ベース基板１５には、前記回路基板１４と一体化された際に、回路基板１４の裏面に実装した電子部品１３が逃げる凹部１８が形成される。また、前記ベース基板１５の側面には、前記回路基板１４に形成された第１のスルーホール２３に連通する第２のスルーホール２４が設けられる。さらに、前記第２のスルーホール２４と導通する外部接続電極１７が前記ベース基板１５の裏面側に形成される。なお、前記凹部１８の代わりに、ベース基板１５を貫通する窓孔を形成してもよい。このような窓孔を設けることによって、前記電子部品１３を避けてベース基板１５を回路基板１４に密着させることができる。   The base substrate 15 is formed with a recess 18 through which the electronic component 13 mounted on the back surface of the circuit board 14 escapes when integrated with the circuit board 14. Further, a second through hole 24 communicating with the first through hole 23 formed in the circuit board 14 is provided on the side surface of the base substrate 15. Further, an external connection electrode 17 that is electrically connected to the second through hole 24 is formed on the back side of the base substrate 15. Note that a window hole penetrating the base substrate 15 may be formed instead of the recess 18. By providing such a window hole, the base substrate 15 can be adhered to the circuit board 14 while avoiding the electronic component 13.

図４は前記回路基板１４の表面、図５は前記回路基板１４の裏面における回路構成例を示したものである。図４に示されるように、回路基板１４の表面には、光半導体チップ１２の実装スペースと、この実装スペースに載置される光半導体チップ１２のチップ電極部に対応して設けられる第１の電極パターン２１と、この第１の電極パターン２１と繋がる第１のスルーホール２３とが形成されている。光半導体チップ１２は、前記回路基板１４の表面の略中央部に固定され、各チップ電極部に対応する第１の電極パターン２１とがボンディングワイヤを介して接続される。一方、前記回路基板１４の裏面は、図５に示したように、コンデンサや抵抗等の電子部品１３の実装スペースと、この実装スペースに固定される電子部品１３の各電極部に対応して設けられる第２の電極パターン２２が形成されている。前記電子部品１３は、第２の電極パターン２２上に形成された導電性の接着層を介して接続される。なお、第１のスルーホール２３は、第１の電極パターン２１及び第２の電極パターン２２に対応する本数分が形成される。   4 shows a circuit configuration example on the front surface of the circuit board 14, and FIG. 5 shows a circuit configuration example on the back surface of the circuit board 14. As shown in FIG. 4, on the surface of the circuit board 14, a mounting space for the optical semiconductor chip 12 and a first electrode provided corresponding to the chip electrode portion of the optical semiconductor chip 12 placed in this mounting space. An electrode pattern 21 and a first through hole 23 connected to the first electrode pattern 21 are formed. The optical semiconductor chip 12 is fixed to a substantially central portion of the surface of the circuit board 14 and is connected to the first electrode pattern 21 corresponding to each chip electrode portion via a bonding wire. On the other hand, as shown in FIG. 5, the back surface of the circuit board 14 is provided so as to correspond to the mounting space of the electronic component 13 such as a capacitor and a resistor, and each electrode portion of the electronic component 13 fixed to the mounting space. A second electrode pattern 22 is formed. The electronic component 13 is connected via a conductive adhesive layer formed on the second electrode pattern 22. Note that the number of the first through holes 23 corresponding to the first electrode pattern 21 and the second electrode pattern 22 is formed.

前記ベース基板１５は、ポリイミド、ガラスエポキシあるいはＢＴレジン等の樹脂材で形成されている。このベース基板１５には、前記回路基板１４の裏面に実装されている電子部品１３と対向した位置に凹部１８が設けられ、側面には、前記回路基板１４に設けられた第１のスルーホール２３と連通するように第２のスルーホール２４が設けられる。なお、このベース基板１５は、前記回路基板１４と略同じ形状及び大きさであり、厚さは前記回路基板１４の裏面に実装した電子部品１３の高さと同じか、それ以上に設定される。   The base substrate 15 is formed of a resin material such as polyimide, glass epoxy, or BT resin. The base substrate 15 is provided with a recess 18 at a position facing the electronic component 13 mounted on the back surface of the circuit board 14, and a first through hole 23 provided in the circuit board 14 on the side surface. A second through hole 24 is provided to communicate with the second through hole 24. The base substrate 15 has substantially the same shape and size as the circuit board 14, and the thickness is set to be equal to or higher than the height of the electronic component 13 mounted on the back surface of the circuit board 14.

前記ベース基板１５は、電子部品１３が実装されている回路基板１４の裏面に接合される。この接合は、前記第１のスルーホール２３と第２のスルーホール２４との接合面に配設された異方性導電材料を介して行われる。この異方性導電材料は、ペースト状とシート状の２種類のタイプがあるがいずれを用いても構わない。このような異方性導電材料を用いることで、スルーホールの深さ方向には導電性を有する一方、接合平面においては導電性を有しないため、隣接するスルーホール間でのショートを発生させることなく確実に導通及び接合することができる。   The base substrate 15 is bonded to the back surface of the circuit board 14 on which the electronic component 13 is mounted. This joining is performed via an anisotropic conductive material disposed on the joining surface between the first through hole 23 and the second through hole 24. There are two types of anisotropic conductive materials, paste and sheet, whichever may be used. By using such an anisotropic conductive material, while having conductivity in the depth direction of the through hole, it does not have conductivity in the bonding plane, so that a short circuit between adjacent through holes is generated. And can be reliably connected and joined.

前記回路基板１４は、透光性を有する樹脂材によって表面を封止する。このような樹脂材で封止することによって、光の入射及び出射に影響を与えることなく、光半導体チップ１２を埃や湿気から保護することができる。   The surface of the circuit board 14 is sealed with a resin material having translucency. By sealing with such a resin material, the optical semiconductor chip 12 can be protected from dust and moisture without affecting the incidence and emission of light.

図６は前記光半導体パッケージ１１をマザーボード等の実装基板２０上に表面実装したときの状態を示したものである。このように、前記回路基板１４の表面に実装した光半導体チップ１２や裏面に実装した電子部品１３から延びる第１の電極パターン２１及び第２の電極パターン２２が第１のスルーホール２３から第２のスルーホール２４及び外部接続電極１７にかけて連通しているため、前記外部接続電極１７を実装基板２０に形成されている図示しない電極端子に載置して直接表面実装することができる。また、前述したように、前記電子部品１３を前記凹部１８の代わりに開設される窓孔を備えたベース基板に収めるような構成にすることも可能である。このような構成にした場合には、前記電子部品１３が前記窓孔の内周面によって囲われると共に、前記ベース基板１５を実装基板２０に実装することで前記電子部品１３が密閉された状態となるため、前記電子部品１３を保護するための樹脂による封止が不要となる。   FIG. 6 shows a state when the optical semiconductor package 11 is surface-mounted on a mounting substrate 20 such as a mother board. As described above, the first electrode pattern 21 and the second electrode pattern 22 extending from the optical semiconductor chip 12 mounted on the front surface of the circuit board 14 and the electronic component 13 mounted on the back surface are second through the first through hole 23. Therefore, the external connection electrode 17 can be mounted on an electrode terminal (not shown) formed on the mounting substrate 20 and directly mounted on the surface. Further, as described above, the electronic component 13 may be configured to be accommodated in a base substrate having a window hole that is opened instead of the recess 18. In such a configuration, the electronic component 13 is surrounded by the inner peripheral surface of the window hole, and the electronic component 13 is sealed by mounting the base substrate 15 on the mounting substrate 20. Therefore, sealing with resin for protecting the electronic component 13 becomes unnecessary.

本実施形態では、回路基板１４の表面に発光ダイオードや半導体レーザ等の光半導体チップ１２を実装する場合について説明したが、このような光以外の他の半導体チップを実装することによって、小型化及び高機能の半導体パッケージを形成することができる。   In the present embodiment, the case where the optical semiconductor chip 12 such as a light-emitting diode or a semiconductor laser is mounted on the surface of the circuit board 14 has been described. A highly functional semiconductor package can be formed.

次に、上記光半導体パッケージ１１の製造方法について説明する。図７乃至図１５は、上記構造の光半導体チップを量産するための一連の工程を示したものである。   Next, a method for manufacturing the optical semiconductor package 11 will be described. 7 to 15 show a series of steps for mass-producing the optical semiconductor chip having the above structure.

図７及び図８は、集合回路基板形成工程を示したものである。最初に、前述した光半導体チップを複数実装形成可能な集合回路基板３４を用意し、この集合回路基板３４の表面３４ａに光半導体チップの実装スペース３６を確保する。次に、前記実装スペース３６上に載置される光半導体チップのチップ電極部に対応する第１の電極パターン２１を形成し、裏面３４ｂには電子部品の実装スペース３７と、この実装スペース３７に載置される電子部品の電極部に対応する第２の電極パターン２２を形成する。また、前記集合回路基板３４の表面３４ａから裏面３４ｂにかけて、前記第１の電極パターン２１と第２の電極パターン２２が繋がる第１のスルーホール２３を形成する。   7 and 8 show the collective circuit board forming step. First, a collective circuit board 34 on which a plurality of optical semiconductor chips described above can be mounted is prepared, and an optical semiconductor chip mounting space 36 is secured on the surface 34 a of the collective circuit board 34. Next, the first electrode pattern 21 corresponding to the chip electrode portion of the optical semiconductor chip placed on the mounting space 36 is formed, and the electronic component mounting space 37 and the mounting space 37 are formed on the back surface 34b. A second electrode pattern 22 corresponding to the electrode portion of the electronic component to be placed is formed. A first through hole 23 is formed from the front surface 34 a to the back surface 34 b of the collective circuit board 34 to connect the first electrode pattern 21 and the second electrode pattern 22.

一方、前記集合回路基板形成工程とは別工程の集合ベース基板形成工程によって、図９に示すような集合ベース基板３５を形成する。この集合ベース基板３５は、前記集合回路基板３４と略同じ大きさに形成され、前記集合回路基板３４の裏面３４ｂに実装される電子部品を収容させるための凹部１８を所定間隔ごとに複数配列形成する。また、前記集合ベース基板３５には、前記集合回路基板３４と重ね合わせて接合した際に、第１のスルーホール２３と上下に連通するように、表面から裏面にかけて第２のスルーホール２４及び外部接続電極１７を形成する。   On the other hand, a collective base substrate 35 as shown in FIG. 9 is formed by a collective base substrate forming step different from the collective circuit substrate forming step. The collective base board 35 is formed to be approximately the same size as the collective circuit board 34, and a plurality of recesses 18 for accommodating electronic components mounted on the back surface 34b of the collective circuit board 34 are formed at predetermined intervals. To do. Further, the second through hole 24 and the outside from the front surface to the rear surface are connected to the collective base substrate 35 so as to communicate with the first through hole 23 in the vertical direction when being joined to the collective circuit substrate 34 in an overlapping manner. A connection electrode 17 is formed.

次に、図１０に示すように、前記集合回路基板３４の裏面３４ｂに形成された第２の電極パターン２２上に電子部品１３を実装した後、図１１及び図１２に示すように、前記電子部品１３を凹部１８に収容するようにして前記集合ベース基板３５を接合する。前記電子部品１３の実装は、第２の電極パターン２２上に形成した導電接合層３８、前記集合回路基板３４と集合ベース基板３５との接合は、第１のスルーホール２３と第２のスルーホール２４との間に設けられる導電接合層３８を介して行われる。前記導電接合層３８は、ペースト状またはフィルム状の異方性導電部材が用いられる。   Next, as shown in FIG. 10, after mounting the electronic component 13 on the second electrode pattern 22 formed on the back surface 34b of the collective circuit board 34, as shown in FIGS. The assembly base substrate 35 is bonded so that the component 13 is accommodated in the recess 18. The electronic component 13 is mounted on the conductive bonding layer 38 formed on the second electrode pattern 22, and the collective circuit board 34 and the collective base board 35 are joined on the first through hole 23 and the second through hole. 24 is performed via a conductive bonding layer 38 provided between them. For the conductive bonding layer 38, a paste-like or film-like anisotropic conductive member is used.

次に、図１３に示すように、前記集合回路基板３４の表面３４ａに光半導体チップ１２を実装し、第１の電極パターン２１とワイヤボンディングによって接続する。その後、図１４に示した樹脂封止工程に移行し、前記集合回路基板３４の表面３４ａ側に透光性を有する樹脂材を充填して封止用の樹脂体１６を成形する。   Next, as shown in FIG. 13, the optical semiconductor chip 12 is mounted on the surface 34a of the collective circuit board 34 and connected to the first electrode pattern 21 by wire bonding. Thereafter, the process proceeds to a resin sealing step shown in FIG. 14, and a resin material 16 having a light transmitting property is filled on the surface 34a side of the collective circuit board 34 to form a sealing resin body 16.

最後に、図１５に示したチップ分割工程において、前記一連の工程によって形成された集合光半導体パッケージ３１をＸ軸方向及びＹ軸方向に沿ってダイシングする。このダイシングによって、個々の光半導体パッケージ１１が形成される。   Finally, in the chip dividing step shown in FIG. 15, the collective optical semiconductor package 31 formed by the series of steps is diced along the X-axis direction and the Y-axis direction. By this dicing, individual optical semiconductor packages 11 are formed.

なお、上記製造工程では、電子部品１３を集合回路基板３４の裏面３４ｂに実装し、集合ベース基板３５を装着した後、光半導体チップ１２を前記集合回路基板３４の表面３４ａに実装し、最後に樹脂体１６で封止した。このような手順で行うことで、前記樹脂体１６に製造過程で発生するゴミ等の付着を防止することができる。ただし、このような製造手順には限定されず、先に光半導体チップ１２を実装及び樹脂体１６で封止した後、電子部品１３を集合回路基板３４の裏面３４ｂに実装し、最後に集合ベース基板３５を装着して形成してもよい。   In the above manufacturing process, the electronic component 13 is mounted on the back surface 34b of the collective circuit board 34, and after the collective base board 35 is mounted, the optical semiconductor chip 12 is mounted on the surface 34a of the collective circuit board 34. Sealed with resin body 16. By performing in such a procedure, it is possible to prevent the resin body 16 from adhering dust or the like generated during the manufacturing process. However, the manufacturing procedure is not limited to this. The optical semiconductor chip 12 is first mounted and sealed with the resin body 16, and then the electronic component 13 is mounted on the back surface 34b of the collective circuit board 34. The substrate 35 may be attached and formed.

以上、説明したような構造及び製造方法によって、発光ダイオードや半導体レーザ等の光半導体チップやその他の周辺の電子部品が組み込まれた光半導体パッケージの小型化が図られる。このような光半導体パッケージの小型化に伴って、光ピックアップモジュール及びこの光ピックアップモジュールを組み込んだ光ディスク装置の小型化及び高機能化の実現が可能となった。   As described above, the structure and the manufacturing method as described above can reduce the size of an optical semiconductor package in which an optical semiconductor chip such as a light emitting diode or a semiconductor laser and other peripheral electronic components are incorporated. With the miniaturization of such an optical semiconductor package, it has become possible to realize miniaturization and high functionality of an optical pickup module and an optical disk apparatus incorporating the optical pickup module.

本発明に係る光半導体パッケージを光半導体チップの実装面から見た斜視図である。It is the perspective view which looked at the optical semiconductor package which concerns on this invention from the mounting surface of the optical semiconductor chip. 上記光半導体パッケージを電子部品の実装面から見た斜視図である。It is the perspective view which looked at the said optical semiconductor package from the mounting surface of the electronic component. 上記図１に示した光半導体パッケージのＡ−Ａ断面図である。It is AA sectional drawing of the optical semiconductor package shown in the said FIG. 上記光半導体パッケージにおける回路基板の表面の斜視図である。It is a perspective view of the surface of the circuit board in the said optical semiconductor package. 上記光半導体パッケージにおける回路基板の裏面の斜視図である。It is a perspective view of the back surface of the circuit board in the said optical semiconductor package. 上記光半導体パッケージを実装したときの側面図である。It is a side view when the said optical semiconductor package is mounted. 第１の電極パターンが形成された集合回路基板の表面を示す斜視図である。It is a perspective view which shows the surface of the collective circuit board in which the 1st electrode pattern was formed. 第２の電極パターンが形成された集合回路基板の裏面を示す斜視図である。It is a perspective view which shows the back surface of the collective circuit board in which the 2nd electrode pattern was formed. 集合ベース基板の斜視図である。It is a perspective view of an assembly base board. 電子部品を集合回路基板の裏面に実装する工程を示す図である。It is a figure which shows the process of mounting an electronic component on the back surface of an aggregate circuit board. 上記集合回路基板と集合ベース基板とを接合する工程を示す図である。It is a figure which shows the process of joining the said collective circuit board and a collective base board. 上記集合回路基板と集合ベース基板とを対向配置した状態を示す図である。It is a figure which shows the state which has arrange | positioned the said collective circuit board and the collective base board facing each other. 光半導体チップを上記集合回路基板の表面に実装する工程を示す図である。It is a figure which shows the process of mounting an optical semiconductor chip on the surface of the said collective circuit board. 樹脂封止して完成した集合光半導体パッケージの断面図である。It is sectional drawing of the collective optical semiconductor package completed by resin sealing. 上記集合光半導体パッケージを個々の光半導体パッケージにダイシングする工程を示す図である。It is a figure which shows the process of dicing the said collective optical semiconductor package into each optical semiconductor package. 従来の光半導体パッケージの構造を示す斜視図である。It is a perspective view which shows the structure of the conventional optical semiconductor package.

符号の説明Explanation of symbols

１１ 光半導体パッケージ
１２ 光半導体チップ
１３ 電子部品
１４ 回路基板
１５ ベース基板
１６ 樹脂体
１７ 外部接続電極
１８ 凹部
２１ 第１の電極パターン
２２ 第２の電極パターン
２３ 第１のスルーホール
２４ 第２のスルーホール
３１ 集合光半導体パッケージ
３４ 集合回路基板
３５ 集合ベース基板
３８ 導電接合層
DESCRIPTION OF SYMBOLS 11 Optical semiconductor package 12 Optical semiconductor chip 13 Electronic component 14 Circuit board 15 Base board 16 Resin body 17 External connection electrode 18 Recessed part 21 1st electrode pattern 22 2nd electrode pattern 23 1st through-hole 24 2nd through-hole 31 Collective optical semiconductor package 34 Collective circuit board 35 Collective base board 38 Conductive bonding layer

Claims (4)

表面に光半導体チップを実装する第１の電極パターン、裏面に他の電子部品を実装する第２の電極パターン、側面に第１のスルーホールを有する回路基板と、
前記第２の電極パターン上に実装される電子部品を収容する凹部または窓孔、前記第１のスルーホールと導通する第２のスルーホールを有して前記回路基板の裏面に一体に接合されるベース基板とを備え、前記ベース基板の裏面に外部接続電極を設けると共に、前記第１の電極パターン及び前記第２の電極パターンを前記第２のスルーホールを介して導通させたことを特徴とする光半導体パッケージ。 A first electrode pattern for mounting an optical semiconductor chip on the front surface, a second electrode pattern for mounting other electronic components on the back surface, a circuit board having a first through hole on the side surface;
A recess or window hole for accommodating an electronic component mounted on the second electrode pattern, and a second through hole that conducts with the first through hole are integrally joined to the back surface of the circuit board. And a base substrate, and external connection electrodes are provided on the back surface of the base substrate, and the first electrode pattern and the second electrode pattern are made conductive through the second through hole. Optical semiconductor package. 前記回路基板と前記ベース基板とをペースト状またはフィルム状の異方性導電部材を介して接合する請求項１記載の光半導体パッケージ。 The optical semiconductor package according to claim 1, wherein the circuit board and the base substrate are joined via a paste-like or film-like anisotropic conductive member. 前記回路基板と前記電子部品とをペースト状またはフィルム状の異方性導電部材を介して接合する請求項１記載の光半導体パッケージ。 The optical semiconductor package according to claim 1, wherein the circuit board and the electronic component are joined via a paste-like or film-like anisotropic conductive member. 光半導体チップを実装する第１の電極パターンを集合回路基板の表面に、他の電子部品を実装する第２の電極パターンを集合回路基板の裏面に複数形成し、側面に第１のスルーホールを設ける集合回路基板形成工程と、
側面に前記第１のスルーホールと導通する第２のスルーホール、裏面に外部接続電極を設けると共に、前記第２の電極パターン上に実装される電子部品を収容する凹部または窓孔を形成する集合ベース基板形成工程と、
前記第２の電極パターン上にペースト状またはフィルム状の異方性導電部材を介して電子部品を実装した後、前記集合回路基板の裏面に前記集合ベース基板を前記異方性導電部材によって接合する基板接合工程と、
前記第１の電極パターン上に光半導体チップを実装した後、集合回路基板の表面を樹脂で封止する樹脂封止工程と、
前記集合ベース基板と一体になった集合回路基板を個々の光半導体チップに分断するチップ分割工程とを備えたことを特徴とする光半導体パッケージの製造方法。 A plurality of first electrode patterns for mounting an optical semiconductor chip are formed on the surface of the collective circuit board, and a plurality of second electrode patterns for mounting other electronic components are formed on the back surface of the collective circuit board, and first through holes are formed on the side surfaces. An assembly circuit board forming step to be provided;
A set of a second through hole that is electrically connected to the first through hole on a side surface, an external connection electrode on the back surface, and a recess or a window hole that accommodates an electronic component mounted on the second electrode pattern A base substrate forming process;
An electronic component is mounted on the second electrode pattern via a paste-like or film-like anisotropic conductive member, and then the collective base substrate is bonded to the back surface of the collective circuit substrate by the anisotropic conductive member. A substrate bonding process;
A resin sealing step of sealing the surface of the collective circuit board with a resin after mounting the optical semiconductor chip on the first electrode pattern;
A method of manufacturing an optical semiconductor package, comprising: a chip dividing step of dividing an aggregate circuit board integrated with the aggregate base substrate into individual optical semiconductor chips.
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