JP2005332361A5 - - Google Patents

Download PDF

Info

Publication number
JP2005332361A5
JP2005332361A5 JP2004343921A JP2004343921A JP2005332361A5 JP 2005332361 A5 JP2005332361 A5 JP 2005332361A5 JP 2004343921 A JP2004343921 A JP 2004343921A JP 2004343921 A JP2004343921 A JP 2004343921A JP 2005332361 A5 JP2005332361 A5 JP 2005332361A5
Authority
JP
Japan
Prior art keywords
instruction
program
program instructions
data path
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004343921A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005332361A (ja
Filing date
Publication date
Priority claimed from GB0410986A external-priority patent/GB2414308B/en
Application filed filed Critical
Publication of JP2005332361A publication Critical patent/JP2005332361A/ja
Publication of JP2005332361A5 publication Critical patent/JP2005332361A5/ja
Pending legal-status Critical Current

Links

JP2004343921A 2004-05-17 2004-11-29 プログラム命令圧縮装置および方法 Pending JP2005332361A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0410986A GB2414308B (en) 2004-05-17 2004-05-17 Program instruction compression

Publications (2)

Publication Number Publication Date
JP2005332361A JP2005332361A (ja) 2005-12-02
JP2005332361A5 true JP2005332361A5 (https=) 2007-02-22

Family

ID=32527186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004343921A Pending JP2005332361A (ja) 2004-05-17 2004-11-29 プログラム命令圧縮装置および方法

Country Status (3)

Country Link
US (1) US7302552B2 (https=)
JP (1) JP2005332361A (https=)
GB (1) GB2414308B (https=)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
GB2420884B (en) * 2004-12-03 2009-04-15 Picochip Designs Ltd Processor architecture
US7581082B2 (en) * 2005-05-13 2009-08-25 Texas Instruments Incorporated Software source transfer selects instruction word sizes
GB2430773A (en) * 2005-10-03 2007-04-04 Advanced Risc Mach Ltd Alignment of variable length program instructions
US9069547B2 (en) * 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
US20080077772A1 (en) * 2006-09-22 2008-03-27 Ronen Zohar Method and apparatus for performing select operations
US7620797B2 (en) * 2006-11-01 2009-11-17 Apple Inc. Instructions for efficiently accessing unaligned vectors
US7624251B2 (en) * 2006-11-01 2009-11-24 Apple Inc. Instructions for efficiently accessing unaligned partial vectors
CN101398752B (zh) * 2007-09-29 2011-08-31 国际商业机器公司 重叠指令存取单元和重叠指令存取方法
GB2454865B (en) 2007-11-05 2012-06-13 Picochip Designs Ltd Power control
US20100312991A1 (en) * 2008-05-08 2010-12-09 Mips Technologies, Inc. Microprocessor with Compact Instruction Set Architecture
WO2009137108A1 (en) * 2008-05-08 2009-11-12 Mips Technologies, Inc. Microprocessor with compact instruction set architecture
GB2470037B (en) 2009-05-07 2013-07-10 Picochip Designs Ltd Methods and devices for reducing interference in an uplink
GB2470891B (en) 2009-06-05 2013-11-27 Picochip Designs Ltd A method and device in a communication network
GB2470771B (en) 2009-06-05 2012-07-18 Picochip Designs Ltd A method and device in a communication network
GB2474071B (en) 2009-10-05 2013-08-07 Picochip Designs Ltd Femtocell base station
GB2482869B (en) 2010-08-16 2013-11-06 Picochip Designs Ltd Femtocell access control
GB2484489A (en) 2010-10-12 2012-04-18 Advanced Risc Mach Ltd Instruction decoder using an instruction set identifier to determine the decode rules to use.
GB2489716B (en) 2011-04-05 2015-06-24 Intel Corp Multimode base system
GB2489919B (en) 2011-04-05 2018-02-14 Intel Corp Filter
GB2491098B (en) 2011-05-16 2015-05-20 Intel Corp Accessing a base station
US20160179542A1 (en) * 2014-12-23 2016-06-23 Patrick P. Lai Instruction and logic to perform a fused single cycle increment-compare-jump
JP6907487B2 (ja) 2016-09-09 2021-07-21 富士通株式会社 並列処理装置、並列処理装置の制御方法、及び並列処理装置に用いられる制御装置
KR102688577B1 (ko) 2016-09-19 2024-07-26 삼성전자주식회사 전자 장치, vliw 프로세서 및 그 제어 방법들

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057837A (en) * 1987-04-20 1991-10-15 Digital Equipment Corporation Instruction storage method with a compressed format using a mask word
GB2289354B (en) * 1994-05-03 1997-08-27 Advanced Risc Mach Ltd Multiple instruction set mapping
JP2931890B2 (ja) * 1995-07-12 1999-08-09 三菱電機株式会社 データ処理装置
US5826054A (en) * 1996-05-15 1998-10-20 Philips Electronics North America Corporation Compressed Instruction format for use in a VLIW processor
US5922065A (en) * 1997-10-13 1999-07-13 Institute For The Development Of Emerging Architectures, L.L.C. Processor utilizing a template field for encoding instruction sequences in a wide-word format
US6101592A (en) * 1998-12-18 2000-08-08 Billions Of Operations Per Second, Inc. Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
JP4502532B2 (ja) * 2001-02-23 2010-07-14 株式会社ルネサステクノロジ データ処理装置
KR100991700B1 (ko) * 2002-08-16 2010-11-04 코닌클리케 필립스 일렉트로닉스 엔.브이. 처리 장치, 처리 방법 및 컴퓨터로 판독가능한 기록 매체
US7574583B2 (en) * 2002-09-24 2009-08-11 Silicon Hive B.V. Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor

Similar Documents

Publication Publication Date Title
JP2005332361A5 (https=)
US9804851B2 (en) Operand size control
JPH117387A5 (https=)
JP5712295B2 (ja) 次命令タイプフィールド
KR20130016246A (ko) 다중 명령 세트에 의해 사용되는 레지스터 간의 매핑
JP2014194755A (ja) 複数の試験ソースに対するｏｒ試験及びａｎｄ試験機能を提供するために命令をフュージングする方法及び装置
WO2014197310A1 (en) Systems and methods for preventing unauthorized stack pivoting
JP2004054585A5 (https=)
JP2005332361A (ja) プログラム命令圧縮装置および方法
CN104981771A (zh) 基于标量寄存器数据值的向量寄存器寻址和功能
WO2012136975A1 (en) A data processing apparatus and method for performing vector operations
WO2018007782A1 (en) An apparatus and method for performing a rearrangement operation
WO2013085491A1 (en) System, apparatus and method for translating vector instructions
US10409602B2 (en) Vector operand bitsize control
JP2014510351A5 (https=)
JP7377208B2 (ja) データ処理
JP2009526300A (ja) マイクロプロセッサ用の命令セット
CN107851022B (zh) 向量长度查询指令
US7234043B2 (en) Decoding predication instructions within a superscaler data processing system
CN112181495A (zh) 一种断言寄存器操作数指令的实现方法和装置
JP2008129667A (ja) プログラマブルコントローラ
Briejer et al. Energy Efficient Branch Prediction for the Cell BE SPU
KR20070092093A (ko) 다중 마이크로컨트롤러 시스템, 명령어, 및 그의 명령어실행 방법
JPWO2023170373A5 (https=)
JP2002073326A (ja) プログラム実行装置及びプログラム実行方法