JP2005331329A - Method for correcting time - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for correcting time which enables one to correct time instant with a little labor. <P>SOLUTION: In an apparatus provided with a CPU1 having a time operation function of a time-piece and an indicator 3 to which time data calculated with the time operation function is supplied from the CPU1 and indicating time, the time data is stored in a non-volatile memory 4 at every specific time unit. When a source voltage is lowered below a function guarantee voltage and the CPU1 is reset, the time data immediately before the reset which is stored in the non-volatile memory 4 are read out and indicated with the indicator 3. Simultaneously, the start time is calculated from the read-out time data, so as to correct the time indicated after the reset. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a time correction method, and in particular, a time in a device including a CPU having a time calculation function of a clock and a display that displays time by supplying time data calculated by the time calculation function from the CPU. Regarding the correction method.

  Conventionally, as shown in FIG. 15, a clock display function in a device such as an in-vehicle meter is supplied with time data from a CPU 1 having a time calculation function of a real-time clock to a display 3 such as an LCD (liquid crystal display). Is displayed. The power to the CPU 1 is supplied from the battery (+ B) after being stabilized to a power supply voltage such as 5 V by the stabilized power circuit 2. When the power supply voltage to be supplied is abnormal, for example, when the power supply voltage drops below the operation guarantee voltage of the CPU 1, the watchdog timer 5 provided in the stabilized power supply circuit 2 or the like is provided so that the function failure of the CPU 1 does not occur. The CPU 1 is reset by the function of monitoring the power supply.

  When power is supplied again after resetting the CPU 1, as shown in the flowchart of FIG. 16, the CPU 1 is initialized (step S41), and then the time calculation processing of the real-time clock is resumed (step S42).

  However, the initialization initializes the time displayed on the display 3 to be “0:00” or “10:00” and starts from there, so in the case of a slight stop time of about several minutes. However, when correcting the time on the clock display, both the hour and minute must be corrected, which is troublesome.

  Accordingly, an object of the present invention is to provide a time correction method capable of correcting the time with little effort in view of the above-described conventional problems.

  According to a first aspect of the present invention, there is provided a time correction method comprising: a CPU having a time calculation function of a clock; and a display that displays time by supplying time data calculated by the time calculation function from the CPU. The time data is stored in a non-volatile memory every predetermined time unit, and the time immediately before the reset stored in the non-volatile memory when the power supply voltage falls below the operation guarantee voltage and the CPU is reset. The data is read out and displayed on the display, and the time displayed after the reset is corrected by calculating the start time from the read time data.

  According to a second aspect of the present invention, there is provided a time correction method having a time calculation function of a clock, storing time data calculated by the time calculation function in an internal memory every predetermined time unit, and time data from the CPU. The time data is stored in a non-volatile external memory for each predetermined time unit, the power supply voltage drops below the guaranteed operating voltage, and the CPU When reset, the validity of the time data immediately before the reset stored in the internal memory is determined. If there is validity, the time data is supplied to the display for display and the time data is displayed. When the start time is calculated and the validity is not valid, the time data stored in the external memory is supplied to the display for display and the start is started from the time data. By calculating the time, characterized by modifying the time displayed after a reset.

  According to a third aspect of the present invention, in the time adjustment method according to the first or second aspect, the time data is stored in a nonvolatile memory every minute unit.

  According to a fourth aspect of the present invention, in the time correction method according to the third aspect, the nonvolatile memory is composed of one word composed of a time address area composed of a plurality of bits and a time data area composed of a plurality of bits in each address. The time data represented has a time data storage area having a plurality of addresses, and the time data area sequentially stores the time data in minutes, from among the plurality of stored time data, The time data stored immediately before the reset is read out.

  According to a fifth aspect of the present invention, in the time correction method according to the fourth aspect of the invention, the time data is rewritten from the first address every time it is stored from the first address to the last address of the plurality of addresses, and the time address area is It has an odd number of bits that are rewritten from all 0s to all 1s or from all 1s to all 0s each time the time data is rewritten.

  According to a sixth aspect of the present invention, in the time correction method according to the fifth aspect, when the time data is stored, the majority decision of the odd number of bits in the time address area is performed, and the address where the result of the majority decision is changed is changed. When the change point is detected, the time data stored at the address before the address detected as the change point is read as the time data immediately before the reset, and the change point is detected. If not, the head address is regarded as a change point, and the time data stored at the final address is read as the time data immediately before the reset.

  According to the first aspect of the present invention, when the clock display deviates from real time due to a power failure, the time can be corrected with a little effort.

  According to the second aspect of the present invention, when the clock display deviates from real time due to power supply abnormality, the time can be corrected with a little effort. If the time data stored in the internal memory of the CPU cannot be used, the time can be corrected using the time data stored in the non-volatile external memory. In addition, by storing the time data in both the internal memory and the external memory, the time display is unlikely to return to the initial value (0:00 or 1:00) even when the data is destroyed due to power failure, etc. Will improve.

  According to the third aspect of the present invention, if the time during which the clock has been stopped due to a power supply abnormality is within one minute, the corrected time is automatically displayed without performing manual correction work after the abnormality is canceled. Can do. Even when the power supply is abnormal for a short time (such as several minutes) of 1 minute or more, the time can be adjusted with a little effort.

  According to the fourth aspect of the present invention, it is possible to effectively store time data used for time correction after the power supply abnormality is canceled.

  According to the invention of claim 5, a plurality of time data can be stored in a rewritable manner.

  According to the sixth aspect of the invention, the time data immediately before the reset can be accurately read.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a device that implements a time correction method according to the best mode of the present invention. Here, a case where the device is an in-vehicle od / trip meter will be described.

  The in-vehicle od / trip meter has a CPU (microcomputer) 1, a stabilized power supply circuit 2, a display 3 and a nonvolatile memory 4.

  The CPU 1 executes a meter function of a vehicle odometer or trip meter and a time calculation function of a real-time clock.

  The stabilized power supply circuit 2 converts a voltage (for example, 12V) supplied from the battery (+ B) power supply into a stabilized voltage such as 5V, and supplies it to the CPU 1 as a power supply. The stabilized power supply circuit 2 includes a watchdog timer 5 and monitors a power supply voltage supplied to the CPU 1.

  The display 3 is composed of an LCD or the like. Meter data is supplied from the CPU 1, meter display for displaying an odometer indicating the total travel distance of the vehicle or a trip meter indicating any travel distance of the vehicle, and time data is supplied. The time display of the real time clock is performed.

  The non-volatile memory 4 is provided as an external memory of the CPU 1, for example, an EEPROM for storing information for meter display such as the total travel distance, and a part of the address is used for the time correction function. . In other words, the time data generated by the time calculation function of the CPU 1 is supplied to the display 3 and also to the nonvolatile memory 4, and the nonvolatile memory 4 converts a plurality of time data into predetermined time units, for example, Store every minute.

  In the above configuration, the time correction method according to the present invention is performed as follows. The watchdog timer 5 provided in the stabilized power supply circuit 2 is cleared of the timed operation by a clear signal supplied from the CPU 1 at a time interval shorter than the time limit value of the timer while the CPU 1 is operating normally. It is configured as follows. However, when the operation of the CPU 1 is abnormal, for example, when the power supply voltage supplied from the stabilized power supply circuit 2 falls below the operation guarantee voltage of the CPU 1 and the operation of the CPU 1 becomes abnormal, the clear signal is not supplied. The timed operation of the watchdog timer 5 is not cleared and the time is up, and an abnormality detection signal is output from the watchdog timer 5 and supplied to the reset input of the CPU 1. Thereby, the CPU 1 is reset.

  When such a reset operation is performed, when power is supplied to the CPU 1 again after reset is released, the CPU 1 is initialized as shown in the flowchart of FIG. 2 (step S1). Next, the CPU 1 reads out the time data immediately before the reset from the time data stored in the nonvolatile memory 4 in units of minutes and supplies it to the display 3 (step S2). Thereby, the display 3 displays the time immediately before the reset. Next, the CPU 1 resumes the time calculation process (step S3), and calculates a start time from the read time data. Thereby, the display 3 displays the time starting from the time immediately before the reset.

  Therefore, if the time during which the real-time clock has been stopped by the reset operation is within one minute, the real-time time is displayed on the display unit 3 without any correction work. Even when the power supply is abnormal for a short time (such as several minutes) of 1 minute or more, the time can be adjusted with a little effort.

  Next, a clock function including the time correction method of the present invention will be described.

1. Outline First, the operation of storing time data will be described with reference to the flowchart of FIG. 3, which is a part of the subroutine performed during the time calculation process of step S3 in the flowchart of FIG. When the CPU 1 is operating normally, as shown in the flowchart of FIG. 3, an interrupt is generated every second by using the real time clock timer function of the CPU 1 from the time when the battery (+ B) power source is connected (step S11). If an interrupt occurs, the count value (RAM value) of a second counter (RAM) (not shown) that is built in the CPU 1 is updated (step S12). This interruption occurs every second even when the CPU 1 is in the sleep mode. The updated RAM value is stored in an internal memory of the CPU 1 (not shown) such as a RAM.

  Next, based on the count of the second counter (RAM), the CPU 1 determines whether or not 1 minute has passed (step S13). If the answer is no, the process returns. If yes, the process returns to step S14. move on.

  In step S14, the count value (RAM value) of a counter (RAM) (not shown) that is built in the CPU 1 is updated. That is, the RAM value of the minute counter (RAM) is updated every 1 minute. The updated RAM value is stored in the above-described RAM.

  Next, the CPU 1 refers to the updated write address (RAM), and writes the RAM value of the minute counter (RAM) stored therein into the non-volatile memory (hereinafter referred to as EEPROM) 4 (step S15). ). Basically, the RAM value of the minute counter (RAM) is written into the EEPROM 4 every minute, but is written into the EEPROM 4 at the end of the correct time and at the end of the correction mode. After writing to the EEPROM 4, the write address (RAM) storing the counter value (RAM) to be written to the EEPROM 4 next time is updated (step S16).

When the ignition (IG) of the vehicle is turned on, the CPU 1 calculates the current time (H: M (hour: minute)) from the minute counter (RAM) value stored in the RAM according to the following formula, Display.
Minute counter (RAM) / 60 = H (hours)
Minute counter (RAM)% 60 = M (minute)
In the above formula, “/” and “%” are arithmetic operators representing division and remainder, respectively.

2. Data structure 2.1. EEPROM Data Structure The EEPROM 4 has a meter data storage area and a time data storage area. FIG. 4 shows the data structure of the time data storage area. In FIG. 4, among the memory addresses of the EEPROM 4, for example, addresses 91U to 101U are used for storing time data.

  The time data storage area is one word composed of a time data area consisting of 11 bits from 0 to 10 and a time address area consisting of 5 bits from 11 to 15 at each address of 91U to 101U. Each represented time data is stored, and a total of 11 words are secured. The data in the time data area is minute data. That is, since the clock display range is 1:00 to 12:59, the minute data range is 60 to 779 (decimal number).

The possible data range of the time data area and the time address area is as follows.
Time data area: 0x03C to 0x30B
Time address area: 0x00 or 0x1F

2.2. RAM Data Structure The RAM data structure used in the real-time clock function is shown in FIG. As the minute counter (RAM) value, the same time data is stored at four addresses.

3. As for the EEPROM reading time data, basically, the RAM value is preferentially adopted, and if the RAM value cannot be adopted as an unreliable value, the data stored in the EEPROM 4 instead of the RAM value (hereinafter referred to as the EEPROM value). ) Is read and adopted. That is, when the CPU 1 wakes up, a RAM majority decision is made, and a RAM value or an EEPROM value is read based on the decision result.

  FIG. 6 is a diagram for explaining the RAM majority decision. If the four time data RAM [0], RAM [1], RAM [2] and RAM [3] stored simultaneously at the four addresses are A, B, C, and D, respectively, the determination shown in FIG. The majority decision is made by the order method, and the value of the majority decision is adopted. The update order of the RAM array is set as A → B → C → D. Even when the CPU 1 is reset during the update, the majority result is determined by the determination order of FIG. Is done.

  FIG. 7 is a diagram showing the relationship between RAM data and adopted data. That is, whether the RAM value or the EEPROM value is adopted data depends on the majority decision result of the minute counter (RAM) value, the validity of the minute counter, the majority decision result of the time address area of the EEPROM 4, and the time address area of the EEPROM 4 The validity, the majority decision result of the second counter (RAM) value, and the validity of the second counter are determined by OK or NG.

FIG. 8 is a diagram showing criteria for determining the validity of the minute counter, the address area, and the second counter. The validity of the minute counter is OK when the RAM value is 60 to 779, and NG otherwise. The validity of the second counter is OK when the RAM value is 0 to 59, and NG otherwise. The validity of the address area is OK if the address point and data of the EEPROM value are the following values (AND conditions), and NG otherwise.
Address point: 91-101, data: 0x00 or 0x1F

Next, processing performed when the CPU 1 performs WakeUp will be described based on the relationship between the RAM data and the adopted data shown in FIG.
(1) No. When 1, no processing.
(2) No. 2 and no. 3 Resets the hour / second counter (RAM) (= 0).
・ Initialize clock-related registers.
(3) No. 4-No. In 24, when an EEPROM read error has occurred, the address area is set to address: head address = 91, data: 0x1F.
Reset the minute counter (RAM) (= 60 [minutes]).
-Reset the second counter (RAM) (= 0 [seconds]).
・ Initialize clock-related registers.
(4) No. 4-No. At 24, when an EEPROM read error has not occurred, data is read in order from the head address, and a majority decision of the bit contents of 11 to 15 bits (time address area) is made. The 11 to 15 bits are set to all 0 (00000) or all 1 (11111), but may be data other than all 0 or all 1 (for example, 010011, 11100, etc.) due to a power failure. In such a case, according to the majority decision, 010011 is regarded as all 0 and 11100 is regarded as all 1.
・ The address where the result of majority decision is changed is taken as the change point. If a change point is detected, the majority decision is not made thereafter.

  An example of the EEPROM contents in the time data storage area in this case is shown in FIG. In FIG. 9, the bit data in the time address area is 0x00 for addresses 91U to 93U and 0x1F for 94U to 101U, so address 94U is detected as a change point.

• If the change point cannot be detected, the start address is taken as the change point.

  An example of the EEPROM contents in the time data storage area in this case is shown in FIG. In FIG. 10, since the bit data in the time address area is 0x00 at all addresses, the address 91U becomes the changing point.

Store the change point address and data in RAM. For example, in the case of FIG. 9, address: 94U and data: 0x00 are stored in the RAM. In the case of FIG. 10, the address: 91U and the data: 0x1F are stored in the RAM.

(Change point-1) The data at the address (that is, the address immediately before the change point address) is read data (time data). However, when the head address is a change point, the data of the last address is read data (time data). For example, in the case of FIG. 9, since the address of the change point is the head address 94U, the data stored in the previous address 93U is read (adopted) data: 74 [minutes], and in the case of FIG. Since the address of the change point is the start address 91U, the data stored in the final address 101U is read (adopted) data: 90 [minutes].

-Validate the time data of the read EEPROM. The validity criterion is the same as the minute counter validity criterion shown in FIG.
When the validity determination result is OK, the read data is stored in the minute counter (RAM).
When the validity determination result is NG, the minute counter (RAM) is reset (= 60 [minutes]).
-Reset the second counter (RAM) (= 0 [seconds]).
・ Initialize clock-related registers.

  Although the process is performed as described above, there is a unique example in which two change points are generated, which will be described below.

  Assume that the data shown in FIG. 11A is written in the time data storage area of the EEPROM 4. In this case, at the time of WakeUp, when the data of the EEPROM 4 is adopted, + B off → on, IG off → on, 1:30 data is read and “1:30” is displayed.

  Thereafter, it is left for 11 minutes, and the EEPROM is removed when “1:41” is displayed. After desorption, leave for 2 minutes, and install “EEPROM” when “1:43” is displayed. Leave for 2 minutes after installation, turn IG on → off, + B on → off. In this case, two change points are generated as shown in FIG.

  This is because when the minute counter (RAM) value is written (entry) in the EEPROM 4, the write address is incremented by 1 regardless of the write error.

  Therefore, at the time of WakeUp again, when the data of EEPROM4 is adopted, when + B off → on, IG off → on, 1:32 data is read from the first change point and “1:32” is displayed. The

  Next, the process at the time of WakeUp will be described with reference to the flowcharts shown in FIGS.

  First, it is determined whether the majority result of the minute counter (RAM) value, the validity of the minute counter (RAM), the majority result of the address area, and the validity of the address area are all okay (step S301).

  If the answer is yes, then it is determined whether the majority result or validity of the second counter (RAM) is okay (step S302). If the answer is no, the process ends. If yes, the process proceeds to step S303. In step S303, the second counter (RAM) is initialized (reset) (= 0 [seconds]). Next, initialization of the clock-related registers is performed (step S304), and then the processing is terminated.

  On the other hand, if the answer to step S301 is no, it is then determined whether or not an EEPROM 4 read error has occurred (step S305). If the answer is yes (ie, if an EEPROM read error has occurred), then the address area (RAM) is set to the top address (= 91U) (step S306), and then the address data (RAM) is set. It is set to 0x1F (that is, all 1) (step S307).

  Next, the minute counter (RAM) is initialized (= 60 [minutes]) (step S308), then the second counter (RAM) is initialized (= 0 [seconds]) (step S309), then the clock The related registers are initialized (step S310), and the process is then terminated.

  On the other hand, if the answer to step S305 is no (ie, no EEPROM read error has occurred), then time data is read from the head address (step S311).

  Next, the address (i) is updated (step S312), and then it is determined whether or not reading to the last address is completed (i> 11) (step S313). If the answer is no, the process proceeds to step S314, and if yes, the process proceeds to step S318.

  In step S314, time data of (address area + i) is acquired, then majority processing is performed (step S315), and then it is determined whether there is a change point (step S316). If the answer is no, the process proceeds to step S317, and if yes, the process proceeds to step S319. In step S317, the address (i) is incremented by 1 (step S317), and then the process returns to step S313.

  On the other hand, in step S318, the start address is set as the change point address, and then the time address data at the change point and the time data to be read are acquired based on the change point (step S319). Here, the time data to be read based on the change point is the time data stored at the address immediately before the change point address, or the time data stored at the last address when the change point is the start address. is there.

  Next, it is determined whether or not the validity of the read time data is OK (step S320). If the answer is yes, then the read data is stored in the minute counter (RAM) (step S321). ), The process proceeds to step S323, and if the answer is no, then the minute counter (RAM) is initialized (= 60 [minutes] (step S322), and the process proceeds to step S323.

  In step S323, a second counter (RAM) is initialized (= 0 [second]), then a clock related register is initialized (step S324), and then the process is terminated.

4). When writing to EEPROM or writing into EEPROM 4 (entry), a write address and address data are obtained.
The timing for writing (entry) into the EEPROM 4 is when the minute counter (RAM) is updated.
The condition for writing (entry) into the EEPROM 4 includes the end of the correct time, the end of the correction mode, and the update of the minute counter (RAM) during the correction mode.
When writing (entry) to the EEPROM 4, the write address is incremented by 1 regardless of a write error.
• When the write address reaches the final address, move the write address to the top address. At this time, the address data is set to one's complement. That is, 0x1F is set as address data (RAM) when the final address data is 0x00, and 0x00 is set when 0x1F.
• Write (entry into EEPROM) even when a write error occurs.

5). Correct time setting Correct time setting is to reset the minute digit and second data by pressing the clock SW (not shown) within a predetermined time (for example, 0.8 ± 0.08 seconds) during normal clock display. . At the time of resetting, when the minute digit is 00 to 29, the carry to the hour digit is not performed, and when the minute digit is 30 to 59, the carry to the hour digit is performed.

Next, processing at the time of setting the time will be described.
-At the end of the time setting, the time setting value is stored in the minute counter (RAM).
-Reset the second counter (RAM) (= 0 [seconds]).
・ Initialize clock-related registers.
The minute counter (RAM) value in which the correct time value is stored is written (entry) in the EEPROM 4. At the end of the correct time setting, even if the minute counter (RAM) value is the same as before the correct time setting (for example, when the correct time is set while “2:00” is displayed), it is written in the EEPROM 4 ( To enter).

  Next, some examples of processing at the time setting will be described.

(Example 1) When the hour is set on the hour while “1:29” is displayed (with carry to the hour digit)
“10:00” is displayed, and data “10:00” (= 60 [minutes]) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 60 [minutes]) to the EEPROM 4 (entry).

(Example 2) When the hour is set on the hour while “1:30” is displayed (with carry to the hour digit)
“2:00” is displayed, and “2:00” data (= 120 [minutes]) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 120 [minutes]) to the EEPROM 4 (entry).

(Example 3) When the hour is set while “2:00” is displayed (no carry to the hour digit)
“2:00” is displayed, and “2:00” data (= 120 [minutes]) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 120 [minutes]) to the EEPROM 4 (entry).

(Example 4) When the hour is set on the hour while “12:45” is displayed (with carry to the hour digit)
“10:00” is displayed, and data “10:00” (= 60 [minutes]) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 60 [minutes]) to the EEPROM 4 (entry).

6). Correction mode In the correction mode, minute digits and hour digits can be corrected. FIG. 14 shows a mode transition diagram in the correction mode. The correction mode is the minute digit correction mode when the clock SW (not shown) is pressed for a first predetermined time (for example, 0.8 ± 0.08 seconds) or more in the normal clock display, and the second in the minute digit correction mode. When no operation is performed for a predetermined time (for example, 5.0 ± 0.5 seconds) or more, the hour digit correction mode is set. Further, in the time digit correction mode, the second predetermined time (for example, 5.0 ± 0.5 seconds) is set. ) When no operation is performed, the normal clock display is restored. In the minute digit correction mode, the minute digit display on the display unit 3 is blinked, and in the hour digit correction mode, the hour digit display on the display unit 3 is blinked.

Next, processing in the correction mode will be described.
• When the hour digit correction mode ends, the correction value is stored in the minute counter (RAM).
-When the minute digit correction mode is changed to the hour digit correction mode, the minute counter (RAM) is not updated. However, when the minute counter (RAM) is counted up during the hour digit and minute digit correction mode, the minute counter (RAM) is updated and the updated minute counter (RAM) value is written into the EEPROM 4 (entry is entered). ).
At the end of the correction mode, the second counter (RAM) is not reset (= 0 [seconds]) and the clock-related registers are not initialized.
・ If IG is turned off during the correction mode, the correction value is not retained.

  Next, some processing examples in the correction mode will be described.

(Example 1) When the minute counter (RAM) is not counted up in the correction mode (1)
・ Change to correction mode while “2:00” is displayed, and correct to “2:05” in minute digit correction mode.
At the end of the hour digit correction mode, “2:05” data (= 125 [minutes]) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 125 [minutes]) to the EEPROM 4 (entry).

(Example 2) When the minute counter (RAM) is counted up during the minute digit correction mode, the mode shifts to the correction mode at about 2: 5: 55.
-The minute counter (RAM) value was updated when trying to correct the minute digit. The display is also “2:06”.
The minute counter (RAM) value (= 126 [minutes]) updated during the correction mode is written (entered) into the EEPROM 4.
-Correct to "2:10" in minute digit correction mode.
When the hour digit correction mode ends, “2:10” data (= 130 [minutes]) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 130 [minutes]) to the EEPROM 4 (entry).

(Example 3) When the minute counter (RAM) value is counted up just before the correction mode is finished and the correction value is written to the EEPROM (entry) ・ The mode shifts to the correction mode while “2:10” is displayed, and the minute digits Correct to “2:15” in the correction mode.
When the hour digit correction mode ends, “2:15” data (= 135 [minutes]) is stored in the minute counter (RAM).
The minute counter (RAM) was updated immediately before writing (entry) the minute counter (RAM) value (= 135 [minute]) to the EEPROM 4, and the minute counter (RAM) value became 136 [minute].
In the EEPROM 4, “2:16” data (= 136 [minutes]) is written (entered). At this time, the data “2:15” (= 135 [minutes]) is not written (not entered) in the EEPROM 4.

(Example 4) When the minute counter (RAM) is not counted up in the correction mode (2)
・ Change to correction mode while “2:20” is displayed, do not operate clock SW in correction mode, or correct to “2:20” in minute digit correction mode.
At the end of the hour digit correction mode, “2:20” data (= 140 [minutes]) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 140 [minutes]) to the EEPROM 4 (entry).

(Example 5) When the minute counter (RAM) is counted up in the hour digit correction mode. The mode shifts to the correction mode at around 2:59:53.
・ In minute digit correction mode, switch to the hour digit correction mode without operating the SW for more than 5 seconds.
-The minute counter (RAM) value was updated when trying to correct the hour digits. The display is also “3:00”.
The minute counter (RAM) value (= 180 [minutes]) updated during the correction mode is written (entered) into the EEPROM 4.
-Correct to "1:00" in hour digit correction mode.
At the end of the hour digit correction mode, data of “10:00” (= 60 ([minute])) is stored in the minute counter (RAM).
Write the minute counter (RAM) value (= 60 [minutes]) to the EEPROM 4 (entry).

  As described above, when the above-described time correction processing is performed, when the clock display displayed on the display device 3 after the reset is delayed in minutes from real time, the normal clock display is shifted to the minute digit correction mode. Then, the work is adjusted in the direction of adding a minute digit and adjusted in real time. After the operation is completed, when waiting for about 10 seconds, the normal clock display is automatically returned to the normal clock display that matches the real time. .

  Also, if it is delayed from the real time even in the hour digit unit, when shifting from the minute digit correction mode to the hour digit correction mode, work is performed to adjust the hour digit number in real time, and waits for about 5 seconds after the work is completed. Then, the display automatically returns to the normal clock display, and the normal clock display in real time is obtained.

  In the conventional case, since the clock display is initialized to 0:00 or 1:00 at the time of resetting, it is necessary to correct both the minute digit and the hour digit. If there is a delay, the time is automatically corrected without any correction work, and the real-time time is displayed on the display 3. Also, if the delay is in minutes, only the minute digits need be corrected, so the driver can correct the time with little effort.

  As described above, the embodiment of the present invention has been described. However, the present invention is not limited to this, and various modifications and applications are possible.

It is a block diagram of the apparatus which implements the time correction method which concerns on the best form of this invention. It is a flowchart which shows the operation | movement at the time of power-on in the apparatus of FIG. 3 is a flowchart showing a time data storing operation, which is a part of a subroutine performed during the time calculation process of step S3 in the flowchart of FIG. It is a figure which shows the data structure of the time data storage area in EEPROM of the apparatus of FIG. It is a figure which shows the data structure of RAM used by a real-time clock function. It is a figure explaining the majority decision of RAM data. It is a figure which shows the relationship between RAM data and adoption data. It is a figure which shows the determination criteria of the validity of a minute counter, an address area, and a second counter. It is a figure which shows the example of the EEPROM content of the time data storage area for demonstrating the detection of a change point. It is a figure which shows the example of the EEPROM content of the time data storage area for demonstrating the detection of a change point. (A) And (B) is a figure which shows the example of the EEPROM content of the time data storage area for demonstrating the detection of a change point in case two change points arise. It is a flowchart which shows the process at the time of WakeUp. It is a flowchart which shows the process at the time of WakeUp. The mode transition diagram at the time of correction mode is shown. It is a block diagram of the apparatus which has the conventional real-time clock display function. It is a flowchart which shows the operation | movement at the time of power-on in the apparatus of FIG.

Explanation of symbols

1 CPU
2 Stabilized power supply circuit 3 Display 4 EEPROM (nonvolatile memory)
5 Watchdog timer

Claims (6)

In a device comprising a CPU having a time calculation function of a clock, and a display that displays time by supplying time data calculated by the time calculation function from the CPU,
The time data is stored in the nonvolatile memory every predetermined time unit, and the time data immediately before the reset is stored in the nonvolatile memory when the power supply voltage falls below the operation guarantee voltage and the CPU is reset. A time correction method characterized in that the time displayed after resetting is corrected by calculating the start time from the read time data, while reading out and displaying on the display. A CPU having a time calculation function of a clock, storing time data calculated by the time calculation function in an internal memory every predetermined time unit, and a display for displaying the time when the time data is supplied from the CPU In the equipment provided,
The time data is stored in a non-volatile external memory every predetermined time unit, and when the power supply voltage falls below the operation guarantee voltage and the CPU is reset, the time immediately before the reset stored in the internal memory The validity of the data is determined. If the data is valid, the time data is supplied to the display for display, and the time starting from the time data is calculated. A time correction method comprising: correcting the time displayed after resetting by supplying the time data stored in the display to the display and displaying the time data and calculating a time starting from the time data. The time correction method according to claim 1 or 2,
A time correction method, wherein time data is stored in a non-volatile memory every minute. The time correction method according to claim 3,
The nonvolatile memory stores time data having a plurality of addresses in which time data represented by one word composed of a time address area composed of a plurality of bits and a time data area composed of a plurality of bits is stored in each address. Has an area,
In the time data area, time data in minutes are sequentially stored,
A time correction method, wherein time data stored immediately before resetting is read out from a plurality of stored time data. The time correction method according to claim 4,
The time data is rewritten from the top address again every time it is stored from the top address to the last address of multiple addresses,
The time address area has an odd number of bits that are rewritten from all 0s to all 1s or all 1s to all 0s whenever time data is rewritten. The time correction method according to claim 5,
When the time data is stored, the majority decision of the odd number of bits in the time address area is performed,
Detect the address where the majority decision result has changed as a change point,
When the change point is detected, the time data stored in the address before the address detected as the change point is read as the time data immediately before the reset,
A time correction method characterized in that, when a change point is not detected, a head address is regarded as a change point, and time data stored in a final address is read as time data immediately before the reset.

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