JP2005327865A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a pin hole from being left on a surface of a crystalline silicon film. <P>SOLUTION: An amorphous semiconductor film 3 containing silicon is formed on a substrate 1; and a metal containing layer 4 is formed by adding, to the amorphous semiconductor film 3, a metal element which promotes crystallization of the amorphous semiconductor film 3. By performing first heat treatment upon the metal containing layer 4, the amorphous semiconductor film is crystallized and by irradiating a crystallized semiconductor film 5a to be formed with first laser light, the crystallized semiconductor film 5a is further crystallized. A gettering layer 7 comprised of a semiconductor containing a rate gas element is formed above the crystallized semiconductor film 5a, and the metal element is gettered to the gettering layer 7, thereby removing or reducing the metal element contained in the crystallized semiconductor film 5a. After the gettering layer 7 is removed, the crystallized semiconductor film 5a is irradiated with second laser light or strong light of energy density lower than that of the first laser light, so that a pin hole on the surface of the crystallized semiconductor film 5a is buried. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device having a circuit including thin film transistors (hereinafter referred to as TFTs). Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and a semiconductor device manufactured according to the present invention includes a semiconductor integrated circuit (microprocessor, signal processing) configured using TFTs. A liquid crystal display device having a circuit or a high-frequency circuit), a light-emitting display device, and an electronic device.

  TFTs are often used for driving circuits and pixel portions of liquid crystal display devices and light-emitting display devices (for example, organic EL display devices). When a crystalline silicon film is used for the active layer of the TFT, high field effect mobility can be realized. Since the field effect mobility directly affects the response characteristics of the TFT, it directly affects the display capability of a liquid crystal display device having the TFT as a drive circuit. Therefore, it is necessary to form a crystalline semiconductor film with good quality.

It is known that when a metal element such as nickel is added to crystallize an amorphous silicon film, the metal element serves as a catalyst to promote crystallization, and the temperature required for crystallization decreases. It has also been found that crystallization further proceeds when the crystalline silicon film thus formed is irradiated with a laser. However, if the metal element remains in the crystalline silicon film that is the active layer of the TFT, the electrical characteristics of the TFT may vary. Therefore, it is necessary to remove the metal element from the crystalline silicon film after crystallization. Therefore, the present applicant forms a semiconductor film containing a barrier layer and a rare gas element on the crystalline silicon film in this order, and includes the semiconductor film as a metal element gettering layer, thereby including the semiconductor film in the crystalline silicon film. A method for removing or reducing the metal element is developed (see, for example, Patent Document 1).
JP 2002-324808 A

  In the method for removing or reducing the metal element contained in the crystalline silicon film, pinholes may be formed on the surface of the crystalline silicon film when the gettering layer and the barrier layer are removed by etching after gettering. . This reason is presumed to be either the first or the second shown below.

  First, the first reason will be described with reference to the cross-sectional views of FIG. As shown in FIG. 16A, when the crystalline silicon film 1002 over the base film 1001 is irradiated with a laser, irregularities are formed on the surface and protrusions are formed. Metal elements concentrate on the protrusions, and an alloy 1009 of metal and Si is formed. Next, a barrier layer 1004 made of an oxide film is formed, but the barrier layer 1004 is not formed in a portion where the alloy 1009 is formed. Next, a gettering layer 1006 made of a semiconductor film is formed over the barrier layer 1004, and heat treatment is performed. As a result, most of the metal element contained in the crystalline silicon film 1002 is gettered to the gettering layer 1006. At this time, the surface layer of the gettering layer 1006 is oxidized to form an oxide film 1008.

  Next, as shown in FIG. 16B, the oxide film 1008 is removed by performing etching using the gettering layer 1006 as an etching stopper. Next, as shown in FIG. 16C, the gettering layer 1006 is removed by performing etching using the barrier layer 1004 as an etching stopper. At this time, since the barrier layer 1004 is not formed on the portion of the crystalline silicon film 1002 where the alloy 1009 is formed, the crystalline silicon film 1002 is also etched together with the gettering layer 1006 to form the pinhole 1010. The

  Next, the second reason will be described with reference to FIG. As shown in FIG. 17A, when the crystalline silicon film 1002 over the base film 1001 is irradiated with laser, protrusions are partially formed. Metal elements concentrate on the protrusions, and an alloy 1009 of metal and Si is formed. Next, a barrier layer 1004 and a gettering layer 1006 made of a semiconductor film are formed in this order. At this time, the barrier layer 1004 is also formed on the protrusion.

  Then, heat treatment is performed as shown in FIG. As a result, most of the metal element contained in the crystalline silicon film 1002 is gettered to the gettering layer 1006. At this time, the surface layer of the gettering layer 1006 is oxidized to form an oxide film 1008. The metal element which has formed the alloy 1009 moves to the gettering layer 1006, and an alloy 1011 of a semiconductor and a metal is formed in the gettering layer 1006.

Next, as shown in FIG. 17C, the oxide film 1008 is removed by performing etching using the gettering layer 1006 as an etching stopper. At this time, since the alloy 1011 is also etched, a portion of the barrier layer 1004 located under the alloy 1011 is also etched away.
Next, as shown in FIG. 17D, the gettering layer 1006 is removed by etching using the barrier layer 1004 as an etching stopper. At this time, the portion where the alloy 1009 is present in the crystalline silicon film 1002 is etched together with the gettering layer 1006 because the barrier layer 1004 is not formed thereon, and a pinhole 1010 is formed.

When pinholes are formed in a crystalline semiconductor film such as a crystalline silicon film in this way, the characteristics of the TFT and the like are affected. For this reason, it is desirable to prevent pinholes from remaining in the crystalline semiconductor film.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the number of pinholes on the surface of a crystalline semiconductor film.

In order to solve the above problems, a method for manufacturing a first semiconductor device according to the present invention includes:
Forming an amorphous semiconductor film containing silicon over a substrate having an insulating surface;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Removing or reducing the metal element contained in the crystallized semiconductor film by gettering the metal element to the gettering layer;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam.

  According to this method for manufacturing a semiconductor device, since the crystallized semiconductor film is irradiated with the second laser light having an energy density lower than that of the first laser light, the gettering layer functioning as a gettering sink for the metal element is formed. Even if a pinhole is formed in the crystallized semiconductor film during removal, the pinhole can be filled. Therefore, the number of pinholes remaining in the crystallized semiconductor film in the manufactured semiconductor device can be reduced.

  In the first method for manufacturing a semiconductor device, the step of forming the barrier layer may be a step of oxidizing the surface of the crystallized semiconductor film with a solution containing ozone.

A method for manufacturing a second semiconductor device according to the present invention includes:
Forming an amorphous semiconductor film containing silicon over a substrate having an insulating surface;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Removing the oxide film formed on the surface of the crystallized semiconductor film by etching;
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Moving the metal element to the gettering layer to gettering;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a third laser beam having an energy density lower than that of the first laser beam.

According to the method for manufacturing the second semiconductor device, the same effect as that of the method for manufacturing the first semiconductor device can be obtained.
In addition, when the amorphous semiconductor film is heat-treated to form a crystallized semiconductor film, an oxide film may be formed on the surface of the crystallized semiconductor film. When this oxide film is removed by etching, pinholes may be formed on the surface of the crystallized semiconductor film. On the other hand, in the second method for manufacturing a semiconductor device, the crystallized semiconductor film is irradiated with the first laser beam and then irradiated with the second laser beam. For this reason, even when a pinhole is formed on the surface of the crystallized semiconductor film when the oxide film is etched, the pinhole can be filled.

A method for manufacturing a third semiconductor device according to the present invention includes:
Forming an amorphous semiconductor film containing silicon over a substrate having an insulating surface;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Removing or reducing the metal element contained in the crystallized semiconductor film by gettering the metal element to the gettering layer;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam; and forming a gate insulating film on the crystallized semiconductor film;
Forming a gate electrode on the gate insulating film;
It comprises.

A fourth method for manufacturing a semiconductor device according to the present invention includes:
Forming a gate electrode over a substrate having an insulating surface;
Forming a gate insulating film on the gate electrode;
Forming an amorphous semiconductor film containing silicon on the gate insulating film;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Removing or reducing the metal element contained in the crystallized semiconductor film by gettering the metal element to the gettering layer;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam.

  In any of the above methods for manufacturing a semiconductor device, the step of gettering may be a step of performing a second heat treatment on the amorphous semiconductor film and the gettering layer. It may be a step of irradiating with strong light. Further, the step may be a step of performing heat treatment on the gettering layer and the amorphous semiconductor film and irradiating with strong light.

In any of the above semiconductor device manufacturing methods, the metal element is preferably one or more selected from Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. .
In any of the above-described methods for manufacturing a semiconductor device, the rare gas element contained in the gettering layer is preferably one or more selected from He, Ne, Ar, Kr, and Xe.

  As described above, according to the present invention, even when a pinhole is formed in the crystallized semiconductor film when the gettering layer functioning as a gettering sink for the metal element is removed, the pinhole can be filled. Therefore, the number of pinholes remaining in the crystallized semiconductor film in the manufactured semiconductor device can be reduced.

BEST MODE FOR CARRYING OUT THE INVENTION

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The method for manufacturing a semiconductor device according to the present embodiment includes a step of forming an amorphous semiconductor film on an insulating surface, a step of adding a metal element (for example, nickel) that promotes crystallization to the amorphous semiconductor film, A step of forming a crystallized semiconductor film by crystallizing the amorphous semiconductor film by heat treatment; a step of irradiating a first laser beam to increase the crystallinity of the crystallized semiconductor film; A step of forming an oxide film which is a barrier layer on the semiconductor film; a step of forming a gettering layer on the barrier layer; and a heat treatment of the crystallized semiconductor film, the barrier layer, and the gettering layer. The step of gettering the metal element in the gettering layer, the step of removing the gettering layer and the barrier layer, and the energy density lower than that of the first laser light on the crystallized semiconductor film (for example, 30 m / Cm ² ~60mJ / cm ² as the energy density is low) the second laser beam inert gas atmosphere, and a step of irradiating with vacuum or air to fill the pinholes on the crystallized semiconductor film.

  First, a base insulating film 2 is formed over a substrate 1 as shown in FIG. Here, as the substrate 1, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed on the surface thereof may be used. Also, a plastic substrate that can withstand the processing temperatures of all the steps described later may be used.

The base insulating film 2 is provided so that an element (for example, alkali metal) contained in the substrate 1 does not diffuse into the semiconductor film formed in the upper layer. As the base insulating film 2, an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is used. For example, an insulating film in which the following first and second layers are stacked is exemplified. The first layer is a first silicon oxynitride film formed using SiH ₄ , NH ₃ , and N ₂ O as reaction gases, and the film thickness is 50 to 100 nm. The second layer is a second silicon oxynitride film formed using SiH ₄ and N ₂ O as reaction gases, and the film thickness is 100 to 150 nm. Further, the base insulating film 2 may have a single layer structure. In this case, as the base insulating film 2, it is preferable to use a silicon nitride film (SiN film) or a second silicon oxynitride film (SiN _x O _y film (X >> Y)) formed by the above-described process. During gettering, since the metal element (for example, nickel) tends to move to a region having a high oxygen concentration, it is preferable that the base insulating film 2 be a silicon nitride film. Alternatively, an insulating film having a three-layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used as the base insulating film 2.

Next, a semiconductor film (hereinafter referred to as an amorphous semiconductor film) 3 having an amorphous structure is formed on the base insulating film 2 by, for example, a sputtering method. The amorphous semiconductor film 3 is formed from a semiconductor material whose main component is silicon. For example, the amorphous semiconductor film 3 is an amorphous silicon film or an amorphous silicon germanium film, and is formed to a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a good crystal structure in the subsequent crystallization process, the concentration of impurities such as oxygen and nitrogen contained in the amorphous semiconductor film 3 is set to 5 × 10 ¹⁸ / cm ³ (secondary ion mass spectrometry. (Atomic concentration measured by (SIMS)) should be reduced below. These impurities interfere with subsequent crystallization, and also increase the density of capture centers and recombination centers even after crystallization. For this purpose, it is desirable not only to use a high-purity material gas, but also to use a CVD apparatus capable of performing mirror surface treatment (electropolishing treatment) in the reaction chamber or having an oil-free vacuum exhaust system.

  Next, the amorphous semiconductor film 3 is crystallized. Here, the technique described in JP-A-8-78329 is used. The technology described in this publication is based on an amorphous silicon film (also referred to as an amorphous silicon film) by selectively adding a metal element that promotes crystallization and performing a heat treatment so that the amorphous region starts from the added region. The silicon film is crystallized. Details are as follows.

  First, as shown in FIG. 1B, a metal-containing layer 4 is formed on the surface of the amorphous semiconductor film 3. The metal-containing layer 4 is a metal element having a catalytic action that promotes crystallization of a semiconductor film (for example, one or more selected from Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au) Seeds). When the metal element is Ni, the metal-containing layer 4 is formed, for example, by applying a nickel acetate salt solution containing 1 to 100 ppm of nickel by weight with a spinner. As a method for forming the metal-containing layer 4, there is a method of forming an extremely thin film by sputtering, vapor deposition, or plasma treatment in addition to coating. Although an example in which the coating is performed on the entire surface is shown here, a metal-containing layer may be selectively formed by forming a mask. The metal-containing layer 4 may be formed before the amorphous semiconductor film 3 is formed, that is, under the amorphous semiconductor film 3.

Next, as shown in FIG. 1C, the substrate 1, the base insulating film 2, the amorphous semiconductor film 3, and the metal-containing layer 4 are subjected to heat treatment. Then, an alloy of a metal element and a semiconductor is formed in the semiconductor, and crystallization proceeds with this alloy as a nucleus. As a result, the amorphous semiconductor film 3 is crystallized, and a semiconductor film (hereinafter referred to as a crystallized semiconductor film) 5a having a crystal structure is formed. Note that the concentration of oxygen contained in the crystallized semiconductor film 5a is preferably 5 × 10 ¹⁸ / cm ³ or less. Here, after heat treatment for dehydrogenation (450 ° C., 1 hour), heat treatment for crystallization (550 to 650 ° C. for 4 to 24 hours) is performed.

  Further, the amorphous semiconductor film 3 can be crystallized by irradiating with strong light instead of heat treatment. In this case, any one of infrared light, visible light, and ultraviolet light or a combination thereof can be used. Typically, a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure Light emitted from a sodium lamp or a high-pressure mercury lamp is used. The lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to about 600 to 1000 ° C. Note that if necessary, heat treatment for releasing hydrogen contained in the amorphous semiconductor film 3 having an amorphous structure may be performed before irradiation with strong light. Further, crystallization may be performed by performing both heat treatment and irradiation with strong light.

  Note that an oxide film (not shown) is formed on the surface of the crystallized semiconductor film 5a in the above-described heat treatment or intense light irradiation treatment, but this oxide film is preferably removed by etching before the next step.

  Next, as shown in FIG. 1D, in order to increase the crystallization rate of the crystallized semiconductor film 5a (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, The film 5a is irradiated with the first laser light in the air or an oxygen atmosphere. Note that when the first laser light is irradiated, unevenness is formed on the surface of the crystallized semiconductor film 45a as shown in the enlarged view of FIG. Then, the metal agglomerates at the tip of the convex portion, and a semiconductor-metal alloy (for example, NiSi) 5b is formed. Although not shown, the surface layer of the crystallized semiconductor film 5a is oxidized, but this oxide film functions as a part of a barrier layer described later.

The first laser beam is a pulse oscillation type or continuous oscillation type excimer laser with a wavelength of 400 nm or less, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandride laser, sapphire laser. Etc. can be used. In addition, light emitted from an ultraviolet lamp may be used in place of these laser beams.
In the case of using the above-described laser, the laser light emitted from the laser oscillator may be condensed linearly with an optical system and irradiated onto the semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When a pulse oscillation type excimer laser is used, for example, the pulse oscillation frequency is set to 30 Hz and the laser energy density is set to 100 to 500 mJ / cm ² . When a pulse oscillation type YAG laser or YVO ₄ laser is used, the pulse oscillation frequency is set to 1 to 10 kHz using the second harmonic or the third harmonic, and the laser energy density is set to 300 to 600 mJ / cm ^2. good. The laser energy density in this embodiment is 390 mJ / cm ² . Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate. At this time, it is preferable to set the laser beam superposition ratio (overlap ratio) to 80 to 98%.

In the case of using a continuous wave laser (e.g. a continuous outgoing type YVO ₄ laser), a harmonic by a nonlinear optical element of the laser light emitted from the YVO ₄ laser of a continuous oscillation output 10 W (second harmonic to a fourth Harmonics). In addition, there is a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the amorphous semiconductor film 3. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 0.5 to 2000 cm / s.

The metal element (here, nickel) remains in the crystallized semiconductor film 5a thus obtained. Even if the metal element is not uniformly distributed in the film, it often remains on average at a concentration exceeding 1 × 10 ¹⁹ / cm ³ . Of course, various semiconductor elements including TFTs can be formed even in such a state, but in the present embodiment, the element is removed by the following method.

  First, as shown in FIG. 1E, by treating the surface of the crystallized semiconductor film 5a with an ozone-containing aqueous solution (typically ozone water), an oxide film (chemical oxide and chemical oxide) is formed on the surface of the crystallized semiconductor film 5a. Called). As a result, a barrier layer 6 made of an oxide film having a total thickness of 1 to 10 nm is formed. The barrier layer 6 functions as an etching stopper when only the gettering layer is selectively removed in a later step.

  Here, instead of the ozone-containing aqueous solution, the barrier layer 6 (chemical oxide) can be formed in the same manner by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid or the like is mixed with hydrogen peroxide. Alternatively, the barrier layer 6 may be formed by irradiating ultraviolet rays in an oxygen atmosphere to generate ozone and oxidizing the surface of the crystallized semiconductor film 5a with this ozone.

  Further, an oxide film of about 1 to 10 nm may be deposited as the barrier layer 6 by plasma CVD, sputtering, vapor deposition, or the like. When plasma CVD, sputtering, vapor deposition, or the like is used to form the barrier layer 6, the surface of the crystallized semiconductor film 5a is washed to remove a natural oxide film or an oxide film formed by laser light irradiation. It is desirable to form later.

When using a plasma CVD method for forming the barrier layer 6, as the raw material gas silane-based gas (monosilane, disilane, trisilane, etc.) and using nitrogen oxide gas (gas to be expressed in NO _x). For example, monosilane (SiH ₄ ) and nitrous oxide (N ₂ O), TEOS gas and N ₂ O, or TEOS gas and N ₂ O and O ₂ are used as source gases, and the oxidation is 10 nm or less, preferably 5 nm or less. A silicon nitride film is formed. This silicon oxynitride film is crystallized compared to an oxide film (called chemical oxide) obtained with an ozone-containing aqueous solution (typically ozone water) or an oxide film obtained by ultraviolet irradiation in an oxygen atmosphere. The adhesiveness with the semiconductor film 5a is high, and peeling does not easily occur in the subsequent process (formation of a gettering layer). In the case of using the plasma CVD method, an argon plasma treatment may be performed before the formation of the barrier layer in order to increase the adhesion.

  As another method for forming the barrier layer 6, there is a method in which a thin oxide film is formed by heating to about 200 to 350 ° C. using a clean oven. The barrier layer 6 is not particularly limited as long as it is formed by any one of the above methods or a combination of these methods, but a metal element (for example, nickel) in the crystallized semiconductor film 5a is obtained by subsequent gettering. ) Must be a film quality or film thickness that can be transferred to the gettering layer. Note that in the case of the silicon oxynitride film in the above-described thickness range, the metal element can pass through the barrier layer and move to the gettering site.

  Next, as shown in FIG. 2A, a gettering layer 7 containing a rare gas element is formed on the barrier layer 6 as a gettering site. Here, a semiconductor film containing a rare gas element is formed as the gettering layer 7 by a sputtering method. Although it is desirable to adjust the sputtering conditions as appropriate so that no rare gas element is added to the amorphous semiconductor film 3 described above, the sputtering conditions are set so that the rare gas element is added when the gettering layer 7 is formed. Adjust accordingly. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Among them, argon (Ar) which is an inexpensive gas is preferable. Here, a gettering layer 7 is formed by sputtering a target made of silicon in an atmosphere containing a rare gas element. There are two meanings in which the gettering layer 7 contains a rare gas element ion which is an inert gas. One is to form a dangling bond and impart distortion to the semiconductor film constituting the gettering layer 7, and the other is to impart distortion between the lattices of the semiconductor film. In order to give strain between the lattices of the semiconductor film, it is preferable to use an element having an atomic radius larger than that of the element constituting the semiconductor film (for example, silicon) such as argon (Ar), krypton (Kr), or xenon (Xe). In addition, when a rare gas element is contained in the semiconductor film, not only lattice distortion occurs but also dangling bonds are formed, so that the gettering ability of the semiconductor film is further improved.

Note that in the case where the gettering layer 7 is formed using a target containing phosphorus, which is an impurity element of one conductivity type, gettering can be performed using the Coulomb force of phosphorus in addition to gettering using a rare gas element.
Further, during gettering, a metal element (for example, nickel) tends to move to a region having a high oxygen concentration, so that the oxygen concentration contained in the gettering layer 7 is the oxygen concentration contained in the amorphous semiconductor film 3. A higher concentration, for example, 5 × 10 ¹⁸ / cm ³ or more is desirable.

Next, as shown in FIG. 2B, the crystallized semiconductor film 5a, the barrier layer 6 and the gettering layer 7 are subjected to heat treatment (for example, heat treatment or treatment for irradiating intense light) to getter metal elements (for example, nickel). The metal element in the crystallized semiconductor film 5a is reduced in concentration or removed. That is, by heating or irradiating strong light, the metal element moves in the direction of the arrow in FIG. 2B (that is, the direction from the crystallized semiconductor film 5a through the barrier layer 6 toward the gettering layer 7). Then, the metal element contained in the crystallized semiconductor film 5a is removed or the concentration of the metal element is reduced. In order for the metal element to be gettered, the metal element only needs to move by a distance of at least the thickness of the crystallized semiconductor film 5a. Therefore, gettering can be completed in a relatively short time. Here, it is sufficient that the metal element hardly remains in the crystallized semiconductor film 5a, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less. Gettering.

  In this specification, gettering means that a metal element in a gettering region (here, the crystallized semiconductor film 5a) is released by thermal energy and moves to a gettering site by diffusion. Accordingly, the gettering depends on the processing temperature, and the gettering proceeds in a shorter time as the temperature is higher. Depending on the heat treatment conditions of the gettering, the crystallinity ratio of the crystallized semiconductor film 5a can be increased simultaneously with the gettering, and defects remaining in the crystal grains can be repaired, that is, crystallinity can be improved.

  When performing the process of irradiating strong light as the heat treatment for gettering, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and it is turned on 1 to 10 times, preferably 2 to 6 times. repeat. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably about 700 to 750 ° C.

In the case where the heat treatment for gettering is performed by heat treatment, the heat treatment may be performed in a nitrogen atmosphere at 450 to 800 ° C. for 1 to 24 hours, for example, at 550 ° C. for 14 hours. In addition to this heat treatment, strong light may be irradiated.
This heat treatment oxidizes the surface layer of the gettering layer 7 to form an oxide film 7a.

  Next, as shown in FIG. 2C, the oxide film 7a is removed by etching. Next, etching is performed using the barrier layer 6 as an etching stopper, and only the gettering layer 7 is selectively removed. At this time, a portion of the surface layer of the crystallized semiconductor film 5a where the semiconductor-metal alloy (for example, NiSi) 5b is formed is also etched, and the pinhole 8 is formed. The reason for this is as described with reference to FIGS.

As a method of selectively etching only the gettering layer 7, wet etching with an alkaline solution such as dry etching using plasma with ClF ₃ or an aqueous solution containing hydrazine or tetraethylammonium hydroxide (chemical formula (CH ₃ ) 4 NOH) is used. There is etching.

  Next, as shown in FIG. 2D, the barrier layer 6 made of an oxide film is removed by, for example, an etchant containing hydrofluoric acid.

Next, as shown in FIG. 2E, the crystallized semiconductor film 5a is irradiated with a second laser beam in an air atmosphere, a nitrogen atmosphere, or a vacuum. The energy density of the second laser light is set lower than that of the first laser light used in the step shown in FIG. The energy density difference between the first laser beam and the second laser beam is preferably, for example, 30 mJ / cm ² or more and 80 mJ / cm ² or less. This preferable energy density difference depends on the thickness of the crystallized semiconductor film 5a and the like. Different. As this laser light (second laser light), excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of a YAG laser are used. Further, instead of excimer laser light, light emitted from an ultraviolet lamp may be used.
By irradiating the crystallized semiconductor film 5a with the second laser beam, the semiconductor element moves from the periphery of the pinhole 8 to the pinhole 8 in the surface layer of the crystallized semiconductor film 5a, and the pinhole 8 is filled.

Each photograph in FIG. 3 is an SEM photograph (5000 times magnification) in which the surface of the crystallized semiconductor film 5a is enlarged. FIG. 3A is an SEM photograph of the surface of the crystallized semiconductor film 5a before irradiation with the second laser beam. FIGS. 3B to 3E each have an energy density of 369.5 mJ / cm ² and 351. ^{.7mJ / cm 2, 328.3mJ / cm} 2, a SEM photograph of the crystallized semiconductor film 5a surface after irradiation with the second laser beam 309.0mJ / cm ^2. Table 1 shows the number of pinholes per unit area existing on the surface of the crystalline silicon film after the treatment under each condition. The number of pinholes was measured by counting pinholes included in one screen using SEM. The unit area here is a region (for example, 3021 μm ² ) displayed on one screen at the magnification described above. The energy density of the first laser beam is 389 mJ / cm ² .

As shown in the photograph of FIG. 3A, when the second laser beam was not irradiated, a plurality of pinholes existed on the surface of the crystalline silicon film 5a. As shown in Table 1, the number was 5 per unit area (pinhole density was 1.7E-3 / μm ² ). On the other hand, as shown in the photographs of FIGS. 3B to 3E, the number of pinholes was reduced when the second laser beam was irradiated. As shown in Table 1, when the energy density of the second laser beam is 369.5 mJ / cm ² , the number of pinholes is one per unit area (the pinhole density is 3.3E-4 / μm ² ). And 1/5 compared to the non-irradiated case. Also, when the energy density of the second laser beam was 351.7 mJ / cm ² or less, pinholes almost disappeared.

  As is apparent from the photographs shown in FIG. 3 and Table 1, pinholes can be removed from the surface of the crystallized semiconductor film 5a by irradiating the second laser beam. The benefits of eliminating pinholes are enormous. For example, the coverage of the film formed on the crystallized semiconductor film 5a (for example, the gate insulating film of the TFT) is improved. Thereby, when the source and drain of the TFT are formed with the crystallized semiconductor film 5a, the gate leakage current is reduced. Further, the breakdown voltage failure of the gate insulating film is reduced. Thus, the reliability of the TFT can be improved.

  In addition, when the rare gas element has been added to the crystallized semiconductor film 5a when the gettering layer 7 is formed, the rare gas element in the crystallized semiconductor film 5a is irradiated by irradiating the second laser beam. It can also be removed or reduced.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIG. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
First, as shown in FIG. 4A, a base insulating film 2 is formed on a substrate 1, and an amorphous semiconductor film (not shown) is further formed thereon. Next, a metal-containing layer (not shown) is formed on the surface of the amorphous semiconductor film, and the amorphous semiconductor film is crystallized by heat treatment to form a crystallized semiconductor film 5a. These steps are substantially the same as the steps shown in FIGS. 1A to 1C of the first embodiment.

Here, since the heat treatment is performed in an atmosphere containing oxygen (for example, in the air), an oxide film 5c is formed on the surface layer of the crystallized semiconductor film 5a.
Therefore, as shown in FIG. 4B, it is necessary to remove the oxide film 5c by performing etching using, for example, an etchant containing hydrofluoric acid. At this time, pinholes may be formed on the surface of the crystallized semiconductor film 5a.

  Next, after irradiating the surface of the crystallized semiconductor film 5a with the first laser light to improve the crystallization rate of the crystallized semiconductor film 5a, the crystallized semiconductor film 5a is irradiated with the second laser light, Fill the pinhole. Here, the irradiation conditions of the first laser beam and the second laser beam are substantially the same as the irradiation conditions of the second laser beam in the first embodiment. However, the energy density of the second laser beam may be different from that of the first embodiment.

  Next, as shown in FIG. 4C, a barrier layer 6 and a gettering layer 7 are formed, and heat treatment is performed to getter the metal element contained in the crystallized semiconductor film 5a. The details of these processes are substantially the same as the processes shown in FIGS. 1E to 2B in the first embodiment. Note that an oxide film 7a is formed on the surface of the gettering layer 7 by heat treatment.

  Next, as shown in FIG. 4D, the oxide film 7a, the gettering layer 7 and the barrier layer 6a are removed. Next, the pinhole formed in the crystallized semiconductor film 5a is filled by irradiating the crystallized semiconductor film 5a with a third laser beam (corresponding to the second laser beam in the first embodiment). These processes are substantially the same as the processes shown in FIGS. 2C to 2E in the first embodiment.

  According to the second embodiment, the same effect as that of the first embodiment can be obtained. Even if a pinhole is formed when the oxide film 5c is removed from the crystallized semiconductor film 5a, the pinhole is filled because the second laser beam is irradiated after the first laser beam. . Therefore, the coverage of the film formed on the crystallized semiconductor film 5a (for example, the gate insulating film of the TFT) is improved. When the TFT source and drain are formed of the crystallized semiconductor film 5a, the gate leakage current is reduced. Further, the breakdown voltage failure of the gate insulating film is reduced. Thus, the reliability of the TFT can be improved.

(Experiment)
In order to show that the pinhole is filled by irradiating the second laser beam, the inventors conducted the following experiment to prepare a sample.

  First, a sample was prepared in which a base insulating film was formed above a glass substrate and an amorphous silicon film was formed thereon by plasma CVD. Next, after applying a solution containing 10 ppm of nickel in terms of weight, a heat treatment was performed at 500 ° C. for 1 hour, followed by further heat treatment at 550 ° C. for 4 hours to form a crystalline silicon film. Next, the crystalline silicon film was treated with a 1% hydrofluoric acid solution for 3 minutes. This processing time is longer than the time required to remove the surface oxide film from the crystalline silicon film. For this reason, the surface oxide film is removed, and pinholes are formed on the surface of the crystalline silicon film.

Next, the crystalline silicon film was irradiated with a first laser beam (excimer laser) in an air atmosphere. Here, the energy density of the first laser beam was 419.2 mJ / cm ² . Next, a second laser beam (excimer laser) was irradiated to the crystalline silicon film at 30 Hz in an air atmosphere. A plurality of samples were prepared by changing the energy density of the second laser beam. For comparison, a sample not irradiated with the second laser beam was also produced.
Next, an SEM photograph of the prepared sample surface was taken at a magnification of 5000 times. The number of pinholes included in the unit area was counted. The definition of the unit area and the number of pinholes are the same as in the first embodiment.

  Table 2 shows the relationship between the number of pinholes and the energy density of the second laser beam. FIG. 5 is a graph of the data in Table 2.

As can be seen from the graphs in Table 2 and FIG. 5, in the state where the second laser beam is not irradiated, there are 7 pinholes per unit area on the surface of the crystalline silicon film (the pinhole density is 2.3E-3). Many / μm ² ). On the other hand, when the second laser beam is irradiated, there are almost no pinholes, or even if there are two pinholes per unit area (the pinhole density is 6.6E-4 / μm ² ), it becomes very small. It was. This experiment also shows that the pinhole is removed from the surface of the crystalline silicon film by irradiating the crystalline silicon film with the second laser beam.

The SEM photograph of each sample is shown in FIG. When the second laser beam is not irradiated (FIG. 6I), pinholes exist on the surface of the sample. The energy density of the second laser light is 408.1 mJ / cm ² (FIG. 6A), 389.8 mJ / cm ² (FIG. 6C), 379.3 mJ / cm ² (FIG. 6D) , And 338.7 mJ / cm ² (FIG. 6H), pinholes are also present. However, when these samples were viewed in a wider range than the imaged area, the number of pinholes was small. The energy density of the second laser beam is 399.4 mJ / cm ² (FIG. 6B), 370.3 mJ / cm ² (FIG. 6E), 361.7 mJ / cm ² (FIG. 6F). ) And 348.9 mJ / cm ² (FIG. 6G), there are almost no pinholes on the surface of the sample.

(Third embodiment)
Next, a third embodiment will be described with reference to FIG. This embodiment is a method of forming a TFT using the crystallized semiconductor film 5a formed according to the first or second embodiment. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 7A, a base insulating film 2 is formed on a substrate 1, and a crystallized semiconductor film 5a is further formed thereon. Here, since the crystallized semiconductor film 5a is subjected to the processing shown in FIGS. 1D to 2E in the first embodiment, the metal element does not exist or the amount of the metal element is reduced. Has been. Further, no pinhole is present on the surface of the crystallized semiconductor film 5a.

  Next, as shown in FIG. 7B, a photoresist film (not shown) is applied on the crystallized semiconductor film 5a, and this photoresist film is exposed and developed to form a resist pattern. Next, the crystallized semiconductor film 5a is etched using this resist pattern as a mask to form a crystallized semiconductor layer 10 having a desired shape. At this time, it is desirable to form a thin oxide film on the surface of the crystallized semiconductor film 5a by treating the surface of the crystallized semiconductor film 5a with ozone water before applying the photoresist film.

  Next, as illustrated in FIG. 7C, the surface of the crystallized semiconductor layer 10 is washed with a hydrofluoric acid-containing etchant, and then a gate insulating film 12 is formed over the crystallized semiconductor layer 10. The gate insulating film 12 is formed of an insulating film containing silicon as a main component. It is desirable that the surface cleaning process and the gate insulating film 12 forming process are continuously performed without being exposed to the atmosphere.

  Next, after cleaning the surface of the gate insulating film 12, a metal film containing Al, Cu, W, or the like as a main component is formed on the entire surface including the gate insulating film 12. Next, a photoresist film (not shown) is applied on the metal film, and the photoresist film is exposed and developed to form a resist pattern. Next, the gate electrode 13 is formed on the gate insulating film 12 by etching the metal film using the resist pattern as a mask. Next, using the gate electrode 13 as a mask, n-type impurity ions (ions such as P and As, in this case, P ions) are introduced into the crystallized semiconductor film 5a to form the source region 14 and the drain region 15. In order to activate the n-type impurity, heat treatment, intense light irradiation, or laser light irradiation is performed. At this time, plasma damage to the interface between the gate insulating film 12 and the crystallized semiconductor layer 10 and the gate insulating film 12 can be recovered simultaneously with activation. In particular, in an atmosphere of room temperature to 300 ° C., it is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface. YAG laser is a preferred activation means because of its simple maintenance.

  Next, an interlayer insulating film 16 is formed on the entire surface including the gate insulating film 12 and the gate electrode 13, and hydrogenation is performed. Next, a resist pattern is formed on the interlayer insulating film 16, and the interlayer insulating film 16 is etched using the resist pattern as a mask, thereby forming contact holes located on the source region 14 and the drain region 15, respectively. Next, a conductive film (for example, Al alloy wiring) is formed on the interlayer insulating film 16 and in the contact hole, and the conductive film is patterned to form the source electrode 17 and the drain electrode 18. Through the above process, a TFT (n-channel TFT) is formed.

When the TFT is formed in this way, the concentration of the metal element contained in the channel formation region 19 can be less than 1 × 10 ¹⁷ / cm ³ . In addition, since the number of pinholes on the semiconductor surface of the TFT is drastically reduced, the characteristics of the TFT can be improved.

  Note that the present invention is not limited to the TFT structure shown in FIG. 7C, and can be applied to TFTs having other structures. For example, a lightly doped drain (LDD) structure having an LDD region between a channel formation region and a drain region (or source region) may be used. In this structure, regions (hereinafter referred to as LDD regions) to which an impurity element is added at a low concentration are provided between a source region and a channel region, and between a drain region and a channel formation region. Further, a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film may be employed.

In this embodiment, an n-channel TFT has been described. Needless to say, a p-channel TFT can be formed by using a p-type impurity element instead of an n-type impurity element.
In this embodiment, the top gate type TFT has been described as an example. However, for example, the present invention can be applied to a forward stagger type TFT.

  In addition, the second laser beam is not irradiated before patterning the crystallized semiconductor film 5a, the crystallized semiconductor layer 10 having a desired shape is formed by patterning, and the oxide film formed at the time of patterning is removed. After that, the second laser beam may be irradiated in an air atmosphere, an inert gas atmosphere, or a vacuum to fill the pinholes on the surface of the crystallized semiconductor layer 10.

(Fourth embodiment)
Next, a third embodiment will be described with reference to FIG. This embodiment is a method of manufacturing an inverted stagger type (bottom gate type) TFT. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
First, as shown in FIG. 8A, a metal film mainly composed of Al, Cu, W or the like is formed on the substrate 1. Next, a photoresist film (not shown) is applied on the metal film, and the photoresist film is exposed and developed to form a resist pattern. Next, the gate electrode 21 is formed on the substrate 1 by etching the metal film using the resist pattern as a mask.

Next, the gate insulating film 22 is formed on the entire surface including the gate electrode 21. The gate insulating film 22 is formed of an insulating film containing silicon as a main component.
Next, an amorphous semiconductor film is formed over the gate insulating film 22. Next, the amorphous semiconductor film is crystallized to form the crystallized semiconductor film 5a, and further the first laser light is irradiated to increase the crystallization rate of the crystallized semiconductor film 5a. The method for crystallizing the amorphous semiconductor film is substantially the same as that in the first embodiment.

  Next, as shown in FIG. 8B, a barrier layer 6 is formed, a gettering layer 7 is further formed thereon, and heat treatment is performed to getter the metal element contained in the crystallized semiconductor film 5a. . The details of these processes are substantially the same as the processes shown in FIGS. 1E to 2B in the first embodiment. Note that an oxide film 7a is formed on the surface of the gettering layer 7 by heat treatment.

  Next, as shown in FIG. 8C, the oxide film 7a, the gettering layer 7 and the barrier layer 6a are removed. Next, the pinhole formed in the crystallized semiconductor film 5a is filled by irradiating the crystallized semiconductor film 5a with the second laser beam. These processes are substantially the same as the processes shown in FIGS. 2C to 2E in the first embodiment.

Next, as shown in FIG. 8D, a photoresist film (not shown) is applied on the crystallized semiconductor film 5a, and this photoresist film is exposed and developed to form a resist pattern. Next, the crystallized semiconductor film 5a is etched using this resist pattern as a mask, thereby forming a crystallized semiconductor layer 24 having a desired shape.
Next, a photoresist film is applied on the crystallized semiconductor layer 24, and this photoresist film is exposed and developed to form a resist pattern 23. Next, using the resist pattern 23 as a mask, n-type impurity ions (ions such as P and As, in this case, P ions) are introduced into the crystallized semiconductor layer 24 to form the source region 24a and the drain region 24b. In order to activate the n-type impurity, heat treatment, intense light irradiation, or laser light irradiation is performed.

  Next, as shown in FIG. 8E, an interlayer insulating film 25 is formed over the entire surface including the crystallized semiconductor layer 24. Next, a resist pattern is formed on the interlayer insulating film 25, and the interlayer insulating film 25 is etched using the resist pattern as a mask, thereby forming contact holes 25a and 25b located on the source region 24a and the drain region 24b, respectively. To do. Next, a conductive film (for example, an Al alloy film) is formed on the interlayer insulating film 25 and in the contact hole, and the conductive film is patterned to form the source electrode 26a and the drain electrode 26b. Through the above steps, an inverted staggered TFT (n-channel TFT) is formed.

  Also in this embodiment, the same effect as that of the third embodiment can be obtained.

(Example)
[Embodiment 1] Embodiment 1 of the present invention will be described with reference to FIGS. In this embodiment, a pixel portion and a TFT (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate are manufactured at the same time.

  First, as shown in FIG. 9A, the base insulating film 101 and the polysilicon layers 102 to 106 separated in an island shape are formed in this order on the glass substrate 100 by the method shown in the second embodiment. To do. Since the polysilicon layers 102 to 106 are the same as the crystallized semiconductor layer 10 in the second embodiment, the steps up to forming them are the same as those in the second embodiment, so the description is simplified. This will be described below.

First, the base insulating film 101 is formed over the glass substrate 100. Although a two-layer structure is used as the base insulating film 101 in this embodiment, a single-layer film of an insulating film or a structure in which three or more layers are stacked may be used. For example, the base insulating film 101 is formed as follows. First, as a first layer of the base insulating film 101, a first silicon oxynitride film (composition ratio Si = 32%, O = 27%, N) is formed by plasma CVD using SiH ₄ , NH ₃ , and N ₂ O as reaction gases. = 24%, H = 17%) with a film thickness of 50 nm. Next, as the second layer of the base insulating film 101, a second silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%) is formed by plasma CVD using SiH ₄ and N ₂ O as reaction gases. , H = 2%) to a thickness of 100 nm.

  Next, an amorphous silicon film which is an example of an amorphous semiconductor film is formed over the base insulating film 101 to a thickness of 50 nm by a plasma CVD method. Next, a nickel acetate salt solution containing 10 ppm of nickel by weight is applied by a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used.

  Next, the amorphous silicon film is crystallized by heat treatment to form a polysilicon film which is an example of a crystallized semiconductor film. For this heat treatment, heat treatment by an electric furnace or irradiation with strong light may be used. What is necessary is just to perform the heat processing by an electric furnace for about 4 to 24 hours, for example at 500 to 650 degreeC. Here, after a heat treatment for dehydrogenation (500 ° C., 1 hour), a heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a polysilicon film. Note that heat treatment may be performed using a lamp annealing apparatus instead of the electric furnace.

Next, in order to increase the crystallization rate of the polysilicon film and repair defects remaining in the crystal grains, the first laser beam (XeCl: wavelength 308 nm) is irradiated in the air or an oxygen atmosphere. As the first laser light, excimer laser light having a wavelength of 400 nm or less, or second harmonic and third harmonic of a YAG laser is used. In any case, if pulsed laser light having a repetition frequency of about 10 to 1000 Hz is condensed to 100 to 500 mJ / cm ² by an optical system and irradiated while scanning the surface of the silicon film with an overlap rate of 90 to 95%. Good. Here, irradiation with the first laser beam is performed in the atmosphere at a repetition frequency of 30 Hz and an energy density of 410 mJ / cm ² . Note that the first laser light irradiation is very important in removing or reducing a rare gas element (here, argon) in the silicon film. Next, the surface is treated with ozone water for 120 seconds to form an oxide film having a total thickness of 1 to 5 nm, thereby forming a barrier layer composed of this oxide film and an oxide film formed by irradiation with the first laser beam (see FIG. (Not shown).

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed to a thickness of 150 nm over the barrier layer by a sputtering method. The deposition conditions here are, for example, a pressure in the chamber of 0.3 Pa, a gas (Ar) flow rate of 50 (sccm), a deposition power of 3 kW, and a substrate temperature of 150 ° C. Note that the atomic concentration of the argon element contained in the amorphous silicon film under the above conditions is 3 × 10 ²⁰ / cm ^{3 to} 5 × 10 ²⁰ / cm ³ , and the atomic concentration of oxygen is 1 × 10 ¹⁹ / cm ^{3 to} 3. × 10 ¹⁹ / cm ³ Thereafter, heat treatment is performed at 650 ° C. for 3 minutes using a lamp annealing apparatus, thereby gettering metal atoms in the polysilicon film into the amorphous silicon film.
Next, the amorphous silicon film containing an argon element as a gettering site is selectively removed by etching using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid.

Next, second laser light irradiation is performed in an air atmosphere, a nitrogen atmosphere, or a vacuum to fill the pinhole formed in the polysilicon film surface. As the second laser light, excimer laser light having a wavelength of 400 nm or less, or second harmonic and third harmonic of a YAG laser are used. Note that light emitted from an ultraviolet lamp may be used instead of the second laser light. At this time, the energy density of the second laser light is made smaller than the energy density of the first laser light, preferably 30 to 80 mJ / cm ² . Here, the second laser beam is irradiated at an energy density of 360 mJ / cm ² .

  In this embodiment, the second laser beam is irradiated on the entire surface. However, the second laser beam may be selectively irradiated only on a necessary region.

  Next, the surface of the obtained polysilicon film is treated with ozone water to form a thin oxide film on the surface of the polysilicon film. Next, a mask made of resist is formed, and the polysilicon layers 102 to 106 separated into islands are formed by performing etching processing into a desired shape using the mask. After these polysilicon layers are formed, the mask is removed.

  Note that after the polysilicon layers 102 to 106 are formed, a p-type impurity element or an n-type impurity element may be added in order to control the threshold value (Vth) of the TFT. The p-type impurity element is a periodic group 13 element such as boron (B), aluminum (Al), or gallium (Ga). The n-type impurity element is periodic such as phosphorus (P) or arsenic (As). It is a group 15 element.

  Next, after removing the oxide film with an etchant containing hydrofluoric acid, the surfaces of the polysilicon layers 102 to 106 are washed, and then a gate insulating film 107 is formed. In this embodiment, a 115 nm thick silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) formed by plasma CVD is used as the gate insulating film 107. Use.

  Next, a first conductive film 108 a with a thickness of 20 to 100 nm, a second conductive film 108 b with a thickness of 100 to 400 nm, and a third conductive film 108 c with a thickness of 20 to 100 nm are formed over the gate insulating film 107. A conductive layer to be a gate electrode is formed by sequentially stacking the layers. In this embodiment, a tungsten film with a thickness of 50 nm is formed on the gate insulating film 107 as the first conductive film 108a, and an aluminum-titanium alloy (Al-Ti) film with a thickness of 500 nm is formed as the second conductive film 108b. A titanium film with a thickness of 30 nm is used as the third conductive film 108c.

In addition to the above-described materials, as the conductive material for forming the first to third conductive films 108a to 108c, an element selected from Ta, W, Ti, Mo, Al, and Cu, or the aforementioned element is mainly used. An alloy material or a compound material as a component can be used. For example, tungsten nitride may be used instead of tungsten in the first conductive film 108a. In the second conductive film 108b, an aluminum / silicon alloy (Al—Si) film may be used instead of the aluminum / titanium alloy (Al—Ti) film. In the third conductive film 108c, a titanium nitride film may be used instead of the titanium film.
Further, the conductive layer to be the gate electrode is not limited to a three-layer structure, and may be a two-layer structure of a tantalum nitride film and a tungsten film, for example. Alternatively, a single-layer semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used as the conductive layer to be the gate electrode.

Next, as shown in FIG. 9B, a photoresist film is applied over the third conductive film 108c, and this photoresist film is exposed and developed to form masks 110 to 115 made of a resist film. Form. Next, using the masks 110 to 115, a first etching process for forming gate electrodes and wirings is performed by dry etching.
In this first etching process, ICP (Inductively Coupled Plasma) is suitable as the plasma for etching. In this case, the film is etched into a desired tapered shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.). be able to.

  In the first etching process, for example, after the first etching is performed, the second etching is subsequently performed.

In the first etching, as an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ or the like, a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ , or the like, or O ₂ is used as appropriate. There is no limitation on the etching gas to be used, but here it is suitable to use BCl ₃ , Cl ₂ and O ₂ . Each gas flow rate is, for example, 65/10/5 (sccm). Then, 450 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma, and etching is performed for about 117 seconds. At this time, RF power (13.56 MHz) of 300 W is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. By this first etching, the second conductive film 108b and the third conductive film 108c are etched, and an end portion of the first conductive film 108a is tapered.

In the second etching, CF ₄ , Cl ₂ and O ₂ are used as etching gases. These gas flow rates are 25/25/10 (sccm), respectively. Then, 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching is performed for about 30 seconds. At this time, 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, each of the first to third conductive films 108a to 108c is etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film 107, the etching time may be increased by about 10 to 20%.

By this first etching process, first shape conductive layers 117 to 122 (first conductive layers 117 a to 122 a and second conductive layers are formed on the gate insulating film 107, which are first to third conductive layers. Conductive layers 117b to 122b and third conductive layers 117c to 122c) are formed. In addition, a region of the gate insulating film 107 that is not covered with the first shape conductive layers 117 to 122 is etched and thinned by about 20 to 50 nm.
In the first etching process described above, the shape of the resist mask is set to an appropriate shape, and an appropriate bias voltage is applied to the substrate side, so that the end portions of the first shape conductive layers 117 to 122 are formed. An appropriate taper shape can be obtained. For example, under the above conditions, the angle of the tapered portion is 15 to 45 °.

Next, as shown in FIG. 9C, a second etching process is performed using the masks 110 to 115 as they are. In the second etching process, BCl ₃ and Cl ₂ are used as etching gases. Each gas flow rate is 20/60 (sccm). Then, 600 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching. At this time, 100 W of RF (13.56 MHz) power is applied to the substrate side (sample stage). By this second etching process, the second conductive layers 117b to 122b made of aluminum containing a small amount of titanium and the third conductive layers 117c to 122c made of titanium are anisotropically etched, so that the second shape Conductive layers 124 to 129 (specifically, first conductive layers 124a to 129a, second conductive layers 124b to 129b, and third conductive layers 124c to 129c) are formed. At this time, a region of the gate insulating film 107 that is not covered with the second shape conductive layers 124 to 129 is slightly etched and thinned.

  In FIGS. 9B and 9C, the length of the tapered portion of the first conductive layer is shown as the same length in all the first conductive layers. There is a dependency on Therefore, the length of each tapered portion of the first conductive layers 124a to 129a varies depending on the wiring width.

Then, a first doping process is performed while leaving the masks 110 to 115 as they are, and an impurity element imparting n-type is added to the polysilicon layers 102 to 106. The doping process may be performed by, for example, a plasma doping method or an ion implantation method. In the case of ion implantation conditions, the implantation conditions are, for example, a dose amount of 1.5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 keV. For example, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity. In the first doping process, the second shape conductive layers 124 to 128 are also used as masks, so that two first impurity regions 130 to 134 are formed in a self-aligned manner in the polysilicon layers 102 to 106, respectively. The An impurity element imparting n-type is added to the first impurity regions 130 to 134 in a concentration range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ .
In this embodiment, the first doping process is performed without removing the masks 110 to 115. However, the first doping process may be performed after the masks 110 to 115 are removed.

  Next, after removing the masks 110 to 115, as shown in FIG. 10A, a photoresist film is applied over the entire surface, and the photoresist film is exposed and developed to form masks 135 and 136. The mask 135 is a mask that protects the channel formation region and its peripheral region in the polysilicon layer 103 that constitutes one of the p-channel TFTs of the drive circuit, and the mask 136 is a polysilicon layer that forms the TFT of the pixel portion. 105 is a mask for protecting the channel formation region 105 and its peripheral region.

  Next, a second doping process is performed using the masks 135 and 136 to form impurity regions in the polysilicon layers 102, 104, and 106 that are not covered by the mask. The doping process may be performed by, for example, a plasma doping method or an ion implantation method. In the case of ion implantation conditions, the implantation conditions are such that the acceleration voltage is 60-100 kV.

At this time, in each of the polysilicon layers 102, 104, and 106, the dose amount differs between the region where the second shape conductive layers 124 to 128 are present and the region where the second shape conductive layers 124 to 128 are not present because there is a difference in the film thickness of the upper layer. Therefore, when two low-concentration second impurity regions 180, 181, and 182 are formed in the polysilicon layers 102, 104, and 106, respectively, below the second shape conductive layers 124 to 128, respectively. At the same time, third impurity regions 137, 139, 141 adjacent to the outside of the second impurity region are formed. Impurities are also introduced into portions of the polysilicon layers 103 and 105 that are not covered with the masks 135 and 136, so that two third impurity regions 138 and 140 are formed. Specifically, an n-type impurity element is added to the third impurity regions 137 to 141 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Further, an n-type impurity element is added to the second impurity regions 180 to 182 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ .

  In FIG. 10A, for the sake of convenience, the lengths of the tapered portions of the first conductive layers 124a to 129a are all the same, but in actuality, the first conductive layers 124a to 129a are respectively tapered portions depending on the wiring width. May vary in length. In this case, the widths of the second impurity regions 180, 181, and 182 are also different from each other, and the widths of the third impurity regions 137, 139, and 141 are also different from each other.

  Next, as shown in FIG. 10B, after the masks 135 and 136 are removed, a new photoresist film is applied, and the photoresist films are exposed and developed to form masks 142 to 144. Masks 142, 143, and 144 are formed above polysilicon layers 102, 104, and 105, respectively. Further, no mask is formed above the polysilicon layers 103 and 106 where the p-channel TFT is formed.

  Next, a third doping process is performed using the masks 142 to 144 using, for example, a plasma doping method or an ion implantation method. By this third doping process, a p-type impurity element is added to portions of the polysilicon layers 103 and 106 forming the p-channel TFT that are not covered with the second shape conductive layers 125 and 128.

As a result, a fourth impurity region 147 and fifth impurity regions 145 and 146 are formed in the polysilicon layer 103, and a fourth impurity region 150 and fifth impurity regions 148 and 149 are formed in the polysilicon layer 106. Is done. A p-type impurity element is added to the fourth impurity regions 147 and 150 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . The fifth impurity regions 145, 146, 148, and 149 are doped with phosphorus (P) imparting n-type in the steps shown in FIGS. 9C and 10A. Since the concentration of the impurity element is added 1.5 to 3 times (for example, 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ ), the conductivity type is p-type. Of the fifth impurity regions, the regions 145 and 148 have lower n-type and p-type impurity element concentrations than the regions 146 and 149, respectively.
Note that the polysilicon layer 106 serves as a semiconductor layer forming a storage capacitor in the pixel portion.

Through the above steps, impurity regions having n-type or p-type conductivity are formed in the polysilicon layers 102 to 106, respectively. The second shape conductive layers 124 to 127 serve as gate electrodes, and the second shape conductive layer 128 serves as one electrode forming a storage capacitor in the pixel portion. Further, the second shape conductive layer 129 forms a source wiring in the pixel portion.
Note that the manufacturing steps are not particularly limited to the above-described order as long as each second-shaped conductive layer and each impurity region (first impurity region to fifth impurity region) can be formed. The order of doping may be changed as appropriate.

  Next, as shown in FIG. 10C, after the masks 142 to 144 are removed, an insulating film (not shown) covering almost the entire surface is formed. In this example, a 50 nm-thickness silicon oxide film was formed by plasma CVD. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

  Next, a step of activating the impurity element added to each of the polysilicon layers 102 to 106 is performed. This activation process is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination of these methods. It is processing. However, in this embodiment, since the second conductive layers 124a to 129a (see FIG. 9C) constituting the second shape conductive layers 124 to 129 are made of a material mainly composed of aluminum, the activation process is performed. It is necessary to satisfy the heat treatment conditions that the second conductive layers 124a to 129a can withstand.

By the activation process described above, the impurity element is activated, and at the same time, the metal element used as a catalyst when the polysilicon layers 102 to 106 are crystallized is converted into the third impurity regions 137, 139, 140 (see FIG. 10A) and the fifth impurity regions 146 and 149 (see FIG. 10B), and in the portions of the polysilicon layers 102 to 106 mainly serving as channel formation regions. Nickel concentration is reduced. As a result, the crystallinity of the channel formation region is improved, the off-current value of the TFT is lowered, and high field effect mobility can be obtained due to the good crystallinity. Thus, a TFT having good characteristics can be obtained.
In this embodiment, gettering is performed in advance by the method described in the first embodiment at the stage of forming the polysilicon film. Therefore, the gettering by the impurity region here is the second gettering. Become.

  In this embodiment, an example is shown in which an insulating film (not shown) is formed before the activation treatment, but the step of forming the insulating film may be performed after the activation.

  Next, a first interlayer insulating film 151 made of a silicon nitride film is formed. Next, heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) is performed, and a process of hydrogenating the polysilicon layers 102 to 106 is performed. This step is a step of terminating the dangling bonds of the polysilicon layers 102 to 106 by hydrogen contained in the first interlayer insulating film 151, and the polysilicon is formed regardless of the presence or absence of an insulating film (not shown) made of a silicon oxide film. The silicon layers 102-106 can be hydrogenated. However, in this embodiment, since the second conductive layers 124a to 129a (see FIG. 9C) constituting the second shape conductive layers 124 to 129 are made of a material containing aluminum as a main component, hydrogenation is performed. In the process, it is important that the second conductive layers 124 a to 129 a have heat treatment conditions that can withstand heat. Note that as another means of hydrogenation, plasma hydrogenation (treatment of hydrogenation with hydrogen excited by plasma) may be performed.

Next, as shown in FIG. 11, a second interlayer insulating film 152 is formed on the first interlayer insulating film 151. The second interlayer insulating film 152 may be made of an organic insulating material or an inorganic insulating material. In this embodiment, an inorganic siloxane insulating material composed of silicon, oxygen, and hydrogen formed from a siloxane material as a starting material, or hydrogen bonded to silicon among the inorganic siloxane insulating materials is methyl or phenyl. An organic siloxane-based insulating material substituted with such an organic group is used. An acrylic resin film having a thickness of 1.6 μm may be used.
Next, a resist pattern is formed on the second interlayer insulating film 152, and the second interlayer insulating film 152 and the first interlayer insulating film 151 are etched using the resist pattern as a mask, thereby conducting the second shape of the conductive film. Contact holes located on the layer 129 (that is, the source wiring of the pixel portion) and contact holes located on the third impurity regions 137 to 141 formed in the polysilicon layers 102 to 106 are formed. In this embodiment, a plurality of etching processes are sequentially performed. That is, after the second interlayer insulating film is etched using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using the above-described insulating film (not shown) as an etching stopper, and then the insulating film (not shown) is etched. .

  Thereafter, a metal film (for example, Al, Ti, Mo, W, etc.) is formed on the entire surface of the second interlayer insulating film 152 and in each contact hole, and this metal film is patterned to form wirings and pixel electrodes. To do. Note that it is desirable to use a film having excellent reflectivity such as a film containing Al or Ag as a main component or a laminated film thereof as the material of these electrodes and pixel electrodes. Thus, source wirings or drain wirings 153 to 158, a gate wiring 160, a connection wiring 159, and a pixel electrode 161 are formed.

  As described above, the driver circuit 206 including the n-channel TFTs 201 and 203 and the p-channel TFT 202 and the pixel portion 207 including the n-channel TFT 204 and the storage capacitor 205 can be formed over the same substrate in the same process. it can. Hereinafter, in the present specification, such a substrate is referred to as an active matrix substrate for convenience.

  In the active matrix substrate driver circuit 206 formed in this manner, the n-channel TFT 201 includes a channel formation region 162, a second shape conductive layer 124 that forms a gate electrode, and a second shape conductive layer 124. A second impurity region 180 located under a part and two third impurity regions 137 functioning as a source region or a drain region are provided. The p-channel TFT 202 includes a channel formation region 165, a second shape conductive layer 125 that forms a gate electrode, a fourth impurity region 147 located below a part of the second shape conductive layer 125, and a source region Alternatively, the fifth impurity region 146 functioning as a drain region is provided. The n-channel TFT 203 includes a channel formation region 168, a second shape conductive layer 126 that forms a gate electrode, a second impurity region 181 located below a part of the second shape conductive layer 126, and a source region or A third impurity region 139 which functions as a drain region is provided. A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed by appropriately connecting such n-channel TFTs and p-channel TFTs with wirings. Here, it is preferable to use an n-channel TFT 201 or 203 for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.

In the pixel portion 207, the n-channel TFT 204 includes a channel formation region 171, a second shape conductive layer 127 that forms a gate electrode, and a first impurity formed outside the second shape conductive layer 127. A region 133 and a third impurity region 140 functioning as a source region or a drain region are included. In addition, the storage capacitor 205 is formed of an insulating film that is a dielectric (the same film as the gate insulating film 107), an electrode formed of the second shape conductive layer 128, and the polysilicon layer. A fourth impurity region 150 and a fifth impurity region 148 are formed in the polysilicon layer 106.
Here, in the n-channel TFT 204 of the pixel portion 207, the surface characteristics of the polysilicon layer 105 in which each impurity region is formed are irradiated with the second laser light, so that the characteristics of the pixel are improved.

[Example 2]
In the active matrix substrate according to the first example, the gate electrode has a three-layer structure, but in Example 2, the gate electrode of the active matrix substrate has a two-layer structure. This example has the same configuration as that of Example 1 except for the structure of the gate electrode. The display device having such a structure can be manufactured through the same steps as those in Embodiment 1 except for a step of forming a conductive film to be a gate electrode and a step of patterning the conductive film. Hereinafter, only these steps will be described.

  First, as a conductive film to be a gate electrode, a first conductive film made of a TaN film with a thickness of 30 nm and a second conductive film made of a W film with a thickness of 370 nm are stacked. The TaN film is formed by sputtering a Ta target in an atmosphere containing nitrogen. The W film is formed by sputtering a W target. In place of the W film, an alloy film made of W and Mo may be used.

Similar to the conductive film having the three-layer structure in the first embodiment, the film having the two-layer structure is patterned by being etched by an ICP etching method after a mask made of a resist is formed thereon. At this time, the film is etched into a desired tapered shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) Can do. As an etching _{gas, Cl 2, BCl 3, SiCl} 4, CCl 4 chlorine gas or CF ₄ to the typified like, SF _6, fluorine-based gas NF ₃ and the like typified, or O ₂ as appropriate Can be used.

  Specifically, the first etching process and the second etching process are performed on the film having a two-layer structure as in the first embodiment.

As the first etching process, the first and second etchings are performed as in the first embodiment. In the first etching, CF ₄ , Cl ₂ and O ₂ are used as etching gases. Each gas flow rate is, for example, 25/25/10 (sccm). Under such conditions, plasma is generated by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa, and etching is performed using this plasma. At this time, 150 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the first etching, the etching rate of W is, for example, 200.39 nm / min, and the etching rate of TaN is, for example, 80.32 nm / min. The selection ratio of W to TaN is, for example, about 2.5. With this first etching condition, the taper angle of W is, for example, about 26 °.

Subsequently, the second etching is performed under different etching conditions. In the second etching, CF ₄ and Cl ₂ are used as etching gases. Each gas flow rate is, for example, 30/30 (sccm). Under such conditions, plasma is generated by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa, and etching is performed for about 30 seconds. At this time, RF (13.56 MHz) power of 20 W is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. In the second etching described above, the etching rate of W is, for example, 58.97 nm / min, and the etching rate of TaN is 66.43 nm / min.

  In the first etching process, the shape of the mask made of resist is made suitable, and an appropriate bias voltage is applied to the substrate side, so that the end portions of the first conductive layer and the second conductive layer are made appropriate. It can be made into a taper shape. For example, the angle of the tapered portion is 15 to 45 ° under the above-described conditions.

Subsequently, a second etching process is performed. Here, SF ₆ , Cl _2, and O ₂ are used as the etching gas. Each gas flow rate is, for example, 24/12/24 (sccm). Under such conditions, 700 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.3 Pa to generate plasma, and etching is performed using this plasma for, for example, 25 seconds. At this time, 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process described above, the etching rate of W is, for example, 227.3 nm / min, the etching rate of TaN is, for example, 32.1 nm / min, and the selective ratio of W to TaN is, for example, 7.1. . The etching rate for the silicon oxynitride film (SiON) that is the gate insulating film is, for example, 33.7 nm / min, and the selection ratio of W to silicon oxynitride is, for example, 6.83. By this second etching process, the taper angle of W becomes 70 °, for example. In this way, a gate electrode is formed.

  Thereafter, an active matrix substrate is formed by performing the same steps as in the first embodiment.

  In the active matrix substrate formed by the above-described process, the gate electrode is formed by stacking a W film and a TaN film. High nature. For this reason, there is an advantage that the characteristics of the gate electrode are hardly influenced by the processing conditions of activation and hydrogenation.

[Example 3]
This embodiment is a method of manufacturing a reflective active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 or 2.

  First, for example, the same active matrix substrate as that shown in FIG. 11 is obtained by the steps shown in the first or second embodiment. Next, an organic resin film such as an acrylic resin film is formed on the active matrix substrate, and the organic resin film is patterned to form columnar spacers for maintaining the substrate interval at desired positions. Note that spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers. Next, an alignment film is formed on the active matrix substrate and a rubbing process is performed.

  Next, a counter substrate is prepared. The counter substrate is provided with a color filter composed of a colored layer and a light shielding layer in a portion facing the pixel TFT of the active matrix substrate, and a light shielding layer is provided in a portion facing the drive circuit of the active matrix substrate. Yes. Next, a planarizing film that covers both the color filter and the light shielding layer is formed on the prepared counter substrate. Next, a counter electrode made of a transparent conductive film is formed on a portion of the planarizing film facing the pixel TFT. Next, an alignment film is formed on the entire surface of the counter substrate, and a rubbing process is performed.

  Next, after a sealing material is formed on the counter substrate, liquid crystal is dropped on the counter substrate. Here, before dropping the liquid crystal, a protective film may be formed on the sealing material to prevent the sealing material and the liquid crystal from reacting. Thereafter, the active matrix substrate and the counter substrate are bonded together with a sealant. Filler is mixed in the sealing material. By this filler and the above-mentioned columnar spacer, the active matrix substrate and the counter substrate are bonded to each other with a uniform interval. Then, the space between the two substrates is completely sealed with a sealant. In this way, the liquid crystal is sealed between the active matrix substrate and the counter substrate. A known liquid crystal material may be used as the liquid crystal material.

  Note that the liquid crystal may be sealed between the active matrix substrate and the counter substrate as follows. First, the active matrix substrate and the counter substrate are bonded together with a sealing material. Thereafter, a liquid crystal material is injected between the two substrates while exhausting between the two substrates, and the space between the two substrates is completely sealed with a sealant.

  The active matrix liquid crystal display device is completed through the above steps. Then, if necessary, the active matrix substrate or the counter substrate or both substrates are divided into desired shapes. Furthermore, a polarizing plate or the like is appropriately provided using a known technique. Then, using a known technique, a flexible printed circuit board (Flexible Print Circuit: hereinafter referred to as FPC) is attached via an illegal conductive film. A connection electrode (not shown) is formed of, for example, ITO at a portion where the FPC is attached. This connection electrode is partially embedded in a contact hole formed in the interlayer insulating film and the resin film of the active matrix substrate, and is connected to the wiring of the active matrix substrate through this embedded portion.

The configuration of the liquid crystal module thus obtained will be described. A pixel portion is arranged in the center of the active matrix substrate. A plurality of pixels are formed in the pixel portion. A source signal line driving circuit for driving the source signal line is arranged on the upper side of the pixel portion. Gate signal line drive circuits for driving the gate signal lines are arranged on the left and right sides of the pixel portion. The gate signal line driving circuit is symmetrically arranged with respect to the pixel portion, for example. However, the gate signal line driving circuit may be arranged only on one side, and may be selected as appropriate by the designer in consideration of the substrate size in the liquid crystal module. However, a symmetrical arrangement is desirable in view of operation reliability of the circuit, driving efficiency, and the like. Signals are input to each drive circuit from the FPC.
Note that all the drive circuits may be formed above the substrate. Several ICs may be used as part of the driver circuit.

[Example 4]
In Example 3, a method for manufacturing a reflective display device in which a pixel electrode is formed using a reflective metal material is shown; however, in this example, a pixel electrode is formed using a light-transmitting conductive film. A method for manufacturing a mold-type display device will be described. Since the steps up to the formation of the interlayer insulating film are the same as those in the first embodiment, the same reference numerals as those in the first embodiment are used and the description thereof is omitted.

  As shown in the schematic cross-sectional view of FIG. 12, after forming the interlayer insulating film 400 according to the first embodiment, contact holes are formed in the interlayer insulating film 400. Next, a light-transmitting conductive film is formed over the interlayer insulating film 400, and a plurality of connection electrodes 402 are formed by patterning the conductive film. These connection electrodes 402 are connected to the drain region or drain region of the pixel TFT or the capacitor element 205 through a contact hole. In addition, an electrode connected to the source region and drain region of another TFT is formed at the same time as this connection electrode.

  Next, after an interlayer insulating film 409 is formed over the connection electrode 402 and the interlayer insulating film 400, a contact hole is formed in the interlayer insulating film 409. Next, a light-transmitting conductive film is formed over the interlayer insulating film 409, and the pixel electrode 401 is formed by patterning the conductive film. The pixel electrode 401 is connected to the connection electrode 402 through a contact hole.

As the light-transmitting conductive film, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), ITSO (indium tin oxide containing silicon oxide) GZO (Ga-added ZnO) or the like may be used.
As described above, the active matrix substrate 410 is formed.

  Next, a counter substrate 411 is prepared. The counter substrate is provided with a color filter 412 in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Note that a light shielding layer is also provided in a portion corresponding to the drive circuit 206. Further, a planarizing film 407 is provided to cover the color filter 412 and the light shielding layer. A counter electrode 408 made of a light-transmitting conductive film is formed over the planarizing film 407 in a portion corresponding to the pixel portion 207. An alignment film 422 is formed on the entire surface including on the counter electrode 408 and subjected to a rubbing process.

  Next, the liquid crystal 420 is sealed between the active matrix substrate 410 and the counter substrate 411. This sealing method is the same as that in Example 3, and is performed using a sealing material 419 and a sealing material (not shown). Next, a liquid crystal module is manufactured by providing a polarizing plate 403 and the like, and a backlight 404 and a light guide plate 405 are provided and covered with a cover 406. In this way, an active matrix liquid crystal display device as shown in a part of the sectional view in FIG. 12 is completed.

  Note that the cover 406 and the liquid crystal module are attached to each other using an adhesive or an organic resin. In addition, when the substrate 1 and the counter substrate 411 are bonded to each other, the organic resin may be filled between the frame and the substrate by being surrounded by a frame and bonded. In addition, since this embodiment is a transmission type, the polarizing plate 403 is attached to both the active matrix substrate and the counter substrate.

[Example 5]
This embodiment is a method for manufacturing a light-emitting display device provided with an electroluminescent element, using the active matrix substrate formed in Embodiment 1 or 2. An electroluminescent element is, for example, an EL (Electro Luminescence) element, and includes an organic compound (an organic light emitting material) that emits light when an electric field is applied (hereinafter referred to as an organic light emitting layer), an anode, and a cathode. Yes. For a light-emitting display device using an electroluminescent element, a TFT is an essential element for realizing an active matrix driving method. That is, in a light-emitting display device using an electroluminescent element, at least a TFT that functions as a switching element and a TFT that supplies current to the electroluminescent element are provided in each pixel. In this issuance display device, the luminance of the pixel is determined by the on-current (Ion) of the TFT that supplies current to the electroluminescent element, regardless of the circuit configuration and driving method of the pixel. For this reason, for example, when the white display is performed on the entire screen, the display on the screen may vary if the on-current of each pixel is not constant. On the other hand, in this embodiment, since the variation in the on-current of the TFT is reduced as described above, the display is less likely to vary. Note that the layer containing an organic compound (organic light emitting material) may contain an inorganic material (such as silicon or silicon oxide).
The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  13A is a top view illustrating the display module, and FIG. 13B is a cross-sectional view taken along line A-A ′ in FIG. 13A. In the substrate 1, a pixel portion 207 is formed in the center portion, and a source side drive circuit 206 a and a gate side drive circuit 206 b are formed in the drive circuit portion. The source side drive circuit 206a and the gate side drive circuit 206b have substantially the same configuration as the drive circuit 206 of the first embodiment except for the TFT structure. A sealing substrate 1 a is disposed above the substrate 1, but the space between the substrate 1 and the sealing substrate 1 a is sealed with a sealing material 518.

  A wiring 508 is disposed in a portion of the substrate 1 that does not overlap with the sealing substrate 1a. The wiring 508 is a wiring for receiving a video signal and a clock signal from the FPC 509 serving as an external input terminal and transmitting these signals to the source side driver circuit 206a and the gate side driver circuit 206b. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto.

Next, a cross-sectional structure is described with reference to FIG. An insulating film 510 is provided over the substrate 1, and a pixel portion 207 and a gate side driver circuit 206 b are formed above the insulating film 510. In the pixel portion 207, a current control TFT 511, a plurality of pixels including a first electrode 512 electrically connected to the drain of the current control TFT 511, and a switching TFT 513 are formed. The gate side driver circuit 206b is formed using a CMOS circuit in which an n-channel TFT 523 and a p-channel TFT 524 are combined.
These TFTs (including 511, 513, 523, and 524) are inversely staggered TFTs. To manufacture them, the above-described fourth embodiment may be used.

The first electrode 512 functions as an anode of an electroluminescent element (EL element). The first electrode 512 is a single-layer film that is transparent or translucent to visible light and has a high work function (for example, ITO, indium zinc oxide, titanium nitride, chromium, tungsten, zirconium, platinum, or the like). In addition, it is preferable to use a laminated film of titanium nitride and a film containing aluminum as a main component, or a three-layer film of the laminated film and the titanium nitride film. In addition, when a laminated structure is used, the wiring resistance is lowered and a good ohmic contact can be obtained.
An electroluminescent layer (e.g., an EL layer) 516 and a second electrode 517 are formed over the first electrode 512.

  The electroluminescent layer 516 is formed of a light emitting layer, a charge transport layer, or a charge injection layer, but any combination thereof is possible. For example, a low molecular weight organic EL material or a high molecular weight organic EL material may be used as the light emitting layer, but a thin film made of a light emitting material (single compound) that emits light (fluorescence) by singlet excitation, or light emission by triplet excitation ( A thin film made of a phosphorescent material (triplet compound) can also be used. It is also possible to use inorganic materials such as silicon carbide for the charge transport layer and the charge injection layer. In addition to these, known materials can be used. Note that the electroluminescent layer 516 is formed by an evaporation method using an evaporation mask or a droplet discharge method (inkjet method).

The second electrode 517 functions as a cathode of the electroluminescent element, but also functions as a wiring common to all pixels, and is electrically connected to the FPC 509 through the wiring 508. All elements included in the pixel portion 207 are covered with the electroluminescent layer 516 and the second electrode 517. However, an insulating layer 514 is provided between each element except the first electrode 512 and the electroluminescent layer 516. The second electrode 517 may be formed using a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF _2, or CaN).
A space between the substrate 1 and the sealing substrate 1a is filled with a filler 507. For the filler 507, an inert gas such as Ar, a sealing material, or a desiccant can be used, for example.

  With the above structure, a light-emitting display device that emits light toward the substrate 1 side can be obtained. Then, the light-emitting element can be sealed with a sealant 518 and a protective film, and completely blocked from the outside. Accordingly, it is possible to prevent the entry of substances that promote deterioration due to oxidation of the electroluminescent layer such as moisture and oxygen from the outside. Therefore, a highly reliable light-emitting device can be obtained.

As a first modification of the fifth embodiment, the light may be emitted in the direction opposite to that in FIG. In this case, the first electrode 512 functions as a cathode of the light-emitting element, and the second electrode 517 functions as an anode. The second electrode 517 has a structure in which a transparent material (for example, ITO, In ₂ O ₃ —ZnO, or ZnO) is stacked on a thin metal film, for example.

  As a second modification of the fifth embodiment, both the first electrode 512 and the second electrode 517 may be formed of a light transmissive material. In this case, the light emitting display device emits light from both the substrate 1 side and the sealing substrate 1a side.

[Example 6]
The driving circuit and the pixel portion formed by implementing the present invention can be used for various display modules (active matrix type liquid crystal module, active matrix type electroluminescent module) as shown in Examples 3 to 5. In this embodiment, an electronic device incorporating these display modules is shown.

  Here, examples of the electronic device include a video camera, a digital camera, a head mounted display (goggles type display), a car navigation system, a projector, a car stereo, a personal computer, a portable information terminal (mobile computer, mobile phone, electronic book, etc.), and the like. It is done. Examples of these are shown in FIGS.

  FIG. 14A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The display module manufactured by the method shown in Examples 3 to 5 is used for the display portion 2003.

  FIG. 14B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. For this display portion 2102, a display module manufactured by the method shown in Examples 3 to 5 is used.

  FIG. 14C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. A display module manufactured by the method shown in Examples 3 to 5 is used for this display portion 2205.

  FIG. 14D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. For this display portion 2302, a display module manufactured by the method shown in Examples 3 to 5 is used.

  FIG. 14E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. A display module manufactured by the method shown in Examples 3 to 5 is used for the display portion 2402.

  FIG. 14F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, an image receiving portion (not shown), and the like. A display module manufactured by the method shown in Examples 3 to 5 is used for the display portion 2502.

  FIG. 15A shows a cellular phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, an image input portion (CCD, image sensor, etc.) 2907, and the like. A display module manufactured by the method shown in Examples 3 to 5 is used for this display portion 2904.

  FIG. 15B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. Display modules manufactured by the methods described in Examples 3 to 5 are used for the display portions 3002 and 3003.

  FIG. 15C illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. A display module manufactured by the method shown in Examples 3 to 5 is used for the display portion 3103. Incidentally, the display shown in FIG. 14C is a medium or small size display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate having a side of 1 m and perform mass production by performing multiple chamfering.

  As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

6A and 6B illustrate a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The figure which shows the next process of FIG. The SEM photograph of the surface of the crystallized semiconductor film produced by 1st Embodiment. 8A and 8B illustrate a method for manufacturing a semiconductor device according to a second embodiment. The graph which shows the relationship between the energy density of a 2nd laser beam, and the number of pinholes. SEM photograph of the surface of crystalline silicon film fabricated by experiment 8A and 8B illustrate a method for manufacturing a semiconductor device according to a third embodiment. 8A and 8B illustrate a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 3 shows a method for manufacturing an active matrix substrate according to Example 1; The figure which shows the next process of FIG. The figure which shows the next process of FIG. 9 is a schematic cross-sectional view showing an active matrix liquid crystal display device according to Example 4. FIG. (A) is the plane schematic of the light emission display apparatus which concerns on Example 5, (B) is AA 'sectional drawing of (A). FIG. 10 is a schematic diagram of an electronic apparatus using a display device that is an electronic apparatus according to Example 6 and is manufactured using the present invention. FIG. 10 is a schematic diagram of an electronic apparatus using a display device that is an electronic apparatus according to Example 6 and is manufactured using the present invention. The figure which shows the 1st reason which can make a pinhole in a crystallized semiconductor film. The figure which shows the 2nd reason which can make a pinhole in a crystallized semiconductor film.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Base insulating film, 3 ... Amorphous semiconductor film, 4 ... Metal-containing layer, 5a ... Crystallized semiconductor film, 6 ... Barrier layer, 7 ... Gettering layer, 8 ... Pinhole, 10 ... Crystal Semiconductor layer, 12 ... Gate insulating film, 13 ... Gate electrode, 14 ... Source region, 15 ... Drain region, 16 ... Interlayer insulating film, 17 ... Gate electrode, 18 ... Drain electrode

Claims (10)

Forming an amorphous semiconductor film containing silicon over a substrate having an insulating surface;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Removing or reducing the metal element contained in the crystallized semiconductor film by gettering the metal element to the gettering layer;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam.   2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the barrier layer is a step of oxidizing the surface of the crystallized semiconductor film with a solution containing ozone. . Forming an amorphous semiconductor film containing silicon over a substrate having an insulating surface;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Removing the oxide film formed on the surface of the crystallized semiconductor film by etching;
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Moving the metal element to the gettering layer to gettering;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a third laser beam having an energy density lower than that of the first laser beam. Forming an amorphous semiconductor film containing silicon over a substrate having an insulating surface;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Removing or reducing the metal element contained in the crystallized semiconductor film by gettering the metal element to the gettering layer;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam; and forming a gate insulating film on the crystallized semiconductor film;
Forming a gate electrode on the gate insulating film;
A method for manufacturing a semiconductor device comprising: Forming a gate electrode over a substrate having an insulating surface;
Forming a gate insulating film on the gate electrode;
Forming an amorphous semiconductor film containing silicon on the gate insulating film;
Adding a metal element that promotes crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
Performing a first heat treatment on the amorphous semiconductor film to crystallize the amorphous semiconductor film to form a crystallized semiconductor film; and
Irradiating the crystallized semiconductor film with a first laser beam to further crystallize the crystallized semiconductor film;
Forming a barrier layer for protecting the crystallized semiconductor film on the crystallized semiconductor film;
Forming a gettering layer made of a semiconductor containing a rare gas element on the barrier layer;
Removing or reducing the metal element contained in the crystallized semiconductor film by gettering the metal element to the gettering layer;
Removing the gettering layer by etching using the barrier layer as a stopper;
Removing the barrier layer;
Irradiating the crystallized semiconductor film with a second laser beam having an energy density lower than that of the first laser beam. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the gettering step is a step of performing a second heat treatment on the gettering layer and the amorphous semiconductor film. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the gettering step is a step of irradiating the gettering layer and the amorphous semiconductor film with strong light. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device according to claim 1, wherein the gettering step is a step of performing heat treatment on the gettering layer and the amorphous semiconductor film and irradiating with strong light. In the manufacturing method of the semiconductor device according to any one of claims 1 to 8,
The method for manufacturing a semiconductor device, wherein the metal element is one or more selected from Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. In the manufacturing method of the semiconductor device according to any one of claims 1 to 9,
The method of manufacturing a semiconductor device, wherein the rare gas element contained in the gettering layer is one or more selected from He, Ne, Ar, Kr, and Xe.