JP2005323197A - Viterbi decoding method and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that decoding performance is deteriorated in the case of performing Viterbi decoding by collectively executing arithmetic processing for a decoded word consisting of a plurality of bits. <P>SOLUTION: Processing for selecting a maximum likelihood path for a decoded word which is a convolution code on the basis of a state metric value and a branch metric value in each state is executed up to the final time of the decoded word, and in the case of executing decoding by tracing back the decoded word from the 0 state, the processing for selecting the maximum likelihood is executed in each n-bits (n is an integer ≥2), and at the time of starting tracing-back when the total number of bits of the decoded word is not n's multiple, paths to be candidates for selection are limited to specific paths p, q which can be candidates by the number of bits of n bits or less. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a Viterbi decoding method and apparatus suitable for application to, for example, a communication terminal that receives data encoded by a convolutional code and performs maximum likelihood decoding.

  As one of methods for decoding a convolutional code, a Viterbi decoding method is known. This Viterbi decoding method is a maximum likelihood decoding method for convolutional codes, and by selecting a sequence closest to the received code sequence (this is called a maximum likelihood path) from among code sequences that can be generated from the encoder on the transmission side. Perform error correction.

  This maximum likelihood path selection method does not compare and verify all paths, but obtains the Hamming distance between all code strings that can be generated on the transmission side and the received code string, and the cumulative value of this Hamming distance is the smallest. Based on the selection of the path (ie, the path with the highest likelihood), and after that, only the path required for decoding (survival path) is examined. If the path length is long enough, The points (roots) of the surviving paths merge to have the same value, and any surviving path is decoded back to the same value.

  Therefore, a correct decoded word can be reproduced by examining a path length that does not increase the decoding error rate and using the data at a point back by that length as the decoded word.

  FIG. 6 is a block diagram showing an example of a Viterbi decoding apparatus using such a Viterbi decoding method. The Viterbi decoding apparatus shown in this figure includes a branch metric calculation circuit 101, an ACS (add, compare, select) circuit 102, a normalization circuit 103, a state metric storage circuit 104, a path memory circuit 105, and a maximum likelihood decoding. A determination circuit 106, and when data (input data) output from the transmission side is input, a sequence closest to the received code sequence (from the code sequence that can be generated from the encoder on the transmission side ( (Maximum likelihood path) is selected, and decoded data is generated based on this selection.

  When the input data is input, the branch metric calculation circuit 101 calculates a branch metric of the input data and supplies the calculation result (branch metric) to the ACS circuit 102.

  The ACS circuit 102, which is a circuit that performs addition, comparison, and selection (so-called ACS calculation), is divided into a branch metric supplied from the branch metric calculation circuit 101 and a state metric (cumulative sum) supplied from the state metric storage circuit 104. Based on each of the two paths joining a certain state, the Hamming distance between the received code and the path (branch metric) and the cumulative sum of the branch metrics so far (state metric) are added and compared, Based on the comparison result, the one with the highest likelihood is selected, the selection content is supplied to the path memory circuit 105, and the newly obtained cumulative sum (state metric) is supplied to the normalization circuit 103.

  In this case, when the constraint length is “3”, the Hamming distance (branch metric) between the received code and the path for each of the two paths that merge into a certain state as shown in the transition diagram of FIG. 7 for each time slot. ) And the cumulative sum (state metric) of the branch metrics so far are added and compared, and the one with the highest likelihood is selected based on the comparison result.

  The normalization circuit 103 normalizes the state metric output from the ACS circuit 102 to a value within a preset range, and supplies this to the state metric storage circuit 104.

  The state metric storage circuit 104 stores the normalized state metric supplied from the normalization circuit 103 and returns it to the ACS circuit 102.

  The path memory circuit 105 includes a plurality of path memory cells, and the input data is selected and temporarily stored in each path memory cell based on the selection signal output from the ACS circuit 102. The selection contents output from the above are stored, and the selection contents are supplied to the maximum likelihood decoding determination circuit 106.

  The maximum likelihood decoding determination circuit 106 determines the maximum likelihood path based on the selection content stored in the path memory circuit 105, generates decoded data, and outputs this.

  Note that a transmission-side encoder generally adds a tail bit to the end of data to be encoded so that encoding always ends in zero state.

Patent Document 1 discloses an example of a Viterbi decoding device.
JP-A-5-136700

  By the way, as described above, when the path selection information obtained in the trellis calculation process and the metric value of each state are stored in the memory and Viterbi decoding is performed, it is stored in the memory for each time slot. When the arithmetic processing is performed, the number of times the memory is accessed to obtain the decoding result is large, which is a factor that hinders the speeding up of the decoding operation. For this reason, in Patent Document 1 described above, it is proposed to perform trellis operations collectively over a plurality of times (that is, decoded words of a plurality of bits).

  For example, trellis operations are performed collectively over a 2-bit decoded word. By performing the trellis operation in a lump in this way, the number of times the memory is accessed is reduced accordingly, leading to faster decoding operation.

  However, when a plurality of bits of decoded words are collectively processed in this way, the decoding performance may deteriorate depending on the decoding state. Specifically, for example, when the total number of bits of the decoded word is not a multiple of the decoded word of one ACS operation, the decoding performance may deteriorate.

  Hereinafter, this will be described with reference to FIGS. FIG. 8 is a general trellis diagram when the number of bits of a decoded word processed by one ACS operation is 1 (that is, when a plurality of decoded words are not processed in a lump). Here, the constraint length is 3 (4 states), and the path from the four states [0], [1], [2], [3] at time t to the state [0] at time t + 2 is as follows: There are paths a, b, c, and d as paths from time t to time t + 1, and paths e and f as paths from time t + 1 to time t + 2. In FIG. 8, when time t + 2 is the start point of traceback, selecting any one of these paths a to f from state [0] at time t + 2 is based on the metric value of each state. By doing so, it is decoded correctly.

  Next, an example in which the number of bits of a decoded word processed by one ACS operation is 2 is shown in FIG. In this case, if the time t + 2 is the start point of the traceback, any one of the four states [0], [1], [2], and [3] at the time t is obtained by one ACS calculation. Will be selected.

  Here, when the time t is an even number, the decoding result is completely equivalent to the 1-bit traceback shown in FIG. 8 and the 2-bit traceback shown in FIG. However, in the case of the configuration that performs the 2-bit processing of FIG. 9, the path memory is always additionally written in units of 2 bits. Therefore, when the total number of bits of the decoded word is an odd number, dummy bits corresponding to puncture bits are set to 1. It is necessary to take measures such as adding bits to make the processing unit an even number. In other words, the traceback process performed from the original path memory at time t + 1 is performed from time t + 2.

  In this way, if the traceback processing that should be performed from the path memory at time t + 1 is performed from time t + 2, there is a possibility that a path that should not be selected may be selected. Will deteriorate.

  The present invention has been made in view of such a point, and an object of the present invention is to solve the problem that the decoding performance deteriorates when a Viterbi decoding is performed by collectively processing a decoding word of a plurality of bits.

  The present invention performs a process of selecting a maximum likelihood path for a decoded word, which is a convolutional code, based on a state metric value and a branch metric value in each state until the last time of the decoded word, and traceback from 0 state. When performing decoding, the process of selecting the maximum likelihood path is calculated in units of n bits (n is an integer of 2 or more), and when the traceback starts when the total number of bits of the decoded word is not a multiple of n, Paths that are candidates for selection are restricted to specific paths that can be candidates with the number of bits of n bits or less.

  In this way, even when decoding processing is performed in units of multiple bits that can be performed with less memory access, when it is necessary to handle the number of bits that are less than or equal to multiple bits in that processing unit, A path is selected with an accuracy in the number of bits of a plurality of processing units or less.

  According to the present invention, even when decoding processing is performed in units of a plurality of bits that can be performed with less memory access, when it is necessary to handle the number of bits equal to or less than a plurality of bits in the processing unit, the processing unit Therefore, a path is selected with accuracy with a number of bits equal to or less than a plurality of bits, and an incorrect path is not selected. Therefore, even when the Viterbi decoding process is performed in units of multiple bits capable of high-speed processing or the like, the processing accuracy can be maintained the same as in the case of performing in 1-bit units.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
In this example, the present invention is applied to a case where various communication devices such as a mobile phone terminal receive and decode a convolutional code. That is, for example, as shown in FIG. 1, an RF (high frequency) unit 2 to which an antenna 1 is connected receives a signal in a predetermined frequency band, supplies the received signal to a demodulator 3, and demodulates it. A demodulated signal encoded with a convolutional code is obtained. This demodulated signal is supplied to the decoder 4 for decoding. In this example, a Viterbi decoder is used as the decoder 4 to perform Viterbi decoding. A specific configuration of the Viterbi decoder 4 will be described later.

  Data obtained as a result of decoding by the Viterbi decoder 4 is supplied to the reception data processing unit 5 to perform data processing on the reception data. In the data processing unit, for example, error correction is performed as necessary.

  FIG. 2 is a diagram illustrating a configuration example of this example of the Viterbi decoder 4 included in such a reception system. Here, it is assumed that a convolutional code with constraint length = 3 (4 states) is decoded. The configuration will be described with reference to FIG. 2. The reception signal obtained at the reception signal input terminal 11 is supplied to the ACS calculation unit 12. The ACS calculation unit 12 is a circuit that performs addition, comparison, and selection (so-called ACS calculation).

  Specifically, the ACS calculation unit 12 calculates a branch metric of the received signal, and each of the two merged into a certain state based on the branch metric and the state metric (cumulative sum) stored in the memory. For each path, add the Hamming distance (branch metric) between the received code and the path and the cumulative sum of the branch metrics so far (state metric) and compare them. The selected contents are stored in the memory (path memory), and the newly obtained cumulative sum (state metric) is normalized and stored in the memory (state metric memory). The calculation process in the ACS calculation unit 12 is executed under the control of the control signal 31 a from the trellis calculation process control unit 31 in the control unit 30.

  As the memory for storing the result in the ACS calculation unit 12, a four-state convolutional code is handled here, so that the first to fourth memories 21 to 24 corresponding to the number of states are used as shown in FIG. The path memories 21a to 24a and the state metric memories 21b to 24b are provided in the memories 21 to 24, respectively. The state metric values stored in the respective state metric memories 21 b to 24 b are returned to the ACS calculation unit 12. The path selection data stored in each of the path memories 21 a to 24 a is supplied to the result output unit 13. Data storage and reading in each of the memories 21 to 24 are executed under the control of the memory control unit 32 in the control unit 30. In FIG. 2, the first to fourth four memories 21 to 24 are illustrated as individual memories. For example, a memory area of one memory is divided to form four memories 21 to 24. Also good.

  The result output unit 13 performs a traceback process using the path selection data stored in the path memories 21a to 24a of the memories 21 to 24, obtains a decoded result for each decoded word, and outputs the decoded result as a decoded result. Output from the terminal 14. The trace back process in the result output unit 13 is executed under the control of the control signal 32 a from the trellis calculation process control unit 31 in the control unit 30.

  In this case, in this example, as a calculation process in the ACS calculation unit 12 and a traceback process in the result output unit 13, when a decoded word having a predetermined number of bits is handled, the process is performed in units of 2 bits. By performing processing in units of 2 bits, the number of times of accessing the memories 21 to 24 and the like are reduced accordingly, the processing load at the time of Viterbi decoding is reduced, and the decoding processing speed is increased.

  When the total number of bits of a decoded word is an odd number when processing in units of 2 bits, a dummy bit equivalent to a puncture bit is added to the last 1 bit to always add 2 bits at a time. It can be processed. Since the traceback process is a process that follows in the reverse direction, the data to which one dummy bit is added is handled in the first process. In this example, when traceback is performed on data with one dummy bit added, selectable paths are limited to specific paths among the four paths.

  This point will be described with reference to FIG. 3 and FIG. 4. FIG. 3 shows a final 2-bit trellis diagram when the number of bits of a decoded word processed by one ACS operation is 1 bit. . In this example, the time t + 2 is the last bit position (that is, the trace back start position), and when processing one bit at a time, the trace back processing is performed following time t + 1, time t,. Here, the state at the traceback start position in Viterbi decoding is always 0 state. Accordingly, there are two paths that can be selected by the traceback in the 0 state at time t + 2: the path e connected to the 0 state and the path f connected to the 1 state. Similarly, there are four paths a, b, c, and d that can be selected in 0 state or 1 state at time t + 1, and all four states can be selected at time t two bits before time t + 2. .

  Next, FIG. 4 shows a final 2-bit trellis diagram when the number of bits of a decoded word processed in one ACS operation is 2 bits. In this example, the time t + 2 is the final bit position (ie, the traceback start position), and processing is performed 2 bits at a time. Therefore, the traceback processing is performed in the order of time t + 2, time t, time t-2,. As can be seen from the example of FIG. 3 described above, when tracing back from time t + 2 to time t, all states 0, 1, 2, 3 can be selected from the 0 state that is the trace back start position. In the example of FIG. 4 in which 2 bits are handled, the paths p, q, r, and s connected to the four states 0, 1, 2, and 3 can be selected, and the four paths p, q, r, and s are selected. Among them, the one with the highest likelihood is selected.

  On the other hand, when the total number of bits of the decoded word to be traceback processed at that time is an odd number, 1 bit of dummy bits corresponding to the puncture bit is added to the 2 bits at the start of the traceback processing. When this is applied to FIG. 3, it corresponds to the traceback processing from time t + 2 to time t + 1, and there is only traceback corresponding to path e or path f. Therefore, at the start of the traceback process when the total number of bits of the decoded word is an odd number of bits, only the paths p and q are present among the four paths p, q, r, and s shown in FIG. By selecting a path with the highest likelihood from the paths p and q, a correct traceback process without error is performed. There is no need for such path restrictions except at the start of traceback processing.

  To summarize the processing in this example, the control shown in the flowchart of FIG. 5 is performed. That is, it is determined whether or not the number of bits of the decoded word is an odd number (step S1). If it is not an odd number, the optimum path based on the stored data in the memory without limiting the path at the time of traceback is determined. Trace back processing is performed while selecting (step S2). If the number of bits is an odd number, the path selected based on the stored data in the memory is limited to either the path p or q at the start of traceback. Trace back processing is performed while selecting an optimum path based on the stored data (step S3).

  Performing Viterbi decoding in this way has the effect of reducing the processing burden during Viterbi decoding because processing is performed in units of 2 bits, but in this example, by processing such a plurality of bits collectively in this way When there is a surplus bit at the end, the path selection at the start of traceback does not become a path selection that does not exist, and the Viterbi decoding accuracy can be prevented from deteriorating.

  In the description so far, the processing example has been described in the case where the operation is performed every 2 bits, and the total number of bits of the decoded word is an odd number of bits. is there. That is, when the operation is performed every n bits (n is an integer of 2 or more) and the total number of bits of the decoded word is not a multiple of n, the operation with the number of bits smaller than n bits is performed at the start of traceback. When performing, as in the above-described embodiment, the paths that are candidates for selection may be limited to paths that can be candidates with the number of bits.

  In addition, as a device to which the Viterbi decoding of the present invention is applied, any device that receives a convolutional code can be applied to various devices such as a wireless communication terminal such as a mobile phone terminal and a wired communication device.

  Further, in the above-described embodiment, in addition to being configured as a receiving apparatus incorporating a dedicated circuit for performing the Viterbi decoding process illustrated in FIGS. 1 and 2, for example, a data processing apparatus such as a personal computer apparatus may receive the data. A card or board to be processed may be mounted, and Viterbi decoding may be executed by arithmetic processing using software (program) incorporated in the data processing apparatus.

It is the block diagram which showed the example of receiving structure of the terminal by one embodiment of this invention. It is the block diagram which showed the structural example of the Viterbi decoder by one embodiment of this invention. It is a trellis diagram of Viterbi decoding, and is an example of the last two bits when the number of bits of a decoded word processed by one ACS operation is one. It is a trellis diagram of Viterbi decoding, and is an example of the last two bits when the number of bits of a decoded word processed by one ACS operation is two. It is a trellis diagram of Viterbi decoding, and is an example of the last two bits when the number of bits of a decoded word processed by one ACS operation is two. It is the block diagram which showed an example of the conventional Viterbi compound machine. It is an example of the trellis diagram of Viterbi decoding. It is a trellis diagram of Viterbi decoding, and is an example when the number of bits of a decoded word processed by one ACS operation is 1. It is a trellis diagram of Viterbi decoding, and is an example in the case where the number of bits of a decoded word processed by one ACS operation is 2.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... RF part, 3 ... Demodulator, 4 ... Decoder, 5 ... Reception data processing part, 11 ... Receive signal input terminal, 12 ... ACS calculation part, 13 ... Result output part, 14 ... Decoding result output Terminals 21 to 24... Memory, 30... Control unit, 31... Trellis calculation processing control unit, 32.

Claims (6)

For a decoded word that is a convolutional code, the process of selecting the maximum likelihood path is performed up to the last time of the decoded word based on the state metric value and the branch metric value in each state, and the decoding is performed by tracing back from the 0 state. In the Viterbi decoding method to be performed,
The process of selecting the maximum likelihood path is calculated in units of n bits (n is an integer of 2 or more),
A Viterbi decoding method that restricts a path that is a candidate for selection to a specific path that can be a candidate with the number of bits equal to or less than the n bits when traceback is started when the total number of bits of the decoded word is not a multiple of n. The Viterbi decoding method according to claim 1,
The value of n is 2,
A Viterbi decoding method that restricts a path that is a candidate for selection at the start of traceback to a specific path that can be a candidate when traceback is performed by one bit when the total number of bits of the decoded word is an odd number. The Viterbi decoding method according to claim 1 or 2,
A Viterbi decoding method in which, when the number of bits of the decoded word is not a multiple of n and the total number of bits is not a multiple of n, a dummy bit is added to perform n bits when calculating the remaining bits. For a decoded word that is a convolutional code, a state metric value and a branch metric value in each state are calculated, and a process of selecting the maximum likelihood path based on the calculation result is performed in units of n bits (n is an integer of 2 or more). A calculation unit to perform in
A memory for storing the state metric value and the branch metric value calculated by the calculation unit;
Traceback is performed using the value stored in the memory until the last time of the decoded word to obtain a decoded result, and is selected at the start of traceback when the total number of bits of the decoded word is not a multiple of n A Viterbi decoding device comprising: a result output unit that restricts a candidate path to a specific path that can be a candidate with the number of bits of n bits or less. The Viterbi decoding device according to claim 4,
The value of n is 2,
When the total number of bits of the decoded word is an odd number, the result output unit restricts a path that is a candidate for selection at the start of traceback to a specific path that can be a candidate when tracing back only one bit. apparatus. The Viterbi decoding device according to claim 4 or 5,
Since the total number of bits of the decoded word is not a multiple of n and the total number of bits is not a multiple of n, when calculating the remaining bits in the calculation unit, a dummy bit is added to calculate n bits. Decoding device.

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