JP2005323140A - Frequency converter, its method and pseudo low pitch sound reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency converter having small processing delay times, and to provide its method. <P>SOLUTION: A half-period inspection detecting means 13 detects the half-period points (zero-cross points) of an input signal. An address/amplitude control means 14 generates a read address to a buffer memory 12 on the basis of the detected half-period points, while generating a control information for controlling the amplitude polarity of an output signal, and converting the output signal into a continuous ringing. The read address moves each section, partitioned at the detected period points repeatedly, by N fold in the forward direction at a speed (N represents frequency conversion rate) at the N times of a write. Accordingly, since a frequency is converted while using a half period as a processing unit, the frequency can be converted with the processing delay time smaller than a conventional system which uses one period as the processing unit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a frequency conversion apparatus and method for converting the frequency of an original sound according to a frequency conversion rate.

  Conventionally, for various purposes, a frequency conversion device that converts the frequency of the original sound (for example, a harmonic generation device that generates harmonics of the original sound) has been used. In the acoustic field, this frequency conversion device is equipped in an effector device, an acoustic signal processing device that generates harmonics of a low-frequency component and uses the virtual pitch effect to improve the bass sound. The overtone is a sound obtained by converting the frequency of the original sound into an integral multiple.

  In general frequency conversion, the characteristics of the input signal are arbitrary. However, in this specification, the input signal is limited to “an input signal that can be regarded as having periodicity in a short time”. When this condition is met, a conventional frequency conversion method called the zero cross method can be used.

  In the zero cross method, when an input signal X for one cycle as shown in FIG. 20A is given, a compressed signal X ′ obtained by compressing the input signal X on the time axis by 1 / N times is obtained. In this method, the obtained compressed signal X ′ is repeatedly reproduced N times. Here, N is a frequency conversion rate and is a constant larger than 1 (N = 3 in FIG. 3, that is, frequency conversion of 3 times).

  FIG. 21 shows a conventional frequency converter using the zero cross method. As shown in FIG. 21, the frequency converter includes an input terminal 211, a buffer memory 212 that stores an input signal input from the input terminal 211, and a read address generating unit 214 that generates a read address of the buffer memory 212. And an output terminal 215 for outputting an input signal of an address generated by the read address generating means 214.

  As a result, the data of the section to be repeatedly reproduced (input signal X for one cycle) is stored in the buffer memory 212, and the read address generating means 214 can perform the compression and repeated reproduction on the time axis so as to perform the read address. Is generated.

  Here, in order to perform repetitive reproduction, the data of the section to be repetitive reproduction, that is, the input signal X for one cycle is stored in the buffer memory 212, and then the compressed signal X ′ is output from the output terminal 215. Good.

  However, in this case, as shown in FIG. 22, the output signal from the output terminal 215 is delayed by at least the cycle T of the signal X from the input signal to the input terminal 211. In this specification, the time from the start of input of an input signal to the start of output of an output signal is referred to as a processing delay time.

When the processing delay time is large, various problems may occur. For example, when video and audio are played back simultaneously in a certain device, it is conceivable that the playback video and playback audio will be out of synchronization, so-called lip sync, and the playback quality will deteriorate. In the prior art, since the buffer memory 212 needs to store the entire signal X for one cycle, if the processing delay time is long, the capacity of the buffer memory 212 must be increased, and the circuit scale is increased. Cost increase is inevitable.
JP 2001-507911 A

  Accordingly, an object of the present invention is to provide a frequency conversion apparatus and method that can reduce the processing delay time.

  The frequency conversion device according to claim 1 is a device for converting an input signal that can be considered to have periodicity in a short time according to a frequency conversion rate, in order to extract a partial waveform signal using periodicity from the input signal. A detecting means for detecting the information of the buffer, a buffer memory capable of storing at least a partial waveform of the input signal, and a reading speed from the buffer memory and a writing speed to the buffer memory based on the information detected by the detecting means. And a control means for generating a compressed partial waveform obtained by compressing the waveform on the time axis by a frequency conversion rate, and generating an output signal using the compressed partial waveform.

  With this configuration, since the compressed partial waveform is used, the processing delay time can be made shorter than that of the prior art, and degradation of reproduction quality can be suppressed. Further, the buffer memory only needs to store a capacity smaller than one cycle of the input signal, so that the circuit scale can be reduced and the cost can be reduced. Furthermore, it is possible to carry out frequency conversion at an intended frequency conversion rate while using a compressed partial waveform.

  According to a second aspect of the present invention, in addition to the configuration of the first aspect, the frequency conversion device further includes amplitude polarity switching means for switching the amplitude polarity of the output signal to a normal phase or a reverse phase, and the detection means detects a symmetric point of the input signal. The partial waveform is delimited by the symmetry points detected by the detection means, and the control means generates a read address from the buffer memory based on the symmetry points detected by the symmetry point detection means. , Including address / amplitude control means for generating control information to the amplitude / polarity switching means so that the output signal becomes a continuous signal, and the address / amplitude control means has a moving speed of the read address from the buffer memory to the buffer memory. Generate a compressed partial waveform so that the frequency conversion rate times the moving speed of the write address of Controlling the dynamic direction, in separated in a section in a symmetrical point detected by the detecting means compressed partial waveform, it generates an output signal by using a predetermined number of repetitions repeated.

  With this configuration, the continuity of the output signal can be ensured while using the compressed partial waveform.

  In the frequency converter according to claim 3, in addition to the configuration according to claim 2, the predetermined number of repetitions is equal to the frequency conversion rate.

  With this configuration, it is possible to repeat the reproduction of the compressed partial waveform for each partial waveform of the input signal, and to simplify the processing.

  In the frequency converter according to claim 6, in addition to the configuration according to claim 2, the width of the partial waveform on the time axis is ½ of the period of the input signal.

  With this configuration, when the frequency conversion rate is N, the processing delay time can be reduced to [(N-1) / N] / 2 times that of the prior art.

  In the frequency converter according to claim 7, in addition to the configuration according to claim 2, the width of the partial waveform on the time axis is ¼ of the period of the input signal.

  With this configuration, when the frequency conversion rate is N, if N is an odd number, the processing delay time can be reduced to [(N-1) / N] / 4 times that of the prior art, and if N is an even number, the processing delay time is reduced to the prior art. Can be shortened to ½ times.

  In the frequency converter according to claim 8, in addition to the configuration according to claim 6, the control information alternately switches the amplitude polarity of the output signal between the normal phase and the reverse phase while the current partial waveform is used. This is information for instructing to take over the amplitude polarity immediately before the transition to the use of the next partial waveform.

  In the frequency conversion device according to claim 9, in addition to the configuration according to claim 7, the control information is switched in units of ½ period of the output signal. The control information is information for instructing to alternately switch the amplitude polarity of the output signal between the normal phase and the reverse phase except at the time of switching.

  With these configurations, the continuity of the output signal can be ensured while using the compressed partial waveform.

  According to the present invention, the processing delay time can be shortened, the required capacity of the buffer memory can be reduced, the circuit scale can be reduced, and the cost can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings. Prior to the description of the specific configuration, the principle of the first frequency conversion method in the present invention will be described with reference to FIGS. The partial waveform in the first frequency conversion method is a waveform corresponding to ½ period of the input signal.

(Frequency conversion ratio: N = 2, 6, 10,...)
Now, it is assumed that the waveform of one cycle of the input signal can be decomposed into a first partial waveform X1 and a second partial waveform X2 as shown in FIG. 2A, for example, based on the zero cross point.

  When the frequency conversion rate is N, as shown in FIG. 2B, the first partial waveform X1 and the second partial waveform X2 are compressed N times on the time axis, respectively, and compressed partial waveforms are obtained. When it is generated and this compressed partial waveform is repeatedly reproduced N times, the desired reproduction can be realized.

  Further, as shown in FIG. 2B, it is necessary to control the amplitude polarity of the output signal to make the output signal continuous. That is, in FIG. 2B, the amplitude polarity is set to the positive phase in the section described as the normal phase, and the amplitude polarity is set to the reverse phase in the section described as the reverse phase.

  If N = 2, the partial waveform signal obtained by compressing the first partial waveform X1 by 1/2 on the time axis is reproduced once in the positive phase within a quarter cycle of the input signal. Further, in the next quarter cycle of the input signal, a partial waveform signal obtained by compressing the first partial waveform X1 by 1/2 on the time axis is reproduced once in reverse phase.

  Further, in the next quarter cycle of the input signal, the partial waveform signal obtained by compressing the second partial waveform X2 by 1/2 on the time axis is reproduced once in reverse phase. Further, within the next 1/4 cycle of the input signal, a partial waveform signal obtained by compressing the second partial waveform X2 by 1/2 on the time axis is reproduced once in the positive phase.

  If the above processing is executed for each cycle of the input signal, the result (output signal) of FIG. 2B is obtained by converting the frequency of the input signal shown in FIG. .

  The above description relates to the case of N = 2. However, the above-described processing can be similarly extended for frequency conversion ratios N = 6, 10, 14, 18,... (That is, N = 2 + 4 * i, i is an integer of 0 or more).

(In the case of frequency conversion rate N = 3, 7, 11, 15, 19,...)
As described above, the input signal is assumed to be as shown in FIG.

  As shown in FIG. 3A, if N = 3, the partial waveform signal obtained by compressing the first partial waveform X1 to 1/3 on the time axis within the 1/6 period of the input signal is in positive phase. Play once. Further, within the next 1/6 cycle of the input signal, a partial waveform signal obtained by compressing the first partial waveform X1 to 1/3 on the time axis is reproduced once in reverse phase. Further, within the next 1/6 cycle, the partial waveform signal obtained by compressing the first partial waveform X1 to 1/3 is reproduced once in the normal phase.

  Further, within the next 1/6 cycle of the input signal, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/3 on the time axis is reproduced once in the normal phase. Further, within the next 1/6 cycle of the input signal, a partial waveform signal obtained by compressing the second partial waveform X2 to 1/3 on the time axis is reproduced once in reverse phase. Further, within the next 1/6 cycle, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/3 is reproduced once in the positive phase.

  If the above processing is executed for each period of the input signal, the result (output signal) in FIG. 3B is obtained by converting the frequency of the input signal shown in FIG. .

  The above description relates to the case of N = 3. However, the above-described processing can be similarly extended for frequency conversion ratios N = 7, 11, 15, 19,... (That is, N = 3 + 4 * i, i is an integer of 0 or more).

(In the case of frequency conversion rate N = 4, 8, 12, 16, 20,...)
As described above, the input signal is assumed to be as shown in FIG.

  As shown in FIG. 3B, if N = 4, the partial waveform signal obtained by compressing the first partial waveform X1 to ¼ on the time axis within the 1/8 period of the input signal is in a positive phase. Play once. Further, in the next 1/8 cycle of the input signal, a partial waveform signal obtained by compressing the first partial waveform X1 to 1/4 on the time axis is reproduced once in reverse phase. Further, within the next 1/8 cycle, the partial waveform signal obtained by compressing the first partial waveform X1 to 1/4 is reproduced once in the normal phase. Further, within the next 1/8 cycle, a partial waveform signal obtained by compressing the first partial waveform X1 to 1/4 is reproduced once in reverse phase.

  Further, in the next 1/8 cycle of the input signal, a partial waveform signal obtained by compressing the second partial waveform X2 to 1/4 on the time axis is reproduced once in reverse phase. Further, within the next 1/8 cycle of the input signal, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/4 on the time axis is reproduced once in the normal phase. Further, in the next 1/8 cycle, a partial waveform signal obtained by compressing the second partial waveform X2 to 1/4 is reproduced once in reverse phase. Further, within the next 1/8 cycle, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/4 is reproduced once in the positive phase.

  If the above processing is executed for each cycle of the input signal, the result (output signal) in FIG. 3B is obtained by converting the frequency of the input signal shown in FIG. .

  The above description relates to the case of N = 4. However, the above-described processing can be similarly extended for frequency conversion ratios N = 8, 12, 16, 20,... (That is, N = 4 + 4 * i, i is an integer of 0 or more).

(In the case of frequency conversion rate N = 5, 9, 13, 17, 21,...)
As described above, the input signal is assumed to be as shown in FIG.

  As shown in FIG. 3C, if N = 5, the partial waveform signal obtained by compressing the first partial waveform X1 to 1/5 on the time axis within the 1/10 period of the input signal is in positive phase. Play once. Further, within the next 1/10 period of the input signal, a partial waveform signal obtained by compressing the first partial waveform X1 to 1/5 on the time axis is reproduced once in reverse phase. Further, within the next 1/10 period, the partial waveform signal obtained by compressing the first partial waveform X1 to 1/5 is reproduced once in the normal phase. Further, within the next 1/10 period, the partial waveform signal obtained by compressing the first partial waveform X1 to 1/5 is reproduced once in reverse phase. Further, within the next 1/10 period, the partial waveform signal obtained by compressing the first partial waveform X1 to 1/5 is reproduced once in the normal phase.

  Further, within the next 1/10 period of the input signal, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/5 on the time axis is reproduced once in the normal phase. Further, within the next 1/10 period of the input signal, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/5 on the time axis is reproduced once in reverse phase. Further, within the next 1/10 period, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/5 is reproduced once in the normal phase. Further, within the next 1/10 period, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/5 is reproduced once in reverse phase. Further, within the next 1/10 period, the partial waveform signal obtained by compressing the second partial waveform X2 to 1/5 is reproduced once in the normal phase.

  If the above processing is executed for each period of the input signal, the result (output signal) in FIG. 3C is obtained by converting the frequency of the input signal shown in FIG. .

  The above description relates to the case of N = 5. However, the above-described processing can be similarly extended for frequency conversion ratios N = 9, 13, 17, 21,... (That is, N = 5 + 4 * i, i is an integer of 0 or more).

  From the above description, it will be understood that the first frequency conversion method in the present invention can be applied when the frequency conversion rate N is an arbitrary integer of 2 or more.

  According to the first frequency conversion method, the following first rule applies to amplitude control regardless of the frequency conversion rate N.

  The first partial waveform X1 (current partial waveform) is played back in the positive phase for the first time, and then played back while switching between the positive phase and the reverse phase. The second partial waveform X2 (next partial waveform) takes over the last amplitude control of the first partial waveform X1 and is the same amplitude control as the last amplitude control (if positive phase, positive phase, if negative phase) The second partial waveform X2 is reproduced alternately in the normal phase / reverse phase.

  The frequency conversion apparatus according to Embodiments 1 and 2 of the present invention performs frequency conversion using the first frequency conversion method and its rules. Hereinafter, specific configurations of the first and second embodiments will be described, and according to the first and second embodiments, it is shown that the processing delay time can be shortened as compared with the prior art.

  Based on the above first frequency conversion method, a specific configuration will be described below.

(Embodiment 1)
FIG. 1A is a block diagram of a frequency conversion device according to Embodiment 1 of the present invention. As shown to Fig.1 (a), the frequency converter of this form is provided with the following element.

  The input terminal 11 inputs an input signal. The buffer memory 12 stores an input signal input from the input terminal 11.

  The 1/2 period point detecting means 13 is a start point on the time axis of the input signal, and a 1/2 period point (symmetric point of the input signal) that the input signal has advanced by 1/2 period on the time axis from this start point. Is detected. In this embodiment, the half-cycle point detection means 13 has three zero cross points of the input signal (both the point where the sign of the input signal switches from positive to negative, or the point where the sign of the input signal switches from negative to positive. The half-cycle point detection means 13 detects these three zero-cross points, so that the waveform of one cycle of the input signal is 1 in the first half on the time axis. It is decomposed into a first partial waveform X1 located in the / 2 period and a second partial waveform X2 located in the latter half period (see FIG. 2A).

  The amplitude polarity switching unit 15 multiplies the output signal from the buffer memory 12 by “+1” (normal phase) or “−1” (reverse phase) in accordance with the control of the address / amplitude control unit 24, and the amplitude polarity of the output signal Switch.

  The output terminal 16 outputs an output signal from the amplitude / polarity switching means 15 to the outside.

  The address / amplitude control means 14 generates a read address for the buffer memory 12 and controls the amplitude polarity switching of the amplitude polarity switching means 15. The address / amplitude control means 14 controls the amplitude polarity switching means 15 based on the first rule.

  The half cycle point detection means 13 may be connected to the input terminal 11 as shown in FIG. 1A, or may be connected to the buffer memory 12 as shown in FIG. As shown in FIG. 1C, the buffer memory 12 and the amplitude polarity switching means 15 may be connected in the middle.

  Hereinafter, the operation of the frequency conversion apparatus according to the first embodiment of the present invention will be described with reference to the drawings. An input signal input from the input terminal 11 is written in the buffer memory 12. At the same time, the half cycle point detection means 13 detects the zero cross point of the input signal.

  Information on the zero-cross point detected by the half-cycle point detector 13 is sent to the address / amplitude controller 14. The address / amplitude control means 14 generates a read address for the buffer memory 12. The read address moves while repeating each section of the detected zero cross point N times at a speed of N times in the forward direction. As a result, a compressed partial waveform is generated. The read address update operation will be described in detail later.

  The address / amplitude control means 14 switches the amplitude polarity in the amplitude polarity switching means 15 in a timely manner when the read address reaches each half cycle point during the read address update operation. The switching follows the first rule.

  The read address generated by the address / amplitude control means 14 is sent to the buffer memory 12. Then, the corresponding sample (data of the input signal specified by the read address) is read from the buffer memory 12, and externally controlled from the external terminal 16 under the control of the amplitude polarity (normal phase / reverse phase) by the amplitude polarity switching means 15. An output signal is output.

  Next, with reference to FIGS. 4 and 5, the write / read operation with respect to the buffer memory 12 and the relationship between the input signal and the output signal at that time will be described using a specific example.

  4 and 5 show the operation when the frequency conversion rate is N = 2 in accordance with the time series (point A → point B → point C → point D → point E). Here, it is assumed that the zero-cross points of the signal are detected at times t = 0, 10, and 20. In the following, the operation of both addresses at each time will be described.

  Point A (time t = 0 to 4): As shown in FIG. 4A, the write address is incremented by “1” from “0”, and the sample values at time t = 0 to 4 are sequentially stored in the buffer memory 12. Written. At this time, the read address does not operate.

  Point B (time t = 5 to 9): As shown in FIG. 4B, the write address continues to increase by “1”, and the sample values at time t = 5 to 9 are sequentially written to the buffer memory 12. . The read address starts the operation at time t = 5 (that is, the operation starts after the write address). Then, the read address is incremented by “2” from “0”, and as a result, sample values at times t = 0, 2, 4, 6, and 8 (total of 5) written in the buffer memory 12 are read. . The read signal is output at the same sampling period as that of writing. The reason why the increment of the read address is double the increment of the write address is that the output signal is obtained by compressing the input signal twice on the time axis.

  Here, in order to prevent the read address from overtaking the write address (if invalid, invalid data is output), it is necessary to operate the read address with a delay of 5 unit time or more from the write address. Along with this, the output signal is also delayed by that time from the input signal, and this becomes the processing delay time in the first embodiment.

  Point C (time t = 10 to 14): As shown in FIG. 4C, the write address continues to increase by “1”, and the sample values at time t = 10 to 14 are sequentially written to the buffer memory 12. . The read address that has reached the zero cross point (address 10) is reset to the previous zero cross point (address 0). Then, the read address is incremented by “2” again, and sample values at times t = 0, 2, 4, 6, and 8 (total of 5) written in the buffer memory 12 are read. The read signal is output by the amplitude / polarity switching means 15 in the opposite phase and with the same sampling period as that of writing.

  Point D (time t = 15 to 19): As shown in FIG. 5A, the write address continues to increase by “1”, and the sample values at time t = 15 to 19 are sequentially written to the buffer memory 12. . The read address continues to increase by “2”, and sample values at times t = 10, 12, 14, 16, and 18 (a total of 5) written in the buffer memory 12 are read, and the same sampling cycle as the write Is output. The read signal is output at the same sampling period as that of writing.

  Point E (time t = 20 to 24): As shown in FIG. 5B, the write address continues to increase by “1”, and the sample values at time t = 10 to 14 are sequentially written to the buffer memory 12. . The read address that has reached the zero cross point (address 20) is reset to the previous zero cross point (address 10). Then, the read address is incremented by “2” again, and sample values at times t = 10, 12, 14, 16, and 18 (a total of five) written in the buffer memory 12 are read. The read signal is output with the same sampling period as that of writing, with the amplitude polarity being controlled to the opposite phase by the amplitude polarity switching means 15.

  The case where the frequency conversion rate is N = 2 has been described above. Further, when the frequency conversion rate N is not 2, similarly, the read address moves at a speed N times the write address. At this time, when the read address reaches the zero cross point, the read address is reset to the previous zero cross point. This resetting operation is performed N-1 times for each section.

The required processing delay time is obtained from the relationship of the amount of movement (FIG. 6) when both addresses reapproach (when the read address reaches each zero cross point for the first time), and is calculated as follows. The
[(N-1) / N] T / 2 (1)
Here, N is the frequency conversion rate, and T is the period of the input signal. Compared with the conventional technique (processing delay time: T), a processing delay time of [(N-1) / N] / 2 is sufficient. If N = 2, [(N-1) / N] / 2 = 1/4.

  As described above, since this frequency conversion device uses the symmetry of the waveform and performs frequency conversion in units of 1/2 cycle, processing can be performed with a smaller processing delay time. As a result, the required capacity of the buffer memory becomes smaller than that of the prior art.

  In the above description, the number of repetitions of each waveform is equal to the frequency conversion rate. However, as shown in FIG. 7, the number of repetitions of the first partial waveform X1 and the number of repetitions of the second partial waveform X2 are You can also make them different.

  Furthermore, in the above description, the input signal is assumed to be a stationary sine wave for convenience of description. However, the present invention can be similarly applied to an approximate sine wave whose amplitude and period vary globally, and other periodic signals having symmetry.

(Embodiment 2)
The second embodiment of the present invention will be described below with reference to the drawings. The configuration of the second embodiment is the same as that of the first embodiment (FIGS. 1A to 1C).

  In the first embodiment, the address / amplitude control means 14 controls the moving direction of the address of the buffer memory 12 only in the forward direction (direction in which the address increases), but in the second embodiment, the address / amplitude control means 14. Controls the movement direction of the address of the buffer memory 12 using both the forward direction and the reverse direction (direction in which the address becomes smaller).

  Hereinafter, the address / amplitude control means 14 moving the address of the buffer memory 12 and outputting the sample value of the address moved from the buffer memory 12 to the amplitude polarity switching means 15 is referred to as reproduction. The moving direction is called the playback direction.

  Next, the principle of integer multiple frequency conversion (frequency conversion rate: N = 2 to 5) when reproduction in the reverse direction is also used will be described with reference to FIGS.

  As in the first embodiment, it is assumed that the waveform of one cycle of the input signal can be decomposed into a first partial waveform X1 and a second partial waveform X2 as shown in FIG. 8A, for example.

  8B and 9A to 9C, the section described as “forward” indicates that the address moving direction is the forward direction, and the section described as “reverse”. Shows that the moving direction of the address is the reverse direction.

  As shown in FIG. 8B and the like, both the first partial waveform X1 and the second partial waveform X2 are alternately switched between the forward direction and the reverse direction during the repeated reproduction. It is done.

  Accordingly, when the frequency conversion rate is N, the address / amplitude control means 14 moves the read address of the buffer memory 12 at a speed N times the write address. As a result, a compressed partial waveform signal obtained by compressing either the first partial waveform X1 or the second partial waveform X2 by N times on the time axis is output to the amplitude polarity switching means 15.

  Further, the address / amplitude control means 14 folds the read address of the buffer memory 12 from the forward direction to the reverse direction or from the reverse direction to the forward direction during the first half cycle of the input signal. A compressed partial waveform signal obtained by compressing the partial waveform X1 of 1 on the time axis by N times is repeatedly reproduced a total of N times.

  Further, the address / amplitude control means 14 folds the read address of the buffer memory 12 from the forward direction to the backward direction or from the backward direction to the forward direction during the latter half cycle of the input signal. The signal of the compressed partial waveform obtained by compressing the partial waveform X2 of No. 2 by N times on the time axis is repeatedly reproduced N times in total.

  FIG. 8B shows the case of N = 2. Similarly, FIG. 9A shows the case of N = 3, FIG. 9B shows the case of N = 4, and FIG. Cases 5 are shown respectively. It will be easily understood that the present invention can be similarly applied to the case where N is 6 or more.

  In the above control method, the moving direction of the address when the second partial waveform X2 is first reproduced is set to the forward direction. However, actually, when the second partial waveform X2 is reproduced first. The address moving direction can also be reversed. However, it is preferable to start from the forward direction. This is because the processing delay time becomes smaller.

  In addition, for example, an irregular control method shown in FIG. 10 (frequency conversion rate: N = 3) is also conceivable. As described above, the reproduction direction can be variously changed based on the direction of the first embodiment, and both are included in the scope of the present invention.

  In addition, when the moving direction control of the address in both directions and the amplitude control are combined, the half-period point detecting unit 13 sets the maximum point and / or the minimum point of the input signal as a symmetric point. That is, the ½ period point detecting means 13 extracts a partial waveform of the input signal based on the maximum point and / or the minimum point of the input signal. More specifically, the half-cycle point detection means 13 may set the maximum point when the amplitude of the input signal changes from increase to decrease, and sets the minimum point when the amplitude of the input signal changes from decrease to increase. .

  For example, when the waveform of the input signal is a cosine wave as shown in FIG. 11A, the half-cycle point detection means 13 determines the first from the input signal based on the maximum point and the minimum point. The partial waveform X1 and the second partial waveform X2 can be extracted.

  When N = 2, the address / amplitude control means 14 can output the output signal shown in FIG. Similarly, as shown in FIG. 12b (a) when N = 3, FIG. 12 (b) when N = 4, and FIG. 12 (c) when N = 5, the address / amplitude control means 14 An output signal can be output from the terminal 16.

  Here, as described above, it will be easily understood that the present invention can be applied to a case where N is 6 or more.

  In the second embodiment, similarly to the first embodiment, the processing can be performed with a smaller processing delay time, and the necessary buffer memory capacity can be reduced as compared with the conventional technique.

  Similarly to the first embodiment, the detection location of the half cycle point is set to the buffer memory 12 or the output signal of the buffer memory 12 as shown in FIGS. 1B and 1C. Is also possible.

  Further, similarly to the first embodiment, the number of repetitions of the first partial waveform X1 and the second partial waveform X2 is not necessarily the same.

  Further, it is also possible to apply in the same manner to an approximately positive phase chord wave whose amplitude and period fluctuate globally and other periodic signals having symmetry. is there.

(Embodiment 3)
Prior to description of the specific configuration, the principle of the second frequency conversion method in the present invention will be described with reference to FIGS. The partial waveform in the second frequency conversion method is a waveform corresponding to ¼ period of the input signal. This is a type in which a quarter cycle is a processing unit for time axis compression operation and repeated reproduction operation. In the second frequency conversion method, in addition to the amplitude control, the address moving direction described in the second embodiment is also controlled. Both these controls make the output signal continuous.

  Now, the waveform of one cycle of the input signal is based on the zero cross point, the maximum point, and the minimum point, for example, as shown in FIG. 14A, the first partial waveform X1, the second partial waveform X2, It can be decomposed into a partial waveform X3 and a fourth partial waveform X4. In addition, what is necessary is just to process similarly to Embodiment 2 about a local maximum point and a local minimum point.

  If the frequency conversion rate is N, as shown in FIG. 14B, the first partial waveform X1, the second partial waveform X2, the third partial waveform X3, and the fourth partial waveform X4 are respectively When the compressed partial waveform is generated N times on the time axis to generate a compressed partial waveform, and the compressed partial waveform is reproduced N times, the desired reproduction can be realized. In FIG. 14B, N = 2.

(In the case of frequency conversion rate N = 2, 6, 10, 14, 18,...)
Next, a method for controlling the address movement direction will be described.

  As shown in FIG. 14B, the first partial waveform X1 is first switched to “order” for the first time and “reverse” for the second time. Next, the second partial waveform X2 is switched to “reverse” for the first time and “forward” for the second time. For the third partial waveform X3, the first time is switched to “forward” and the second time to “reverse”. Finally, the fourth partial waveform X4 is switched to “reverse” for the first time and “forward” for the second time.

  Next, amplitude control will be described. First, during the second repetition of the first partial waveform X1, a positive phase is obtained. Then, during the second repetition of the second partial waveform X2, the phase is switched to the opposite phase. During the second repetition of the third partial waveform X3, the phase is reversed, and during the second repetition of the fourth partial waveform X4, the phase is switched to the positive phase.

  By performing the above for each period, the frequency is converted to twice as a result. In the same manner, the frequency conversion rate can be expanded to N = 2, 6, 10, 14, 18,... (That is, N = 2 + 4 * i, i is an integer of 0 or more).

(In the case of frequency conversion rate N = 3, 7, 11, 15, 19,...)
Next, the case of FIG. 15A (N = 3) is taken as an example. For the first partial waveform X1, a partial waveform signal compressed to 1/3 on the time axis is repeatedly reproduced three times. Similarly, for the second partial waveform X2, the third partial waveform X3, and the fourth partial waveform X4, the partial waveform signal compressed to 1/3 on the time axis is repeatedly reproduced three times.

  A method of controlling the address moving direction at this time will be described. First, the first partial waveform X1 is switched to “order” for the first time, “reverse” for the second time, and “order” for the third time. Next, the second partial waveform X2 is switched to “order” for the first time, “reverse” for the second time, and “order” for the third time. The third partial waveform X3 is switched to “order” as it is for the first time, “reverse” for the second time, and “order” for the third time. As for the fourth partial waveform X4, the first time is switched to “order” as it is, the second time is “reverse”, and the third time is “forward”.

  Next, amplitude control will be described. First, for the first partial waveform X1, the first and second repetitions are in phase. Switch to reverse phase for the third time. The first time of the next second partial waveform X2 is switched to the reverse phase as it is, and the second and third times are switched to the positive phase. The first and second repetitions of the third partial waveform X3 are in the normal phase, and the third is switched to the reverse phase. The first time of the fourth partial waveform X4 is switched to the reverse phase as it is, and the second and third times are switched to the positive phase.

  By performing the above for each period, the frequency is converted to three times as a result. In the same manner, the frequency conversion rate can be expanded to N = 3, 7, 11, 15, 19,... (That is, N = 3 + 4 * i, i is an integer of 0 or more).

(In the case of frequency conversion rate N = 4, 8, 12, 16, 20,...)
Next, the case of FIG. 15B (N = 4) is taken as an example. For the first partial waveform X1, a partial waveform signal compressed to ¼ on the time axis is repeatedly reproduced four times. Similarly, the partial waveform signals compressed to ¼ on the time axis for the second partial waveform X2, the third partial waveform X3, and the fourth partial waveform X4 are repeatedly reproduced four times.

  A method of controlling the address moving direction at this time will be described. First, the first partial waveform X1 is switched to “order” for the first time, “reverse” for the second time, “order” for the third time, and “reverse” for the fourth time. Next, for the second partial waveform X2, the first time is “reverse” as it is, the second time is “order”, the third time is “reverse”, the fourth time is “reverse”, and the fourth time is “forward”. For the third partial waveform X3, the first time is switched to “order” as it is, the second time is “reverse”, the third time is “order”, and the fourth time is “reverse”. As for the fourth partial waveform X4, the first time is “reverse” as it is, the second time is “reverse”, the third time is “forward”, and the fourth time is “reverse”.

  Next, amplitude control will be described. First, the first and second repetitions of the first partial waveform X1 are in phase. Switch to reverse phase for the third and fourth times. The first and second times of the next second partial waveform X2 are switched to the normal phase, and the third and fourth times are switched to the reverse phase. The first and second repetitions of the third partial waveform X3 are in reverse phase, and are switched to the positive phase in the third and fourth times. For the fourth partial waveform X4, the first and second times are switched to the reverse phase, and the third and fourth times are switched to the positive phase.

  By performing the above for each period, the frequency is converted to four times as a result. In the same manner, the frequency conversion rate can be expanded to N = 4, 8, 12, 16, 20,... (That is, N = 4 + 4 * i, i is an integer of 0 or more).

(In the case of frequency conversion rate N = 5, 9, 13, 17, 21,...)
Next, the case of FIG. 15C (N = 5) is taken as an example. For the first partial waveform X1, a partial waveform signal compressed to 1/5 on the time axis is repeatedly reproduced five times. Similarly, the partial waveform signal compressed to 1/5 on the time axis is repeatedly reproduced five times for the second partial waveform X2, the third partial waveform X3, and the fourth partial waveform X4.

  A method of controlling the address moving direction at this time will be described. First, the first partial waveform X1 is switched to “order” for the first time, “reverse” for the second time, “order” for the third time, “reverse” for the fourth time, and “order” for the fifth time. Next, the second partial waveform X2 is switched to “order” for the first time, “reverse” for the second time, “order” for the third time, “reverse” for the fourth time, and “forward” for the fifth time. As for the third partial waveform X3, the first time is changed to “order”, the second time is “reverse”, the third time is “order”, the fourth time is “reverse”, the fourth time is “reverse”, and the fifth time is “forward”. For the fourth partial waveform X4, the first time is switched to “order”, the second time is “reverse”, the third time is “order”, the fourth time is “reverse”, the fourth time is “reverse”, and the fifth time is “forward”.

  Next, amplitude control will be described. First, for the first partial waveform X1, the first and second repetitions are in phase. The third and fourth times are switched to the reverse phase, and the fifth time is switched to the normal phase. The first time of the next second partial waveform X2 is the normal phase as it is, the second and third times are switched to the reverse phase, and the fourth and fifth times are switched to the positive phase. The first and second times of the third partial waveform X3 are in the normal phase, and the third and fourth times are switched to the reverse phase, and the fifth time is switched to the positive phase. The first time of the fourth partial waveform X4 is the normal phase as it is, the second and third times are in reverse phase, and the fourth and fifth times are in positive phase.

  By performing the above for each period, the frequency is converted to 5 times as a result. In the same manner, the frequency conversion rate can be expanded to N = 5, 9, 13, 17, 21,... (That is, N = 5 + 4 * i, i is an integer of 0 or more).

  From the above description, it will be understood that the second frequency conversion method in the present invention can be applied when the frequency conversion rate N is an arbitrary integer of 2 or more.

Here, the address movement direction and amplitude control have the following regularity common to each frequency conversion rate.
“Rules for switching the direction of address movement (in the case of a quarter cycle)”
The first repetition of the first partial waveform X1 is “order”, and thereafter, “order” and “reverse” are alternately switched for each repetition. In the first iteration of the second partial waveform X2, the previous amplitude control ("forward" if "forward", "reverse" if "reverse") is taken over. Then, after the second time, similarly to the first partial waveform X1, the amplitude control is switched alternately every repetition. The third partial waveform X3 and the fourth partial waveform X4 are the same as the second partial waveform X2.
"Rules for amplitude control (in case of 1/4 cycle)"
Starting from the normal phase, the switching is performed in units of ½ period of the output signal, and the control is performed by alternately switching the normal phase and the reverse phase. However, at the time of switching to an integral multiple of the frequency conversion rate N (Nth, 2Nth, 3Nth,...), The immediately preceding amplitude control (normal phase if positive phase, negative phase if negative phase) ).

  Based on the second frequency conversion method described above, a specific configuration will be described below.

  FIG. 13A is a block diagram of a frequency conversion device according to Embodiment 3 of the present invention. As shown to Fig.13 (a), the frequency converter of this form is provided with the following element. In addition, about the component similar to Fig.1 (a), description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  The buffer memory 22 stores an input signal input from the input terminal 11. Here, since the third embodiment is based on the second frequency conversion method, it is sufficient for the buffer memory 22 to have a capacity capable of storing an input signal for ¼ period of the input signal.

  The quarter period point detection means 23 detects a start point on the time axis of the input signal and a quarter period point in which the input signal has advanced from the start point by a quarter period on the time axis. In this embodiment, the quarter period point detection means 23 detects a quarter period point (a point of symmetry of the input signal) based on the zero cross point, the maximum point, and the minimum point of the input signal. The quarter cycle point detection means 23 detects five quarter cycle points, so that the waveform of one cycle of the input signal is the first one located in the earliest quarter cycle in order on the time axis. A partial waveform X1, a second partial waveform X2 located in a quarter period following the first partial waveform X1, a third partial waveform X3 located in a quarter period following the second partial waveform X2, and , And the fourth partial waveform X4 located in a quarter cycle following the third partial waveform X3 (see FIG. 14A).

  The address / amplitude control means 24 generates a read address for the buffer memory 22 and controls the amplitude polarity switching of the amplitude polarity switching means 15. The address / amplitude control means 24 controls the amplitude / polarity switching means 15 based on the “amplitude control rule (in the case of a quarter cycle)”. The address / amplitude control means 24 generates a read address for the buffer memory 22 on the basis of the “rule of switching of the moving direction of the address (in the case of a quarter cycle)”.

  The quarter cycle point detection means 23 may be connected to the input terminal 11 as shown in FIG. 13A, or may be connected to the buffer memory 22 as shown in FIG. As shown in FIG. 13C, the buffer memory 22 and the amplitude polarity switching means 15 may be connected in the middle.

  Next, the operation will be described. The input signal is written in the buffer memory 22, and the quarter cycle point detection means 23 detects a quarter cycle point.

  The address / amplitude control means 24 generates a read address for the buffer memory 22. The read address moves while being repeated N times so as to fold back each section of the detected quarter cycle point. Here, the read address is updated based on the “rule for switching the moving direction of the address (in the case of a quarter cycle)”.

  Further, during this update operation, the address / amplitude control means 24 switches the amplitude polarity in the amplitude polarity switching 15 in a timely manner when the read address reaches each quarter period point. The switching is in accordance with the “amplitude control rule (in the case of ¼ period)” already described.

  The address generated as described above is sent to the buffer memory 22. The corresponding sample is read from the buffer memory 22, the amplitude polarity switching means 15 determines the amplitude polarity, and the output of the amplitude polarity switching means 15 is output to the outside via the output terminal 16.

  Similar to the first frequency conversion method, the processing delay time in this embodiment (second frequency conversion method) is obtained from the relationship between the movement amount of the write / read address when the two addresses are closest. Here, only the result is shown.

When the frequency conversion rate N is an odd number (3, 5, 7, 9,...),
[(N-1) / N] T / 4 (2)
When the frequency conversion rate N is an even number (2, 4, 8,...),
T / 2 (3)
It becomes.

  Thus, in any case, the processing delay time is shortened compared to the processing delay time T of the prior art. Therefore, the required capacity of the buffer memory 22 is smaller than that of the prior art. Compared to the first embodiment, the processing delay time is halved for odd-order overtones, but the processing delay time is longer for even-order overtones.

  Further, as in the previous embodiments, the number of repetitions of each partial waveform X1 to X4 is not necessarily the same.

  For even-order overtones, if the setting shown in FIG. 16 (frequency conversion rate: N = 2) or FIG. 17 (frequency conversion rate: N = 4) is used, even in the case of even-order overtones, equation (2) ) Processing delay time can be reduced.

  In the above description, the input signal is assumed to be a stationary positive-phase chord wave for convenience of description. However, the present invention can be similarly applied to a substantially positive phase wave whose amplitude and period vary globally, and other periodic signals having symmetry.

  Furthermore, it is possible to extend the above-described way of thinking and use a 3/4 cycle as a processing unit.

(Embodiment 4)
Next, a case where the frequency conversion device according to any one of Embodiments 1 to 3 is applied to an acoustic device will be described with reference to FIGS.

  FIGS. 18A and 18B show the basic configuration of a pseudo bass reproduction device that generates overtones related to the bass range and enhances the bass feeling by the virtual pitch effect. In FIG. 18 (a), the low-pass filter 182 extracts a low-frequency component from the input signal input from the input terminal 181, and the harmonic sequence generator 183 generates a harmonic sequence based on the low-frequency component. The data is output to the adder 185. The delay 184 is provided to adjust the processing delay time for the low-pass filter 182 and the harmonic string generation means 183, and the input signal delayed by the delay 184 is output to the adder 185. The adder 185 adds these two input signals and outputs the addition result to the output terminal 186.

  FIG. 18B shows a pseudo bass reproduction apparatus obtained by changing the configuration of FIG. This pseudo bass reproduction apparatus includes a band dividing unit 187, and a plurality of harmonic string generating units 188a to 188b provided at the subsequent stage of the band dividing unit 187 include a harmonic sequence for each band signal divided by the band dividing unit 187. Is generated.

  The harmonic string generating means 183 and 188a to 188b shown in FIGS. 18A and 18B can be configured as shown in FIG. In FIG. 19, the frequency converter described in the first to third embodiments can be used for the double frequency conversion means 192a,. An input signal is input from the input terminal 191, and the double frequency conversion means 192a,..., N frequency conversion means 192c generates each harmonic. Each harmonic overtone is subjected to gain adjustment by the gain adjusters 193a to 193c, and then synthesized by the adder 194. The addition result of the adder 194 is output from the output terminal 195 to the outside.

  According to the present invention, the processing delay time related to the overtone generation process can be reduced, and therefore the processing delay time of the entire pseudo bass reproduction apparatus can be reduced. Further, since the delay amount of the delay 184 can be reduced accordingly, the memory amount related to this can also be reduced.

  Here, it is not necessary to match the delay amount of each band uniformly. For example, a configuration is possible in which the amount of delay of the high-frequency harmonic generation means is less than that of the low-band harmonic generation means within the minimum required processing delay time. This configuration is highly effective in that the delay on the high frequency side where the problem of processing delay time tends to become more prominent can be reduced.

  In the pseudo bass reproduction apparatus, frequency conversion is performed on a signal in the low frequency range, and one cycle of the original signal becomes long. Therefore, the processing delay time and the amount of processing memory are likely to be problematic, and the application of the present invention is particularly effective. In addition, the configuration in which the band division processing is introduced as shown in FIG. 18B approaches an ideal state (the input signal that is the basis of the frequency conversion is a sine wave) for implementing the present invention. High compatibility.

  The frequency conversion device according to the present invention can be suitably used, for example, in the acoustic field.

(A) Block diagram of the frequency converter in the first embodiment of the present invention (b) Block diagram of the frequency converter in the first embodiment of the present invention (c) Block of the frequency converter in the first embodiment of the present invention Figure (A) Exemplary diagram of input signal in the first embodiment of the present invention (b) Exemplary diagram of output signal in the first embodiment of the present invention (A) Exemplary diagram of an output signal in the first embodiment of the present invention (b) Exemplary diagram of an output signal in the first exemplary embodiment of the present invention (c) Exemplary diagram of an output signal in the first exemplary embodiment of the present invention (A) An explanatory diagram of an address operation in the first embodiment of the present invention (b) An explanatory diagram of an address operation in the first embodiment of the present invention (c) An explanatory diagram of an address operation in the first embodiment of the present invention (A) Explanatory drawing of address operation in Embodiment 1 of this invention (b) Explanatory drawing of address operation in Embodiment 1 of this invention Explanatory drawing of processing delay time in Embodiment 1 of this invention Exemplary diagram of output signal in Embodiment 1 of the present invention (A) Illustration of input signal in embodiment 2 of the present invention (b) Illustration of output signal in embodiment 2 of the present invention (A) Illustration of output signal in embodiment 2 of the present invention (b) Illustration of output signal in embodiment 2 of the present invention (c) Illustration of output signal in embodiment 2 of the present invention Exemplary diagram of output signal in Embodiment 2 of the present invention (A) Illustration of input signal in embodiment 2 of the present invention (b) Illustration of output signal in embodiment 2 of the present invention (A) Illustration of output signal in embodiment 2 of the present invention (b) Illustration of output signal in embodiment 2 of the present invention (c) Illustration of output signal in embodiment 2 of the present invention (A) Block diagram of the frequency converter in the third embodiment of the present invention (b) Block diagram of the frequency converter in the third embodiment of the present invention (c) Block of the frequency converter in the third embodiment of the present invention Figure (A) Exemplary diagram of input signal in Embodiment 3 of the present invention (b) Exemplary diagram of output signal in Exemplary Embodiment 3 of the present invention (A) Exemplary diagram of output signal in embodiment 3 of the present invention (b) Exemplary diagram of output signal in exemplary embodiment 3 of the present invention (c) Exemplary diagram of output signal in exemplary embodiment 3 of the present invention Exemplary diagram of output signal in embodiment 3 of the present invention Exemplary diagram of output signal in embodiment 3 of the present invention (A) Block diagram of the pseudo bass reproduction apparatus in the present invention (b) Block diagram of the pseudo bass reproduction apparatus in the present invention Block diagram of overtone generation means in the present invention (A) Illustration of conventional input signal (b) Illustration of conventional output signal Block diagram of a conventional frequency converter Illustration of conventional processing delay time

Explanation of symbols

11, 181, 191, 211 Input terminals 12, 22, 212 Buffer memory 13 1/2 period detection means 14, 24 Address / amplitude control means 15 Amplitude polarity switching means 16, 186, 195, 215 Output terminal 23 1/4 period Detection means 182 Low-pass filter 183, 188a to 188c Overtone sequence generation means 184 Delay 185, 194 Adders 192a to 192c Frequency conversion means 193a to 193c Gain adjuster 214 Read address generation means

Claims (23)

A device that converts an input signal that can be regarded as having periodicity in a short time according to a frequency conversion rate,
Detecting means for detecting information for extracting a partial waveform signal using periodicity from the input signal;
A buffer memory capable of storing at least the partial waveform of the input signal;
Based on the information detected by the detection means, the reading speed from the buffer memory and the writing speed to the buffer memory are controlled, and a compressed partial waveform obtained by compressing the partial waveform to the frequency conversion rate is multiplied on the time axis. A frequency converter comprising: control means for generating and generating an output signal using the compressed partial waveform. Amplitude polarity switching means for switching the amplitude polarity of the output signal to normal phase or reverse phase,
The detection means includes symmetry point detection means for detecting a symmetry point of the input signal, and the partial waveform is divided by the symmetry points detected by the symmetry point detection means,
The control means generates a read address from the buffer memory based on the symmetry point detected by the symmetry point detection means, and controls the amplitude polarity switching means so that the output signal becomes a continuous signal. Including address and amplitude control means for generating
The address / amplitude control means includes:
Generating the compressed partial waveform such that the moving speed of the read address from the buffer memory is the frequency conversion factor times the moving speed of the write address to the buffer memory;
Control the moving direction of the read address of the buffer memory;
2. The frequency conversion apparatus according to claim 1, wherein the compressed partial waveform is repeatedly used a predetermined number of times within an interval delimited by the symmetry points detected by the symmetry point detection means. The frequency conversion apparatus according to claim 2, wherein the predetermined number of repetitions is equal to the frequency conversion rate. 4. The frequency conversion apparatus according to claim 2, wherein said address / amplitude control means sets a moving direction of a read address of said buffer memory as a forward direction. 4. The frequency converter according to claim 2, wherein the address / amplitude control means switches a moving direction of the read address of the buffer memory by setting a moving direction of the read address of the buffer memory as a forward direction or a reverse direction. 5. The frequency converter according to claim 2, wherein a width of the partial waveform on the time axis is ½ of a period of the input signal. 5. The frequency converter according to claim 2, wherein a width of the partial waveform on the time axis is ¼ of a cycle of the input signal. The control information is information for instructing to alternately switch the amplitude polarity of the output signal between the normal phase and the reverse phase while the current partial waveform is being used, and shifts to use of the next partial waveform. The frequency converter according to claim 6, which is information instructing to take over the amplitude polarity immediately before the transition. The control information is information that is switched in units of ½ period of the output signal, and instructing to take over the amplitude polarity immediately before the switching at the time of the integral multiple of the frequency conversion rate, the control information is 8. The frequency conversion device according to claim 7, wherein the frequency conversion device is information for instructing to alternately switch the amplitude polarity of the output signal between the normal phase and the reverse phase except at the time of switching. The frequency conversion apparatus according to claim 2, wherein the symmetry point detection unit includes a zero cross point of the input signal in the symmetry point. The frequency conversion device according to claim 2 or 10, wherein the symmetry point detection means includes the maximum value of the input signal and the minimum value of the input signal at the symmetry point. A pseudo bass reproduction device including a frequency conversion device that converts an input signal that can be regarded as having periodicity in a short time according to a frequency conversion rate,
The frequency converter is
Detecting means for detecting information for extracting a partial waveform signal using periodicity from the input signal;
A buffer memory capable of storing at least the partial waveform of the input signal;
Based on the information detected by the detection means, the reading speed from the buffer memory and the writing speed to the buffer memory are controlled, and a compressed partial waveform obtained by compressing the partial waveform to the frequency conversion rate is multiplied on the time axis. A pseudo bass reproduction apparatus comprising: control means for generating and generating an output signal using the compressed partial waveform. A method of converting an input signal that can be regarded as having periodicity in a short time according to a frequency conversion rate,
A detection step for detecting information for extracting a partial waveform signal using periodicity from the input signal;
Storing the input signal in at least the partial waveform buffer memory;
Based on the information detected in the detecting step, the reading speed from the buffer memory and the writing speed to the buffer memory are controlled, and a compressed partial waveform obtained by compressing the partial waveform to the frequency conversion factor times on the time axis is obtained. And a control step of generating an output signal using the compressed partial waveform. Amplitude polarity switching step for switching the amplitude polarity of the output signal to normal phase or reverse phase,
The detection step includes a symmetry point detection step of detecting a symmetry point of the input signal, and the partial waveform is delimited by the symmetry point of the input signal,
The control step includes generating a read address from the buffer memory based on the symmetry point detected in the symmetry point detection step, and generating control information so that the output signal becomes a continuous signal,
In the step of generating the control information,
Generating the compressed partial waveform such that the moving speed of the read address from the buffer memory is the frequency conversion factor times the moving speed of the write address to the buffer memory;
Control the moving direction of the read address of the buffer memory;
14. The frequency conversion method according to claim 13, wherein the output signal is generated by repeatedly using the compressed partial waveform within a section delimited by the symmetry point a predetermined number of times. The frequency conversion method according to claim 14, wherein the predetermined number of repetitions is equal to the frequency conversion rate. 16. The frequency conversion method according to claim 14, wherein in the step of generating the control information, a moving direction of the read address of the buffer memory is a forward direction. 16. The frequency conversion method according to claim 14, wherein, in the step of generating the control information, a moving direction of the read address of the buffer memory is set to a forward direction or a reverse direction, and the moving direction of the read address of the buffer memory is switched. 17. The frequency conversion method according to claim 14, wherein a width of the partial waveform on the time axis is ½ of a period of the input signal. 17. The frequency conversion method according to claim 14, wherein a width of the partial waveform on the time axis is ¼ of a period of the input signal. The control information is information for instructing to alternately switch the amplitude polarity of the output signal between the normal phase and the reverse phase while the current partial waveform is being used, and shifts to use of the next partial waveform. 19. The frequency conversion method according to claim 18, which is information instructing to take over the amplitude polarity immediately before the transition. The control information is information that is switched in units of ½ period of the output signal, and instructing to take over the amplitude polarity immediately before the switching at the time of the integral multiple of the frequency conversion rate, the control information is 20. The frequency conversion method according to claim 19, wherein the frequency conversion method is information instructing to alternately switch the amplitude polarity of the output signal between a normal phase and a reverse phase except when switching. The frequency conversion method according to claim 14, wherein in the symmetry point detection step, a zero cross point of the input signal is included in the symmetry point. The frequency conversion method according to claim 14 or 22, wherein in the symmetry point detection step, a local maximum value of the input signal and a local minimum value of the input signal are included in the symmetry point.

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