JP2005322766A - Designing method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the extraction of charge-up countermeasure information from layout pattern data in a short period of time. <P>SOLUTION: Layout pattern data for a circuit block that constitute a semiconductor integrated circuit are created (S1). Next, pattern data for a charge-up countermeasure necessary for charge up is extracted from the layout pattern data (S2). Next, charge-up countermeasure information is extracted from the pattern data for the charge-up countermeasure (S3). Then, an automatic layout and wiring tool (automatic layout program) is caused to operate based on the charge-up countermeasure information to perform automatic layout and wiring of the circuit block (S4). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a method for designing a semiconductor integrated circuit capable of realizing automatic placement and routing in consideration of charge-up countermeasures.

  Conventionally, in a plasma process that realizes microfabrication of a semiconductor integrated circuit, a charge-up phenomenon that causes destruction of a semiconductor element and a decrease in reliability has been a problem. For example, a metal layer is processed by patterning a resist on the metal layer and plasma etching the metal layer using the resist as a mask. At this time, the gate oxide film of the MOS transistor is charged by the charge charged in the resist. May be damaged, and the destruction and reliability of the MOS transistor may be deteriorated.

As a measure for preventing such a charge-up phenomenon, there is a measure for pattern layout in addition to a measure for process technology. As a measure for the pattern layout, a design rule for charge-up measures is determined based on a gate area, an antenna ratio, and the like, and a pattern layout is performed based on this rule.
JP 2000-150607 A JP 2003-209172 A

  By the way, when the present inventor examined a method for designing a semiconductor integrated circuit in consideration of such charge-up countermeasures, the following problems became clear. As shown in FIG. 5, layout pattern data of a circuit block (for example, a memory circuit) having a semiconductor integrated circuit is created (S11). This layout pattern data is called GDS data (stream data).

  Then, this layout pattern data is read into the working memory area of the computer, a predetermined information extraction program is operated, and charge-up countermeasure information (for example, the area of the diffusion layer connected to a specific terminal of the circuit block is obtained from the layout pattern data. Then, the area of the gate and information on the wiring length from the terminal to the diffusion layer or the gate are extracted (S12).

  However, since the amount of layout pattern data is generally enormous, there has been a problem that it takes an enormous amount of time to extract the information for charge-up countermeasures.

  Therefore, the semiconductor integrated circuit design method of the present invention creates layout pattern data of circuit blocks constituting the semiconductor integrated circuit, extracts charge-up countermeasure pattern data necessary for charge-up countermeasures from the layout pattern data, Charge-up countermeasure information is extracted from the charge-up countermeasure pattern data.

  In addition to the above configuration, the circuit block is automatically placed and routed using an automatic place and route tool based on the charge-up countermeasure information. In addition to the above configuration, the charge-up countermeasure information includes information on the area of the diffusion layer connected to the specific terminal of the circuit block, the area of the gate, and the wiring length from the terminal to the diffusion layer or the gate. It is characterized by including.

  According to the present invention, the charge-up countermeasure pattern data necessary for the charge-up countermeasure is extracted from the layout pattern data, and the charge-up countermeasure information is extracted from the charge-up countermeasure pattern data. It becomes possible to do.

  In particular, so-called circuit IP is used in recent semiconductor integrated circuit designs. By creating the circuit IP under the charge-up countermeasure information creation environment of the present invention, an accurate charge-up countermeasure information file can be created in a short time. This is particularly effective for creating a charge-up countermeasure information file for a large-scale circuit IP.

  Therefore, according to the present invention, it is possible to completely take charge-up countermeasures using the automatic placement and routing tool. Further, the physical verification at the time of final verification of the layout pattern also results in zero error, and no design rule violation for charge-up occurs. This eliminates pattern correction iterations, leading to TAT reduction of the semiconductor integrated circuit.

  Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart for explaining a method of designing a semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram showing an example of a charge-up countermeasure pattern necessary for charge-up countermeasures extracted from the layout pattern data. FIG. 3 is a diagram showing an example of charge-up countermeasure information extracted from the charge-up countermeasure pattern data.

  As shown in FIG. 1, the semiconductor integrated circuit design method of the present invention creates layout pattern data of a circuit block (for example, a memory circuit) having a semiconductor integrated circuit (S1). This layout pattern data is called GDS data (stream data). Next, charge-up countermeasure pattern data necessary for charge-up countermeasures is extracted from the layout pattern data (S2).

  Here, the charge-up countermeasure pattern data necessary for the charge-up countermeasure is, for example, the pattern data of the metal wiring constituting a certain terminal (node), and the pattern of the diffusion layer and the gate connected to the metal wiring. It is data. The longer the metal wiring, the more electric charges are charged in the plasma process, and the greater the damage given to the gate oxide film of the MOS transistor. Therefore, the charge-up countermeasure here is to design so as to satisfy the design rule that regulates the length of the metal wiring to a certain value or less according to the area of the diffusion layer and gate connected to the metal wiring. .

  Specifically, as shown in FIG. 2, for example, for the output terminal Y11, the charge-up countermeasure pattern includes a metal wiring MA connected to the output terminal Y11 and an output MOS transistor connected via the metal wiring MA. This is a pattern of diffusion layers D1 and D2 of MT1 and diffusion layers D3 and D4 of another output MOS transistor MT2. The original layout pattern data includes other data such as gate electrodes and contacts, but this charge-up countermeasure pattern data does not include them, and other parts not related to charge-up countermeasures. Is not included at all.

  The input terminal A11 has a pattern of metal wiring MB and gates G1 and G2 connected to the input terminal A11. The gates G1 and G2 correspond to the gate portions of the input MOS transistors MT3 and MT4 (the gate oxide film portions of the MOS transistors), respectively, but do not include other unnecessary data in the same manner. Therefore, the amount of data is much smaller than the original layout pattern data.

  Therefore, the next step, that is, the step of reading the charge-up countermeasure pattern data into the working memory area of the computer, operating a predetermined information extraction program, and extracting the charge-up countermeasure information from the charge-up countermeasure pattern data is shortened. It can be processed in time (S3).

  Here, as shown in FIG. 3, the charge-up countermeasure information includes the length of the metal wiring connected to each of the terminals Y1, Y2,... Information on whether the wiring is the layer) The gate area of the gate connected to the metal wiring, the diffusion area of the diffusion layer, and the like are included. In the charge-up countermeasure pattern data of FIG. 2, for example, information on the length of the metal wiring MA connected to the output terminal Y11, the wiring level, and the areas of the diffusion layers D1 to D4.

  Based on the charge-up countermeasure information, an automatic placement and routing tool (automatic placement program) is operated to perform automatic placement and routing of the circuit block. FIG. 4 is a diagram for explaining an example of such automatic placement and routing. In this example, automatic placement and routing of two circuits IP1 and IP2 is performed. The automatic placement and routing tool performs placement of two circuits IP1 and IP2 and necessary wiring between them based on connection information (net list information) of circuit elements.

  For example, it is assumed that one output terminal Y11 of the circuit IP1 is connected to the input terminal A21 of the circuit IP2 by the metal wiring M1. At this time, the automatic placement and routing tool refers to the charge-up countermeasure information corresponding to the output terminal Y11 and the input terminal A21, determines the length of the metal wiring M1 so as to satisfy the predetermined charge-up countermeasure design rule, If there is a design rule violation, change its length.

5 is a flowchart illustrating a method for designing a semiconductor integrated circuit according to an embodiment of the present invention. It is a figure which shows an example of the pattern for a charge-up countermeasure required for the charge-up countermeasure extracted from layout pattern data. It is a figure which shows an example of the chargeup countermeasure information extracted from the pattern data for chargeup countermeasures. It is a figure explaining the automatic arrangement | positioning wiring by the design method of the semiconductor integrated circuit which concerns on one Embodiment of this invention. It is a flowchart explaining the design method of the semiconductor integrated circuit which this inventor examined.

Explanation of symbols

Y11 output terminal A11 input terminal D1, D2, D3, D4 diffusion layer G1, G2 gate MT1, MT2, MT3, MT4 MOS transistor

Claims (3)

Layout pattern data for circuit blocks constituting a semiconductor integrated circuit is created, charge-up countermeasure pattern data necessary for charge-up countermeasures is extracted from the layout pattern data, and charge-up countermeasure information is extracted from the charge-up countermeasure pattern data. A method for designing a semiconductor integrated circuit, comprising extracting the semiconductor integrated circuit. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein automatic placement and routing of the circuit block is performed using an automatic placement and routing tool based on the charge-up countermeasure information. The charge-up countermeasure information includes information on an area of a diffusion layer connected to a specific terminal of the circuit block, an area of a gate, and a wiring length from the terminal to the diffusion layer or the gate. A method for designing a semiconductor integrated circuit according to claim 1 or 2.

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