JP2005322174A - Arithmetic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic device capable of continuously carrying out a process for executing different computation depending on an input condition, of preventing an useless processing in the case where the process is interrupted when a condition is satisfied, and of improving transfer efficiency. <P>SOLUTION: This arithmetic device includes: an address generator 12 for providing an address ADR12 to a bank 111 to read first data for computation of a computing unit 15 and for outputting the first data as first source data DT11; an address generator 13 for providing an address ADR13 to a bank 112 to read second data for computation of the computing device 15 and for outputting the second data as second source data DT12 along with a control signal CTLOP for computation; and the computing unit 15 for executing conditional execution computation according to the control signal CTLOP to the first source data DT11 and the second source data DT12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a so-called data flow type arithmetic apparatus.

  In the case of a conventional data flow type arithmetic unit, continuous data is transferred from a memory, and one kind of predetermined operation is continuously performed on the transferred data.

  However, in the case of such an arithmetic unit, it is impossible to continuously perform processing that performs different calculations depending on input conditions.

  Further, even if the processing is interrupted halfway if a certain condition is satisfied, a predetermined number of processings must be performed, so that useless processing has been performed.

  Furthermore, when data having a word length smaller than the data bus width is accumulated, there is a disadvantage that transfer efficiency is deteriorated, for example, when 8-bit data is handled in a 32-bit bus system.

  The present invention has been made in view of such circumstances, and an object of the present invention is to be able to continuously perform processing that performs different calculations depending on input conditions, and to interrupt processing in the middle if the conditions are satisfied. An object of the present invention is to provide an arithmetic unit that can prevent useless processing in such a case and can improve transfer efficiency.

  In order to achieve the above object, an arithmetic device according to a first aspect of the present invention includes a first generation device that generates first source data, second source data, and the second source. A second generation device that outputs a control signal added to the data, the first source data by the first generation device, and the control signal for the second source data by the second generation device. And an arithmetic unit that performs a predetermined operation by switching the operation type accordingly.

  Preferably, the memory has a memory for storing the first source data and the second source data, and the first generation device generates an address for reading the first source data, and the address The first source data read based on the second source data is output to the computing unit, and the second generation device generates an address for reading the second source data, and reads the second source data based on the second address. Source data and the control signal are output to the computing unit.

  Preferably, the apparatus further includes a third generation device that receives an operation result of the operation unit, generates an address, and writes the operation result in the memory.

  An arithmetic device according to a second aspect of the present invention includes a first generation device that generates first source data, a second generation device that generates second source data, and a second generation device of the second generation device. A first arithmetic unit that performs predetermined arithmetic processing on the second source data to generate third source data, adds a control signal to the third source data, and outputs the third source data; A second computing unit that performs a predetermined computation by switching a computation type according to the control signal for the first source data by the generation device and the third source data by the first computing unit.

  Preferably, the memory has a memory for storing the first source data and the second source data, and the first generation device generates an address for reading the first source data, and the address The first source data read based on the second source data is output to the second arithmetic unit, and the second generation device generates an address for reading the second source data, and reads based on the address. The second source data is output to the first arithmetic unit.

  Preferably, the apparatus further includes a third generation device that receives an operation result of the second arithmetic unit, generates an address, and writes the operation result in the memory.

  Preferably, the second arithmetic unit adds and outputs a control signal to the arithmetic result, generates an address in response to the arithmetic result and the control signal of the second arithmetic unit, and outputs the arithmetic result to the above A third generation device for writing to the memory is further included.

  An arithmetic device according to a third aspect of the present invention includes a first generation device that generates first source data, a second generation device that generates second source data, and a first generation device of the first generation device. A first arithmetic unit that performs predetermined arithmetic processing on the first source data and the second source data by the second generation device to generate third source data; and a third arithmetic unit by the first arithmetic unit. A second arithmetic unit that performs a predetermined operation on the source data and outputs a control signal, and receives a calculation result and a control signal by the second arithmetic unit, and receives the second and third A third generation device that generates a control signal for controlling the generation operation of the generation device.

  Preferably, the memory has a memory for storing the first source data and the second source data, and the first generation device generates an address for reading the first source data, and the address The first source data read based on the second source data is output to the second arithmetic unit, and the second generation device generates an address for reading the second source data, and reads based on the address. The third generation device that outputs the second source data to the first arithmetic unit receives the calculation result of the second arithmetic unit and the control signal, generates an address, and stores the calculation result in the memory Write to.

  According to a fourth aspect of the present invention, a memory for storing first, second, third, and fourth source data and an address for reading the first source data are generated, and based on the address A first generation device that outputs the read first source data, an address for reading the second source data, and a first control signal for the second source data read based on the address A second generation device that adds and outputs, a third generation device that generates an address for reading the third source data, and outputs the third source data read based on the address; Address data is generated by performing an operation on the first source data by the first generation device and the second source data by the second generation device according to the first control signal. In order to read out the fourth source data based on the address data and the second control signal by the first arithmetic unit that outputs the address data with a second control signal added thereto. A fourth generation device that generates a fourth source data read out based on the address, a third source data by the third generation device, and a fourth source data by the fourth generation device. A second computing unit that performs a predetermined computation on the source data of 4 and outputs, and receives an operation result of the second computing unit, generates an address, and writes the operation result to the memory A generator.

  Preferably, the arithmetic unit treats and accumulates a plurality of data when performing accumulation with data having a word length smaller than the bus width.

According to the present invention, for example, when the operation is switched from addition to subtraction only when a specific index condition is satisfied, the arithmetic unit itself does not know the array index, that is, the memory address, so The side that issues the address, that is, the second generation device generates the control signal.
A control signal is passed to the computing unit together with the data read from the memory by the second generation device, whereby a series of processing is performed in which the computation is performed and the result is written into the memory, for example.

According to the present invention, it is possible to continuously perform processing that performs different calculations depending on input conditions.
Further, if the condition is satisfied, there is an advantage that it is possible to suppress useless processing when the processing is interrupted in the middle, and to improve transfer efficiency.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a configuration diagram showing a first embodiment of a data flow type arithmetic unit according to the present invention.

  The arithmetic device 10 includes a memory 11 having a plurality (three in FIG. 1) of banks 111 to 113, first to third address generation devices 12 (AG0) provided in response to the banks 111 to 113, 13 (AG1), 14 (AG2), and a computing unit (PE) 15.

  The address generator 12 gives the address ADR12 and the control signal CTL12 to the bank 111, reads the first data for the calculation of the calculator 15, and outputs the first data to the calculator 15 as the first source data DT11.

  The address generation device 13 gives the address ADR13 and the control signal CTL13 to the bank 112, reads the second data for the calculation of the calculator 15, and calculates the calculator 15 as the second source data DT12 together with the calculation control signal CTLOP. Output to.

  The address generation device 14 gives the address ADR 14 and the control signal CTL 14 to the bank 113 and stores the calculation result of the calculator 15 in the bank 113.

  The computing unit 15 performs, for example, the following condition execution computation corresponding to the control signal CTLOP on the first source data DT11 by the address generation device 12 and the second source data DT12 by the address generation device 13, and the computation result S15 (Destination) is output to the address generator 14.

The control method of the computing unit 15 will be described by taking a conditional execution computation as an example.
The following example is a C language program example in which the array index is a branching condition.

<Program example 1>
for (i = 0; i <256; i ++) {
if (i> 254) out [i] = a [i]-b [i];
else out [i] = a [i] + b [i];
}

FIGS. 2A to 2C are diagrams illustrating the calculation execution state of the calculator 15.
This is an operation that switches from addition to subtraction only when a specific index condition is satisfied, but the calculator itself does not know the array index, that is, the memory address, so the control to switch the operation is the side that issues the address, That is, the address generation device 13 generates the control signal CTLOP.

  In this example, since there are two types of calculation, it is sufficient that the control line has a 1-bit signal line, and the control signal CTLOP is sent to the calculator 15 together with the data read from the memory by the address generator 13 as shown in FIG. Then, a series of flows is realized in which the operation is performed and the result is written to the bank 113 of the memory 11 again.

Second Embodiment
FIG. 3 is a block diagram showing a second embodiment of the data flow type arithmetic unit according to the present invention.

  The arithmetic unit 20 includes a memory 11 having a plurality (three in FIG. 3) of banks 211 to 213, and first to third address generators 22 (AG0) provided corresponding to the banks 111 to 113, 23 (AG1), 24 (AG2), a first computing unit (PE0) 25, and a second computing unit (PE1) 26.

  The address generation device 22 gives the address ADR22 and the control signal CTL22 to the bank 211, reads the first data for the calculation of the calculator 26, and outputs it as the first source data DT21 to the calculator 26.

  The address generation device 23 gives the address ADR23 and the control signal CTL23 to the bank 212, reads the first data for the calculation of the calculator 25, and outputs it to the calculator 25 as the second source data DT22.

  The address generator 24 gives the address ADR 24 and the control signal CTL 24 to the bank 213 and stores the calculation result of the calculator 26 in the bank 213.

  The arithmetic unit 25 performs a comparison operation based on the second source data DT22 by the address generation device 23, and outputs it to the arithmetic unit 26 as the third source data DT23 together with the operation control signal CTLOP.

  The computing unit 26 performs, for example, the following condition execution computation corresponding to the control signal CTLOP on the first source data DT21 by the address generation device 22 and the third source data DT23 by the address generation device 23, and the computation result S26 (Destination) is output to the address generator 24.

The control method of the calculators 25 and 26 will be described by taking a condition execution calculation as an example.
The following example is a C language program example in which the array index is a branching condition.
Here, as another example, a program example in which the data value becomes a branch condition is shown below.

<Program example 2>
for (i = 0; i <256; i ++) {
if (a [i]> 0) out [i] = a [i] + b [i];
else out [i] = a [i];
}

4A to 4C are diagrams showing the calculation execution states of the calculators 25 and 26. FIG.
In this example, the type of calculation is switched depending on the array value that is the input of the arithmetic unit. As shown in FIG. 3, two arithmetic units are connected in cascade, and comparison operation is performed by the arithmetic unit 25 in the previous stage. A control signal CTLOP for switching the calculation of the calculator 26 is generated.
At this time, the calculation result of the calculator 25 at the previous stage is output as the same value as the input value.
This is because the data and the control signal are synchronized even when the arithmetic unit 25 is pipelined.
Note that the two examples shown above are examples in which two types of operations are switched, but in principle three or more types of switching can be performed, and in that case, the control signal also requires 2 bits or more.

<Third Embodiment>
FIG. 5 is a block diagram showing a third embodiment of the data flow type arithmetic unit according to the present invention.

  The arithmetic device 20A of the third embodiment is different from the arithmetic device 20 of the second embodiment in that the control signal CTLOP generated by the comparison operation in the arithmetic unit 25 is used as the control signal MEMWE of the address generator. .

  A program example in which the control signal generated by the comparison operation is used to control the address generation device is shown below.

<Program example 3>
j = 0;
for (i = 0; i <256; i ++) {
if (a [i]> 0) out [j ++] = a [i] + b [i];
}

  6A to 6E are diagrams showing the calculation execution states of the calculators 25 and 26 and the control state of writing to the memory.

In this example, the array index is incremented only when the value of the data serving as the operation input satisfies the condition, and the operation result is written to the memory.
FIG. 5 is a configuration example for realizing this example, but the two computing units 25 and 26 are cascaded as in FIG. 3, but the latter computing unit 26A always performs a fixed computation, The control signal CTLOP generated by the comparison operation of the operation unit 25 in the previous stage passes through the subsequent stage as it is and is delivered to the address generation device 24 for writing data together with the data.
Even if the arithmetic unit is pipelined, the data and the control signal are always synchronized because the control signal passes through the same path as the data.
The memory writing address generator 24 controls the address and writing (WE) to the memory using this control signal.

<Fourth embodiment>
FIG. 7 is a block diagram showing a fourth embodiment of the data flow type arithmetic unit according to the present invention.

  This computing device 30 includes a memory 31 having a plurality of (three in FIG. 7) banks 311 to 313, first to third address generation devices 32 (AG0) provided corresponding to the banks 311 to 313, 33 (AG1), 34 (AG2), a first computing unit (PE0) 35, and a second computing unit (PE1) 36.

The address generation device 32 gives the address ADR 32 and the control signal CTL 32 to the bank 311, reads the first data for the calculation of the calculator 35, and outputs it as the first source data DT 31 to the calculator 35.
The address generation device 32 receives the control signal CTLEND from the address generation device 34 and ends the read operation.

The address generation device 33 gives the address ADR33 and the control signal CTL33 to the bank 312 to read out the second data for the calculation of the calculator 35 and outputs it as the second source data DT32 to the calculator 35.
The address generation device 33 receives the control signal CTLEND from the address generation device 34 and ends the read operation.

The address generator 34 gives the address ADR 34 and the control signal CTL 34 to the bank 313 based on the control signal CTLWE from the calculator 36 and stores the calculation result of the calculator 36 in the bank 313.
Further, the address generation device 34 generates a control signal CTLEND for ending a series of processing based on the control signal CTLWE from the arithmetic unit 36 and outputs the control signal CTLEND to the address generation devices 32 and 33.

  The computing unit 35 performs, for example, the following conditional execution operation on the first source data DT1 by the address generation device 22 and the second source data DT32 by the address generation device 33, and outputs the result to the third source data. The data DT33 is output to the calculator 36.

  The calculator 36 performs a comparison calculation based on the third source data DT33 by the calculator 35, and outputs a calculation result S36 (Destination) to the address generator 34 together with the memory write control signal CTLWE.

  The following is an example of a program that terminates loop processing halfway depending on the calculation result.

<Program example 4>
for (i = 0; i <256; i ++) {
if ((a [i]-b [i]) == 0) break;
out [i] = a [i]-b [i];
}

  FIGS. 8A to 8E are diagrams showing the calculation execution state, the write control to the memory, and the read end control state of the calculators 35 and 36 in FIG.

In this operation, the operation result of the preceding operation unit 35 is compared by the subsequent operation unit 36, and the control signal CTLWE generated thereby is transferred to the address generation device 34 for writing data together with the data.
The memory write address generator 34 controls the address and write (WE) to the bank 313 of the memory 31 by the control signal CTLWE. At this time, the memory write address generator 34 controls the memory read address generator. By generating the control signal CTLEND that terminates the operation for 32 and 33, the reading operation of the banks 311 and 312 of the memory 33 is also terminated, whereby the series of processing operations can be completely terminated.

<Fifth Embodiment>
FIG. 9 is a block diagram showing a fifth embodiment of the data flow type arithmetic unit according to the present invention.

  The arithmetic device 40 includes a memory 41 having a plurality (five in FIG. 9) of banks 411 to 415, first to fifth address generation devices 42 (AG0) provided in response to the banks 411 to 415, 43 (AG1), 44 (AG2), 45 (AG3), 46 (AG4), a first computing unit (PE0) 47, and a second computing unit 48 (PE1).

  The address generation device 42 gives the address ADR 42 and the control signal CTL 42 to the bank 411, reads the first data for the calculation of the calculator 47, and outputs it as the first source data DT41 to the calculator 45.

  The address generation device 43 gives the address ADR43 and the control signal CTL43 to the bank 412 to read out the second data for the calculation of the calculator 45, and as the second source data DT42 together with the first control signal CTLOP of the calculation The result is output to the calculator 45.

  The address generation device 44 gives the address ADR 44 and the control signal CTL 44 to the bank 413, reads out the third data for the calculation of the calculator 48, and outputs it as the third source data DT43 to the calculator 48.

  The address generator 45 gives the address ADR45 and the control signal CTL35 to the bank 414 based on the control signal CTLAD and the address data S47 by the calculator 37 to read the fourth data, and the calculator 48 as the fourth source data DT44. Output to.

  The address generation device 46 gives the address ADR 46 and the control signal CTL 46 to the bank 415 and stores the calculation result S48 of the calculator 48 in the bank 415.

  The computing unit 47 generates the address data S47 by, for example, a predetermined calculation according to the first control signal CTLOP with respect to the first source data DT41 by the address generating device 42 and the second source data DT42 by the address generating device 43. And output to the address generator 45 together with the second control signal CTLAD.

  The computing unit 48 performs a predetermined operation on the third source data DT43 by the address generation device 44 and the fourth source data DT44 by the address generation device 45, and sends an operation result S48 (Destination) to the address generation device 24. Output.

  An example of using an arithmetic unit for address calculation is shown below.

<Program example 5>
for (i = 0; i <256; i ++) {
index = a [i] * b [i];
out [i] = c [index] + d [i];
}

In this embodiment, as shown in FIG. 9, after calculating an address using one end calculator (P 47), the address generator 45 reads the memory using the address, and the final calculator 48 uses the final address. You will get a good result.
It is also possible to generate more complicated addresses by further combining conditional execution operations.

It should be noted that general still image and moving image processing is often based on 8-bit data, so in a system using a 32-bit bus, the bus utilization efficiency deteriorates.
Therefore, the present invention improves transfer efficiency / processing efficiency by focusing on the case of accumulation processing and processing four pieces of bit data together.

For example, it is assumed that there are 16 pieces of 8-bit data and arranged on the memory as shown in FIG.
When data is read and processed one by one as usual, as shown in FIG. 11, 16 memory transfers occur.
On the other hand, as shown in FIG. 12, when four data are read out, four transfers are sufficient.

  FIG. 13 and FIG. 14 are process block diagrams in the case of reading one by one and four by four. In FIGS. 13 and 14, reference numeral 51 denotes an accumulator, and 52 denotes an adder.

As shown in FIG. 14, when four data are read out, the four pieces of data are separated from the data gathered into one at a time in the arithmetic unit, and then added to one, and this is accumulated.
Further, when calculating the sum of absolute differences with respect to reference data frequently used in moving image encoding, etc., as shown in FIG. 15, four absolute differences are simultaneously obtained and added to one, and then accumulation is performed. This can be achieved. In FIG. 15, reference numerals 53-1 to 53-4 denote difference absolute value calculation units (AbsDiff).
This can also be applied to the case of 16-bit data. In this case, two 16-bit data are processed together.

When the data flow type arithmetic unit is mounted, the inside is often pipelined, so the latency until the final result is obtained increases.
Therefore, it is desirable for such an arithmetic device to operate as continuously as possible, so that the conditional execution calculation of the present invention is possible, so that what has been executed in several steps in the past can be executed once. Thus, efficient operation is possible.

  On the other hand, the method of accumulating a plurality of data in one makes it possible to greatly reduce the amount of processing when processing a large amount of data such as motion detection in moving image encoding processing, which increases the efficiency of the device. Contribute.

  Hereinafter, a specific configuration example of the address generation device employed in the present embodiment will be described.

  FIG. 16 is a diagram illustrating a configuration example of an address generation device that generates an address based on input data, such as the address generation device 14 of FIG. 1 and the address generation device 46 of FIG. 9.

  16 includes registers 101 and 102 for setting initial values, registers 103 and 104 for setting step values, registers 105 for setting fixed values, arithmetic units 106 and 107, selection Devices 108 and 109, counters 110 and 111, and an arithmetic device 112.

  The arithmetic device 106 performs a predetermined operation such as addition based on the step value of the register 103 and the value fed back from the counter 110 and outputs the operation result to the selection device 108.

  The arithmetic device 107 performs a predetermined operation such as addition based on the step value of the register 104 and the value fed back from the counter 111 and outputs the operation result to the selection device 109.

  The selection device 108 selects either the set value of the register 101 or the output of the arithmetic unit 106 based on a control signal (not shown) and outputs the selected value to the counter 110.

  The selection device 109 selects either the set value of the register 102 or the output of the arithmetic unit 107 based on a control signal (not shown) and outputs it to the counter 111.

  The counter 110 sets a count value based on the set value (initial value) of the register 101 selected by the selection device 108 or the value of the calculation result of the calculation device 106, feeds back this value to the calculation device 106, and the first address The calculated count value ACNTV11 is output to the arithmetic unit 112.

  The counter 111 sets a count value based on the set value (initial value) of the register 102 selected by the selection device 109 or the value of the calculation result of the calculation device 107, feeds back this value to the calculation device 107, and receives the second address. The calculated count value ACNTV12 is output to the arithmetic unit 112.

  The arithmetic unit 111, based on a control signal (not shown), the first address calculation count value ACNTV11 by the counter 110, the second address calculation count value ACNTV12 by the counter 111, a fixed value set in the register 105, and input data A predetermined calculation is performed based on DIN to calculate an address ADR.

Here, the address generation operation of the address generation device 100 of FIG. 16 will be described in association with the timing charts of FIGS.
17A shows the count value CNT110 of the counter 210, FIG. 17B shows the count value CNT111 of the counter 111, FIG. 17C shows the first address calculation count value ACNTV11, and FIG. FIG. 17E shows the fixed address SCV set in the register 105, FIG. 17F shows the input data DIN to the arithmetic unit 112, and FIG. 17G shows the arithmetic unit 112. Addresses ADR calculated in FIG.

Address generation is performed as follows.
Registers 101 and 102 store 0 as the initial value of the counter, and registers 103 and 104 store 1 as the step value.

The arithmetic device 106 and the arithmetic device 107 each perform addition.
The selection device 108 selects the value of the register 201 every three cycles, and otherwise selects the value of the arithmetic device 106.
The selection device 109 always selects the value of the calculation result of the calculation device 109.
As a result, the count values CNT110 and CNT111 of the counter 110 and the counter 111 take values as shown in FIGS.
By operating in this way, the first address calculation count value ACNTV11 and the second address calculation count value ACNTV12 take values as shown in FIGS.

Also, as shown in FIGS. 17E and 17F, 0 is set as the fixed value SCV in the register 105, and the input data DIN (0,1,0,1,2,0,1,2) every cycle. , 3 ....) are supplied.
Then, the arithmetic unit 112 performs the following arithmetic operation to calculate the address ADR.

(Equation 1)
ADR = ACNTV11 + ACNTV12 + SCV + DIN

  Here, as the input data DIN, data read from the memory using another address generation device (not shown) or a result obtained by executing a predetermined operation on the read data from the memory as in the present embodiment may be used. it can.

  It is obvious that the calculation executed by the calculation device 111 can be a general calculation such as subtraction or multiplication, and is not limited to addition.

  According to this example, a complicated address pattern can be generated as compared with a simple address pattern generated by a conventional DSP or the like.

  FIG. 18 is a diagram illustrating a configuration example of an address generation device that can generate a control signal, such as the address generation device 13 of FIG. 1 or the address generation device 43 of FIG.

  The address generation device 200 includes a register 201 for setting an initial value, a register 202 for setting a step value, a calculation device 203, a selection device 204, a counter 205, a calculation device 206, a parameter register 207, a timing counter 208, a control device 209, And a control signal generator 210. Further, it has a start signal TRG and a control input CTLIN as inputs.

  The arithmetic device 203 performs a predetermined operation such as addition based on the step value of the register 202 and the value fed back from the counter 205, and outputs the operation result to the selection device 204.

  The selection device 204 selects either the set value of the register 201 or the output of the arithmetic unit 203 based on a control signal (not shown) and outputs the selected value to the counter 205.

The counter 205 sets a count value according to the set value (initial value) of the register 201 selected by the selection device 204 or the value of the calculation result of the calculation device 204, feeds back this value to the calculation device 206, and has a first address. The calculated count value ACNTV21 is output to the arithmetic unit 206 and the control signal generator 210.
The counter 205 starts a count-up operation in response to the control signal S209a from the control device 209.

  The arithmetic unit 206 calculates an address ADR by performing a predetermined operation based on the first address calculation count value ACNTV21 by the counter 312 based on a control signal (not shown).

  The parameter register 207 is set with an address generation delay value from the outside.

  The timing counter 208 counts up the counter value when the activation signal TRG is input, and counts the timing at which address generation is delayed until the value set in the parameter register 207 is reached.

The control device 209 determines whether or not the count value CNT208 of the timing counter 208 has reached a predetermined delay value set in the parameter register 207, and outputs the control signal S209a to the counter 205 when determining that it has reached. Thus, the count-up of the counter 205 is validated.
In addition, after the timing count value CNT208 of the timing counter reaches the set value, the control device 209 controls the output of the control signal S209b to the control signal generation device 210 so that the address valid signal AVLD is validated.

The control signal generator 210 generates an address valid signal AVLD from the control input CTLIN and this valid state.
The control signal generator 210 activates the address valid signal AVLD in response to the control signal S209b from the controller 209, and the address when the count value of the counter 205, that is, the first address calculation count value ACNTV21 reaches a predetermined end value. The valid signal AVLD is disabled.
The control signal generator 210 can make the control output CTLOUT valid or invalid when the count value of the counter 205 reaches a specific value.

Here, the address generation operation in the address generation device 200 of FIG. 18 will be described in association with the timing charts of FIGS.
19A shows the activation signal TRG given to the timing counter 208, FIG. 19B shows the timing count value CNT208 of the timing counter 208, and FIG. 19C shows the first address calculation count value ACNTV21 by the counter 205. 19D shows the address ADR calculated by the arithmetic unit 206, FIG. 19E shows the address valid signal AVLD generated by the control signal generator 210, and FIG. 19F shows the control input CTLIN. FIG. 19G shows the control output CTLOUT.

Address generation is performed as follows.
An address generation delay value “4” is set in the parameter register 207, and as shown in FIG. 19A, the timing counter 208 is incremented by a start signal TRG as a trigger signal input from the outside.
Then, as shown in FIG. 19B, when the count value CNT 208 of the timing counter 208 reaches a predetermined delay value “4” set in the parameter register 207, the control device 209 operates the address generation counter 205. In this manner, the control signal S209a is output to the counter 205 to enable the counter 205 to count up.

Register 201 stores 0 as the initial value of the counter, and register 202 stores 2 as the step value. The arithmetic unit 203 performs addition, for example.
The selection device 204 always selects the value of the arithmetic device 203.
By operating in this way, the first address calculation count value ACNTV21 takes a value as shown in FIG.

  The arithmetic unit 206 calculates the address ADR using the first address calculation count value ACNTV21.

In parallel with the address generation, the address valid signal AVLD / control output CTLOUT can be output.
As shown in FIGS. 19E to 19G, the address valid signal AVLD is generated by the control device 209 and the control signal generation device 210 based on the control input CTLIN, the activation signal TRG, and the timing count value CTL208.
The control device 209 makes the address valid signal AVLD valid by the control signal S209b after the timing count value CNT208 reaches the set value, and makes the address valid signal AVLD invalid when the count value of the counter 205 reaches the end value. .

The control signal generator 210 makes the control output CTLOUT valid or invalid when the count value of the counter 205 reaches a specific value.
As shown in FIGS. 19C and 19G, in this example, the control output CTLOUT is enabled when the first address calculation count value ACNTV21 becomes “6” and “12”.

According to this example, since it is possible to output the control signal and the address valid signal simultaneously with the address generation, there is an advantage that the memory and the arithmetic unit can be flexibly controlled using these signals. is there.
In addition, since the address generation timing can be controlled by a parameter, it is possible to easily cope with a case where there is a time dependency in reading from or writing to a plurality of memories.

It is a block diagram which shows 1st Embodiment of the data flow type arithmetic unit which concerns on this invention. It is a figure which shows the calculation execution state of the calculator of FIG. It is a block diagram which shows 2nd Embodiment of the data flow type arithmetic unit which concerns on this invention. It is a figure which shows the calculation execution state of the calculator of FIG. It is a block diagram which shows 3rd Embodiment of the data flow type arithmetic unit which concerns on this invention. It is a figure which shows the calculation execution state of the calculator of FIG. 5, and the write-in control state to memory. It is a block diagram which shows 4th Embodiment of the data flow type arithmetic unit which concerns on this invention. It is a figure which shows the calculation execution state of the calculator of FIG. 7, the write-in control to a memory, and the read end control state. It is a block diagram which shows 5th Embodiment of the data flow type arithmetic unit which concerns on this invention. It is a figure which shows an example of the arrangement | sequence of 8-bit data. It is a figure which shows the example in the case of reading 8-bit data one by one. It is a figure which shows the example in the case of reading 8 bits data 4 each. It is a figure which shows the example in the case of calculating 8 bit data one by one. It is a figure which shows the example in the case of calculating 8 bits data 4 each. It is a figure which shows the example which calculates | requires a difference absolute value. It is a figure which shows the structural example of the address generation apparatus which produces | generates an address based on input data like the address generation apparatus 14 of FIG. 1, and the address generation apparatus 46 of FIG. FIG. 17 is a timing chart for explaining an address generation operation of the address generation device of FIG. 16. FIG. It is a figure which shows the structural example of the address generation apparatus which can produce | generate a control signal like the address generation apparatus 13 of FIG. 1, and the address generation apparatus 43 of FIG. It is a timing chart for demonstrating the address generation operation | movement of the address generation apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Arithmetic unit, 11 ... Memory, 111-113 ... Bank, 12-14 (AG0-AG2) ... Address generator, 15 (PE) ... Arithmetic unit, 20, 20A ... Arithmetic unit, 21 ... Memory, 211-213 ... banks, 22 to 24 (AG0 to AG2) ... address generation device, 25 (PE0) ... computing unit, 26 (PE1) ... computing unit, 30 ... computing device, 31 ... memory, 311 to 313 ... bank, 32 to 34 (AG0 to AG2) ... address generation device, 35 (PE0) ... computing unit, 36 (PE1) ... computing unit, 40 ... computing device, 41 ... memory, 411-315 ... bank, 42-36 (AG0-AG4) ... Address generating device, 47 (PE0) ... arithmetic unit, 48 (PE1) ... arithmetic unit, 100 ... address generating device, 101, 102 ... registers for setting initial values, 103, 104 ... Register for setting step value, 105: Register for setting fixed value, 106, 107 ... Arithmetic unit, 108, 109 ... Selection unit, 110, 111 ... Counter, 112 ... Arithmetic unit, 200 ... Address generating unit, 201 ... Initial Register for setting a value, 202... Setting a step value, 203... Arithmetic unit, 204... Selection unit, 205 ... Counter, 206 ... Arithmetic unit, 207 ... Parameter register, 208 ... Timing counter, 209. Control signal generator, TRG ... Start signal, CTLIN ... Control input, CTLOUT ... Control output, AVLD ... Address valid signal.

Claims (14)

A first generation device for generating first source data;
A second generation device that generates second source data and outputs a control signal added to the second source data;
An arithmetic unit that performs a predetermined operation by switching an operation type according to the control signal for the first source data by the first generation device and the second source data by the second generation device. Arithmetic unit. A memory for storing the first source data and the second source data;
The first generation device generates an address for reading the first source data, outputs the first source data read based on the address to the arithmetic unit,
The second generation device generates an address for reading the second source data, and outputs the second source data read based on the address and the control signal to the arithmetic unit. Arithmetic unit. The arithmetic unit according to claim 2, further comprising a third generation unit that receives an arithmetic result of the arithmetic unit, generates an address, and writes the arithmetic result in the memory. The arithmetic unit according to claim 1, wherein the arithmetic unit treats and accumulates a plurality of data when performing accumulation with data having a word length smaller than the bus width. A first generation device for generating first source data;
A second generation device for generating second source data;
A first calculation process is performed on the second source data of the second generation device to generate third source data, and a control signal is added to the third source data for output. An arithmetic unit;
A first computing unit that performs a predetermined computation by switching an operation type according to the control signal for the first source data by the first generation device and the third source data by the first computing unit. Arithmetic unit having. A memory for storing the first source data and the second source data;
The first generation device generates an address for reading the first source data, outputs the first source data read based on the address to the second arithmetic unit,
The said 2nd production | generation apparatus produces | generates the address for reading said 2nd source data, and outputs the 2nd source data read based on the said address to a said 1st arithmetic unit. Arithmetic unit. The arithmetic unit according to claim 6, further comprising a third generation unit that receives an arithmetic result of the second arithmetic unit, generates an address, and writes the arithmetic result in the memory. The second calculator adds a control signal to the calculation result and outputs the result,
The arithmetic unit according to claim 6, further comprising a third generation unit that receives an arithmetic result of the second arithmetic unit and a control signal, generates an address, and writes the arithmetic result in the memory. 6. The arithmetic unit according to claim 5, wherein at least one of the first and second arithmetic units handles a plurality of pieces of data and performs accumulation when performing accumulation with data having a word length smaller than the bus width. A first generation device for generating first source data;
A second generation device for generating second source data;
A first arithmetic unit that performs predetermined arithmetic processing on the first source data of the first generation device and the second source data of the second generation device to generate third source data;
A second arithmetic unit that performs a predetermined operation on the third source data by the first arithmetic unit and adds a control signal to output;
And a third generation device that receives a calculation result and a control signal by the second arithmetic unit and generates a control signal for controlling a generation operation of the second and third generation devices. A memory for storing the first source data and the second source data;
The first generation device generates an address for reading the first source data, outputs the first source data read based on the address to the second arithmetic unit,
The second generation device generates an address for reading the second source data, and outputs the second source data read based on the address to the first arithmetic unit. The third generation The arithmetic device according to claim 10, wherein the device receives an arithmetic result of the second arithmetic unit and a control signal, generates an address, and writes the arithmetic result in the memory. 11. The arithmetic unit according to claim 10, wherein at least one of the first and second arithmetic units treats a plurality of data as a unit and performs accumulation when accumulating with data having a word length smaller than the bus width. A memory for storing first, second, third, and fourth source data;
A first generation device that generates an address for reading the first source data and outputs the first source data read based on the address;
A second generation device that generates an address for reading the second source data, adds a first control signal to the second source data read based on the address, and outputs the second control data;
A third generation device for generating an address for reading the third source data and outputting the third source data read based on the address;
The address data is generated by performing an operation on the first source data by the first generation device and the second source data by the second generation device according to the first control signal, and the address A first computing unit that outputs the data by adding a second control signal;
The first arithmetic unit generates an address for reading the fourth source data based on the address data and the second control signal, and outputs the fourth source data read based on the address. 4 generators;
A second arithmetic unit that performs a predetermined operation on the third source data by the third generation device and the fourth source data by the fourth generation device, and outputs the result.
An arithmetic unit comprising: a fifth generation device that receives an arithmetic result of the second arithmetic unit, generates an address, and writes the arithmetic result in the memory. 14. The arithmetic unit according to claim 13, wherein at least one of the first and second arithmetic units handles a plurality of pieces of data and performs accumulation when accumulating with data having a word length smaller than the bus width.

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