JP2005318388A - Transmission gate for sample-hold circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmission gate capable of making capacitances equal to each other without the need for adjustment of sizes of MOS-FETs and the concentration with respect to the transmission gate configured to reduce noise in a holding state. <P>SOLUTION: In the transmission gate for a sample-hold circuit provided with P channel and N channel field effect transistors connected in parallel between an input terminal and a hold capacitor, field effect transistors whose sources and drains are respectively short-circuited and the size of which is halved are connected in series between the respective field effect transistors and the hold capacitor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a transmission gate used in a sample and hold circuit, and relates to a transmission gate configured to reduce noise during holding.

  As shown in FIG. 2, a transmission gate is used in which N-channel and P-channel MOS field effect transistors (FETs) are combined to form a pair of gates, and a drive pulse is applied to each of the gates. When the transistor is turned on by the drive pulse, the sample mode is operated, and when the transistor is turned off, the hold mode is operated, and a signal is detected and output by an arbitrary sampling pulse. The drive pulse is applied to the gates of the P-channel and N-channel MOS-FETs. In this example, the signal inverted by the inverter is applied to the gates of the N-channel MOS-FETs. As shown in FIG. 3A, when the P channel side becomes “L” and the N channel side becomes “H”, the sample mode (period) in which charges are accumulated in the capacitor by the input signal is set. On the contrary, as shown in FIG. 3B, when the P channel side becomes “H” and the N channel side becomes “L”, the input signal is cut off, and the hold mode (the charge accumulation state is maintained in the capacitor). Period).

When handling a very small input signal such as a hall sensor, noise is generated in the output-side hold capacitor when the transmission gate opens and closes. Due to this noise, as shown in FIG. 4, the hold level of the hold voltage Vout changes, so that an accurate hold voltage cannot be obtained. As shown in FIG. 5, the main cause of noise is that a gate drive pulse is injected into the hold capacitor through the gate-source capacitance Cgs and the gate-drain capacitance Cgd of the MOS-FET. In the sample mode, as shown in FIG. 6A, the charge Q = C _A (1.5-0) is accumulated in the capacitor C _A and the charge Q = C _B (3-1.5) is accumulated in the capacitor C _B. Has been. In the hold mode, as shown in FIG. 6B, the charge Q = C _A (1.5-3) is transferred to the capacitor C _A and the charge Q = C _B (1.5-0) is transferred to the capacitor C _B. Have been accumulated.

If the capacitances C _A and C _B shown in FIGS. 7A and 7B are equal, the potential at the midpoint does not change even if the potentials at both ends of the capacitor are switched, so no noise is generated (the principle of voltage division of the capacitor). ). Therefore, as a countermeasure, a countermeasure (equalizing the transistor size) is adopted to equalize the capacitances of the N-channel and P-channel FETs. However, the capacities are not equal due to variations in masks and etching, and it is inevitable that variations occur between products. In particular, in ion implantation, the ratio of the P-type diffusion concentration for the P channel and the N-type diffusion concentration for the N channel must be matched, and this variation is a major cause.
JP 2002-207053 A Japanese Patent Laid-Open No. 9-21832 Japanese Patent Laid-Open No. 5-119076

  The present invention provides a structure for removing the noise intruding into the hold capacitor, and a transmission capable of adjusting the capacitance without adjusting the size of the MOS-FET or adjusting the concentration. Get the gate.

  The present invention solves the above-mentioned problem by adding a transistor having a size half that of a sample-hold transistor pair. That is, in the transmission gate of a sample-and-hold circuit having a P-channel and an N-channel field effect transistor connected in parallel between the input terminal and the hold capacitor, each field effect transistor is interposed between each field effect transistor and the hold capacitor. The field-effect transistors having a source and drain short-circuited in a size half the size of the above are characterized by being connected in series.

  According to the present invention, since transistors of 1/2 size are added and connected to each other, the total sum of the gate capacities on the N channel side and the P channel side as seen from the hold capacitor becomes equal. Utilizing the fact that the potential of two capacitors of the same capacity is constant even if they are alternately switched between the “High” level and the “Low” level if the potentials at the same capacitor are at the dividing point. It is.

  A sample-and-hold N-channel and P-channel transistor pair and a P-channel and N-channel transistor that are ½ the size of each transistor are prepared. These half-sized transistors are connected between the N-channel and P-channel transistors for sample and hold and the hold capacitor. Since these half-sized transistors only obtain capacitance, the source and drain are short-circuited. These transistors can be formed on the same silicon substrate simultaneously by a series of processes.

An embodiment of the present invention will be described with reference to FIG. The transmission gate is composed of a P-channel MOS-FET and an N-channel MOS-FET connected in parallel, and is connected between the input terminal V _IN and the output terminal V _OUT . Also, a hold capacitor is connected to the output side of the transmission gate and one end is grounded. An N-channel MOS-FET is connected in series to a P-channel MOS-FET, and this MOS-FET is formed so that its size is halved. Further, a P-channel MOS-FET having a half size is connected in series with the N-channel MOS-FET. In all of these half-sized MOS-FETs, the source and drain are short-circuited.

  The P-channel MOS-FET and the N-channel MOS-FET connected to the P-channel MOS-FET constituting the transmission gate, and the N-channel MOS-FET and the P-channel MOS-FET connected to the N-channel MOS-FET are connected to a drive pulse source, respectively. When one is “High”, the other is driven to be “Low”. A MOS-FET whose source and drain are short-circuited does not itself operate as a MOS-FET.

In FIG. 1, the capacitance C ₁ generated in the upper P-channel MOS-FET and the MOS-FET portion where the source-drain connected thereto is short-circuited is C ₁ = C _P + C _{N / 2} + C _{N / 2} = C _P + C _N
And the lower capacitance C ₂ is
C ₂ = C _N + C _{P / 2} + C _{p / 2} = C _N + C _P
Thus, C ₁ = C ₂ and the sum of the two capacitors becomes equal. Therefore, even if the upper MOS-FET gate and the lower MOS-FET gate are alternately changed between the “High” level and the “Low” level, the potential at the connection point does not change and no noise is generated. When transistors of the same type are formed on the same silicon substrate, variations in capacitance due to variations in manufacturing are less likely to occur, making it easy to align characteristics.

  The present invention can be used for a transmission gate suitable for a sample and hold circuit of a Hall sensor that handles a minute current. Of course, the present invention is not limited to this, and the present invention can be used for all circuits that need to reduce the influence of noise.

Circuit diagram showing an embodiment of the present invention Circuit diagram showing transmission gate Illustration of its operation Illustration of the operation waveform Equivalent circuit diagram of the capacitance Equivalent circuit diagram of the capacitance Illustration of the capacity

Explanation of symbols

P _CH : P channel MOS-FET
N _CH : N-channel MOS-FET
C _GS : Gate-source capacitance
C _GD : Capacitance between gate and drain

Claims (3)

In a transmission gate of a sample and hold circuit comprising a P-channel and an N-channel field effect transistor connected in parallel between an input terminal and a hold capacitor,
A sample-and-hold in which a field-effect transistor having a source and a drain short-circuited in a size half the size of each field-effect transistor is connected in series between each field-effect transistor and a hold capacitor. Circuit transmission gate. In a transmission gate of a sample and hold circuit comprising a P-channel and an N-channel field effect transistor connected in parallel between an input terminal and a hold capacitor,
Between the P-channel field effect transistor and the hold capacitor, an N-channel field effect transistor whose source and drain are short-circuited with a size that is half the size of the P-channel field effect transistor is connected in series. A P-channel field effect transistor having a source and drain short-circuited in a size half the size of the N-channel field effect transistor is connected in series between the N-channel field effect transistor and the hold capacitor. The transmission gate of the sample and hold circuit. In a transmission gate comprising P-channel and N-channel field effect transistors connected in parallel between an input end and an output end,
Between the P-channel field effect transistor and the output end, an N-channel field effect transistor having a size that is half the size of the P-channel field effect transistor and whose source and drain are short-circuited is connected in series. Between the N-channel field effect transistor and the output end, a P-channel field-effect transistor having a source and drain short-circuited in a size half the size of the N-channel field-effect transistor is connected in series. A transmission gate characterized by that.

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