JP2005316647A - 集積回路の配線解析方法、論理合成方法、回路分割方法 - Google Patents

集積回路の配線解析方法、論理合成方法、回路分割方法 Download PDF

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Publication number
JP2005316647A
JP2005316647A JP2004132748A JP2004132748A JP2005316647A JP 2005316647 A JP2005316647 A JP 2005316647A JP 2004132748 A JP2004132748 A JP 2004132748A JP 2004132748 A JP2004132748 A JP 2004132748A JP 2005316647 A JP2005316647 A JP 2005316647A
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Prior art keywords
wiring
integrated circuit
circuit
hierarchical
analysis method
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JP2004132748A
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Japanese (ja)
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JP2005316647A5 (enExample
Inventor
Toshiyuki Sadakane
利行 定兼
Takeshi Saito
健 斉藤
Yoshio Inoue
善雄 井上
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2004132748A priority Critical patent/JP2005316647A/ja
Priority to US11/111,720 priority patent/US7418688B2/en
Publication of JP2005316647A publication Critical patent/JP2005316647A/ja
Publication of JP2005316647A5 publication Critical patent/JP2005316647A5/ja
Priority to US12/219,371 priority patent/US8108809B2/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2004132748A 2004-04-28 2004-04-28 集積回路の配線解析方法、論理合成方法、回路分割方法 Pending JP2005316647A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004132748A JP2005316647A (ja) 2004-04-28 2004-04-28 集積回路の配線解析方法、論理合成方法、回路分割方法
US11/111,720 US7418688B2 (en) 2004-04-28 2005-04-22 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
US12/219,371 US8108809B2 (en) 2004-04-28 2008-07-21 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit

Applications Claiming Priority (1)

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JP2004132748A JP2005316647A (ja) 2004-04-28 2004-04-28 集積回路の配線解析方法、論理合成方法、回路分割方法

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JP2009069820A Division JP4762326B2 (ja) 2009-03-23 2009-03-23 集積回路の配線解析方法

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JP2005316647A true JP2005316647A (ja) 2005-11-10
JP2005316647A5 JP2005316647A5 (enExample) 2007-03-15

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US (2) US7418688B2 (enExample)
JP (1) JP2005316647A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016126727A (ja) * 2015-01-08 2016-07-11 株式会社ソシオネクスト 設計支援装置、および設計支援方法

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US7580824B1 (en) * 2005-12-21 2009-08-25 Altera Corporation Apparatus and methods for modeling power characteristics of electronic circuitry
US8127260B1 (en) * 2006-11-22 2012-02-28 Cadence Design Systems, Inc. Physical layout estimator
US8370786B1 (en) * 2010-05-28 2013-02-05 Golden Gate Technology, Inc. Methods and software for placement improvement based on global routing
US8316335B2 (en) * 2010-12-09 2012-11-20 International Business Machines Corporation Multistage, hybrid synthesis processing facilitating integrated circuit layout
US8782582B1 (en) 2013-03-13 2014-07-15 Atrenta, Inc. Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
US8745567B1 (en) 2013-03-14 2014-06-03 Atrenta, Inc. Efficient apparatus and method for analysis of RTL structures that cause physical congestion
JP6328974B2 (ja) 2014-03-28 2018-05-23 株式会社メガチップス 半導体装置及び半導体装置の設計手法
DE102017127276A1 (de) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek
CN112347732B (zh) * 2020-11-27 2024-08-06 北京百瑞互联技术股份有限公司 一种集成电路分层走线规划方法、装置、存储介质及设备

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
JP3904620B2 (ja) 1995-03-07 2007-04-11 株式会社ルネサステクノロジ 自動配置配線装置
JPH0945776A (ja) 1995-07-27 1997-02-14 Toshiba Corp 半導体論理集積回路のレイアウト設計法
JPH10116915A (ja) 1996-08-21 1998-05-06 Matsushita Electric Ind Co Ltd Ｌｓｉの配線長推定方法および面積推定方法
US6209123B1 (en) * 1996-11-01 2001-03-27 Motorola, Inc. Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
US7065729B1 (en) * 1998-10-19 2006-06-20 Chapman David C Approach for routing an integrated circuit
US6611951B1 (en) * 2000-11-30 2003-08-26 Lsi Logic Corporation Method for estimating cell porosity of hardmacs
JP4723740B2 (ja) * 2001-03-14 2011-07-13 富士通株式会社 密度一様化配置問題の最適解探索方法および密度一様化配置問題の最適解探索プログラム
US6578183B2 (en) * 2001-10-22 2003-06-10 Silicon Perspective Corporation Method for generating a partitioned IC layout
JP2003242190A (ja) 2002-02-21 2003-08-29 Hitachi Ltd 半導体集積回路のフロアプラン方法
JP4078123B2 (ja) * 2002-06-05 2008-04-23 株式会社ルネサステクノロジ フロアプラニング装置
US7225116B2 (en) * 2002-08-20 2007-05-29 Cadence Design Systems, Inc. Method for eliminating routing congestion in an IC layout
US7200827B1 (en) * 2003-05-14 2007-04-03 Apex Design Systems, Inc. Chip-area reduction and congestion alleviation by timing-and-routability-driven empty-space propagation
US7073149B2 (en) * 2004-03-03 2006-07-04 Xilinx, Inc. System for representing the logical and physical information of an integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016126727A (ja) * 2015-01-08 2016-07-11 株式会社ソシオネクスト 設計支援装置、および設計支援方法

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US20080295055A1 (en) 2008-11-27
US8108809B2 (en) 2012-01-31
US7418688B2 (en) 2008-08-26
US20050246676A1 (en) 2005-11-03

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