JP2005311299A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the leakage current between adjacent interconnect lines increases or interconnection parasitic capacitance increases in a lower-layer metal wirings, constituting an MIM (Metal-Insulator-Metal) capacitor using a high dielectric insulation film made of tantalum oxide, etc., when attempt is made to control increase in the leakage current or lowering of the dielectric breakdown withstand voltage in the MIM capacitor. <P>SOLUTION: In the MIM capacitor composed of an upper electrode 204, a capacitance film 401, and a lower electrode 700, an insulation film is formed that has an opening on the lower electrode, a capacitance film is formed so that it is brought into contact with the lower electrode via the opening, the upper electrode is formed on the capacitance film; the upper electrode and the capacitance film are left behind such that they completely encompass the opening; and then, by leaving behind the insulation film and the lower electrode, such that they have the same width as, or a width larger than, that of the upper electrode and the capacitance film, thus the insulation film and the capacitance film is formed between the upper electrode and the lower electrode at the end of the MIM capacitor, which enables leakage current to be decreased, between the adjacent interconnect lines and interconnection parasitic capacitance to be reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a highly reliable and high-performance capacitive element and a method for manufacturing the same.

  In an IC (Integrated Circuit) that handles analog signals, passive elements such as a capacitive element, a resistive element, and an inductor element are important components of an integrated circuit. Conventionally, since these passive elements have been difficult to be built in an IC chip, they have been mounted as external components on a mounting board. However, in recent years, there is a strong need for high-speed and space-saving systems, and attempts have been made to incorporate these passive elements into the IC chip.

  The most common method for forming a capacitive element in an IC chip is a capacitive element having a structure in which an insulating film is sandwiched between polycrystalline silicon. This type of capacitive element is called a PIP capacitor (PIP: Polysilicon-Insulator-Polysilicon) because of its structure. Since polycrystalline silicon is used as the electrode material, the resistance is high, and since the deposition temperature of the polycrystalline silicon exceeds the upper limit temperature of the wiring process, it must be formed close to the silicon substrate, and therefore parasitic There are problems such as an increase in capacity. As a method for solving such a problem, an MIM (Metal-Insulator-Metal) capacitor in which the upper and lower sides of an insulating film are sandwiched between metal electrodes has attracted attention.

The features and problems of the MIM capacitor will be described with reference to the conventional process diagrams shown in FIGS.
As shown in FIG. 2A, after a titanium nitride film having a thickness of 50 nm, an aluminum alloy film having a thickness of 400 nm, and a titanium nitride film having a thickness of 50 nm are sequentially formed on the substrate 100 on which the semiconductor element is formed, A first processing resist 600 is formed in a desired region by using a lithography method, and dry etching is performed using the first processing resist 600 as a mask to form a first barrier metal layer 205 made of titanium nitride having a thickness of 50 nm, A first metal wiring 700 constituted by a first aluminum layer 206 made of an aluminum alloy with a thickness of 400 nm and a second barrier metal layer 207 made of titanium nitride with a thickness of 50 nm was formed.

  Next, as shown in FIG. 2B, after the first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by plasma CVD so as to cover the first metal wiring 700. After increasing the flatness of the first interlayer insulating layer 304 using a chemical mechanical polishing method, the first interlayer insulating layer is exposed using the lithography method and the dry etching method so that the first metal wiring 700 is exposed. An opening 501 formed in the layer was provided. A region where the opening is provided is a region which becomes a MIM capacitor. Next, a capacitor film 400 made of a silicon oxide film having a thickness of 50 nm is exposed to the inside of the opening 501 formed in the first interlayer insulating layer by using a plasma CVD method using tetraethoxysilane as a raw material. The metal wiring 700 was formed so as to cover it. Next, a second processing resist 601 having an opening in a desired region is formed on the capacitor film 400 in order to form a connection hole for electrical connection to the first metal wiring in a region other than the MIM capacitor. Then, dry etching is performed using the second processing resist 601 as a processing mask to form a second opening 502.

  Next, as shown in FIG. 3A, a tungsten film is formed by sputtering and CVD so as to fill the opening formed in the first interlayer insulating layer 304, and chemical mechanical polishing is performed. The first conductive plug 250 and the second conductive plug 251 were formed by removing the tungsten film in the region other than the opening using As shown in FIG. 3B, a titanium nitride film with a thickness of 50 nm, an aluminum alloy film with a thickness of 400 nm, and a titanium nitride film with a thickness of 50 nm are sequentially formed, and then the lithography method and the dry etching method are used. The third barrier metal layer 208 made of titanium nitride with a thickness of 50 nm, the second aluminum layer 209 made of aluminum alloy with a thickness of 400 nm, and the fourth barrier metal layer 210 made of titanium nitride with a thickness of 50 nm A second metal wiring 701 to be configured was formed. Through the above steps, it is possible to form an MIM capacitor including the first metal wiring 700, the capacitor film 400, the first conductive plug 250, and the second metal wiring 701. Hereinafter, the MIM capacitor formed in accordance with the above process will be referred to as Conventional Example 1.

The MIM capacitor based on Conventional Example 1 can be formed in the wiring process because the electrode formation temperature is 450 ° C. or lower, and a metal material having low electrical resistance can be used as the electrode. It becomes possible to solve the problems that have.
However, the MIM capacitor configured as described above has a drawback that it is difficult to improve performance. In the above method, a connection hole is formed in a wiring located in a lower layer serving as a lower electrode, and then a capacitor film is formed using a CVD method. Materials that can be formed by the CVD method at a temperature lower than the upper limit temperature (450 ° C.) of the wiring process are generally a silicon oxide film and a silicon nitride film, and their relative dielectric constants are about 4 and 7, respectively. Since the lower limit film thickness that can be formed without defects in a connection hole having a depth equal to or higher than the wiring height is about 50 nm, the upper limit of the capacitance density is 0.7 fF per square micrometer in the case of silicon oxide, In the case of silicon nitride, it becomes 1.2 fF per square micrometer, and it is difficult to reduce the area of the MIM element in the IC chip, and there is a problem that the IC chip area increases.

As a method for solving this problem, a method using a material (high dielectric constant material) having a higher relative dielectric constant than silicon oxide or silicon nitride has been studied. In general, tantalum oxide, hafnium oxide, titanium oxide, and the like have been studied as materials having a relative dielectric constant of 20 or more. A conventional example of the MIM capacitor forming process using such a high dielectric constant material will be described with reference to FIG.
As shown in FIG. 4A, a first barrier film 200 made of a titanium nitride film with a thickness of 50 nm and a first aluminum film made of an aluminum alloy with a thickness of 400 nm are formed on a substrate 100 on which a semiconductor element is formed. 201, a second barrier metal film 202 made of a titanium nitride film with a thickness of 50 nm, a capacitive film 400 made of a tantalum oxide film with a thickness of 50 nm using a reactive sputtering method, and an upper electrode 203 made of titanium nitride with a thickness of 50 nm. Are sequentially formed, and a first processing resist 600 is formed in a desired region by using a lithography method.

Next, after processing the upper electrode 203 and the capacitive film 400 using the first processing resist 600 as a mask, a second processing resist 601 is formed by using a lithography method, and the first barrier metal layer is formed by a dry etching method. 205, a first metal wiring 700 constituted by the first aluminum layer 206 and the second barrier metal layer 207 was formed (FIG. 4B).
Next, as shown in FIG. 4C, a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by using a plasma CVD method, and then first by using a chemical mechanical polishing method. The interlayer insulating layer 304 was planarized. Next, using lithography and dry etching, an opening is provided so that the processed upper electrode 204 or the first metal wiring 700 is exposed, and the processed upper electrode 204 is connected to the opening. A first conductive plug 250 made of tungsten and a second conductive plug 251 made of tungsten connected to the first metal wiring 700 were formed. Finally, a third barrier layer 208 made of a titanium nitride film with a thickness of 50 nm and a second aluminum layer 209 made of an aluminum alloy with a thickness of 400 nm in a desired region by combining a sputtering method, a lithography method, and a dry etching method, A second metal wiring 701 composed of a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm was formed. Through the above steps, an MIM capacitor including the first metal wiring 700, the processed capacitance film 401, the processed upper electrode 204, the first conductive plug 250, and the second metal wiring 701 is formed. Is possible. Hereinafter, the MIM capacitor formed in accordance with the above process will be referred to as Conventional Example 2.

  Since the MIM capacitor based on Conventional Example 2 can use tantalum oxide (relative permittivity of 24) having a film thickness of 50 nm, a capacitance density of 4 fF per square micrometer can be realized, and the area of the capacitor in the IC chip can be reduced. It becomes possible to do. However, the MIM capacitor formed in this way has a drawback that the dielectric breakdown voltage is low and the leakage current is large. In the above method, the upper electrode 204 processed at the end of the MIM capacitor and the end of the processed capacitance film 401 coincide with each other, and the first metal wiring that is the lower electrode is directly below the end. 700 is located. Since the end portion of the capacitive film has many defects, there is a possibility that the leakage current increases or the dielectric breakdown voltage decreases in the structure in which the end portion of the capacitive film is in direct contact with the upper electrode and the lower electrode. On the other hand, in the process diagram shown in FIG. 4A, after processing the upper electrode 203 and the capacitor film 400 using the first processing resist 600, the capacitor film 401 processed by lithography and dry etching is performed again. It is possible to shift the end portion from the end portion of the processed upper electrode 204. In this way, it is possible to prevent the upper electrode 204 processed at the end of the MIM capacitor from matching with the end of the processed capacitive film 401, but the upper electrode 203 on the capacitive film 400 can be prevented from matching. Since dry etching is performed, there is a drawback that plasma damage or local film reduction occurs in the region immediately below the processed upper electrode 204 end in the capacitor film 400, and the breakdown voltage is reduced.

As a method for solving this problem, a structure is proposed in which a capacitor film and a second insulating layer are sandwiched immediately below the end of the upper electrode of the MIM capacitor. In this way, it is possible to minimize an increase in leakage current and a decrease in dielectric breakdown voltage at the end of the MIM capacitor. A conventional example of such a MIM capacitor forming process will be described with reference to FIGS.
As shown in FIG. 5A, a first barrier metal layer 205 made of titanium nitride having a thickness of 50 nm and a first aluminum layer made of an aluminum alloy having a thickness of 400 nm are formed on a substrate 100 on which a semiconductor element is formed. 206, after forming a first metal wiring 700 constituted by a second barrier metal layer 207 made of titanium nitride having a thickness of 50 nm, a first CVD oxide made of silicon oxide having a thickness of 100 nm is formed by plasma CVD. An intermediate layer 300 was formed on the entire surface.

Next, as shown in FIG. 5B, an opening is formed in the first intermediate layer 300 using a lithography method and a dry etching method so that the surface of the first metal wiring 700 is exposed. A capacitive film 400 made of tantalum oxide having a film thickness of 50 nm was formed in order by a reactive sputtering method so as to cover the opening, and an upper electrode 203 made of a titanium nitride film having a film thickness of 50 nm was formed in this order by the reactive sputtering method. Then, the 1st process resist 600 was formed in the desired area | region using the lithography method.
Next, as shown in FIG. 6C, dry etching was performed using the first processed resist 600 as a mask to form a processed capacitive film 401 and a processed upper electrode 204. At this time, an etching residue 800 composed of the upper electrode 203 and the capacitor film 400 was present on the side wall portion of the first metal wiring 700.

  Next, as shown in FIG. 6A, a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed using a plasma CVD method, and then a first using a chemical mechanical polishing method. The interlayer insulating layer 304 was planarized. Next, using lithography and dry etching, an opening is provided so that the processed upper electrode 204 or the first metal wiring 700 is exposed, and the processed upper electrode 204 is connected to the opening. A first conductive plug 250 made of tungsten and a second conductive plug 251 made of tungsten connected to the first metal wiring 700 were formed. Finally, as shown in FIG. 6B, a third barrier layer 208 made of a titanium nitride film having a thickness of 50 nm is formed in a desired region by combining sputtering, lithography, and dry etching, and aluminum having a thickness of 400 nm. A second metal wiring 701 composed of a second aluminum layer 209 made of an alloy and a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm was formed. Through the above steps, an MIM capacitor including the first metal wiring 700, the processed capacitance film 401, the processed upper electrode 204, the first conductive plug 250, and the second metal wiring 701 is formed. Is possible. Hereinafter, the MIM capacitor formed in accordance with the above process will be referred to as Conventional Example 3.

  In the MIM capacitor based on the conventional example 3, although the upper electrode 204 processed at the end of the MIM capacitor and the end of the processed capacitance film 401 coincide with each other, another insulating film is formed immediately below the end. Since a certain first intermediate layer 300 is formed, it is possible to suppress an increase in leakage current at the end of the MIM capacitor and a decrease in dielectric breakdown voltage. However, the MIM capacitor formed in this way has two main drawbacks. One is that, as shown in FIG. 6B, tantalum oxide having a high dielectric constant or titanium nitride, which is a conductive material, is likely to remain as the etching residue 800 between the adjacent first metal wirings 700. There is a concern that the parasitic capacitance of the first metal wiring 700 increases and the leakage current between the wirings increases. Another drawback is particularly problematic in the narrow wiring pitch region. The problem is that, as shown in FIG. 6C, when the wiring interval of the first metal wiring 700 is narrow, the first intermediate layer 300 occupies most of the volume between the adjacent wirings. Caused by In recent ICs, it has been required to reduce the inter-wiring capacitance as much as possible due to demands such as an improvement in operation speed. Therefore, an insulating film having a small relative dielectric constant (about 3.5 or less) called a low-k material is often used as an insulating film around the wiring. However, based on the conventional example 3, as shown in FIG. 6C, between the adjacent wirings is occupied by the first intermediate layer having a high relative dielectric constant (about 4). There is little room for material to enter, which greatly hinders the reduction of parasitic capacitance of wiring.

JP 2001-320026 A JP 2003-188264 A JP 2003-282719 A

  The problem to be solved by the invention is to suppress an increase in leakage current and a decrease in dielectric breakdown voltage in a MIM capacitor using a high dielectric constant insulating film such as tantalum oxide as a capacitive film, which can increase the capacitance density of the MIM capacitor. In order to achieve this, in the lower layer metal wiring that constitutes a part of the lower electrode of the MIM capacitor, the leakage current between adjacent wirings increases and the wiring parasitic capacitance increases.

  In the MIM capacitor composed of the upper electrode, the capacitor film, and the lower electrode, the above-described problem is that an insulating film having an opening is formed on the lower electrode, and the capacitor film is formed in contact with the lower electrode through the opening. And forming an upper electrode on the capacitor film, leaving the upper electrode and the capacitor film so as to completely include the opening, and thereafter, the width of the upper electrode and the capacitor film is the same as or wider than the width of the capacitor electrode. By leaving the insulating film and the lower electrode, the insulating film and the capacitive film are formed between the upper electrode and the lower electrode at the end of the MIM capacitor.

  In the MIM capacitor composed of the upper electrode, the capacitor film, and the lower electrode, the above problem is that the lower electrode is formed and processed so as to include a connection hole opened on the processed lower wiring, and the surface of the lower electrode is An insulating film having an opening narrower than the lower electrode is formed so as to be exposed, a capacitor film is formed so as to be in contact with the lower electrode through the opening, and an upper electrode is formed on the capacitor film Then, the insulating film and the capacitive film are formed between the upper electrode and the lower electrode at the end of the MIM capacitor by performing processing so as to completely include the opening and leaving the upper electrode and the capacitive film. Is achieved.

  According to the present invention, in the metal wiring formed adjacent to the MIM capacitor while minimizing the problems such as increase in leakage current and reduction in dielectric breakdown voltage while increasing the capacitance density of the MIM capacitor, It is possible to reduce the leakage current between them and the wiring parasitic capacitance, and it is possible to obtain a semiconductor device having a high-performance and high-reliability MIM capacitor.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, each drawing is drawn typically and the place unnecessary for description is abbreviate | omitted.

  7 and 8 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. The following will be described in order. A first barrier film 200 made of a titanium nitride film with a film thickness of 50 nm, a first aluminum film 201 made of an aluminum alloy with a film thickness of 400 nm, and a film thickness of 50 nm are formed on the substrate 100 on which the semiconductor element is formed by sputtering. After forming the second barrier metal film 202 made of the titanium nitride film, the plasma CVD method is used to form the first intermediate layer 300 made of silicon oxide having a thickness of 100 nm, and the lithography method and the dry etching method are used. Then, the first opening 500 was formed in a desired region of the first intermediate layer 300. Next, a reactive sputtering method is used so as to cover the first opening 500, the capacitive film 400 made of a tantalum oxide film with a thickness of 50 nm, and the upper electrode 203 made of titanium nitride with a thickness of 50 nm using a sputtering method. Then, a hard mask 301 made of silicon oxide having a thickness of 100 nm was formed by using a plasma CVD method (FIG. 7A).

  Next, as shown in FIG. 7B, a first processing resist 600 is formed by using a lithography method so as to protect a region where the MIM capacitor is to be formed, and this first processing resist 600 is used as an etching mask. Then, a processed hard mask 302, a processed upper electrode 204, and a processed capacitance film 401 were formed by dry etching using a fluorine-based halogen gas. Thereafter, the first processed resist 600 remaining by the asher was removed (FIG. 7C). Since the dry etching in this step does not involve processing of a fine pattern, the end point of etching can be easily determined. In addition, even if the capacitive film 400 that is the workpiece remains partially, it does not cause a big problem in the subsequent process.

  Next, in a region other than the region covered with the processed hard mask 302, a second processing resist 601 is formed on the region where the metal wiring is to be formed by using a lithography method, and the second processing resist 601 is etched. The first intermediate layer 300 was dry-etched as a mask (FIG. 8A). Subsequently, using a metal etching apparatus, dry etching using a chlorine-based gas using the processed hard mask 302, the second processed resist, and the processed first intermediate layer 303 directly therebelow as an etching mask. To form a first metal wiring 700 constituted by the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207, and the second processed resist was removed by asher ( FIG. 8B). In this step, since a hard mask with little dimensional shift is used as a processing mask, the first metal wiring 700 can be processed with good dimensional controllability.

  Next, as shown in FIG. 8C, a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by using a plasma CVD method, and then the first interlayer insulating layer 304 is formed by using a chemical mechanical polishing method. The interlayer insulating layer 304 was planarized. Next, using lithography and dry etching, an opening is provided so that the processed upper electrode 204 or the first metal wiring 700 is exposed, and the opening is made of tungsten connected to the upper electrode 204. The first conductive plug 250 and the second conductive plug 251 made of tungsten connected to the first metal wiring 700 were formed.

  Finally, a third barrier layer 208 made of a titanium nitride film with a thickness of 50 nm and a second aluminum layer 209 made of an aluminum alloy with a thickness of 400 nm in a desired region by combining a sputtering method, a lithography method, and a dry etching method, A second metal wiring 701 composed of a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm was formed. Through the above steps, the MIM including the first metal wiring 700, the processed capacitor film 401, the upper electrode 204, the first conductive plug 250, and the second metal wiring 701 as shown in FIG. A semiconductor device having a capacitor can be formed.

FIG. 9 shows a planar layout of the MIM capacitor formed by the above process. The cross-sectional views shown in FIGS. 1, 8, and 9 are cross-sections along AA ′ in FIG. A cross-sectional view in the BB ′ direction in FIG. 9 is shown in FIG. In the layout diagram shown in FIG. 9, an opening 755 provided in the first intermediate layer is a region that functions as an MIM capacitor. A first intermediate layer 303 made of silicon oxide having a film thickness of 100 nm is formed at the edge of the MIM capacitor, that is, at the peripheral edge of the region 755, immediately below the upper electrode represented by the region 754.
In addition to the structure shown in Example 1, structures prepared by changing the film thickness of the first intermediate layer 300 to 0, 10, 50, 200, and 300 nm were also prepared. Here, the structure in which the thickness of the first intermediate layer is 0 nm is essentially the same structure as that of Conventional Example 2.

The performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor thus formed were examined. As a result, a capacitance density of 4 fF / μm ² was obtained regardless of the thickness of the first intermediate layer. On the other hand, when the voltage dependency of the leakage current density flowing through the MIM capacitor was evaluated, the first value that satisfied the standard value of dielectric breakdown voltage (the leakage current density was 1 μA or less per square centimeter at a voltage of 10 V) The intermediate layer 300 had a structure with a film thickness between 50 nm and 200 nm. The reason why the dielectric breakdown voltage does not meet the standard was examined in detail. When the film thickness of the first intermediate layer was 0 nm and 10 nm, the lower electrode 700 and the upper electrode were formed at the end of the capacitor film 401 at the end of the MIM capacitor. It has been found that 204 may be directly opposed across the capacitive film 401. For this reason, it is considered that the dielectric breakdown voltage may have decreased due to the increase in leakage current at the MIM end. On the other hand, when the film thickness of the first intermediate layer was 300 nm, it was observed that the capacitive film 400 was locally thin near the end of the opening provided in the first intermediate layer. This is probably because the lack of coverage of the tantalum oxide film at the end of the opening has become apparent because the film thickness of the first intermediate layer has become too thick. That is, if the first intermediate layer is too thin (for example, 10 nm or less), the effect of suppressing an increase in leakage current at the end of the MIM capacitor is lost, while if the first intermediate layer is too thick (for example, 300 nm or more). It was found that the sputter coverage at the edge of the opening was lowered and the dielectric breakdown voltage was lowered.
Next, in addition to the structure shown in Example 1, a structure using a SiOC film formed by plasma CVD as a first interlayer insulating film was also prepared. The relative dielectric constant of this SiOC film is 2.9. For comparison, a structure based on the process diagram shown in Conventional Example 3 was also prepared.

The performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor thus formed were examined. As a result, regardless of the type of the first interlayer insulating film, a performance of a capacitance density of 4 fF / μm ² and a dielectric breakdown voltage satisfying the standard value were obtained. On the other hand, a difference occurred in the parasitic capacitance of the first metal wiring and the leakage current density between the adjacent first metal wirings. As shown in FIG. 11, in the MIM capacitor formed based on this example using a SiOC film as the first interlayer insulating film, the parasitic capacitance between adjacent wirings is 1.36 pF per 1 cm of the opposing length. When formed based on the conventional example 3, it becomes 1.56 pF, and the parasitic capacitance increases by about 15%, which hinders high-speed circuit operation and low power consumption. On the other hand, when silicon oxide was used for the first interlayer insulating film, there was no significant difference in parasitic capacitance between Example 1 and Conventional Example 3. However, when the short-circuit yield between adjacent wirings was evaluated using the same inter-layer comb capacitor structure formed by the adjacent first metal wiring 700, the short-circuit yield tends to decrease when formed based on the conventional example 3. It was.

  That is, according to the embodiment of the present invention, a first intermediate layer made of a 100 nm-thickness silicon oxide layer having an opening is formed on the lower electrode, and a capacitor film and an upper electrode are formed so as to cover the opening. By processing the upper electrode, the capacitor film, the first intermediate layer, and the lower electrode so as to completely include the opening, a high capacity is achieved while minimizing an increase in leakage current and a decrease in dielectric breakdown voltage. It is possible to form a semiconductor device capable of simultaneously reducing the parasitic capacitance of the wiring layer corresponding to the lower electrode of the MIM capacitor and improving the short circuit yield between the wirings corresponding to the MIM capacitor capable of obtaining the density.

In this embodiment, tantalum oxide having a film thickness of 50 nm is used as the capacitor film, but the film thickness and material are not limited thereto. Since the capacitance density increases in inverse proportion to the thickness of the capacitance film, the smaller the thickness, the better from the viewpoint of capacitance density. However, since the dielectric breakdown voltage also decreases as the film thickness is reduced, there is a thin film limit depending on the voltage used. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Further, in this embodiment, a single-layer insulating film is used as the capacitive film. However, this capacitive film can have a laminated structure as required. For example, a band gap is formed above and below the tantalum oxide film. Leakage current density can be reduced by sandwiching with large aluminum oxide or the like.

  In this embodiment, a silicon oxide film having a film thickness of 100 nm is mainly used as the first intermediate layer, but the film thickness and material are not limited to these. As described above, the first intermediate layer has a preferable film thickness range, and good characteristics of about 50 nm to 200 nm are obtained in the range where the current manufacturing apparatus is used. If a method with better step coverage is adopted as a method of forming the capacitive film, the upper limit of the first intermediate layer can be easily expected to spread to a region of 200 nm or more, but there is no merit in increasing this film thickness unnecessarily. Few. Further, although silicon oxide formed by a plasma CVD method is used as the material used for the first intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. When silicon nitride, silicon oxynitride, or aluminum oxide is used, it can be used as a light-absorbing layer at the time of dry etching or at the time of lithography, but it has the disadvantage that the parasitic capacitance of the wiring increases due to its high dielectric constant. . On the other hand, silicon carbide, nitrogen-containing silicon carbide, SiOC film, and the like have a low relative dielectric constant and are effective in reducing parasitic capacitance, but have a drawback that leakage current is difficult to reduce. Furthermore, in this embodiment, a single layer of silicon oxide is used as the first intermediate layer, but it is also possible to form a laminated structure composed of a plurality of layers. Specifically, in a structure in which silicon nitride is used as a layer in contact with the lower electrode and silicon oxide is used as an upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer can be easily controlled. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the upper electrode, but the thickness and material are not limited to this. If the upper electrode is too thin, the upper electrode may be pierced when the connection hole is opened, and the underlying capacitive film may be damaged. On the other hand, if the film thickness is too thick, a resistor is inserted in series with the MIM capacitor, so that the high frequency characteristics may be deteriorated. In the range where titanium nitride is used, about 50 nm to 100 nm is preferable. In addition to titanium nitride, tantalum, tungsten, and metals mainly composed of nitrides thereof, aluminum, alloys thereof, and the like can be used as upper electrode materials. Furthermore, titanium nitride is used as the barrier metal used for the first and second metal wirings. However, as described above, it is also possible to use a metal mainly composed of tantalum, tungsten, and nitride thereof in addition to titanium nitride. If there is a margin in reliability, it is possible to use a structure that does not use a barrier metal. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.

  Further, in this embodiment, as shown in the layout drawing of FIG. 9, the upper electrode and the upper layer wiring are connected by one connection hole 756 located in the opening. However, the position, number, and size of the connection holes are not limited to this example. As the size of the connection hole is larger, the parasitic resistance is smaller and the high frequency characteristics are better. However, in the case of tungsten generally formed by the CVD method, there is an upper limit size. In the case where the connection hole is filled with an aluminum alloy, the size restriction is eased, but this may cause an increase in the number of processes such as interlayer insulation film planarization and metal planarization. In this embodiment, the connection hole position is inside the opening. In this configuration, the parasitic resistance associated with the upper electrode is minimized, but if the amount of overetching when the connection hole is opened is too large, the capacitive film may be damaged. On the other hand, when the connection hole is provided outside the opening, that is, inside the region 754 in FIG. 9 and outside the region 755, the margin for capacitive film damage caused by overetching is greatly improved. . The reason is that even if the connection hole penetrates the upper electrode and reaches the capacitor film, the first intermediate layer exists immediately below the capacitor film, so damage to the capacitor film does not directly lead to deterioration of the MIM capacitor characteristics. It is. However, since the parasitic resistance due to the sheet resistance of the upper electrode increases, the high frequency characteristics may be adversely affected. In the layout drawing of FIG. 9, the MIM capacitor has an opening 755 formed in only one first intermediate layer. However, the MIM capacitor can be divided into a plurality of openings. It is.

In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When this intoxicating Low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film includes a laminated film composed of the plurality of insulating films. Further, when such a low-k material is used, it is often difficult to apply the tungsten CVD method due to restrictions such as process temperature. In this case, it is preferable to bury the connection hole with aluminum or the like.
In this embodiment, an aluminum wiring obtained by processing the second metal wiring by the dry etching method is used, but an aluminum wiring or a copper wiring using a damascene method can be used as necessary. At this time, it is possible to reduce the number of processes by applying a dual damascene method in which connection holes are formed at the same time.

  12 and 13 are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. In the following, description will be given in order.

  As shown in FIG. 12A, a first barrier film 200 made of a titanium nitride film having a thickness of 50 nm and an aluminum alloy having a thickness of 400 nm are formed on a substrate 100 on which a semiconductor element is formed by sputtering. After forming a first aluminum film 201 and a second barrier metal film 202 made of a titanium nitride film with a thickness of 50 nm, a first intermediate layer 300 made of silicon oxide with a thickness of 100 nm is formed by plasma CVD. Then, after forming an opening in a desired region of the first intermediate layer 300 using a lithography method and a dry etching method, a reactive sputtering method is used so as to cover the opening, and an oxidation with a film thickness of 50 nm is performed. A capacitor film 400 made of a tantalum film and an upper electrode 203 made of titanium nitride having a film thickness of 50 nm were formed by sputtering. Thereafter, a first processing resist 600 was formed using a lithography method so as to protect a region where the MIM capacitor is to be formed.

Next, the processed upper electrode 204 and the processed capacitance film 401 are formed by dry etching using a fluorine-based halogen gas using the first processed resist 600 as an etching mask, and then the first remaining by the asher. The processing resist 600 was removed. Thereafter, a second processing resist 601 was formed by using a lithography method so as to protect the region where the MIM capacitor is to be formed and the region where the metal wiring is to be formed (FIG. 12B).
Next, the first intermediate layer 300 was dry-etched using the second processed resist 601 as an etching mask. Subsequently, dry etching is performed using a metal etching apparatus, and the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207 are configured using the second processing resist 601 as an etching mask. A first metal wiring 700 was formed (FIG. 12C).

  Next, as shown in FIG. 13A, after the second processing resist 601 is removed by an asher, a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by plasma CVD. Thereafter, the first interlayer insulating layer 304 was planarized using a chemical mechanical polishing method. Next, using lithography and dry etching, an opening is provided so that the processed upper electrode 204 or the first metal wiring 700 is exposed, and the opening is made of tungsten connected to the upper electrode 204. The first conductive plug 250 and the second conductive plug 251 made of tungsten connected to the first metal wiring 700 were formed.

Finally, a third barrier layer 208 made of a titanium nitride film with a thickness of 50 nm and a second aluminum layer 209 made of an aluminum alloy with a thickness of 400 nm in a desired region by combining a sputtering method, a lithography method, and a dry etching method, A second metal wiring 701 composed of a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm was formed. Through the above steps, the first metal wiring 700, the processed capacitor film 401, the upper electrode 204, the first conductive plug 250, and the second metal wiring 701 as shown in FIG. It is possible to form a semiconductor device having an MIM capacitor.
In addition to the structure shown in Example 2, a structure using a SiOC film formed by plasma CVD as a first interlayer insulating film was also prepared.

As a result of investigating the performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor formed as described above, the standard values of the capacitance density and the dielectric breakdown voltage equivalent to those shown in Example 1 were obtained. In addition, the parasitic capacitance between the adjacent first metal wirings and the short yield were also the same values as in Example 1.
That is, according to the embodiment of the present invention, a first intermediate layer made of a 100 nm-thickness silicon oxide layer having an opening is formed on the lower electrode, and a capacitor film and an upper electrode are formed so as to cover the opening. By processing the upper electrode, the capacitor film, the first intermediate layer, and the lower electrode so as to completely include the opening, a high capacity is achieved while minimizing an increase in leakage current and a decrease in dielectric breakdown voltage. It is possible to form a semiconductor device capable of simultaneously reducing the parasitic capacitance of the wiring layer corresponding to the lower electrode of the MIM capacitor and improving the short circuit yield between the wirings corresponding to the MIM capacitor capable of obtaining the density.

In this embodiment, unlike the first embodiment, a resist mask is used for processing the laminated aluminum film directly under the MIM capacitor. Since a hard mask is not used, there is a merit that the hard mask film forming step can be omitted, although it is slightly disadvantageous in terms of dimensional controllability during microfabrication.
In this embodiment, tantalum oxide having a film thickness of 50 nm is used as the capacitor film, but the film thickness and material are not limited thereto. Since the capacitance density increases in inverse proportion to the thickness of the capacitance film, the smaller the thickness, the better from the viewpoint of capacitance density. However, since the dielectric breakdown voltage also decreases as the film thickness is reduced, there is a thin film limit depending on the voltage used. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Further, in this embodiment, a single-layer insulating film is used as the capacitive film. However, this capacitive film can have a laminated structure as required. For example, a band gap is formed above and below the tantalum oxide film. Leakage current density can be reduced by sandwiching with large aluminum oxide or the like.

  In this embodiment, a silicon oxide film having a film thickness of 100 nm is mainly used as the first intermediate layer, but the film thickness and material are not limited to these. As described above, the first intermediate layer has a preferable film thickness range, and good characteristics of about 50 nm to 200 nm are obtained in the range where the current manufacturing apparatus is used. If a method with better step coverage is adopted as a method of forming the capacitive film, the upper limit of the first intermediate layer can be easily expected to spread to a region of 200 nm or more, but there is no merit in increasing this film thickness unnecessarily. Few. Further, although silicon oxide formed by a plasma CVD method is used as the material used for the first intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. When silicon nitride, silicon oxynitride, or aluminum oxide is used, it can be used as a light-absorbing layer at the time of dry etching or at the time of lithography, but it has the disadvantage that the parasitic capacitance of the wiring increases due to its high dielectric constant. . On the other hand, silicon carbide, nitrogen-containing silicon carbide, SiOC film, and the like have a low relative dielectric constant and are effective in reducing parasitic capacitance, but have a drawback that leakage current is difficult to reduce. Furthermore, in this embodiment, a single layer of silicon oxide is used as the first intermediate layer, but it is also possible to form a laminated structure composed of a plurality of layers. Specifically, in a structure in which silicon nitride is used as a layer in contact with the lower electrode and silicon oxide is used as an upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer can be easily controlled. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the upper electrode, but the thickness and material are not limited to this. If the upper electrode is too thin, the upper electrode may be pierced when the connection hole is opened, and the underlying capacitive film may be damaged. On the other hand, if the film thickness is too thick, a resistor is inserted in series with the MIM capacitor, so that the high frequency characteristics may be deteriorated. In the range where titanium nitride is used, about 50 nm to 100 nm is preferable. In addition to titanium nitride, tantalum, tungsten, and metals mainly composed of nitrides thereof, aluminum, alloys thereof, and the like can be used as upper electrode materials. Furthermore, titanium nitride is used as the barrier metal used for the first and second metal wirings. However, as described above, it is also possible to use a metal mainly composed of tantalum, tungsten, and nitride thereof in addition to titanium nitride. If there is a margin in reliability, it is possible to use a structure that does not use a barrier metal. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.

  Further, in this embodiment, the configuration shown in the layout drawing of FIG. However, it is different from the embodiment in that the first metal wiring 750 is located outside the region 754 showing the upper electrode. When an actual application is considered, it is not limited to the position, number, and size of the connection holes as shown in the second embodiment. As the size of the connection hole is larger, the parasitic resistance is smaller and the high frequency characteristics are better. However, in the case of tungsten generally formed by the CVD method, there is an upper limit size. In the case where the connection hole is filled with an aluminum alloy, the size restriction is eased, but this may cause an increase in the number of processes such as interlayer insulation film planarization and metal planarization. In this embodiment, the connection hole position is inside the opening. In this configuration, the parasitic resistance associated with the upper electrode is minimized, but if the amount of overetching when the connection hole is opened is too large, the capacitive film may be damaged. On the other hand, when the connection hole is provided outside the opening, that is, inside the region 754 in FIG. 9 and outside the region 755, the margin for capacitive film damage caused by overetching is greatly improved. . The reason is that even if the connection hole penetrates the upper electrode and reaches the capacitor film, the first intermediate layer exists immediately below the capacitor film, so damage to the capacitor film does not directly lead to deterioration of the MIM capacitor characteristics. It is. However, since the parasitic resistance due to the sheet resistance of the upper electrode increases, the high frequency characteristics may be adversely affected.

In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When this intoxicating Low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film includes a laminated film composed of the plurality of insulating films. Further, when such a low-k material is used, it is often difficult to apply the tungsten CVD method due to restrictions such as process temperature. In this case, it is preferable to bury the connection hole with aluminum or the like.
In this embodiment, an aluminum wiring obtained by processing the second metal wiring by the dry etching method is used, but an aluminum wiring or a copper wiring using a damascene method can be used as necessary. At this time, it is also possible to reduce the number of processes by applying a dual damascene method in which connection holes are formed simultaneously.

14 and 15 are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. In the following, description will be given in order.
As shown in FIG. 14A, a 50-nm-thick titanium nitride film, a 400-nm-thick aluminum alloy, and a 50-nm-thick titanium nitride film are formed on a substrate 100 on which a semiconductor element is formed by sputtering. After that, a first metal wiring 700 constituted by the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207 was formed by using a lithography method and a dry etching method. Next, after a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by using a plasma CVD method, the first interlayer insulating layer 304 is planarized by using a chemical mechanical polishing method. It was. Next, using a lithography method and a dry etching method, an opening is provided so that the first metal wiring 700 in a desired region is exposed, and a first conductive plug 250 made of tungsten is formed in the opening. A second conductive plug 251 was formed. Next, a titanium nitride film having a thickness of 50 nm is formed by sputtering so as to cover the first conductive plug 250 and the second conductive plug 251, and the lithography method and the dry etching method are combined. The lower electrode 211 processed so as to cover the first conductive plug 250 was formed. Thereafter, a silicon oxide film having a thickness of 100 nm is formed by using a plasma CVD method, and then a first intermediate layer 300 having an opening 500 is formed in the processed lower electrode 211 by using a lithography method and a dry etching method. .

Next, a capacitor film 400 made of tantalum oxide having a thickness of 50 nm is formed so as to cover the opening 500 and in contact with the processed lower electrode 211, and further made of titanium nitride having a thickness of 50 nm by sputtering. An upper electrode 203 was formed. Thereafter, a first processing resist 600 was formed by using a lithography method so as to cover a region to be left as an MIM capacitor (FIG. 14B).
Next, the upper electrode 203, the capacitor film 400, and the first intermediate layer 300 were dry-etched using the first processing resist 600 as a processing mask. Thereafter, a third barrier film 212 made of a titanium nitride film having a thickness of 50 nm, a second aluminum film 213 made of an aluminum alloy having a thickness of 400 nm, and a fourth film made of a titanium nitride film having a thickness of 50 nm are formed on the entire surface by sputtering. A barrier metal film 214 was formed (FIG. 15A).

Next, as shown in FIG. 15B, a second processed resist 601 is formed by lithography in a region where metal wiring is to be formed, and nitrided to a thickness of 50 nm by dry etching using a chlorine-based gas. A second metal composed of a third barrier layer 208 made of a titanium film, a second aluminum layer 209 made of an aluminum alloy having a thickness of 400 nm, and a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm. A wiring 701 was formed. Finally, the excess second processing resist 601 is removed by an asher so that the first metal wiring 700, the first conductive plug 250, the processed lower electrode 211, the processed capacitance film 401, and the processed capacitor film 401 are processed. A semiconductor device having an MIM capacitor composed of the upper electrode 204 and the second metal wiring 701 can be formed.
In addition to the structure shown in Example 3, structures prepared by changing the thickness of the first intermediate layer 300 to 0, 10, 50, 200, and 300 nm were also prepared.

The performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor thus formed were examined. As a result, similar to Example 1, a performance with a capacitance density of 4 fF / μm ² was obtained regardless of the thickness of the first intermediate layer. On the other hand, the reason why the standard value of the dielectric breakdown voltage of the MIM capacitor was satisfied was that the film thickness of the first intermediate layer 300 was between 50 nm and 200 nm, as in Example 1. When the reason why the dielectric breakdown voltage does not meet the standard was examined in detail, when the thickness of the first intermediate layer was 0 nm and 10 nm, the first intermediate layer formed on the end and side walls of the lower electrode 211 was formed. It was found that the layer and the capacitive film were thin. For this reason, it is considered that the dielectric breakdown voltage may have decreased due to an increase in leakage current at the lower electrode end. On the other hand, when the thickness of the first intermediate layer was 300 nm, it was observed that the capacitive film 400 was locally thin near the end of the opening provided in the first intermediate layer 303. . This is probably because the lack of coverage of the tantalum oxide film at the end of the opening has become apparent because the film thickness of the first intermediate layer has become too thick. That is, if the first intermediate layer is too thin (for example, 10 nm or less), the effect of suppressing an increase in leakage current at the end of the MIM capacitor is lost, while if the first intermediate layer is too thick (for example, 300 nm or more). It was found that the sputter coverage at the edge of the opening was lowered and the dielectric breakdown voltage was lowered.

Further, as in the first embodiment, the periphery of the first metal wiring 700 and the second metal wiring 701 is not covered with the first intermediate layer having a high relative dielectric constant. It has been found that the parasitic capacitance increases, and problems such as an increase in signal delay and an increase in power consumption hardly occur.
That is, according to the embodiment of the present invention, the lower electrode is formed so as to cover the connection hole opened in the lower layer metal wiring, and the first oxide film is formed of a 100 nm-thickness silicon oxide layer having an opening on the lower electrode. By forming an intermediate layer, forming a capacitive film and an upper electrode so as to cover the opening, and processing the upper electrode, the capacitive film, and the first intermediate layer in a form completely including the opening, A semiconductor device having an MIM capacitor capable of obtaining a high capacitance density while minimizing an increase in leakage current and a decrease in dielectric breakdown voltage can be formed.

In the present embodiment, unlike the first embodiment, the material film directly under the capacitance film of the MIM capacitor is a metal film formed separately from the aluminum wiring, so that the material can be selected independently of the barrier metal used in the aluminum wiring. In addition, it has the characteristic that it is not easily affected by hillocks and the like generated on the aluminum wiring. On the other hand, since the lower electrode processing step is newly added, the total number of steps increases.
In this embodiment, tantalum oxide having a film thickness of 50 nm is used as the capacitor film, but the film thickness and material are not limited thereto. Since the capacitance density increases in inverse proportion to the thickness of the capacitance film, the smaller the thickness, the better from the viewpoint of capacitance density. However, since the dielectric breakdown voltage also decreases as the film thickness is reduced, there is a thin film limit depending on the voltage used. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Further, in this embodiment, a single-layer insulating film is used as the capacitive film. However, this capacitive film can have a laminated structure as required. For example, a band gap is formed above and below the tantalum oxide film. Leakage current density can be reduced by sandwiching with large aluminum oxide or the like.

  In this embodiment, a silicon oxide film having a film thickness of 100 nm is mainly used as the first intermediate layer, but the film thickness and material are not limited to these. As described above, the first intermediate layer has a preferable film thickness range, and good characteristics of about 50 nm to 200 nm are obtained in the range where the current manufacturing apparatus is used. If a method with better step coverage is adopted as a method of forming the capacitive film, the upper limit of the first intermediate layer can be easily expected to spread to a region of 200 nm or more, but there is no merit in increasing this film thickness unnecessarily. Few. Further, although silicon oxide formed by a plasma CVD method is used as the material used for the first intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. When silicon nitride, silicon oxynitride, or aluminum oxide is used, it can be used as a light-absorbing layer at the time of dry etching or at the time of lithography, but it has the disadvantage that the parasitic capacitance of the wiring increases due to its high dielectric constant. . On the other hand, silicon carbide, nitrogen-containing silicon carbide, SiOC film, and the like have a low relative dielectric constant and are effective in reducing parasitic capacitance, but have a drawback that leakage current is difficult to reduce. Furthermore, in this embodiment, a single layer of silicon oxide is used as the first intermediate layer, but it is also possible to form a laminated structure composed of a plurality of layers. Specifically, in a structure in which silicon nitride is used as a layer in contact with the lower electrode and silicon oxide is used as an upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer can be easily controlled. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the lower electrode and the upper electrode, but the thickness and material are not limited to this. When the electrode film thickness is too thick, a resistor is inserted in series with the MIM capacitor, so that the high frequency characteristics may be deteriorated. In the range where titanium nitride is used, about 50 nm to 100 nm is preferable. In addition to titanium nitride, tantalum, tungsten, and metals mainly composed of nitrides thereof, aluminum, alloys thereof, and the like can be used as upper electrode materials. Furthermore, titanium nitride is used as the barrier metal used for the first and second metal wirings. However, as described above, it is also possible to use a metal mainly composed of tantalum, tungsten, and nitride thereof in addition to titanium nitride. If there is a margin in reliability, it is possible to use a structure that does not use a barrier metal. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.

In this embodiment, the first metal wiring 700 and the lower electrode 211 are connected by a single connection hole. However, as long as electrical connection between the two is ensured, the number, position, and shape of the connection holes are sufficient. Can be arbitrarily selected. Needless to say, the larger the connection hole, the better in order to reduce the parasitic resistance inserted in series with the MIM capacitor.
In the present embodiment, the connection hole is completely filled with tungsten by the first conductive plug 250, but the effectiveness of the present invention is not limited to this structure and material. As a material for the first conductive plug 250, it is also possible to use a conductor mainly composed of aluminum or copper in addition to tungsten. Further, the surface of the first conductive plug 250 does not necessarily coincide with the surface of the first interlayer insulating film 304, and dents and bumps are formed so as not to affect the reliability. However, it is possible to respond.

  In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When such a low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film includes a laminated film composed of the plurality of insulating films.

  In this embodiment, aluminum wiring obtained by processing the first metal wiring by the dry etching method is used, but aluminum wiring or copper wiring using damascene method may be used as necessary.

16 and 17 are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. In the following, description will be given in order.
As shown in FIG. 16A, a titanium nitride film with a thickness of 50 nm, an aluminum alloy with a thickness of 400 nm, and a titanium nitride film with a thickness of 50 nm are formed on the substrate 100 on which the semiconductor element is formed by sputtering. After that, a first metal wiring 700 constituted by the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207 was formed by using a lithography method and a dry etching method. Next, after a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by using a plasma CVD method, the first interlayer insulating layer 304 is planarized by using a chemical mechanical polishing method. It was. Next, after an etch stopper layer made of silicon nitride having a thickness of 50 nm is formed by a CVD method, an opening is formed by using a lithography method and a dry etching method so that the first metal wiring 700 in a desired region is exposed. A first conductive plug 250 made of tungsten and a second conductive plug 251 were formed in the opening. Next, a titanium nitride film having a thickness of 50 nm is formed by sputtering so as to cover the first conductive plug 250 and the second conductive plug 251, and the lithography method and the dry etching method are combined. The lower electrode 211 processed so as to cover the first conductive plug 250 was formed. Thereafter, a silicon oxide film having a thickness of 100 nm is formed by using a plasma CVD method, and then a first intermediate layer 300 having an opening 500 is formed in the processed lower electrode 211 by using a lithography method and a dry etching method. .

Next, a capacitor film 400 made of tantalum oxide having a thickness of 50 nm is formed so as to cover the opening 500 and in contact with the processed lower electrode 211, and further made of titanium nitride having a thickness of 50 nm by sputtering. An upper electrode 203 was formed. Thereafter, a first processing resist 600 was formed by using a lithography method so as to cover a region to be left as an MIM capacitor (FIG. 16B).
Next, the upper electrode 203, the capacitor film 400, and the first intermediate layer 300 were dry-etched using the first processing resist 600 as a processing mask. After that, a second interlayer insulating film 306 made of silicon oxide having a thickness of 500 nm was formed using a plasma CVD method, and the second interlayer insulating layer 306 was planarized using a chemical mechanical polishing method. Thereafter, a second processing resist 601 was formed by a lithography method in a region where a metal wiring is to be formed (FIG. 17A).

  Next, as shown in FIG. 17B, dry etching is performed using the upper electrode 204 and the etch stopper 305 as an etching stop layer to form an opening in the second interlayer insulating film. Next, a tantalum nitride film with a thickness of 50 nm and a copper film with a film thickness of 100 nm are sequentially formed by sputtering, and then electrolytic copper plating is performed using a copper plating solution containing a copper sulfate aqueous solution as a main component. The opening provided in was embedded. Thereafter, the copper film and the tantalum nitride film in an excess region are removed by using a chemical mechanical polishing method, and a second metal wiring 701 composed of the first copper layer 216 and the fifth barrier metal layer 215 is formed. Formed. In this way, the first metal wiring 700, the first conductive plug 250, the processed lower electrode 211, the processed capacitance film 401, the processed upper electrode 204, and the second metal wiring 701 are configured. It is possible to form a semiconductor device having an MIM capacitor.

As a result of examining the performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor formed as described above, it was found that the same reliability and performance as those shown in Example 3 were obtained.
That is, according to the embodiment of the present invention, the lower electrode is formed so as to cover the connection hole opened in the lower layer metal wiring, and the first oxide film is formed of a 100 nm-thickness silicon oxide layer having an opening on the lower electrode. By forming an intermediate layer, forming a capacitive film and an upper electrode so as to cover the opening, and processing the upper electrode, the capacitive film, and the first intermediate layer in a form completely including the opening, A semiconductor device having an MIM capacitor capable of obtaining a high capacitance density while minimizing an increase in leakage current and a decrease in dielectric breakdown voltage can be formed.

  In the present embodiment, unlike the first embodiment, the material film directly under the capacitance film of the MIM capacitor is a metal film formed separately from the aluminum wiring, so that the material can be selected independently of the barrier metal used in the aluminum wiring. In addition, it has the characteristic that it is not easily affected by hillocks and the like generated on the aluminum wiring. On the other hand, since the lower electrode processing step is newly added, the total number of steps increases.

  In this embodiment, tantalum oxide having a film thickness of 50 nm is used as the capacitor film, but the film thickness and material are not limited to this. Since the capacitance density increases in inverse proportion to the thickness of the capacitance film, the smaller the thickness, the better from the viewpoint of capacitance density. However, since the dielectric breakdown voltage also decreases as the film thickness is reduced, there is a thin film limit depending on the voltage used. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Further, in this embodiment, a single-layer insulating film is used as the capacitive film. However, this capacitive film can have a laminated structure as required. For example, a band gap is formed above and below the tantalum oxide film. Leakage current density can be reduced by sandwiching with large aluminum oxide or the like.

  In this embodiment, silicon nitride having a film thickness of 50 nm is used as the etch stopper layer, but the film thickness and material are not limited to this. Since silicon nitride has a high relative dielectric constant, a low-k film typified by silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used to reduce parasitic capacitance. . In this embodiment, the etch stopper layer is formed on the first interlayer insulating film and below the lower electrode 211. However, the present invention is not limited to this position, and the upper electrode 204 and the capacitor film 401 are formed. It is also possible to form the coating. In this case, the MIM capacitor portion is not exposed to the plasma during the processing of the second interlayer insulating film, and is exposed to the plasma only when the etch stopper layer is removed after the processing is completed. Further, when the restriction on the controllability of the wiring height is loose, a structure in which this etch stopper layer is not provided can be used.

  In this embodiment, a silicon oxide film having a film thickness of 100 nm is mainly used as the first intermediate layer, but the film thickness and material are not limited to these. As described above, the first intermediate layer has a preferable film thickness range, and good characteristics of about 50 nm to 200 nm are obtained in the range where the current manufacturing apparatus is used. If a method with better step coverage is adopted as a method of forming the capacitive film, the upper limit of the first intermediate layer can be easily expected to spread to a region of 200 nm or more, but there is no merit in increasing this film thickness unnecessarily. Few. Further, although silicon oxide formed by a plasma CVD method is used as the material used for the first intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. When silicon nitride, silicon oxynitride, or aluminum oxide is used, it can be used as a light-absorbing layer at the time of dry etching or at the time of lithography, but it has the disadvantage that the parasitic capacitance of the wiring increases due to its high dielectric constant. . On the other hand, silicon carbide, nitrogen-containing silicon carbide, SiOC film, and the like have a low relative dielectric constant and are effective in reducing parasitic capacitance, but have a drawback that leakage current is difficult to reduce. Furthermore, in this embodiment, a single layer of silicon oxide is used as the first intermediate layer, but it is also possible to form a laminated structure composed of a plurality of layers. Specifically, in a structure in which silicon nitride is used as a layer in contact with the lower electrode and silicon oxide is used as an upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer can be easily controlled. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the lower electrode and the upper electrode, but the thickness and material are not limited to this. When the electrode film thickness is too thick, a resistor is inserted in series with the MIM capacitor, so that the high frequency characteristics may be deteriorated. In the range where titanium nitride is used, about 50 nm to 100 nm is preferable. In addition to titanium nitride, tantalum, tungsten, and metals mainly composed of nitrides thereof, aluminum, alloys thereof, and the like can be used as upper electrode materials. Furthermore, titanium nitride is used as the barrier metal used for the first metal wiring, and tantalum nitride is used as the barrier metal used for the second metal wiring. As described above, titanium tantalum nitride, tungsten, and nitrides thereof are used. It is possible to use a metal as a main component, and it is also possible to use a structure that does not use a barrier metal as long as there is a margin in reliability. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.

  In this embodiment, the first metal wiring 700 and the lower electrode 211 are connected by a single connection hole. However, as long as electrical connection between the two is ensured, the number, position, and shape of the connection holes are sufficient. Can be arbitrarily selected. Needless to say, the larger the connection hole, the better in order to reduce the parasitic resistance inserted in series with the MIM capacitor.

  In the present embodiment, the connection hole is completely filled with tungsten by the first conductive plug 250, but the effectiveness of the present invention is not limited to this structure and material. As a material for the first conductive plug 250, it is also possible to use a conductor mainly composed of aluminum or copper in addition to tungsten. Further, the surface of the first conductive plug 250 does not necessarily coincide with the surface of the first interlayer insulating film 304, and dents and bumps are formed so as not to affect the reliability. However, it is possible to respond.

  In this embodiment, the process using the silicon oxide film as the first interlayer insulating film and the second interlayer insulating film has been described as an example. However, the process is not limited to this material, and the parasitic capacitance of the wiring is reduced. It is also possible to use possible Low-k materials. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When such a low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film and the second interlayer insulating film include a laminated film composed of the plurality of insulating films. It is out.

  In this embodiment, aluminum wiring obtained by processing the first metal wiring by the dry etching method is used, but aluminum wiring or copper wiring using damascene method may be used as necessary.

This embodiment is one of application examples using the manufacturing process of the semiconductor device shown in the second embodiment. The steps for forming the MIM capacitor and the resistor on the same plane are shown in FIGS. This will be described with reference to the cross-sectional view shown. In the following, description will be given in order.
As shown in FIG. 18A, a first barrier film 200 made of a titanium nitride film having a thickness of 50 nm and an aluminum alloy having a thickness of 400 nm are formed on a substrate 100 on which a semiconductor element is formed by sputtering. After forming a first aluminum film 201 and a second barrier metal film 202 made of a titanium nitride film with a thickness of 50 nm, a first intermediate layer 300 made of silicon oxide with a thickness of 100 nm is formed by plasma CVD. Then, after forming an opening in a desired region of the first intermediate layer 300 using a lithography method and a dry etching method, a reactive sputtering method is used so as to cover the opening, and an oxidation with a film thickness of 50 nm is performed. A capacitor film 400 made of a tantalum film and an upper electrode 203 made of tantalum nitride having a film thickness of 25 nm were formed by sputtering. After that, the first processing resist 600 was formed in the region where the MIM capacitor is to be formed using the lithography method, and the second processing resist 601 was formed in the region where the resistor is to be formed.

  Next, with the first processed resist 600 and the second processed resist 601 as an etching mask, the processed upper electrode 204, the processed capacitance film 401, and the processed capacitor film 401 were processed by dry etching using a fluorine-based halogen gas. After the resistor layer 217 and the capacitor film 402 under the resistor layer were formed, the first processed resist 600 and the second processed resist 601 remaining by the asher were removed. Thereafter, a third processing resist 602 was formed using a lithography method so as to protect the region where the MIM capacitor is to be formed and the region where the metal wiring is to be formed (FIG. 18B).

Next, the first intermediate layer 300 was dry-etched using the third processed resist 602 as an etching mask. Subsequently, dry etching is performed using a metal etching apparatus, and the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207 are formed using the third processing resist 602 as an etching mask. A first metal wiring 700 to be formed was formed (FIG. 18C).
Next, as shown in FIG. 19A, after removing the third processing resist 602 with an asher, a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm was formed by plasma CVD. Thereafter, the first interlayer insulating layer 304 was planarized using a chemical mechanical polishing method. Next, using lithography and dry etching, an opening is provided so that the processed upper electrode 204 or the processed resistor layer 217 is exposed, and tungsten connected to the upper electrode 204 is connected to the opening. And a second conductive plug 251 made of tungsten connected to the processed resistor layer 217. Although not disclosed in the drawing, when it is necessary to provide a connection hole in the first metal wiring in which the MIM capacitor and the resistor are not formed, the first intermediate layer 303 is also provided with an opening, One metal wiring 700 needs to be exposed.

Finally, a third barrier layer 208 made of a titanium nitride film with a thickness of 50 nm and a second aluminum layer 209 made of an aluminum alloy with a thickness of 400 nm in a desired region by combining a sputtering method, a lithography method, and a dry etching method, A second metal wiring 701 composed of a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm was formed. Through the above steps, the first metal wiring 700, the processed capacitor film 401, the upper electrode 204, the first conductive plug 250, and the second metal wiring 701 as shown in FIG. It is possible to form a semiconductor device having a resistor composed of the MIM capacitor to be processed and the processed resistor layer 217.
The performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor formed as described above are the same as those in the second embodiment. On the other hand, it was found that the resistor thus formed has a sheet resistance of 92Ω / □. Furthermore, when the temperature coefficient of electrical resistance was evaluated, sufficient performance of −70 ppm / ° C. was obtained.

  That is, according to the embodiment of the present invention, a first intermediate layer made of a 100 nm-thickness silicon oxide layer having an opening is formed on the lower electrode, and a capacitor film and an upper electrode are formed so as to cover the opening. Then, the upper electrode, the capacitor film, the first intermediate layer, and the lower electrode are processed so as to completely include the opening, and the upper electrode and the capacitor film are further processed in a region where a resistor is to be formed when the upper electrode is processed. Then, if the first intermediate layer and the lower electrode are processed so as to include the region where the resistor is to be formed, the MIM capacitor can obtain a high capacitance density while minimizing an increase in leakage current and a decrease in dielectric breakdown voltage. As a result, it is possible to form a semiconductor device capable of simultaneously reducing the parasitic capacitance of the wiring layer corresponding to the lower electrode of the MIM capacitor, improving the short circuit yield, and a resistor having an excellent temperature coefficient.

  In this embodiment, the upper electrode and the resistor are formed of tantalum nitride having a film thickness of 25 nm, but the film thickness and material are not limited thereto. Other materials and different film thicknesses can be used as long as the performance as the upper electrode and the performance as the resistor are not impaired. Specifically, an alloy containing a refractory metal such as titanium, tungsten, or molybdenum and a nitride thereof as a main component can be used. Also, the film thickness can be changed within the range of sheet resistance allowed in circuit design according to the resistivity of the substance forming the resistor. In this embodiment, the upper electrode and the resistor are made of a single layer of tantalum nitride. However, a stacked structure in which a plurality of layers having different compositions and materials can be stacked.

  In this embodiment, tantalum oxide having a film thickness of 50 nm is used as the capacitor film, but the film thickness and material are not limited to this. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Furthermore, in this embodiment, a single-layer insulating film is used as the capacitive film, but this capacitive film may have a laminated structure as necessary.

  In this embodiment, a silicon oxide film having a film thickness of 100 nm is mainly used as the first intermediate layer, but the film thickness and material are not limited to these. As described above, the first intermediate layer has a preferable film thickness range, and in the range where the current manufacturing apparatus is used, good characteristics of about 50 nm to 200 nm are obtained. Depending on this, it is easily predictable that this preferred film thickness range will change to some extent. Further, although silicon oxide formed by a plasma CVD method is used as the material used for the first intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. Furthermore, in this embodiment, a single layer of silicon oxide is used as the first intermediate layer, but it is also possible to form a laminated structure composed of a plurality of layers. Specifically, in a structure in which silicon nitride is used as a layer in contact with the lower electrode and silicon oxide is used as an upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer can be easily controlled. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility.

In the present embodiment, the layout of the MIM portion is almost the same as that shown in the layout drawing of FIG. In consideration of actual application, the point, number, and size of the connection hole as shown in the present embodiment are not limited to those described in the second embodiment.
In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used.

  In this embodiment, an aluminum wiring obtained by processing the second metal wiring by the dry etching method is used, but an aluminum wiring or a copper wiring using a damascene method can be used as necessary. At this time, it is possible to reduce the number of processes by applying a dual damascene method in which connection holes are formed at the same time.

This embodiment is one of application examples using the manufacturing process of the semiconductor device shown in the third embodiment. The steps for forming the MIM capacitor and the resistor on the same plane are shown in FIGS. This will be described with reference to the cross-sectional view shown. In the following, description will be given in order.
As shown in FIG. 20A, a sputtering method is used to form a 50 nm thick titanium nitride film, a 400 nm thick aluminum alloy, and a 50 nm thick titanium nitride film on a substrate 100 on which a semiconductor element is formed. After that, a first metal wiring 700 constituted by the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207 was formed by using a lithography method and a dry etching method. Next, after a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by using a plasma CVD method, the first interlayer insulating layer 304 is planarized by using a chemical mechanical polishing method. It was. Next, using a lithography method and a dry etching method, an opening is provided so that the first metal wiring 700 in a desired region is exposed, and a first conductive plug 250 made of tungsten is formed in the opening. A second conductive plug 251 was formed. Next, a tantalum nitride film having a thickness of 50 nm is formed using a sputtering method so as to cover the first conductive plug 250 and the second conductive plug 251, and the lithography method and the dry etching method are combined. The lower electrode 211 processed so as to cover the first conductive plug 250 and the resistor layer 217 processed so as to cover the second conductive plug 251 were formed. Thereafter, a silicon oxide film having a thickness of 100 nm was formed using a plasma CVD method, and then a first processing resist 600 having an opening in a desired region was formed using a lithography method. The first processed resist 600 needs to have an opening on at least the processed lower electrode 211.

  Next, dry etching is performed using the first processing resist 600 as a processing mask, an opening is provided in the first intermediate layer 300 so that at least the lower electrode 211 is exposed, and then the capacitor is formed so as to cover the opening. A film 400 and an upper electrode 203 were formed (FIG. 20B). Next, after forming a second processing resist 601 using a lithography method so as to cover a region to be left as an MIM capacitor, the upper electrode 203 and the capacitor film 400 are dried using the second processing resist 601 as a processing mask. Etched (FIG. 21 (a)). In this step, the processed resistor layer 217 is not etched because it is protected by the first intermediate layer 303 processed in the upper part.

  Next, after the second processing resist 601 is removed with an asher, a 50 nm-thickness titanium nitride film, a 400 nm-thickness aluminum alloy, and a 50 nm-thickness titanium nitride film are formed on the entire surface by sputtering, followed by a lithography method. And a dry etching method using a chlorine-based gas, a third barrier layer 208 made of a titanium nitride film with a thickness of 50 nm, a second aluminum layer 209 made of an aluminum alloy with a thickness of 400 nm, A second metal wiring 701 composed of the fourth barrier metal layer 210 made of a 50 nm titanium nitride film was formed. In this way, the first metal wiring 700, the first conductive plug 250, the processed lower electrode 211, the processed capacitance film 401, the processed upper electrode 204, and the second metal wiring 701 are configured. Thus, it is possible to form a semiconductor device having a resistor composed of the MIM capacitor and the resistor layer 217 connected to the second conductive plug 251.

FIG. 22 shows an example of a planar layout diagram of the MIM capacitor and resistor formed in the above process. 20 and 21 are cross sections taken along the line AA 'in FIG. 23 is a cross-sectional view in the BB ′ direction in FIG. 22, and FIG. 24 is a cross-sectional view in the CC ′ direction in FIG. 22. In the layout diagram shown in FIG. 22, an opening 755 provided in the first intermediate layer is a region that functions as a MIM capacitor, and a resistor 761 is a region that functions as a resistor.
As a result of examining the performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor and the resistor formed as described above, it was found that the same performance and reliability as those of Example 3 were obtained. It was also found that the resistor formed in this way had a sheet resistance of 92Ω / □. Furthermore, when the temperature coefficient of electrical resistance was evaluated, sufficient performance of −70 ppm / ° C. was obtained.

That is, according to the embodiment of the present invention, the lower electrode is formed so as to cover the connection hole opened in the lower layer metal wiring, and the first oxide film is formed of a 100 nm-thickness silicon oxide layer having an opening on the lower electrode. By forming an intermediate layer, forming a capacitive film and an upper electrode so as to cover the opening, and processing the upper electrode, the capacitive film, and the first intermediate layer in a form completely including the opening, It is possible to form an MIM capacitor capable of obtaining a high capacitance density while minimizing an increase in leakage current and a decrease in breakdown voltage, and further, a resistor is formed by processing a part of the metal film formed as the lower electrode. By forming the first intermediate layer so as to cover the resistor, a semiconductor device in which the resistor can be formed without increasing the number of steps can be obtained.
In the present embodiment, unlike the fifth embodiment, the material film directly under the capacitance film of the MIM capacitor is a metal film formed separately from the aluminum wiring, so that the material can be selected independently of the barrier metal used for the aluminum wiring. In addition, it has the characteristic that it is not easily affected by hillocks and the like generated on the aluminum wiring. On the other hand, since the lower electrode processing step is newly added, the total number of steps increases.

  In this embodiment, the lower electrode and the resistor are formed of tantalum nitride having a film thickness of 25 nm, but the film thickness and material are not limited to this. Other materials and different film thicknesses can be used as long as the performance as the lower electrode and the performance as the resistor are not impaired. Specifically, an alloy containing a refractory metal such as titanium, tungsten, or molybdenum and a nitride thereof as a main component can be used. Also, the film thickness can be changed within the range of sheet resistance allowed in circuit design according to the resistivity of the substance forming the resistor. In this embodiment, the lower electrode and the resistor are made of a single layer of tantalum nitride, but a laminated structure in which a plurality of layers having different compositions and materials can be stacked.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the upper electrode, but the thickness and material are not limited to this. As a material for the upper electrode, in addition to titanium nitride, metal including tantalum, tungsten, and nitride thereof as a main component, aluminum, and an alloy thereof can be used. Furthermore, titanium nitride is used as the barrier metal used for the first and second metal wirings. However, as described above, it is also possible to use a metal mainly composed of tantalum, tungsten, and nitride thereof in addition to titanium nitride. If there is a margin in reliability, it is possible to use a structure that does not use a barrier metal. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.

  In this embodiment, tantalum oxide having a film thickness of 50 nm is used as the capacitor film, but the film thickness and material are not limited to this. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Furthermore, in this embodiment, a single-layer insulating film is used as the capacitive film, but this capacitive film may have a laminated structure as necessary.

In this embodiment, a silicon oxide film having a film thickness of 100 nm is mainly used as the first intermediate layer, but the film thickness and material are not limited to these. As described above, the first intermediate layer has a preferable film thickness range, and in the range where the current manufacturing apparatus is used, good characteristics of about 50 nm to 200 nm are obtained. Depending on this, it is easily predictable that this preferred film thickness range will change to some extent. Further, although silicon oxide formed by a plasma CVD method is used as the material used for the first intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. Furthermore, in this embodiment, a single layer of silicon oxide is used as the first intermediate layer, but it is also possible to form a laminated structure composed of a plurality of layers. Specifically, in a structure in which silicon nitride is used as a layer in contact with the lower electrode and silicon oxide is used as an upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer can be easily controlled. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility.
In this embodiment, the layout configuration shown in FIG. 22 is adopted. When an actual application is considered, the position, number, and size of the connection hole as shown in the present embodiment are not limited to those described in the other embodiments.

  In this embodiment, the connection hole is completely filled with tungsten by the first conductive plug 250 and the second conductive plug 251, but the effectiveness of the present invention is limited to this structure and material. Do not mean. In addition to tungsten, a conductive material mainly composed of aluminum or copper can be used as the conductive material. Further, the surfaces of the first conductive plug 250 and the second conductive plug 251 do not necessarily coincide with the surface of the first interlayer insulating film 304, and the dents and bumps are not affected by the reliability. It is possible to cope with the electrode and capacitor film forming steps.

In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When such a low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film includes a laminated film composed of the plurality of insulating films.
In this embodiment, the aluminum wiring obtained by processing the first metal wiring and the second metal wiring by the dry etching method is used. However, if necessary, aluminum wiring or copper wiring using the damascene method can be used. It is.

This embodiment is one of application examples using the manufacturing process of the semiconductor device shown in the second embodiment, and the steps for forming the MIM capacitor by stacking two stages in the vertical direction are shown in FIG. 25 and FIG. This will be described using a cross-sectional view. In the following, description will be given in order.
As shown in FIG. 25A, a first barrier film 200 made of a titanium nitride film with a thickness of 50 nm and an aluminum alloy with a thickness of 400 nm are formed on a substrate 100 on which a semiconductor element is formed by sputtering. After forming a first aluminum film 201 and a second barrier metal film 202 made of a titanium nitride film with a thickness of 50 nm, a first intermediate layer made of silicon oxide with a thickness of 100 nm is formed by plasma CVD. A tantalum oxide film having a film thickness of 50 nm is formed using a reactive sputtering method so as to cover the opening after providing an opening in a desired region of the first intermediate layer using lithography and dry etching An upper electrode made of titanium nitride having a film thickness of 50 nm was formed using a capacitor film made of Thereafter, the upper electrode 204 processed so as to cover the opening and the processed capacitance film 401 were formed by using a lithography method and a dry etching method.

Next, a second intermediate layer 307 made of silicon oxide having a thickness of 100 nm was formed on the entire surface by plasma CVD. Thereafter, a first processing resist 600 having an opening on at least the processed upper electrode 204 and the processed capacitance film 401 is formed on the second intermediate layer 307 by using a lithography method ((FIG. 25 ( b))).
Next, using the first processed resist 600 as an etching mask, the second intermediate layer 307 was dry-etched until the processed upper electrode 204 was exposed to form a processed second intermediate layer 308. Thereafter, a reactive sputtering method was used to form a second capacitor film 403 made of a tantalum oxide film with a thickness of 50 nm, and a second upper electrode 218 made of titanium nitride with a thickness of 50 nm using a sputtering method ( FIG. 25 (c)).
Next, as shown in FIG. 26A, at least an opening on the processed upper electrode 204 provided in the processed second intermediate layer is covered by using a lithography method and a dry etching method. Thus, the processed second capacitive film 404 and the processed second upper electrode 219 were formed. Subsequently, a second processed resist 601 was formed in a desired region so as to include at least the processed upper electrode 204 and the processed second upper electrode 219 using a lithography method.
Next, after the processed first intermediate layer 303 is dry-etched using the second processing resist 601 as an etching mask, the second barrier metal film 202, the first aluminum film 201, and the first barrier film are subsequently used. 200 was dry-etched to form a first metal wiring 700 constituted by the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207. Next, after removing the second processing resist 601 with an asher, a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by plasma CVD, and then chemical mechanical polishing is used. The first interlayer insulating layer 304 was planarized. Next, using a lithography method and a dry etching method, an opening is provided so that the processed upper electrode 204, the first metal wiring 700, and the processed second upper electrode 219 are exposed. In contrast, the first conductive plug 250 made of tungsten connected to the processed second upper electrode 219, the second conductive plug 251 made of tungsten connected to the processed upper electrode 204, and the first metal wiring. A third conductive plug 252 made of tungsten connected to 700 was formed.

  Finally, a third barrier layer 208 made of a titanium nitride film having a thickness of 50 nm is formed so as to be electrically connected to the second conductive plug 251 by combining a sputtering method, a lithography method, and a dry etching method. A second metal wiring 701 composed of a second aluminum layer 209 made of an aluminum alloy having a thickness of 400 nm, a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm, and a first conductive plug 250. And a sixth barrier layer 220 made of a titanium nitride film with a thickness of 50 nm, electrically connected to the third conductive plug 252, a third aluminum layer 221 made of an aluminum alloy with a thickness of 400 nm, and a thickness of 50 nm A second metal wiring 702 composed of a seventh barrier metal layer 222 made of a titanium nitride film was formed. Through the above steps, the first metal wiring 700, the processed capacitive film 401, the processed upper electrode 204, the processed second capacitive film 404, and the processed metal as shown in FIG. It becomes possible to form a semiconductor device having MIM capacitors stacked in the vertical direction and configured by the second upper electrode 219.

As a result of investigating the performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor formed as described above, a standard value of dielectric breakdown voltage equal to that shown in Example 2 was obtained. In addition, the parasitic capacitance between the adjacent first metal wirings and the short yield were also the same as those in Example 2. On the other hand, in this example, since the MIM capacitors shown in Example 2 were connected in parallel, a capacity density about twice that of Example 2 was obtained.
That is, according to the embodiment of the present invention, a first intermediate layer made of a 100 nm-thickness silicon oxide layer having an opening is formed on the lower electrode, and a capacitor film and an upper electrode are formed so as to cover the opening. Then, the upper electrode and the capacitor film are processed so as to completely include the opening, and a second intermediate layer made of a 100 nm-thickness silicon oxide layer having an opening is formed on the lower electrode, and the opening Leakage current by forming the second capacitive film and the second upper electrode so as to cover the portion, and processing the second upper electrode and the second capacitive film so as to completely include the opening. It is possible to simultaneously reduce the parasitic capacitance of the wiring layer corresponding to the lower electrode of this MIM capacitor and to improve the short-circuit yield between the MIM capacitor, which can obtain a high capacitance density while minimizing the increase and breakdown voltage breakdown. Semiconductor device But the possible formation.

Unlike the second embodiment, this embodiment has a structure in which MIM capacitors are stacked in two stages in the vertical direction. Although the number of manufacturing steps increases, the capacity density per MIM capacitor occupation area can be greatly improved.
In the present embodiment, a structure in which MIM capacitors are stacked in two stages in the vertical direction is used. However, the number of stacked layers may be three or more as required.

  In this example, tantalum oxide having a film thickness of 50 nm was used as the capacitor film and the second capacitor film, but the film thickness and material are not limited thereto. Since the capacitance density increases in inverse proportion to the thickness of the capacitance film, the smaller the thickness, the better from the viewpoint of capacitance density. However, since the dielectric breakdown voltage also decreases as the film thickness is reduced, there is a thin film limit depending on the voltage used. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Further, in this embodiment, a single-layer insulating film is used as the capacitive film. However, this capacitive film can have a laminated structure as required. For example, a band gap is formed above and below the tantalum oxide film. Leakage current density can be reduced by sandwiching with large aluminum oxide or the like. Further, the capacitor film and the second capacitor film do not necessarily need to use the same material, the same manufacturing method, and the same film thickness, and can be used properly according to the application.

  In this embodiment, a silicon oxide film having a thickness of 100 nm is mainly used as the first intermediate layer and the second intermediate layer. However, the present invention is not limited to this thickness and material. As described above, the first intermediate layer and the second intermediate layer have suitable film thickness ranges, and good characteristics of about 50 nm to 200 nm are obtained in the range where the current manufacturing apparatus is used. If a method with better step coverage is adopted as a method of forming the capacitive film, it can be easily predicted that the upper limit of the film thickness extends to a region of 200 nm or more, but there is little merit in increasing this film thickness unnecessarily. Further, although silicon oxide formed by plasma CVD is used as a material for the first intermediate layer and the second intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. When silicon nitride, silicon oxynitride, or aluminum oxide is used, it can be used as a light-absorbing layer at the time of dry etching or at the time of lithography, but it has the disadvantage that the parasitic capacitance of the wiring increases due to its high dielectric constant. . On the other hand, silicon carbide, nitrogen-containing silicon carbide, SiOC film, and the like have a low relative dielectric constant and are effective in reducing parasitic capacitance, but have a drawback that leakage current is difficult to reduce. Furthermore, in this embodiment, single-layer silicon oxide is used as the first intermediate layer and the second intermediate layer, but it is also possible to form a laminated structure including a plurality of layers. Specifically, in the structure where silicon nitride is used as the layer in contact with the lower electrode and silicon oxide is used as the upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer and the second intermediate layer is controlled. It becomes easy to do. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility. In this embodiment, the first intermediate layer and the second intermediate layer use the same film thickness, the same material, and the same manufacturing method. However, the effectiveness of the present invention is not limited to this.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the upper electrode and the second upper electrode, but the thickness and material are not limited to this. If the film thickness is too thin, there is a risk of breaking through the electrode when the connection hole is opened and damaging the capacitive film located below. On the other hand, if the film thickness is too thick, a resistor is inserted in series with the MIM capacitor, so that the high frequency characteristics may be deteriorated. In the range where titanium nitride is used, about 50 nm to 100 nm is preferable. In addition to titanium nitride, tantalum, tungsten, and metals mainly composed of nitrides thereof, aluminum, and alloys thereof can be used as electrode materials.

Furthermore, titanium nitride is used as the barrier metal used for the first, second, and third metal wirings. As described above, a metal containing tantalum, tungsten, and its nitride as a main component is used in addition to titanium nitride. It is also possible to use a structure that does not use a barrier metal as long as the reliability is sufficient. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.
In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When such a low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film includes a laminated film composed of the plurality of insulating films. Further, when such a low-k material is used, it is often difficult to apply the tungsten CVD method due to restrictions such as process temperature. In this case, it is preferable to bury the connection hole with aluminum or the like.

  In this embodiment, the aluminum wiring obtained by processing the second and third metal wirings by the dry etching method is used. However, if necessary, aluminum wiring or copper wiring using the damascene method can be used. At this time, it is possible to reduce the number of processes by applying a dual damascene method in which connection holes are formed at the same time.

This embodiment is one of application examples using the manufacturing process of the semiconductor device shown in Embodiment 7, and details of the present invention will be described with reference to a cross-sectional view shown in FIG. In the following, description will be given in order.
The structure shown in FIG. 26A is created according to the manufacturing process shown in the seventh embodiment.

  Next, after the processed first intermediate layer 303 is dry-etched using the second processing resist 601 as an etching mask, the second barrier metal film 202, the first aluminum film 201, and the first barrier film are subsequently used. 200 was dry-etched to form a first metal wiring 700 constituted by the first barrier metal layer 205, the first aluminum layer 206, and the second barrier metal layer 207. Next, after removing the second processing resist 601 with an asher, a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by plasma CVD, and then chemical mechanical polishing is used. The first interlayer insulating layer 304 was planarized. Next, using a lithography method and a dry etching method, an opening is provided so that the processed upper electrode 204, the first metal wiring 700, and the processed second upper electrode 219 are exposed. In contrast, the first conductive plug 250 made of tungsten connected to the processed second upper electrode 219, the second conductive plug 251 made of tungsten connected to the processed upper electrode 204, and the first metal wiring. A third conductive plug 252 made of tungsten connected to 700 was formed. The manufacturing process so far is the same as that of the seventh embodiment.

Next, a third barrier layer 208 made of a titanium nitride film having a thickness of 50 nm is formed so as to be electrically connected to the second conductive plug 251 by combining sputtering, lithography, and dry etching. A second metal wiring 701 composed of a second aluminum layer 209 made of an aluminum alloy having a thickness of 400 nm, a fourth barrier metal layer 210 made of a titanium nitride film having a thickness of 50 nm, the first conductive plug 250 and the electric Connected sixth barrier layer 220 made of titanium nitride film with a thickness of 50 nm, third aluminum layer 221 made of aluminum alloy with a thickness of 400 nm, and seventh barrier metal made of titanium nitride film with a thickness of 50 nm Nitriding having a film thickness of 50 nm electrically connected to the second metal wiring 702 composed of the layer 222 and the third conductive plug 252 A fourth barrier metal layer 223 made of a tantalum film, a fourth aluminum layer 224 made of an aluminum alloy with a thickness of 400 nm, and a ninth barrier metal layer 225 made of a titanium nitride film with a thickness of 50 nm. Metal wiring 703 was formed.
27, the first metal wiring 700, the processed capacitive film 401, the processed upper electrode 204, the processed second capacitive film 404, and the processed second capacitive film as shown in FIG. It is possible to form a semiconductor device having MIM capacitors stacked in the vertical direction, which is composed of the upper electrode 219.

In the structure of the present embodiment shown in FIG. 27, the separate extraction terminals (702, 703) are formed for the first conductive plug 250 and the third conductive plug 252. It is different from the structure.
FIG. 28 schematically shows an electrical equivalent circuit of the MIM capacitor portion shown in FIG. Here, C1 is a capacitance value of a capacitor composed of the first metal wiring 700, the processed capacitive film 401, and the processed upper electrode 204, and C2 is the processed upper electrode 204 and the processed second electrode. This is the capacitance value of the capacitor composed of the capacitive film 404 and the processed second upper electrode 219. The terminal 1 corresponds to the second metal wiring 701, the terminal 2 corresponds to the third metal wiring 702, and the terminal 3 corresponds to the fourth metal wiring 703. S1, S2, S3, and S4 are electrical switches. When the switch is “ON”, it indicates a conductive state, and “OFF” indicates a non-conductive state.

  FIG. 28 (b) shows the “on / off” state of each switch and the capacitance value obtained between the terminals. For example, if S1 and S2 are set to “ON” and S3 and S4 are set to “OFF”, the capacitance value between the terminal 1 and the terminal 2 (or the terminal 3) is a parallel capacitance (C1 + C2) of C1 and C2. Specifically, in order to set S1 to “ON”, the third metal wiring 702 and the fourth metal wiring 703 may be electrically short-circuited. To set S2 to “ON”, The second metal wiring 701 may be electrically connected to the processed upper electrode 204. In order to set S3 and S4 to “OFF”, the second metal wiring 701, the third metal wiring 702, and the fourth metal wiring 703 may be arranged so as not to be electrically short-circuited. On the other hand, if all of S1, S2, S3, and S4 are set to “OFF”, the capacitance value between the terminal 2 and the terminal 3 is a series capacitance of C1 and C2 (C1 × C2 / (C1 + C2)). Further, when S1 is set to “OFF” and S2 is set to “ON”, S3 is set to “OFF” and S4 is set to “ON”, so that the capacitance value between the terminals 1 and 3 is C1, S3 is set to “ON”, If S4 is set to “OFF”, the capacitance value between the terminal 1 and the terminal 2 is C2. These connection types can also be easily realized by changing the connection method between the metal wirings.

The performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor thus formed were examined. In the structure in which S1 and S2 are “ON” and S3 and S4 are “OFF”, when the capacitance between the second metal wiring and the third metal wiring is measured, a performance with a capacitance density of 8 fF / μm ² is obtained. It was. On the other hand, when S1, S2, S3, and S4 are all set to “OFF” and the capacitance value is measured between the third metal wiring and the fourth metal wiring, the performance of the capacitance density ² fF / μm ² and a very large breakdown voltage was gotten. On the other hand, when S1 is “OFF”, S2 is “ON”, S3 is “OFF”, S4 is “ON”, or S4 is “OFF”, and S3 is “ON”, the capacity density is 4 fF / A performance of μm ² was obtained. In addition, in the semiconductor device having the MIM capacitor formed as described above, the parasitic capacitance between the first adjacent metal wirings and the short yield were the same as those in Example 7.

That is, according to the embodiment of the present invention, a first intermediate layer made of a 100 nm-thickness silicon oxide layer having an opening is formed on the lower electrode, and a capacitor film and an upper electrode are formed so as to cover the opening. Then, the upper electrode and the capacitor film are processed so as to completely include the opening, and a second intermediate layer made of a 100 nm-thickness silicon oxide layer having an opening is formed on the lower electrode, and the opening Leakage current by forming the second capacitive film and the second upper electrode so as to cover the portion, and processing the second upper electrode and the second capacitive film so as to completely include the opening. It is possible to simultaneously reduce the parasitic capacitance of the wiring layer corresponding to the lower electrode of this MIM capacitor and to improve the short-circuit yield between the MIM capacitor, which can obtain a high capacitance density while minimizing the increase and breakdown voltage breakdown. Semiconductor device But the possible formation.
In this embodiment, unlike the seventh embodiment, separate lead wires are provided for the processed upper electrode, the processed second upper electrode, and the first metal wiring. As a result, it is possible to realize a plurality of capacitance values in the same MIM capacitor structure by changing the connection method between the lead wires.

In this embodiment, the “ON / OFF” state of each of the switches S1, S2, S3, and S4 is controlled by connecting / disconnecting the metal wiring, but the switch control method is not limited to this method. It can also be controlled by providing an electrically controllable switch such as a crossbar or using a fuse element or the like.
In the present embodiment, a structure in which MIM capacitors are stacked in two stages in the vertical direction is used. However, the number of stacked layers may be three or more as required.
In this example, tantalum oxide having a film thickness of 50 nm was used as the capacitor film and the second capacitor film, but the film thickness and material are not limited thereto. Since the capacitance density increases in inverse proportion to the thickness of the capacitance film, the smaller the thickness, the better from the viewpoint of capacitance density. However, since the dielectric breakdown voltage also decreases as the film thickness is reduced, there is a thin film limit depending on the voltage used. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Further, in this embodiment, a single-layer insulating film is used as the capacitive film. However, this capacitive film can have a laminated structure as required. For example, a band gap is formed above and below the tantalum oxide film. Leakage current density can be reduced by sandwiching with large aluminum oxide or the like. Further, the capacitor film and the second capacitor film do not necessarily need to use the same material, the same manufacturing method, and the same film thickness, and can be used properly according to the application.

  In this embodiment, a silicon oxide film having a thickness of 100 nm is mainly used as the first intermediate layer and the second intermediate layer. However, the present invention is not limited to this thickness and material. As described above, the first intermediate layer and the second intermediate layer have suitable film thickness ranges, and good characteristics of about 50 nm to 200 nm are obtained in the range where the current manufacturing apparatus is used. If a method with better step coverage is adopted as a method of forming the capacitive film, it can be easily predicted that the upper limit of the film thickness extends to a region of 200 nm or more, but there is little merit in increasing this film thickness unnecessarily. Further, although silicon oxide formed by plasma CVD is used as a material for the first intermediate layer and the second intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. When silicon nitride, silicon oxynitride, or aluminum oxide is used, it can be used as a light-absorbing layer at the time of dry etching or at the time of lithography, but it has the disadvantage that the parasitic capacitance of the wiring increases due to its high dielectric constant. . On the other hand, silicon carbide, nitrogen-containing silicon carbide, SiOC film, and the like have a low relative dielectric constant and are effective in reducing parasitic capacitance, but have a drawback that leakage current is difficult to reduce. Furthermore, in this embodiment, single-layer silicon oxide is used as the first intermediate layer and the second intermediate layer, but it is also possible to form a laminated structure including a plurality of layers. Specifically, in the structure where silicon nitride is used as the layer in contact with the lower electrode and silicon oxide is used as the upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer and the second intermediate layer is controlled. It becomes easy to do. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility. In this embodiment, the first intermediate layer and the second intermediate layer use the same film thickness, the same material, and the same manufacturing method. However, the effectiveness of the present invention is not limited to this.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the upper electrode and the second upper electrode, but the thickness and material are not limited to this. If the film thickness is too thin, there is a risk of breaking through the electrode when the connection hole is opened and damaging the capacitive film located below. On the other hand, if the film thickness is too thick, a resistor is inserted in series with the MIM capacitor, so that the high frequency characteristics may be deteriorated. In the range where titanium nitride is used, about 50 nm to 100 nm is preferable. In addition to titanium nitride, tantalum, tungsten, and metals mainly composed of nitrides thereof, aluminum, and alloys thereof can be used as electrode materials.

  Furthermore, titanium nitride is used as the barrier metal used for the first, second, and third metal wirings. As described above, a metal containing tantalum, tungsten, and its nitride as a main component is used in addition to titanium nitride. It is also possible to use a structure that does not use a barrier metal as long as the reliability is sufficient. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.

In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When such a low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film includes a laminated film composed of the plurality of insulating films. Further, when such a low-k material is used, it is often difficult to apply the tungsten CVD method due to restrictions such as process temperature. In this case, it is preferable to bury the connection hole with aluminum or the like.
In this embodiment, the aluminum wiring obtained by processing the second, third and fourth metal wirings by the dry etching method is used. However, if necessary, aluminum wiring or copper wiring using the damascene method can be used. It is. At this time, it is possible to reduce the number of processes by applying a dual damascene method in which connection holes are formed at the same time.

This embodiment is one of application examples using the manufacturing process of the semiconductor device shown in Embodiment 3, and the steps for forming two layers of MIM capacitors in the vertical direction are shown in FIG. 29 and FIG. This will be described using a cross-sectional view. In the following, description will be given in order. 29 and 30 are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. In the following, description will be given in order.
As shown in FIG. 29A, a 50-nm-thick titanium nitride film, a 400-nm-thick aluminum alloy, and a 50-nm-thick titanium nitride film are formed on a substrate 100 on which a semiconductor element is formed by sputtering. After that, the first barrier metal layer 205, the first aluminum layer 206, the first barrier metal layer 207 constituted by the first barrier metal layer 205, and the eighth barrier metal layer 207 using the lithography method and the dry etching method are used. A fourth metal wiring 703 constituted by the barrier metal layer 223, the fourth aluminum layer 224, and the ninth barrier metal layer 225 was formed. Next, after a first interlayer insulating layer 304 made of a silicon oxide film having a thickness of 1000 nm is formed by using a plasma CVD method, the first interlayer insulating layer 304 is planarized by using a chemical mechanical polishing method. It was. Next, using lithography and dry etching, an opening is provided so that the first metal wiring 700 and the fourth metal wiring 703 in a desired region are exposed, and the opening is made of tungsten. One conductive plug 250 and a second conductive plug 251 were formed. Next, a titanium nitride film having a thickness of 50 nm is formed by sputtering so as to cover the first conductive plug 250 and the second conductive plug 251, and the lithography method and the dry etching method are combined. The lower electrode 211 processed so as to cover the first conductive plug 250 was formed. Thereafter, a silicon nitride film having a thickness of 100 nm is formed by using a plasma CVD method, and then processed by a lithography method and a dry etching method so that the processed lower electrode 211 has an opening 500. A layer 303 was formed (FIG. 29A).

Next, a tantalum oxide film with a thickness of 50 nm and a titanium nitride film with a thickness of 50 nm are formed so as to cover the opening 500 and be in contact with the processed lower electrode 211, and then a lithography method and a dry etching method are combined. A processed capacitive film 401 made of tantalum oxide having a film thickness of 50 nm and a processed upper electrode 204 were formed so as to include at least the opening 500 inside (FIG. 29B).
Next, a silicon oxide film having a thickness of 100 nm is formed on the entire surface by plasma CVD, and then an opening 502 including at least part of the opening 500 is formed using lithography and dry etching, and Then, a processed second intermediate layer 308 having an opening with respect to the processed upper electrode 204 was formed (FIG. 29C).
Next, after forming tantalum oxide having a thickness of 50 nm and titanium nitride having a thickness of 50 nm on the entire surface, a combination of a lithography method and a dry etching method is performed, and at least the opening 502 is completely included in the upper portion. A processed second capacitor film 404 made of tantalum oxide having a film thickness of 50 nm and a processed second upper electrode 219 were formed so that a part of the surface of the electrode 204 was exposed (FIG. 30A). .
Next, after removing the processed first intermediate layer in the region where at least the second conductive plug 251 is formed by using a lithography method and a dry etching method, a film thickness of 50 nm is formed by sputtering on the entire surface. After forming a titanium nitride film, an aluminum alloy film having a thickness of 400 nm, and a titanium nitride film having a thickness of 50 nm, the second conductive plug 251 and the processed second upper electrode are formed using a lithography method and a dry etching method. A third barrier layer 208 made of a titanium nitride film having a thickness of 50 nm and electrically connected to the second layer 209; a second aluminum layer 209 made of an aluminum alloy having a thickness of 400 nm; and a fourth barrier layer made of a titanium nitride film having a thickness of 50 nm. 50 nm thick nitride electrically connected to the second metal wiring 701 composed of the barrier metal layer 210 and the processed upper electrode 204 A third metal comprising a sixth barrier layer 208 made of a tantalum film, a third aluminum layer 209 made of an aluminum alloy with a thickness of 400 nm, and a seventh barrier metal layer 210 made of a titanium nitride film with a thickness of 50 nm A wiring 702 was formed (FIG. 30B).

The MIM capacitor formed in this way is electrically equivalent to the configuration shown in FIG. The third metal wiring 702 of this embodiment corresponds to the terminal 1, the second and fourth metal wirings (701 and 703) correspond to the terminal 2, and the first metal wiring 700 corresponds to the terminal 3. That is, as in the eighth embodiment, it is possible to realize a plurality of capacitance densities with the same MIM capacitor by changing the wiring connection method.
The performance and reliability of the MIM capacitor in the semiconductor device having the MIM capacitor thus formed were examined. In the structure in which S1 and S2 are “ON” and S3 and S4 are “OFF”, when the capacitance between the first metal wiring and the third metal wiring is measured, a performance with a capacitance density of 8 fF / μm ² is obtained. It was. On the other hand, when S1, S2, S3, and S4 are all set to “OFF” and the capacitance value is measured between the first metal wiring and the fourth metal wiring, the performance of the capacitance density of ² fF / μm ² and a very large breakdown voltage was gotten. On the other hand, when S1 is “OFF”, S2 is “ON”, S3 is “OFF”, S4 is “ON”, or S4 is “OFF”, and S3 is “ON”, the capacity density is 4 fF / A performance of μm ² was obtained. In addition, in the semiconductor device having the MIM capacitor formed as described above, the parasitic capacitance between the adjacent first metal wirings and the short yield were the same as those in Example 8.

  That is, according to the embodiment of the present invention, the first electrode is formed of a 100 nm-thickness silicon nitride layer having a lower electrode formed so as to cover the connection hole opened in the lower metal wiring and having an opening on the lower electrode. An intermediate layer is formed, a capacitive film and an upper electrode are formed so as to cover the opening, and the upper electrode, the capacitive film, and the first intermediate layer are processed so as to completely include the opening, and the lower part is processed. A second intermediate layer made of a silicon oxide layer having a thickness of 100 nm having an opening is formed on the electrode, a second capacitor film and a second upper electrode are formed so as to cover the opening, and the opening By processing the second upper electrode and the second capacitive film so as to completely include the portion, an MIM capacitor capable of obtaining a high capacitance density while minimizing an increase in leakage current and a decrease in dielectric breakdown voltage is obtained. A semiconductor device can be formed

Unlike the third embodiment, this embodiment has a structure in which MIM capacitors are stacked in two stages in the vertical direction. Although the number of manufacturing steps increases, a plurality of capacitance densities and breakdown breakdown voltages can be realized by greatly improving the capacitance density per area occupied by the MIM capacitor or changing the connection of the wiring.
In the present embodiment, a structure in which MIM capacitors are stacked in two stages in the vertical direction is used. However, the number of stacked layers may be three or more as required.
In this embodiment, the “ON / OFF” state of each of the switches S1, S2, S3, and S4 is controlled by connecting / disconnecting the metal wiring, but the switch control method is not limited to this method. It can also be controlled by providing an electrically controllable switch such as a crossbar or using a fuse element or the like.
In this example, tantalum oxide having a film thickness of 50 nm was used as the capacitor film and the second capacitor film, but the film thickness and material are not limited thereto. Since the capacitance density increases in inverse proportion to the thickness of the capacitance film, the smaller the thickness, the better from the viewpoint of capacitance density. However, since the dielectric breakdown voltage also decreases as the film thickness is reduced, there is a thin film limit depending on the voltage used. In addition to tantalum oxide, it is possible to use hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, a mixture thereof, and a compound in which nitrogen or the like is mixed therein as a material for the capacitor film. It is also possible to use a ferroelectric material such as PZT, STO, BST. Further, in this embodiment, a single-layer insulating film is used as the capacitive film. However, this capacitive film can have a laminated structure as required. For example, a band gap is formed above and below the tantalum oxide film. Leakage current density can be reduced by sandwiching with large aluminum oxide or the like. Further, the capacitor film and the second capacitor film do not necessarily need to use the same material, the same manufacturing method, and the same film thickness, and can be used properly according to the application.

  In this embodiment, a silicon nitride film with a thickness of 100 nm is used as the first intermediate layer, and a silicon oxide film with a film thickness of 100 nm is used as the second intermediate layer. However, the thickness and material are not limited to these. . As described above, the first intermediate layer and the second intermediate layer have suitable film thickness ranges, and good characteristics of about 50 nm to 200 nm are obtained in the range where the current manufacturing apparatus is used. If a method with better step coverage is adopted as a method of forming the capacitive film, it can be easily predicted that the upper limit of the film thickness extends to a region of 200 nm or more, but there is little merit in increasing this film thickness unnecessarily. Further, although silicon oxide or silicon nitride formed by plasma CVD is used as the material of the intermediate layer, it does not hinder the selection of other materials as long as it meets the original purpose. Specifically, a low-k film typified by silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, SiOC, or the like can be used. When silicon oxynitride or aluminum oxide is used, it can be used as an improvement in the selection ratio at the time of dry etching or as a light absorption layer at the time of lithography, but has a disadvantage that the parasitic capacitance of the wiring increases due to its high relative dielectric constant. On the other hand, silicon carbide, nitrogen-containing silicon carbide, SiOC film, and the like have a low relative dielectric constant and are effective in reducing parasitic capacitance, but have a drawback that leakage current is difficult to reduce. Furthermore, in this embodiment, single-layer insulating films are used as the first intermediate layer and the second intermediate layer, but it is also possible to form a laminated structure including a plurality of layers. Specifically, in the structure where silicon nitride is used as the layer in contact with the lower electrode and silicon oxide is used as the upper layer, the taper angle of the cross section of the opening provided in the first intermediate layer and the second intermediate layer is controlled. It becomes easy to do. When the controllability of the taper angle is good, coverage of the capacitive film is easily improved, which is effective in improving the breakdown voltage. Further, if the controllability of the taper angle is good, the controllability of the opening area of the MIM capacitor is improved, so that there is an advantage that a desired capacitance value can be obtained with good reproducibility. In the present embodiment, the first intermediate layer and the second intermediate layer use the same film thickness and the same manufacturing method, but the effectiveness of the present invention is not limited to this.

  In this embodiment, titanium nitride having a thickness of 50 nm is used as the upper electrode and the second upper electrode, but the thickness and material are not limited to this. If the film thickness is too thin, there is a risk of breaking through the electrode when the connection hole is opened and damaging the capacitive film located below. On the other hand, if the film thickness is too thick, a resistor is inserted in series with the MIM capacitor, so that the high frequency characteristics may be deteriorated. In the range where titanium nitride is used, about 50 nm to 100 nm is preferable. In addition to titanium nitride, tantalum, tungsten, and metals mainly composed of nitrides thereof, aluminum, and alloys thereof can be used as electrode materials. Furthermore, titanium nitride is used as the barrier metal used for the first, second, third, and fourth metal wirings. As described above, tantalum, tungsten, and nitrides thereof are the main components in addition to titanium nitride. It is also possible to use a metal, and it is also possible to use a structure that does not use a barrier metal if there is a margin in reliability. In addition, there is no problem in forming a laminated structure including a plurality of layers for both the upper electrode and the barrier metal.

  In this embodiment, the process using mainly a silicon oxide film as the first interlayer insulating film has been described as an example. However, the present invention is not limited to this material, and a low-k material capable of reducing the parasitic capacitance of the wiring. It is also possible to use. As a Low-k material, a SiOC film (silicon oxide film containing carbon) represented by black diamond (registered trademark: Applied Materials), and SiLK (registered trademark: manufactured by Dow Chemical) are representative. Such organic films, Low-k materials in which voids are introduced, fluorine-containing silicon oxide films, and the like can be used. When such a low-k material is used, some kind of protective insulating film is required. Therefore, the first interlayer insulating film includes a laminated film composed of the plurality of insulating films.

In this embodiment, the aluminum wiring obtained by processing the first and fourth metal wirings by the dry etching method is used, but it is also possible to use an aluminum wiring or a copper wiring using the damascene method if necessary.
Further, in this embodiment, for the sake of simplification of the drawings, the description was made in the form of connection with a single connection hole. However, as long as electrical connection between the two is ensured, the number, position, and shape of the connection holes are It can be arbitrarily selected. Needless to say, the larger the connection hole, the better in order to reduce the parasitic resistance inserted in series with the MIM capacitor.
In this embodiment, the connection hole is completely filled with the first conductive plug 250 and the second conductive plug 251 made of tungsten. However, the effectiveness of the present invention is in this structure and material. It is not limited. In addition to tungsten, it is also possible to use a conductor mainly composed of aluminum or copper as a material for the conductive plug. Further, the surface of the conductive plug does not necessarily need to coincide with the surface of the first interlayer insulating film 304, and dents and bumps that do not affect the reliability are processes for forming the lower electrode and the capacitor film. It is possible.

FIG. 3 is a schematic cross-sectional view of the relevant part showing a manufacturing step of a semiconductor device according to the invention in Example 1. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device based on the prior art example 1, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention based on the prior art example 1, respectively. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention based on the prior art example 2, respectively. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention based on the prior art example 3, respectively. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention based on the prior art example 3, respectively. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention in Example 1, respectively. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention in Example 1, respectively. 1 is a schematic plan layout diagram of the present invention in Example 1. FIG. FIG. 3 is a schematic cross-sectional view of the relevant part of the BB ′ portion of the semiconductor device of the invention in Example 1; 6 is a table comparing parasitic capacitance between adjacent metal wirings in the conventional example and Example 1. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention in Example 2, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 2, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 3, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 3, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 4, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 4, respectively. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention in Example 5, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 5, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 6, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention in Example 6, respectively. FIG. 9 is a schematic plan layout diagram of the present invention in Example 6. FIG. 10 is a schematic cross-sectional view of the relevant part of the BB ′ portion of the semiconductor device of the invention in Example 6. FIG. 10 is a schematic cross-sectional view of the relevant part of the CC ′ portion of the semiconductor device of the invention in Example 6. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention based on the prior art example 7, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention based on the prior art example 7, respectively. It is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention based on the prior art example 8. FIG. (A) is the electrical equivalent circuit of the semiconductor device of this invention based on the prior art example 8, (b) is a table | surface which shows the capacitance value implement | achieved according to each switch state. (A) thru | or (c) are the principal part cross-sectional schematic diagrams of the manufacturing process of the semiconductor device of this invention based on the prior art example 9, respectively. (A) And (b) is a principal part cross-sectional schematic diagram of the manufacturing process of the semiconductor device of this invention based on the prior art example 9, respectively.

Explanation of symbols

100: a substrate on which a semiconductor element is formed,
200: First barrier metal film,
201 ... first aluminum film,
202 ... the second barrier metal film,
203 ... upper electrode,
204 ... processed upper electrode,
205 ... first barrier metal layer,
206 ... first aluminum layer,
207 ... second barrier metal layer,
208 ... a third barrier metal layer,
209 ... second aluminum layer,
210 ... Fourth barrier metal layer,
211 ... Processed lower electrode,
212 ... Third barrier metal film,
213 ... Second aluminum film,
214 ... Fourth barrier metal film,
215 ... the fifth barrier metal layer,
216 ... first copper layer,
217 ... Processed resistor layer,
218 ... second upper electrode,
219 ... Processed second upper electrode,
220 ... Sixth barrier metal layer,
221 ... a third aluminum layer,
222 ... seventh barrier metal layer,
223 ... an eighth barrier metal layer,
224 ... a fourth aluminum layer,
225 ... ninth barrier metal layer,
250 ... first conductive plug,
251 ... Second conductive plug,
252 ... a third conductive plug,
300 ... first intermediate layer,
301 ... Hard mask,
302 ... processed hard mask,
303 ... processed first intermediate layer,
304 ... first interlayer insulating layer,
305 ... Etch stopper layer,
306 ... Second interlayer insulating film,
307 ... second intermediate layer,
308 ... the processed second intermediate layer,
400 ... capacitive membrane,
401 ... Processed capacitive film,
402: Capacitance film under the resistor layer,
403 ... second capacitive membrane,
404 ... the processed second capacitive film,
500 ... first opening,
501 ... an opening formed in the first interlayer insulating layer;
502 ... second opening,
600: First processing resist,
601 ... Second processing resist,
602 ... Third processing resist,
700 ... first metal wiring,
701 ... Second metal wiring,
702 ... Third metal wiring,
703 ... Fourth metal wiring,
750 ... lower layer wiring connected to the MIM capacitor,
751... Upper layer wiring connected to the MIM capacitor,
752 ... lower layer wiring adjacent to the MIM capacitor,
753 ... Upper layer wiring adjacent to the MIM capacitor,
754 ... the upper electrode of the MIM capacitor,
755 ... an opening formed in the first intermediate layer,
756... Connection hole for connecting the upper layer wiring 751 and the upper electrode 754,
757... Connection hole for connecting the upper layer wiring 753 and the lower layer wiring 752;
758 ... first intermediate layer,
759 ... lower layer wiring connected to the resistor,
760 ... resistor,
761... First intermediate layer covering the resistor,
762 ... a connection hole for connecting the resistor 760 and the lower layer wiring 759,
800: Etching residue.

Claims (21)

A first electrode formed on a semiconductor substrate;
An intermediate insulating film provided in the vicinity of the periphery of the upper surface of the first electrode and having an opening in the vicinity of the center;
A capacitive insulating film formed on the intermediate insulating film and in the opening;
A second electrode formed on the capacitive insulating film,
An end of the capacitive insulating film and an end of the second electrode are provided at positions not exceeding the end of the intermediate insulating film.   The semiconductor device according to claim 1, wherein a thickness of the intermediate insulating film is smaller than any width of the opening. Conductor wiring provided on the semiconductor substrate;
An interlayer insulating film having a through hole formed on the conductor wiring;
A first electrode formed on the interlayer insulating film so as to be in contact with the conductive plug embedded in the through hole;
An intermediate insulating film provided so as to cover the vicinity of the upper surface periphery of the first electrode, and having an opening in the vicinity of the center;
A capacitive insulating film formed to cover the intermediate insulating film and the opening;
A second electrode formed on the capacitive insulating film,
The width of the opening is narrower than the width of the first electrode, the width of the intermediate insulating film is larger than the width of the first electrode, and the width of the second electrode and the capacitive insulating film is the opening. A semiconductor device having a width greater than that of the intermediate insulating film and less than or equal to the width of the intermediate insulating film. A first electrode formed on a semiconductor substrate;
An intermediate insulating film provided in the vicinity of the periphery of the upper surface of the first electrode and having an opening in the vicinity of the center;
A capacitive insulating film formed on the intermediate insulating film and in the opening;
A second electrode formed on the capacitive insulating film;
An interlayer insulating film deposited to cover the second electrode and the intermediate insulating film,
A capacitive element comprising the capacitive insulating film sandwiched between the first and second electrodes;
A semiconductor device comprising: a resistance element having the second electrode as a resistance portion and having both terminals connected to a conductive plug layer embedded in a through hole formed in the interlayer insulating film.   The semiconductor device according to claim 1, wherein the intermediate insulating film has a thickness greater than 10 nm and less than 300 nm.   The intermediate insulating film is mainly composed of an insulating film selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, and carbon-containing silicon oxide. 4. The semiconductor device according to any one of 3.   4. The semiconductor device according to claim 1, wherein the intermediate insulating film has a laminated structure including at least two types of insulating films having different etching selection ratios. 5.   4. The capacitive insulating film is mainly composed of an insulating film selected from tantalum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, PZT, STO, and BST. The semiconductor device as described in any one.   The first electrode and the second electrode are mainly composed of a metal selected from titanium, tantalum, tungsten, molybdenum, and nitrides thereof, or aluminum and alloys thereof. The semiconductor device as described in any one. Forming a first conductor film on a semiconductor substrate;
Forming an intermediate insulating film on the first conductor film;
Removing a desired region of the intermediate insulating film so that the first conductor film is exposed, and providing an opening;
Forming a capacitive insulating film on the opening and the intermediate insulating film, and forming a second conductor film on the capacitive insulating film;
Depositing an inorganic film on the second conductor film;
Forming a first processing mask made of the inorganic film on a region including the opening, and patterning the second conductor film and the capacitive insulating film using the first processing mask;
A second processing mask made of a photosensitive film having a shape different from that of the first processing mask is formed, and the second conductor film and the capacitive insulating film processed by the first processing mask and the first And a step of etching the intermediate insulating film and the first conductor film using the region covered with the processing mask of 2 as an etching protection mask. Forming a conductive wiring film on a semiconductor substrate;
Forming an interlayer insulating film on the conductor wiring film;
Removing a desired region of the interlayer insulating film so as to expose the conductor wiring film, and providing a through hole;
Embedding a conductive plug electrically connected to the conductor wiring film in the through hole;
Forming a first conductor film so that one end of the conductive plug contacts;
Forming an intermediate insulating film so as to cover the first conductor film formed so as to cover the through hole;
Forming an opening in the intermediate insulating film such that a part of the first conductor film is exposed;
Forming a capacitive insulating film so as to cover the opening, and forming a second conductor film on the capacitive insulating film;
And a step of etching the second conductor film and the capacitor insulating film using a processing mask formed on the second conductor film so as to include the opening as a protective mask for etching. Production method. Forming a first conductor film on a semiconductor substrate;
Forming an intermediate insulating film on the first conductor film;
Removing a desired region of the intermediate insulating film so that the first conductor film is exposed, and providing an opening;
Forming a capacitive insulating film on the opening and the intermediate insulating film, and forming a second conductor film on the capacitive insulating film;
A first processing mask made of a photosensitive film is formed on the second conductor film on the region including the opening, and the second conductor film and the capacitive insulating film are formed using the first processing mask. Patterning, and
A second processing mask made of a photosensitive film having a shape different from that of the first processing mask is formed, and the second conductor film and the capacitive insulating film processed by the first processing mask and the first And a step of etching the intermediate insulating film and the first conductor film using the region covered with the processing mask of 2 as an etching protection mask.   13. The method of manufacturing a semiconductor device according to claim 10, wherein the thickness of the intermediate insulating film is greater than 10 nm and less than 300 nm.   11. The intermediate insulating film is mainly composed of an insulating film selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-containing silicon carbide, aluminum oxide, and carbon-containing silicon oxide. 12. A method for manufacturing a semiconductor device according to any one of 12 above.   13. The method of manufacturing a semiconductor device according to claim 10, wherein the intermediate insulating film has a laminated structure of two or more types of insulating films having different etching selectivity ratios.   13. The capacitive insulating film is mainly composed of an insulating film selected from tantalum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, aluminum oxide, PZT, STO, and BST. The manufacturing method of the semiconductor device as described in any one.   11. The first conductor film and the second conductor film are mainly composed of a metal selected from titanium, tantalum, tungsten, molybdenum and nitrides thereof, or aluminum and alloys thereof. A method for manufacturing a semiconductor device according to any one of claims 1 to 12.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the conductor wiring film is mainly composed of a metal selected from tungsten, titanium, molybdenum and nitrides thereof, or aluminum and alloys thereof.   The conductor wiring film is mainly composed of aluminum and its alloy, and its upper surface and / or lower surface is covered with a layer whose main component is a metal selected from tungsten, titanium, molybdenum, and nitrides thereof. The method of manufacturing a semiconductor device according to claim 11, wherein:   The semiconductor device manufacturing method according to claim 11, wherein the conductor wiring film is mainly composed of a metal selected from tungsten, titanium, molybdenum, and nitrides thereof, or aluminum, copper, and alloys thereof. Method. The conductor wiring film is mainly composed of a metal selected from aluminum, copper, and alloys thereof, and at least one surface thereof is covered with a layer of tungsten, titanium, molybdenum, and a nitride thereof. A method for manufacturing a semiconductor device according to claim 11.

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