CN114639655B - Semiconductor device structure and preparation method thereof - Google Patents

Semiconductor device structure and preparation method thereof Download PDF

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Publication number
CN114639655B
CN114639655B CN202210536819.4A CN202210536819A CN114639655B CN 114639655 B CN114639655 B CN 114639655B CN 202210536819 A CN202210536819 A CN 202210536819A CN 114639655 B CN114639655 B CN 114639655B
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layer
dielectric layer
metal
etching stop
interconnection
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CN114639655A (en
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郭廷晃
郑志成
林智伟
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Hefei Xinjing Integrated Circuit Co Ltd
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Hefei Xinjing Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Abstract

The invention provides a semiconductor device structure and a preparation method thereof. The semiconductor device structure includes: an interconnect conductive layer having an opening therein; a first etch stop layer on the interconnect conductive layer; and the capacitor is positioned on the first etching stop layer, is positioned right above the opening and has a distance with the edge of the opening. According to the semiconductor device structure, the capacitor is arranged right above the opening in the interconnection conductive layer and has a distance with the edge of the opening, and under the condition, even if the interconnection conductive layer deforms to generate a bulge under the influence of temperature, stress and the like, the capacitor cannot be connected with the interconnection conductive layer to cause short circuit; even if the interconnection plugs of the upper electrode plate and the lower electrode plate of the connecting capacitor penetrate through the layer where the interconnection conductive layer is located, the capacitor is not connected with the interconnection conductive layer to cause short circuit due to the fact that the opening is arranged right below the capacitor, so that the failure number of devices can be reduced, the performance of the devices can be improved, and the yield of products can be improved.

Description

Semiconductor device structure and preparation method thereof
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a semiconductor device structure and a preparation method thereof.
Background
With the development of semiconductor technology, there is an increasing interest in the adverse effects (such as device short circuits caused by defects) and corresponding improvement methods caused by the design and manufacturing processes of semiconductor device structures. Generally, the conductive layer in the device is mostly made of metal materials such as aluminum, copper or silver, and these metal materials are deformed by the influence of temperature or stress, etc., so that the conductive layer is in contact with other elements, causing a short circuit inside the device; or some through hole processes are not mature, so that the through holes penetrate through the etching stop layer and then are connected with the conducting layer, short circuit occurs between device structures, and device failure is caused.
Disclosure of Invention
In order to solve the technical problems, the invention designs a semiconductor device structure and a preparation method thereof, which can avoid short circuit between device structures, improve the device performance and reduce the failure rate of devices.
The present invention provides a semiconductor device structure, comprising:
an interconnect conductive layer having an opening therein;
a first etch stop layer on the interconnect conductive layer;
and the capacitor is positioned on the first etching stop layer, is positioned right above the opening and has a distance with the edge of the opening.
The semiconductor device structure of the invention is different from the structure of the related technology, and the position relation of the interconnection conductive layer and the capacitor is set, namely the capacitor is arranged right above the opening in the interconnection conductive layer and has a distance with the edge of the opening, under the condition, even if the interconnection conductive layer deforms to generate a bulge under the influence of temperature, stress and the like, the capacitor is not connected with the interconnection conductive layer to cause short circuit; even if the interconnection plugs of the upper electrode plate and the lower electrode plate which are connected with the capacitor penetrate through the layer where the interconnection conductive layer is located, the capacitor is not connected with the interconnection conductive layer to cause short circuit due to the fact that the opening is arranged right below the capacitor, so that the failure number of devices can be reduced, the performance of the devices is improved, and the yield of products is improved.
In one embodiment, the capacitor includes:
the first electrode plate is positioned on the surface of the interconnection conductive layer;
the capacitor dielectric layer is positioned on the surface of the first electrode plate far away from the interconnection conductive layer;
the second electrode plate is positioned on the surface of the capacitance dielectric layer far away from the first electrode plate;
and the first insulating layer is positioned on the surface of the second electrode plate far away from the capacitor dielectric layer.
In one embodiment, the semiconductor device structure further comprises:
the first metal interlayer dielectric layer is positioned on the surface of the first etching stop layer, which is far away from the interconnection conductive layer;
the second metal interlayer dielectric layer is positioned on the surface of the first metal interlayer dielectric layer, which is far away from the first etching stop layer, and covers the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer;
the second etching stop layer is positioned on the surface of the second metal interlayer dielectric layer far away from the first metal interlayer dielectric layer;
the third metal interlayer dielectric layer is positioned on the surface of the second etching stop layer far away from the second metal interlayer dielectric layer;
the third etching stop layer is positioned on the surface of the third metal interlayer dielectric layer far away from the second etching stop layer;
the fourth metal interlayer dielectric layer is positioned on the surface of the third etching stop layer far away from the third metal interlayer dielectric layer;
and the second insulating layer is positioned on the surface of the fourth metal interlayer dielectric layer far away from the third etching stop layer.
In one embodiment, the semiconductor device structure further comprises:
a first interconnection plug penetrating the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer, the second inter-metal dielectric layer and the first insulating layer in a thickness direction of the semiconductor device structure, and connected to the second electrode plate;
a second interconnection plug penetrating the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer and the second inter-metal dielectric layer in the thickness direction of the semiconductor device structure and connected to the first electrode plate;
and a third interconnection plug which penetrates the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer, the second inter-metal dielectric layer, the first inter-metal dielectric layer and the first etching stop layer in the thickness direction of the semiconductor device structure and is connected with the interconnection conductive layer.
In one embodiment, the semiconductor device structure further comprises a dummy conductive layer located within the opening with a spacing from the interconnect conductive layer.
The invention also provides a preparation method of the semiconductor device structure, which comprises the following steps:
forming a layer of interconnect conductive material;
forming a first etch stop layer on the layer of interconnect conductive material;
forming a capacitor on the first etching stop layer;
etching the interconnection conductive material layer to form an interconnection conductive layer with an opening; the capacitor is located right above the opening and has a distance from the edge of the opening.
According to the preparation method of the semiconductor device structure, the position relation between the interconnection conducting layer with the opening and the capacitor is set through the preparation process, namely the capacitor is arranged right above the opening in the interconnection conducting layer and has a distance with the edge of the opening, and even if the interconnection conducting layer deforms to generate a bulge under the influence of temperature, stress and the like to generate a bulge, the capacitor cannot be connected with the interconnection conducting layer to cause short circuit; even if the interconnection plugs of the upper electrode plate and the lower electrode plate which are connected with the capacitor penetrate through the layer where the interconnection conductive layer is located, the capacitor is not connected with the interconnection conductive layer to cause short circuit due to the fact that the opening is arranged right below the capacitor, so that the failure number of devices can be reduced, the performance of the devices is improved, and the yield of products is improved.
In one embodiment, before forming the capacitor on the first etch stop layer, the method further includes:
and forming a first metal interlayer dielectric layer on the surface of the first etching stop layer far away from the interconnection conducting layer.
In one embodiment, the forming a capacitor on the first etch stop layer comprises:
forming a laminated structure of a first electrode plate, a capacitor dielectric layer, a second electrode plate and a first insulating layer which are sequentially laminated on the surface of the first metal interlayer dielectric layer;
forming a second metal interlayer dielectric layer on the surface of the first metal interlayer dielectric layer far away from the first etching stop layer; the second metal interlayer dielectric layer covers the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer;
the surface of the first metal interlayer dielectric layer is formed with a laminated structure of a first electrode plate, a capacitor dielectric layer, a second electrode plate and a first insulating layer which are sequentially laminated, and the laminated structure comprises:
forming a first electrode material layer on the surface of the first metal interlayer dielectric layer far away from the first etching stop layer;
forming a capacitance dielectric material layer on the surface of the first electrode material layer far away from the first metal interlayer dielectric layer;
forming a second electrode material layer on the surface of the capacitance medium material layer far away from the first electrode material layer;
forming a first insulating material layer on the surface of the second electrode material layer far away from the capacitance medium material layer;
and etching the first insulating material layer, the second electrode material layer, the capacitor dielectric material layer and the first electrode material layer in sequence to form a laminated structure of the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer which are sequentially laminated.
In one embodiment, after forming the capacitor on the first etch stop layer, the method further includes:
forming a second etching stop layer on the surface of the second metal interlayer dielectric layer far away from the first metal interlayer dielectric layer;
forming a third metal interlayer dielectric layer on the surface of the second etching stop layer far away from the second metal interlayer dielectric layer;
forming a third etching stop layer on the surface of the third metal interlayer dielectric layer far away from the second etching stop layer;
forming a fourth metal interlayer dielectric layer on the surface of the third etching stop layer far away from the third metal interlayer dielectric layer;
forming a second insulating layer on the surface of the fourth metal interlayer dielectric layer far away from the third etching stop layer;
sequentially etching the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer, the second inter-metal dielectric layer and the first insulating layer along the thickness direction of the semiconductor device structure to form a first interconnection through hole;
sequentially etching the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer and the second inter-metal dielectric layer along the thickness direction of the semiconductor device structure to form a second interconnection through hole;
sequentially etching the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer, the second inter-metal dielectric layer, the first inter-metal dielectric layer and the first etching stop layer along the thickness direction of the semiconductor device structure to form a third interconnection through hole;
filling metal in the first interconnection hole, the second interconnection hole and the third interconnection through hole to form a first interconnection plug, a second interconnection plug and a third interconnection plug; the first interconnection plug is connected with the second electrode plate, the second interconnection plug is connected with the first electrode plate, and the third interconnection plug is connected with the interconnection conductive layer.
In one embodiment, the interconnect conductive material layer is etched to form an interconnect conductive layer having an opening, and a dummy conductive layer is formed in the opening, wherein the dummy conductive layer has a distance from the interconnect conductive layer.
Drawings
FIG. 1 is a flow chart illustrating the steps of a method of fabricating a semiconductor device structure in accordance with one embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of the structure obtained in step S102 in the method for manufacturing a semiconductor device structure in one embodiment of the present invention;
fig. 3 is a schematic cross-sectional structure view of the structure obtained in step S103 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure view of the semiconductor device structure obtained in step S104 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a structure resulting from formation of a first inter-metal dielectric layer on a surface of a first etch stop layer away from an interconnect conductive material layer in a method for fabricating a semiconductor device structure according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a capacitor formed on a surface of the first IMD layer remote from the first ESL in a method for fabricating a semiconductor device structure according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a step of forming a stacked structure of a first electrode plate, a capacitor dielectric layer, a second electrode plate and a first insulating layer, which are stacked in sequence, on a surface of a first inter-metal dielectric layer in a method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 8 is a schematic cross-sectional structure view of the structure obtained in step S701 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 9 is a schematic cross-sectional structure diagram of the structure obtained in step S702 in the method for manufacturing a semiconductor device structure in one embodiment of the present invention;
fig. 10 is a schematic cross-sectional structure diagram of the structure obtained in step S703 of the method for manufacturing a semiconductor device structure in one embodiment of the present invention;
fig. 11 is a schematic cross-sectional structure view of the structure obtained in step S704 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 12 is a schematic cross-sectional structure view of the structure obtained in step S705 in the method for manufacturing a semiconductor device structure in one embodiment of the present invention;
FIG. 13 is a flowchart illustrating steps subsequent to formation of a capacitor over the first etch stop layer in a method of fabricating a semiconductor device structure in accordance with one embodiment of the present invention;
fig. 14 is a schematic cross-sectional structure view of the structure obtained in step S1301 of the method for manufacturing a semiconductor device structure in an embodiment of the present invention;
fig. 15 is a schematic cross-sectional structure view of the structure obtained in step S1302 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 16 is a schematic cross-sectional structure view of the structure obtained in step S1303 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 17 is a schematic cross-sectional structure view of the structure obtained in step S1304 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 18 is a schematic cross-sectional structure diagram of the structure obtained in step S1305 in the manufacturing method of a semiconductor device structure in one embodiment of the present invention;
FIG. 19 is a flowchart illustrating a step in a method for fabricating a semiconductor device structure according to an embodiment of the present invention after forming a second insulating layer on a surface of the fourth IMD layer remote from the third ESL;
fig. 20 is a schematic cross-sectional structure view of the structure obtained in step S1901 in the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 21 is a schematic cross-sectional view of the structure obtained in step S1902 of the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 22 is a schematic cross-sectional structure view of the structure obtained in step S1903 of the method for manufacturing a semiconductor device structure according to an embodiment of the present invention;
fig. 23 is a schematic cross-sectional structure diagram of the structure obtained in step S1904 in the method for manufacturing a semiconductor device structure in one embodiment of the present invention;
fig. 24 is a schematic cross-sectional structure view of a semiconductor device structure in an embodiment of the present invention;
fig. 25 is a schematic cross-sectional structure of a semiconductor device structure in another embodiment of the present invention.
Description of the drawings:
1. an interconnect conductive layer; 11. a layer of interconnect conductive material; 12. a dummy conductive layer; 13. an opening; 2. a capacitor; 21. a first electrode plate; 211; a first electrode material layer; 22. a capacitor dielectric layer; 221. a layer of capacitive dielectric material; 23. a second electrode plate; 231. a second electrode material layer; 24. a first insulating layer; 241. a first layer of insulating material; 3. a first etch stop layer; 4. a first inter-metal dielectric layer; 5. a second inter-metal dielectric layer; 6. a second etch stop layer; 7. a third inter-metal dielectric layer; 8. a third etch stop layer; 9. a fourth inter-metal dielectric layer; 10. a second insulating layer; 100. a first interconnect via; 101. a first interconnect plug; 200. a second interconnect via; 201. a second interconnection plug; 300. a third interconnect via; 301. and a third interconnection plug.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
With the development of semiconductor technology, there is an increasing interest in the adverse effects (such as device short circuits caused by defects) and corresponding improvement methods caused by the design and manufacturing processes of semiconductor device structures. In general, the conductive layer in the device is mostly made of metal materials such as aluminum, copper or silver, and these metal materials are deformed by the influence of temperature or stress, etc., so that the conductive layer is in contact with other elements, which causes a short circuit inside the device; or some through hole processes are immature, so that the through holes penetrate through the etching stop layer and then are connected with the conducting layer, and short circuit occurs between device structures. Therefore, it is necessary to design some device structures and related manufacturing methods that can avoid short-circuit failure, so as to reduce the failure probability of the device, improve the performance of the device, and improve the yield of the product.
In order to solve the technical problems, the invention designs a semiconductor device structure and a preparation method thereof, which can avoid short circuit between device structures, improve the device performance and reduce the failure rate of devices.
As shown in fig. 1 and 2, the method for manufacturing a semiconductor device structure includes:
s101: forming an interconnect conductive material layer 11;
s102: forming a first etch stop layer 3 on the layer of interconnect conductive material 11; as shown in fig. 2;
s103: forming a capacitor 2 on the first etch stop layer 3; as shown in fig. 3;
s104: etching the interconnect conductive material layer 11 to form an interconnect conductive layer 1 having an opening 13; the capacitor 2 is positioned right above the opening 13 and has a distance with the edge of the opening 13; as shown in fig. 4.
According to the preparation method of the semiconductor device structure, the position relation between the interconnection conducting layer 1 with the opening and the capacitor 2 is set through a preparation process, namely the capacitor 2 is arranged right above the opening 13 in the interconnection conducting layer 1 and has a distance with the edge of the opening, and even if the interconnection conducting layer 1 deforms to generate a bulge under the influence of temperature, stress and the like to generate a bulge, the capacitor 2 cannot be connected with the interconnection conducting layer 1 to cause short circuit; even if the interconnection plugs of the upper and lower electrode plates of the capacitor 2 penetrate through the layer where the interconnection conductive layer 1 is located, the capacitor 2 is not connected with the interconnection conductive layer 1 to cause short circuit because the opening 13 is arranged right below the capacitor 2, so that the failure number of devices can be reduced, the performance of the devices can be improved, and the yield of products can be improved; the first etch stop layer 3 serves to protect the capacitor 2 during etching of the layer of interconnect conductive material 11.
The capacitor 2 is located directly above the opening 13, which means that the capacitor 2 is located vertically above the opening 13, that is, the orthographic projection of the capacitor 2 on the interconnecting conductive layer 1 is located in the opening 13.
In one embodiment, the material of the interconnect conductive material layer 11 may include, but is not limited to, at least one of copper, aluminum, silver, gold, tungsten, cobalt, rhodium, platinum, and molybdenum; the material of the interconnect conductive layer 1 may include, but is not limited to, at least one of copper, aluminum, silver, gold, tungsten, cobalt, rhodium, platinum, and molybdenum; in the present embodiment, the material of the interconnect conductive material layer 11 and the material of the interconnect conductive layer 1 are both preferably copper; the capacitor 2 may include, but is not limited to, a MIM (metal-insulator-metal) capacitor.
In one embodiment, the interconnecting conductive material layer 11 may be formed on a surface of a substrate, and the substrate may be formed therein to include a device region, and devices requiring electrical extraction may be formed in the device region, and the devices may include, but are not limited to, transistors, resistors, capacitors, and the like. After the interconnect conductive layer 1 is formed in step S104, the interconnect conductive layer 1 is electrically connected to the device. Note that if the interconnect conductive layer 1 is formed simultaneously with the formation of the dummy conductive layer, the dummy conductive layer is insulated from the device and is not electrically connected to the device.
In one embodiment, before forming the capacitor 2 on the first etch stop layer 3, a step of forming a first inter-metal dielectric layer 4 on a surface of the first etch stop layer 3 away from the interconnect conductive material layer 11 may be further included, as shown in fig. 5; the capacitor 2 is formed on the surface of the first intermetal dielectric layer 4 away from the first etch stop layer 3, as shown in fig. 6.
Specifically, the material of the first etch stop layer 3 may include, but is not limited to, SiN (silicon nitride), SiC (silicon carbide),At least one of SiCN (silicon carbide nitride), SiON (silicon oxynitride) and SiCO (silicon oxycarbide); the material of the first inter-metal dielectric layer 4 may include but is not limited to SiOCN (silicon oxycarbide), SiCO, SiO 2 At least one of (silicon dioxide), SiN and SiC.
In one embodiment, forming the capacitor 2 on the first etch stop layer 3 may include the steps of:
forming a laminated structure of a first electrode plate, a capacitor dielectric layer, a second electrode plate and a first insulating layer which are sequentially laminated on the surface of the first metal interlayer dielectric layer 4;
forming a second metal interlayer dielectric layer on the surface of the first metal interlayer dielectric layer 4 far away from the first etching stop layer; the second metal interlayer dielectric layer covers the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer.
The material of the first electrode plate may include, but is not limited to, at least one of Ti (titanium) and TiN (titanium nitride), and in this embodiment, the material of the first electrode plate is preferably TiN; the material of the capacitor dielectric layer may include, but is not limited to, Al 2 O 3 (aluminum oxide), HfO 2 (hafnium oxide) and ZrO 2 At least one of (zirconium dioxide); the material of the second electrode plate may include, but is not limited to, at least one of Ti and TiN, and in the present embodiment, the material of the second electrode plate is preferably TiN; the material of the first insulating layer may include, but is not limited to, SiON, SiN, SiO 2 、Si 3 N 4 、Ta 2 O 5 (tantalum pentoxide), TiO 2 (titanium oxide), Al 2 O 3 Or a high molecular polymer, in this embodiment, the material of the first insulating layer is preferably SiO 2 (ii) a The material of the second intermetal dielectric layer may include, but is not limited to, SiOCN, SiCO, SiO 2 SiN and SiC.
In one embodiment, as shown in fig. 7, a stacked structure of a first electrode plate 21, a capacitor dielectric layer 22, a second electrode plate 23 and a first insulating layer 24 stacked in sequence is formed on the surface of the first inter-metal dielectric layer 4, which includes the following steps:
s701: forming a first electrode material layer 211 on the surface of the first inter-metal dielectric layer 4 away from the first etch stop layer 3; as shown in fig. 8;
s702: forming a capacitance dielectric material layer 221 on the surface of the first electrode material layer 211 away from the first inter-metal dielectric layer 4; as shown in fig. 9;
s703: forming a second electrode material layer 231 on the surface of the capacitance dielectric material layer 221 away from the first electrode material layer 211; as shown in fig. 10;
s704: forming a first insulating material layer 241 on the surface of the second electrode material layer 231 away from the capacitor dielectric material layer 221; as shown in FIG. 11;
s705: sequentially etching the first insulating material layer 241, the second electrode material layer 231, the capacitor dielectric material layer 221 and the first electrode material layer 211 to form a stacked structure of the first electrode plate 21, the capacitor dielectric layer 22, the second electrode plate 23 and the first insulating layer 24 which are sequentially stacked; as shown in fig. 12.
The material of the first electrode material layer 211 may include, but is not limited to, at least one of Ti and TiN, and in this embodiment, the material of the first electrode material layer 211 is preferably TiN; the material of the capacitor dielectric material layer 221 may include, but is not limited to, Al 2 O 3 、HfO 2 And ZrO 2 At least one of (a); the material of the second electrode material layer 231 may include, but is not limited to, at least one of Ti and TiN, and in the present embodiment, the material of the second electrode material layer 231 is preferably TiN; the material of the first insulating material layer 241 may include, but is not limited to, SiON, SiN, SiO 2 、Si 3 N 4 、Ta 2 O 5 、TiO 2 、Al 2 O 3 Or a high molecular polymer, in this embodiment, the material of the first insulating material layer 241 is preferably SiO 2 。
In one embodiment, as shown in fig. 13, after forming the capacitor 2 on the first etch stop layer 3, the following steps may be further included:
s1301: forming a second etching stop layer 6 on the surface of the second inter-metal dielectric layer 5, which is far away from the first inter-metal dielectric layer 4; as shown in fig. 14;
s1302: forming a third inter-metal dielectric layer 7 on the surface of the second etching stop layer 6 far away from the second inter-metal dielectric layer 5; as shown in fig. 15;
s1303: forming a third etching stop layer 8 on the surface of the third inter-metal dielectric layer 7 far away from the second etching stop layer 6; as shown in fig. 16;
s1304: forming a fourth inter-metal dielectric layer 9 on the surface of the third etching stop layer 8 far away from the third inter-metal dielectric layer 7; as shown in fig. 17;
s1305: forming a second insulating layer 10 on the surface of the fourth inter-metal dielectric layer 9 far away from the third etching stop layer 8; as shown in fig. 18.
Specifically, the material of the second etch stop layer 6 may include, but is not limited to, at least one of SiN, SiC, SiCN, SiON, and SiCO; the material of the third intermetal dielectric layer 7 may include, but is not limited to, SiOCN, SiCO, SiO 2 At least one of SiN and SiC; the material of the third etch stop layer 8 may include, but is not limited to, at least one of SiN, SiC, SiCN, SiON, and SiCO; the material of the fourth IMD layer 9 may include but is not limited to SiOCN, SiCO, SiO 2 At least one of SiN and SiC; the material of the second insulating layer 10 may include, but is not limited to, SiON, SiN, SiO 2 、Si 3 N 4 、Ta 2 O 5 、TiO 2 、Al 2 O 3 Or a high molecular polymer, in this embodiment, the material of the second insulating layer 10 is preferably SiO 2 。
In one embodiment, as shown in fig. 19, after forming the second insulating layer 10 on the surface of the fourth metal interlayer dielectric layer 9 away from the third etch stop layer 8, the following steps may be further included:
s1901: sequentially etching a second insulating layer 10, a fourth metal interlayer dielectric layer 9, a third etching stop layer 8, a third metal interlayer dielectric layer 7, a second etching stop layer 6, a second metal interlayer dielectric layer 5 and a first insulating layer 24 along the thickness direction of the semiconductor device structure to form a first interconnection through hole 100; as shown in fig. 20;
s1902: sequentially etching a second insulating layer 10, a fourth metal interlayer dielectric layer 9, a third etching stop layer 8, a third metal interlayer dielectric layer 7, a second etching stop layer 6 and a second metal interlayer dielectric layer 5 along the thickness direction of the semiconductor device structure to form a second interconnection through hole 200; as shown in fig. 21;
s1903: sequentially etching a second insulating layer 10, a fourth metal interlayer dielectric layer 9, a third etching stop layer 8, a third metal interlayer dielectric layer 7, a second etching stop layer 6, a second metal interlayer dielectric layer 5, a first metal interlayer dielectric layer 4 and a first etching stop layer 3 along the thickness direction of the semiconductor device structure to form a third interconnection through hole 300; as shown in fig. 22;
s1904: filling metal in the first interconnect via 100, the second interconnect via 200, and the third interconnect via 300 to form a first interconnect plug 101, a second interconnect plug 201, and a third interconnect plug 301; the first interconnection plug 101 is connected to the second electrode plate 23, the second interconnection plug 201 is connected to the first electrode plate 21, and the third interconnection plug 301 is connected to the interconnection conductive layer 1; as shown in fig. 23.
Specifically, the barrier material of the first interconnect via 100, the barrier material of the second interconnect via 200, and the barrier material of the third interconnect via 300 may include, but are not limited to, Ta, TaN, or TiN, and in the present embodiment, the barrier material of the first interconnect via 100, the barrier material of the second interconnect via 200, and the barrier material of the third interconnect via 300 are preferably TiN; the metal filled in the first interconnect via 100, the metal filled in the second interconnect via 200, and the metal filled in the third interconnect via 300 may include, but are not limited to, metal materials such as copper, aluminum, silver, or tungsten; in this embodiment, the filling metal in the first interconnect via 100, the filling metal in the second interconnect via 200, and the filling metal in the third interconnect via 300 are preferably copper.
In one embodiment, the via may be filled with a metal material by a damascene process.
In one embodiment, while the interconnect conductive material layer 11 is etched to form the interconnect conductive layer 1 having the opening 13, a dummy conductive layer 12 (dummy) may be formed in the opening 13, as shown in fig. 25; the dummy conductive layer has a space from the interconnect conductive layer 1.
In one embodiment, the orthographic projection of the capacitance 2 on the interconnect conductive layer 1 may at least partially cover the dummy conductive layer.
The invention also provides a semiconductor device structure. As shown in fig. 4, the semiconductor device structure includes an interconnection conductive layer 1, a capacitor 2, and a first etch stop layer 3; the interconnect conductive layer 1 has an opening 13 therein; the first etching stop layer 3 is located on the interconnect conductive layer 1; the capacitor is located on the first etch stop layer, and is located right above the opening 13, and has a distance from the edge of the opening 13.
According to the semiconductor device structure, by setting the position relation between the interconnection conductive layer 1 and the capacitor 2, namely, the capacitor 2 is arranged right above the opening 13 in the interconnection conductive layer 1 and has a distance with the edge of the opening 13, under the condition, even if the interconnection conductive layer 1 deforms to generate a bulge under the influence of temperature, stress and the like, the capacitor 2 is not connected with the interconnection conductive layer 1 to cause short circuit; even if the interconnection plugs of the upper and lower electrode plates of the capacitor 2 penetrate through the layer where the interconnection conductive layer 1 is located, the capacitor 2 is not connected with the interconnection conductive layer 1 to cause short circuit due to the opening 13 right below the capacitor 2, so that the failure number of devices can be reduced, the performance of the devices can be improved, and the yield of products can be improved.
The capacitor 2 is located right above the opening 13, which means that the capacitor 2 is located vertically above the opening 13, that is, the orthographic projection of the capacitor 2 on the interconnection conductive layer 1 is located in the opening 13.
In one embodiment, the material of the interconnect conductive material layer 11 may include, but is not limited to, at least one of copper, aluminum, silver, gold, tungsten, cobalt, rhodium, platinum, and molybdenum; the material of the interconnect conductive layer 1 may include, but is not limited to, at least one of copper, aluminum, silver, gold, tungsten, cobalt, rhodium, platinum, and molybdenum; in the present embodiment, the material of the interconnect conductive material layer 11 and the material of the interconnect conductive layer 1 are both preferably copper; the capacitor 2 may include, but is not limited to, a MIM capacitor.
In one embodiment, as shown in fig. 24, the capacitor 2 may include a first electrode plate 21, a capacitor dielectric layer 22, a second electrode plate 23, and a first insulating layer 24; the first electrode plate 21 is located on the surface of the interconnecting conductive layer 1; the capacitance dielectric layer 22 is positioned on the surface of the first electrode plate 21 far away from the interconnection conductive layer 1; the second electrode plate 23 is positioned on the surface of the capacitance medium layer 22 far away from the first electrode plate 21; the first insulating layer 24 is located on the surface of the second electrode plate 23 away from the capacitor dielectric layer 22.
The material of the first electrode plate 21 may include, but is not limited to, at least one of Ti and TiN, and in this embodiment, the material of the first electrode plate 21 is preferably TiN; the material of the capacitor dielectric layer 22 may include, but is not limited to, Al 2 O 3 、HfO 2 And ZrO 2 At least one of (a); the material of the second electrode plate 23 may include, but is not limited to, at least one of Ti and TiN, and in the present embodiment, the material of the second electrode plate 23 is preferably TiN; the material of the first insulating layer 24 may include, but is not limited to, SiON, SiN, SiO 2 、Si 3 N 4 、Ta 2 O 5 、TiO 2 、Al 2 O 3 Or a high molecular polymer, in this embodiment, the material of the first insulating layer 24 is preferably SiO 2 。
In one embodiment, still referring to fig. 24, the semiconductor device structure further includes a first inter-metal dielectric layer 4, a second inter-metal dielectric layer 5, a second etch stop layer 6, a third inter-metal dielectric layer 7, a third etch stop layer 8, a fourth inter-metal dielectric layer 9, and a second insulating layer 10; the first etch stop layer 3 is located between the interconnect conductive layer 1 and the capacitor 2; the first metal interlayer dielectric layer 4 is positioned on the surface of the first etching stop layer 3 far away from the interconnection conductive layer 1; the second metal interlayer dielectric layer 5 is positioned on the surface of the first metal interlayer dielectric layer 4 far away from the first etching stop layer 3 and covers the first electrode plate 21, the capacitor dielectric layer 22, the second electrode plate 23 and the first insulating layer 24; the second etching stop layer 6 is positioned on the surface of the second metal interlayer dielectric layer 5 far away from the first metal interlayer dielectric layer 4; the third metal interlayer dielectric layer 7 is positioned on the surface of the second etching stop layer 6 far away from the second metal interlayer dielectric layer 5; the third etching stop layer 8 is positioned on the surface of the third metal interlayer dielectric layer 7 far away from the second etching stop layer 6; the fourth metal interlayer dielectric layer 9 is positioned on the surface of the third etching stop layer 8 far away from the third metal interlayer dielectric layer 7; the second insulating layer 10 is located on the surface of the fourth intermetal dielectric layer 9 away from the third etch stop layer 8.
Specifically, the material of the first etch stop layer 3 may include, but is not limited to, at least one of SiN, SiC, SiCN, SiON, and SiCO; the material of the first intermetal dielectric layer 4 may include, but is not limited to, SiOCN, SiCO, SiO 2 At least one of SiN and SiC; the material of the second intermetal dielectric layer 5 may include, but is not limited to, SiOCN, SiCO, SiO 2 At least one of SiN and SiC; the material of the second etch stop layer 6 may include, but is not limited to, at least one of SiN, SiC, SiCN, SiON, and SiCO; the material of the third intermetal dielectric layer 7 may include, but is not limited to, SiOCN, SiCO, SiO 2 At least one of SiN and SiC; the material of the third etch stop layer 8 may include, but is not limited to, at least one of SiN, SiC, SiCN, SiON, and SiCO; the material of the fourth IMD layer 9 may include but is not limited to SiOCN, SiCO, SiO 2 At least one of SiN and SiC; the material of the second insulating layer 10 may include, but is not limited to, SiON, SiN, SiO 2 、Si 3 N 4 、Ta 2 O 5 、TiO 2 、Al 2 O 3 Or a high molecular polymer, in this embodiment, the material of the second insulating layer 10 is preferably SiO 2 。
In one embodiment, still referring to fig. 24, the semiconductor device structure further includes a first interconnect plug 101, a second interconnect plug 201, and a third interconnect plug 301; the first interconnection plug 101 penetrates through the second insulating layer 10, the fourth metal interlayer dielectric layer 9, the third etching stop layer 8, the third metal interlayer dielectric layer 7, the second etching stop layer 6, the second metal interlayer dielectric layer 5 and the first insulating layer 24 along the thickness direction of the semiconductor device structure, and is connected with the second electrode plate 23; the second interconnection plug 201 penetrates through the second insulating layer 10, the fourth metal interlayer dielectric layer 9, the third etching stop layer 8, the third metal interlayer dielectric layer 7, the second etching stop layer 6 and the second metal interlayer dielectric layer 5 along the thickness direction of the semiconductor device structure, and is connected with the first electrode plate 21; the third interconnection plug 301 penetrates through the second insulating layer 10, the fourth metal interlayer dielectric layer 9, the third etching stop layer 8, the third metal interlayer dielectric layer 7, the second etching stop layer 6, the second metal interlayer dielectric layer 5, the first metal interlayer dielectric layer 4 and the first etching stop layer 3 along the thickness direction of the semiconductor device structure, and is connected to the interconnection conductive layer 1.
Specifically, the structure of the first interconnect plug 101, the structure of the second interconnect plug 201, and the structure of the third interconnect plug 301 may include, but are not limited to, a via plus a filler metal, and the barrier material of the via may include, but is not limited to, Ta, TaN, or TiN, and in this embodiment, the barrier material of the via is preferably TiN; the via filling metal may include, but is not limited to, a metal material such as copper, aluminum, silver, or tungsten, and in this embodiment, the via filling metal is preferably copper.
In one embodiment, as shown in fig. 25, the semiconductor device structure further includes a dummy conductive layer 12, the dummy conductive layer 12 being located within the opening 13 with a space from the interconnect conductive layer 1; the dummy conductive layer 12 may include any one of an unstructured layer (i.e., empty space without any structural arrangement) or a dummy metal layer.
In one embodiment, the orthographic projection of the capacitance 2 on the interconnect conductive layer 1 may at least partially cover the dummy conductive layer 12.
In one embodiment, the interconnecting conductive layer 1 and the dummy conductive layer 12 may be located on a surface of a substrate, and the substrate may include a device region, the device region may include a device that needs to be electrically extracted, and the device may include, but is not limited to, a transistor, a resistor, a capacitor, and the like; the interconnect conductive layer 1 may be electrically connected to a device; while the dummy conductive layer 12 is isolated from the device and is not electrically connected to the device. Therefore, even if the second interconnection plug 201 penetrates the first electrode plate 21 of the capacitor 2 and then comes into contact with the dummy conductive layer 12 located therebelow due to a process problem, a short circuit between the capacitor 2 and other devices is not caused.
The above examples only show several embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A semiconductor device structure, comprising:
an interconnect conductive layer having an opening therein;
a first etch stop layer on the interconnect conductive layer;
the capacitor is positioned on the first etching stop layer, is positioned right above the opening and has a distance with the edge of the opening;
a dummy conductive layer within the opening having a spacing from the interconnect conductive layer.
2. The semiconductor device structure of claim 1, wherein the capacitance comprises:
a first electrode plate on the interconnect conductive layer;
the capacitor dielectric layer is positioned on the surface of the first electrode plate far away from the interconnection conductive layer;
the second electrode plate is positioned on the surface of the capacitance dielectric layer far away from the first electrode plate;
and the first insulating layer is positioned on the surface of the second electrode plate far away from the capacitor dielectric layer.
3. The semiconductor device structure of claim 2, further comprising:
the first metal interlayer dielectric layer is positioned on the surface of the first etching stop layer, which is far away from the interconnection conductive layer;
the second metal interlayer dielectric layer is positioned on the surface of the first metal interlayer dielectric layer, which is far away from the first etching stop layer, and covers the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer;
the second etching stop layer is positioned on the surface of the second metal interlayer dielectric layer, which is far away from the first metal interlayer dielectric layer;
the third metal interlayer dielectric layer is positioned on the surface of the second etching stop layer far away from the second metal interlayer dielectric layer;
the third etching stop layer is positioned on the surface of the third metal interlayer dielectric layer far away from the second etching stop layer;
the fourth metal interlayer dielectric layer is positioned on the surface of the third etching stop layer far away from the third metal interlayer dielectric layer;
and the second insulating layer is positioned on the surface of the fourth metal interlayer dielectric layer, which is far away from the third etching stop layer.
4. The semiconductor device structure of claim 3, further comprising:
a first interconnection plug penetrating the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer, the second inter-metal dielectric layer and the first insulating layer in a thickness direction of the semiconductor device structure, and connected to the second electrode plate;
a second interconnection plug penetrating the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer and the second inter-metal dielectric layer in the thickness direction of the semiconductor device structure and connected to the first electrode plate;
and a third interconnection plug which penetrates the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer, the second inter-metal dielectric layer, the first inter-metal dielectric layer and the first etching stop layer in the thickness direction of the semiconductor device structure and is connected with the interconnection conductive layer.
5. The semiconductor device structure of any one of claims 1 to 4, wherein a material of the first etch stop layer comprises at least one of silicon nitride, silicon carbide nitride, silicon oxynitride, and silicon oxycarbide.
6. A method for fabricating a semiconductor device structure, the method comprising:
forming a layer of interconnect conductive material;
forming a first etch stop layer on the layer of interconnect conductive material;
forming a capacitor on the first etching stop layer;
etching the interconnection conductive material layer to form an interconnection conductive layer with an opening; the capacitor is positioned right above the opening and has a distance with the edge of the opening;
and etching the interconnection conductive material layer to form an interconnection conductive layer with an opening, and simultaneously forming a virtual conductive layer in the opening, wherein the virtual conductive layer and the interconnection conductive layer have a distance.
7. The method of claim 6, wherein before forming the capacitor on the first etch stop layer, further comprising:
and forming a first metal interlayer dielectric layer on the surface of the first etching stop layer far away from the interconnection conductive material layer.
8. The method of claim 7, wherein forming a capacitor on the first etch stop layer comprises:
forming a laminated structure of a first electrode plate, a capacitor dielectric layer, a second electrode plate and a first insulating layer which are sequentially laminated on the surface of the first metal interlayer dielectric layer;
forming a second metal interlayer dielectric layer on the surface of the first metal interlayer dielectric layer far away from the first etching stop layer; the second metal interlayer dielectric layer covers the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer;
the formation of the laminated structure of the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer which are sequentially laminated on the surface of the first metal interlayer dielectric layer comprises the following steps:
forming a first electrode material layer on the surface of the first metal interlayer dielectric layer far away from the first etching stop layer;
forming a capacitance dielectric material layer on the surface of the first electrode material layer far away from the first metal interlayer dielectric layer;
forming a second electrode material layer on the surface of the capacitance medium material layer far away from the first electrode material layer;
forming a first insulating material layer on the surface of the second electrode material layer far away from the capacitance medium material layer;
and etching the first insulating material layer, the second electrode material layer, the capacitor dielectric material layer and the first electrode material layer in sequence to form a laminated structure of the first electrode plate, the capacitor dielectric layer, the second electrode plate and the first insulating layer which are sequentially laminated.
9. The method of claim 8, further comprising, after forming a capacitor on the first etch stop layer:
forming a second etching stop layer on the surface of the second metal interlayer dielectric layer far away from the first metal interlayer dielectric layer;
forming a third metal interlayer dielectric layer on the surface of the second etching stop layer far away from the second metal interlayer dielectric layer;
forming a third etching stop layer on the surface of the third metal interlayer dielectric layer far away from the second etching stop layer;
forming a fourth metal interlayer dielectric layer on the surface of the third etching stop layer far away from the third metal interlayer dielectric layer;
forming a second insulating layer on the surface of the fourth metal interlayer dielectric layer far away from the third etching stop layer;
sequentially etching the second insulating layer, the fourth metal interlayer dielectric layer, the third etching stop layer, the third metal interlayer dielectric layer, the second etching stop layer, the second metal interlayer dielectric layer and the first insulating layer along the thickness direction of the semiconductor device structure to form a first interconnection through hole;
sequentially etching the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer and the second inter-metal dielectric layer along the thickness direction of the semiconductor device structure to form a second interconnection through hole;
sequentially etching the second insulating layer, the fourth inter-metal dielectric layer, the third etching stop layer, the third inter-metal dielectric layer, the second etching stop layer, the second inter-metal dielectric layer, the first inter-metal dielectric layer and the first etching stop layer along the thickness direction of the semiconductor device structure to form a third interconnection through hole;
filling metal in the first interconnection hole, the second interconnection hole and the third interconnection through hole to form a first interconnection plug, a second interconnection plug and a third interconnection plug; the first interconnection plug is connected with the second electrode plate, the second interconnection plug is connected with the first electrode plate, and the third interconnection plug is connected with the interconnection conductive layer.
10. The method for manufacturing a semiconductor device structure according to any one of claims 6 to 9, wherein a material of the first etch stop layer includes at least one of silicon nitride, silicon carbide nitride, silicon oxynitride, and silicon oxycarbide.
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