JP2005309675A - Electronic control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic control device improved in reliability of microcomputer operation. <P>SOLUTION: An engine control ECU 1 comprises a main microcomputer 10 executing an principal engine control such as fuel injection control, and generating a reference clock signal (1 MHz) to be supplied to each part of the engine control ECU 1, and a sub-microcomputer 40 executing other controls which cannot be processed by the main microcomputer 10 (knock control, etc.). The main microcomputer 10 comprises a DPLL circuit 23 multiplying the reference clock signal to a predetermined first multiplied number to generate an operation clock signal (64 MHz), and a CPU 11 in the main microcomputer 10 operates synchronously with the operation clock signal. The sub-microcomputer 40 comprises a DPLL circuit 51 multiplying the reference clock signal to a predetermined multiplied number to generate an operation clock signal (32 MHz), and a CPU 41 in the sub-microcomputer 40 operates synchronously with this operation clock signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic control device including a plurality of microcomputers.

  2. Description of the Related Art Conventionally, for example, an electronic control unit (hereinafter referred to as an ECU) mounted on a vehicle is provided with a known microcomputer (hereinafter referred to as a microcomputer) including a CPU, a RAM, a ROM, and the like. And in electronic control in vehicles, engine control, transmission control, etc. are performed, for example, a microcomputer performs processing according to various control, and controls a vehicle to an appropriate state. Note that the microcomputer is generally configured to operate in synchronization with an operation clock signal having a predetermined frequency (for example, 64 MHz). For this reason, in order to cause the microcomputer to execute processing, it is necessary to supply an operation clock signal to the microcomputer (for example, see Patent Document 1).

  By the way, for example, in engine control, a plurality of control processes such as fuel injection control, ignition timing control, knock control, etc. are generally performed. For this reason, the total processing amount of engine control exceeds the processing capability of one CPU, and often all control related to engine control cannot be executed by one microcomputer (specifically, CPU). Therefore, in such a case, the ECU includes a plurality of microcomputers, and performs overall control using these plurality of microcomputers. Therefore, it is necessary to supply an operation clock signal to each of the plurality of microcomputers.

  As a technique for supplying an operation clock signal to each of a plurality of microcomputers, conventionally, one clock generator that generates and outputs an operation clock signal is installed in the ECU, and an operation output from this clock generator. A device that distributes a clock signal to each microcomputer via a signal transmission line is known.

Further, when the microcomputer is started, it is necessary to start (reset release) the microcomputer after the oscillation state of the operation clock signal is stabilized. For this reason, the time from the start of the microcomputer until the oscillation state is stabilized is predicted, and the operation of the microcomputer is started after this time has elapsed.
JP 2003-99150 A

  However, since the operation clock signal has a high frequency, or because the time from when the microcomputer is activated until the oscillation state is stabilized is predicted, there is a problem that the reliability of the operation of the microcomputer is impaired.

  That is, if the operation clock signal has a high frequency, waveform distortion is likely to occur due to the influence of noise before reaching the microcomputer via the signal transmission line. For this reason, there is a possibility that the frequency of the operation clock signal changes irregularly due to the influence of noise, and the microcomputer executes an unexpected operation. Also, when predicting the time until the oscillation state stabilizes, the oscillation state will stabilize if the time until the oscillation state stabilizes is delayed due to an abnormality in the clock generator. There is a possibility that the operation of the microcomputer is started in a state where it is not, and the microcomputer performs an unexpected operation.

  The present invention has been made in view of these problems, and an object of the present invention is to provide an electronic control device that improves the reliability of microcomputer operation.

  In order to achieve the above object, an electronic control device of the present invention is an electronic control device including a plurality of microcomputers that operate in synchronization with an operation clock signal having a predetermined operation frequency set in advance. An oscillation unit that outputs a reference clock signal that oscillates at a lower set frequency, each of the plurality of microcomputers includes a multiplication unit that multiplies the frequency of the reference clock signal output from the oscillation unit to a predetermined operating frequency, The reference clock signal multiplied by the multiplication means is used as an operation clock signal.

  According to the electronic control device configured as described above, the oscillating means outputs the reference clock signal. Further, the multiplication means provided in each of the plurality of microcomputers multiplies the frequency of the reference clock signal to a predetermined operating frequency. The plurality of microcomputers operate in synchronization with the multiplied reference clock signal.

  That is, since the microcomputer includes the multiplication unit, the frequency of the reference clock signal transmitted from the oscillation unit to the microcomputer can be made lower than the predetermined operating frequency. For this reason, the influence of noise can be reduced as compared with the case where a reference clock signal having a predetermined operating frequency is transmitted to the microcomputer. Therefore, the reliability of the operation of the microcomputer can be improved.

  In the electronic control device of the present invention, the oscillation state of the reference clock signal output by the oscillating means is monitored, and a plurality of times until the electronic control device starts up and the oscillation state shifts from unstable to stable. It is desirable to provide an operation prohibiting means for prohibiting the operation of the microcomputer.

  According to the electronic control device configured as described above, it is possible to prevent the microcomputer from starting the operation even though the oscillation state of the reference clock signal is unstable. Therefore, the reliability of the operation of the microcomputer can be improved.

  In the electronic control device of the present invention, the oscillation means may be provided in any one of the plurality of microcomputers, but the power supply means for supplying power to each of the plurality of microcomputers. The electronic control device may be provided, and the oscillation means may be provided in the power supply means. That is, the microcomputer can be miniaturized because the microcomputer is not provided with the oscillation means. Furthermore, in general, the power supply means receives a power supply voltage having a voltage value higher than that of the power supply necessary for microcomputer operation (microcomputer operation power supply), and reduces the power supply voltage to reduce the microcomputer operation power supply. Have gained. For this reason, the oscillation means can be operated at a voltage higher than the voltage of the microcomputer operating power supply. That is, the oscillation means can be operated more stably than when the oscillation means is provided in the microcomputer.

  In the electronic control device of the present invention, the oscillating means includes a first oscillation unit that generates a first reference clock signal that oscillates at a frequency set lower than a predetermined operating frequency, and a frequency set lower than the predetermined operating frequency. A second oscillation unit that generates a second reference clock signal to oscillate, and monitors the oscillation state of the first reference clock signal, and when the oscillation state of the first reference clock signal is normal, the first reference clock signal The signal may be output as a reference clock signal, and when the oscillation state of the first reference clock signal is abnormal, the second reference clock signal may be output as the reference clock signal.

  According to the electronic control device configured in this way, even if the oscillation state of the first reference clock signal is abnormal, the second reference clock signal is output as the reference clock signal. The microcomputer can be operated in synchronization with the operating clock signal. For this reason, when the oscillation state of the first reference clock signal is abnormal, the microcomputer can be prevented from stopping its operation or performing an unexpected operation.

  Further, when the frequency of the second reference clock signal is set lower than that of the first reference clock signal, if the oscillation state of the first reference clock signal is abnormal, a notification that informs a plurality of microcomputers of that fact And a plurality of microcomputers execute processing corresponding to the abnormality of the oscillation state of the first reference clock signal when notified by the notification means that the oscillation state of the first reference clock signal is abnormal. It may be.

  According to the electronic control apparatus configured as described above, when the oscillation state of the first reference clock signal is abnormal, the plurality of microcomputers know that fact and the oscillation state of the first reference clock signal is abnormal. Therefore, even if the microcomputer operates using the second reference clock signal having a frequency lower than that of the first reference clock signal as the operation clock signal, it is possible to suppress an unexpected operation. .

  The shorter the distance that the reference clock signal is transmitted from the oscillation means to the microcomputer, the less likely the reference clock signal is affected by noise. At least one may be arranged close to the oscillation means.

  Further, a microstrip line and a coplanar line are well known as transmission lines for transmitting a high-frequency signal while suppressing waveform distortion due to the influence of noise. For this reason, in the electronic control device of the present invention, the reference clock signal transmission line for transmitting the reference clock signal from the oscillating means to the plurality of microcomputers may be a microstrip line or a coplanar line.

  In general, in a vehicle, various types of control such as engine control and transmission control are executed using a large number of microcomputers. For this reason, in particular, the electronic control device is preferably mounted on a vehicle.

(First embodiment)
The first embodiment will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an engine control ECU 1 to which the present invention is applied.

The engine control ECU 1 is an electronic control device that is mounted on a vehicle and executes various controls related to engine driving.
As shown in FIG. 1, the engine control ECU 1 is supplied with power from a DC power supply VB (12V in this embodiment) and generates a power supply voltage for microcomputer (5V in this embodiment) that drives each part of the engine control ECU1. At the same time, the power supply IC 70 generates a first reset signal that is linked to the supply state of the microcomputer power supply voltage, and operates upon receiving the supply of the microcomputer power supply voltage from the power supply IC 70, and operates in response to the first reset signal from the power supply IC 70. The state is controlled, main control for controlling the engine such as fuel injection control and ignition timing control is executed, and the reference clock signal supplied to each part of the engine control ECU 1 and the oscillation state of the reference clock signal are linked. And a main microcomputer 10 for generating a second reset signal.

  Further, the engine control ECU 1 receives a first reset signal and a second reset signal, and outputs a logical product (AND) of these input signals as a third reset signal, and a power supply The microcomputer 70 operates in response to the supply of the power supply voltage for the microcomputer from the IC 70 and the supply of the reference clock signal from the main microcomputer 10, and the operation state is controlled by the third reset signal from the AND circuit 90 to monitor the operation state of the main microcomputer 10. And a sub-microcomputer 40 that executes monitoring control and other control (such as knock control) that cannot be processed by the main microcomputer 10.

  Among these, the main microcomputer 10 includes a CPU 11 that executes processing based on a predetermined processing program, a ROM 13 that stores various control programs, a RAM 15 that stores various data, and a voltage value of an input analog signal. An A / D converter 17 for converting the digital signal into a digital value, an input / output port 19 having a plurality of input ports for inputting various digital signals and a plurality of output ports for outputting various digital signals, and a predetermined frequency (this In the embodiment, the clock oscillation circuit 21 that generates a reference clock signal of 1 MHz) and the reference clock signal from the clock oscillation circuit 21 are multiplied by a predetermined first multiplication number (64 times in the present embodiment) and multiplied. DPLL (Digital Phase Locked L) that generates the reference clock signal as an operation clock signal op) An oscillation state determination unit 25 that determines the oscillation state of the reference clock signal from the circuit 23 and the clock oscillation circuit 21 and generates a fourth reset signal that controls the operation state of the CPU 11 based on the determination result; A CPU 27, a ROM 13, a RAM 15, an A / D converter 17, an input / output port 19, and an oscillation state determination unit 25 are provided, and a reset terminal (not shown) to which a first reset signal is input is provided.

  The clock oscillation circuit 21 includes an oscillator 21a arranged outside the main microcomputer 10 and an oscillation unit 21b that drives the oscillator 21a to generate a reference clock signal having a predetermined frequency.

  Further, as shown in FIG. 2A, the oscillation state determination unit 25 performs an up-count operation according to the reference clock signal from the clock oscillation circuit 21, and generates a signal (count signal) corresponding to the count value. And a comparison circuit 25b that compares the count value indicated by the count signal from the counter 25a with a predetermined oscillation state determination value C1 set in advance and generates a fourth reset signal linked to the comparison result. The The comparison circuit 25b sets the fourth reset signal to the Low level when the count value is smaller than the predetermined oscillation state determination value C1, and sets the fourth reset signal to the High level when the count value is larger than the predetermined oscillation state determination value C1. To do.

  The CPU 11 is configured to be in a reset state when the fourth reset signal is at a low level, and to operate when the fourth reset signal is at a high level. The oscillation state determination unit 25 is configured to be in a reset state when the first reset signal is at a low level, and to operate when the first reset signal is at a high level. . The DPLL circuit 23 is configured to operate when supplied with a power supply voltage for a microcomputer.

  Next, the sub-microcomputer 40 includes a CPU 41 that executes processing based on a predetermined processing program, a ROM 43 that stores various control programs, a RAM 45 that stores various data, and a voltage value of an input analog signal. An A / D converter 47 that converts a digital signal into a digital value, a plurality of input ports to which various digital signals are input, an input / output port 49 having a plurality of output ports from which various digital signals are output, and a clock oscillation circuit A DPLL circuit 51 that multiplies the reference clock signal from 21 to a predetermined second multiplication number (32 times in this embodiment) set in advance, and generates the multiplied reference clock signal as an operation clock signal; and CPU 41, ROM 43, RAM 45 , The A / D converter 47 and the input / output port 49, and the bus 53 connected to the input / output port 49 and the reset signal to which the third reset signal is input. Tsu bets terminal and a (not shown) and.

  The CPU 41 enters a reset state when the third reset signal is at a low level, and when the third reset signal changes from a low level to a high level and a predetermined DPLL stabilization time t4 (see FIG. 3) elapses, the CPU 41 is in a reset state. Is configured to operate after being released. The DPLL circuit 51 is configured to operate when supplied with a power supply voltage for a microcomputer.

The sub-microcomputer 40 performs monitoring control by performing data communication with the main microcomputer 10 via the input / output port 49 and the input / output port 19.
Next, the power supply IC 70 receives a DC power supply voltage from the DC power supply VB, adjusts (steps down) the DC power supply voltage to generate a microcomputer power supply voltage, and the microcomputer IC from the voltage adjustment section 71. The value of the power supply voltage is monitored, and the microcomputer power supply voltage is set in advance by predicting that the oscillation state of the reference clock signal will be stable after the power supply voltage for the microcomputer reaches a predetermined determination voltage value V1 (2.5 V in this embodiment) or more. When a predetermined reset release time t1 (see FIG. 3) elapses, a voltage monitoring unit 73 that changes the first reset signal from the low level to the high level is provided.

  In the engine control ECU 1 configured as described above, when the oscillator 21a outputs an oscillation signal (see FIG. 3C), the oscillation unit 21b generates a reference clock signal (frequency: 1 MHz) that matches the frequency of the oscillation signal. Is output to the DPLL circuit 23 in the main microcomputer 10 and also supplied to the outside of the main microcomputer 10 (see FIG. 3D).

  In the main microcomputer 10, the DPLL circuit 23 outputs an operation clock signal (frequency: 64 MHz) obtained by multiplying the frequency of the reference clock signal by 64 (see FIG. 3E), and the CPU 11 operates according to the operation clock signal. To do.

  On the other hand, in the sub-microcomputer 40, the DPLL circuit 51 outputs an operation clock signal (frequency: 32 MHz) obtained by multiplying the frequency of the reference clock signal supplied from the main microcomputer 10 by 32 (see FIG. 3F). The CPU 41 operates in accordance with the clock signal.

  Next, the operation of the engine control ECU 1 when the engine control ECU 1 is activated will be described with reference to FIG. FIG. 3 is a timing chart showing the operation of the engine control ECU 1 at the time of startup.

  3A shows the voltage waveform of the power supply voltage for the microcomputer, FIG. 3B shows the first reset signal, FIG. 3C shows the oscillation signal waveform of the oscillator 21a, FIG. 3D shows the reference clock signal, and FIG. (F) is the operation clock signal of the sub-microcomputer 40, (g) is the count signal, (h) is the fourth reset signal, (i) is a waveform indicating the operation state of the CPU 11, and (j) is the first signal. 2 reset signal, (k) is a waveform indicating the operating state of the CPU 41. When the waveform indicating the operation state of the CPU 11 (CPU 41) is at a high level, the CPU 11 (CPU 41) is in an operating state, and when the waveform is at a low level, it indicates an inactive state. ing.

  First, when an ignition switch (not shown) is turned on and the power supply voltage from the DC power supply VB is supplied to start the engine control ECU 1 (see time T1 in FIG. 3), as shown in FIG. The power supply voltage gradually rises from 0V, and the oscillator 21a starts outputting the oscillation signal (see time T2 in FIG. 3C). Then, after the oscillation signal output start (time T2), the microcomputer power supply voltage value reaches the predetermined determination voltage value V1 (2.5 V) (see time T3 in FIG. 3), and then the predetermined reset release time t1 (this time) When 20 ms in the embodiment has elapsed, the voltage monitoring unit 73 changes the first reset signal from the Low level to the High level (see time T4 in FIG. 3B).

  Then, the counter 25a in the oscillation state determination unit 25 is released from the reset state, and starts outputting a count signal that counts up according to the reference clock signal (see time T4 in FIG. 3G). Thereafter, when the count value of the count signal reaches a predetermined oscillation state determination value C1 (see time T5 in FIG. 3G), it is assumed that the oscillation state of the reference clock signal is stable, and the comparison circuit 25b of the oscillation state determination unit 25 Changes the fourth reset signal from Low level to High level (see time T5 in FIG. 3 (h)). In addition, the time t2 (refer FIG.3 (d)) from the time T4 to the time T5 is about 5 ms, for example. Then, the reset state of the CPU 11 is released, and the CPU 11 starts operating (see time T5 in FIG. 3 (i)).

  Further, when a predetermined initialization processing time t3 (2 ms in the present embodiment) elapses after the reset state of the CPU 11 is released, the CPU 11 changes the second reset signal from the low level to the high level (FIG. 3). (See time T6 in (j)). That is, since the first reset signal is at the high level before the second reset signal is at the high level, the AND circuit 90 sends the third reset signal to the high level when the second reset signal is at the high level. To level. The predetermined initialization processing time t3 is an initialization process for setting the master / slave relationship between the main microcomputer 10 and the sub-microcomputer 40 (RAM, register initialization, etc.). Thus, the time is required before the sub-microcomputer 40 operates.

  When a predetermined DPLL stabilization time t4 (3 ms in the present embodiment) elapses after the third reset signal becomes High level, the reset state of the CPU 41 is released and the CPU 41 starts operation (FIG. 3 ( k) time T7). The predetermined DPLL stabilization time t4 is a time for delaying the start of the operation of the CPU 41 from when the third reset signal becomes High level until the operation of the DPLL circuit 51 is stabilized.

  In the engine control ECU 1 of the present embodiment configured as described above, the main microcomputer 10 and the sub-microcomputer 40 are provided with the DPLL circuit 23 and the DPLL circuit 51, respectively. The frequency of the reference clock signal transmitted between the sub-microcomputers 40 can be made lower than the predetermined first operating frequency (64 MHz) and the predetermined second operating frequency (32 MHz). For this reason, the influence of noise can be reduced as compared with the case where the reference clock signals having the predetermined first operating frequency and the predetermined second operating frequency are transmitted to the main microcomputer 10 and the sub-microcomputer 40, respectively. Therefore, the reliability of the operation of the main microcomputer 10 and the sub microcomputer 40 can be improved.

When the number of oscillations from the start of oscillation of the reference clock signal output from the clock oscillation circuit 21 reaches the predetermined oscillation state determination value C1, the CPU 41 starts operation.
That is, the engine control ECU 1 of the present embodiment monitors the oscillation state of the reference clock signal, and until the engine control ECU 1 is activated and the oscillation state shifts from unstable to stable, the main microcomputer 10 and the sub microcomputer 40 Prohibit operation.

  That is, since the oscillation state of the reference clock signal is monitored, it is possible to prevent the main microcomputer 10 and the sub-microcomputer 40 from starting operation even though the oscillation state of the reference clock signal is unstable. . Therefore, the reliability of the operation of the main microcomputer 10 and the sub microcomputer 40 can be improved.

  In the embodiment described above, the engine control ECU 1 is the electronic control device according to the present invention, the main microcomputer 10 and the sub-microcomputer 40 are the microcomputer according to the present invention, the clock oscillation circuit 21 is the oscillation means according to the present invention, the DPLL circuit 23 and the DPLL circuit 51. Is the multiplication means in the present invention, the oscillation state determination unit 25 is the operation prohibiting means in the present invention, the power supply IC 70 is the power supply means in the present invention, and the predetermined first operating frequency and the predetermined second operating frequency are the predetermined operating frequencies in the present invention. .

(Second Embodiment)
The second embodiment will be described below with reference to the drawings.
FIG. 4 is a block diagram showing the configuration of the engine control ECU 101 to which the present invention is applied.

The engine control ECU 101 is an electronic control device that is mounted on a vehicle and executes various controls related to engine driving.
As shown in FIG. 4, the engine control ECU 101 is supplied with power from a DC power supply VB (12V in this embodiment), and power supply voltage for microcomputers (5V in this embodiment) for driving each part of the engine control ECU 101. A power supply IC 170 for generating a first reset signal linked to the supply state of the microcomputer power supply voltage, a reference clock signal supplied to each part of the engine control ECU 101, and an oscillation stabilization signal linked to the oscillation state of the reference clock signal; A logical product operation circuit (AND circuit) 195 is provided that receives the first reset signal and the oscillation stabilization signal as inputs and outputs the logical product (AND) of these input signals as the second reset signal.

  Further, the engine control ECU 101 operates by receiving the supply voltage of the microcomputer and the reference clock signal from the power supply IC 170, and the operation state is controlled by the second reset signal from the AND circuit 195, so that fuel injection control and ignition timing control are performed. The main microcomputer 110 that executes the main control for controlling the engine and the like, generates a third reset signal that is linked to the oscillation state of the reference clock signal, and inputs the first reset signal and the third reset signal. AND circuit 190 that outputs the logical product (AND) of the input signals as a fourth reset signal, and operates with the supply of the power supply voltage for the microcomputer and the reference clock signal from the power supply IC 170, and the AND circuit The operation state is controlled by the fourth reset signal from 190, and the main microcomputer 11 And a sub-microcomputer 140 to the execution control of operating conditions other that can not be treated with supervisory control and the main microcomputer 110 which monitors (knock control, etc.).

  As shown in FIG. 8A, the main microcomputer 110, the sub microcomputer 140, and the power supply IC 170 are mounted on the board B1, and the main microcomputer 110 and the sub microcomputer 140 are arranged close to the power supply IC 170, respectively. The FIG. 8A is a plan view of the substrate B1 on which the main microcomputer 110, the sub microcomputer 140, and the power supply IC 170 are mounted.

  Between the power supply IC 170 and the main microcomputer 110, a clock line LC1 for transmitting the reference clock signal output from the power supply IC 170 to the main microcomputer 110 and the clock line LC1 are arranged on both sides of the clock line LC1. Two ground lines LG1 are provided. That is, the clock line LC1 is configured to be a coplanar line.

  Similarly, between the power supply IC 170 and the sub-microcomputer 140, a clock line LC2 for transmitting the reference clock signal output from the power supply IC 170 to the sub-microcomputer 140, and both sides of the clock line LC2 along the clock line LC2 are arranged. Two ground lines LG2 are provided. That is, the clock line LC2 is configured to be a coplanar line by the ground line LG2.

  Further, as shown in FIG. 8B, the substrate B1 is a multilayer substrate composed of three substrates B1a, B1b, and B1c. The clock line LC2 and the ground line LG2 are disposed on the substrate B1a, the ground line LG3 is disposed on the substrate B1b, and the signal line L1 is disposed on the substrate B1c. FIG.8 (b) is a figure which shows the AA cross-section part of Fig.8 (a).

  The ground line LG3 is located immediately below the clock line LC2 and the ground line LG2 and is arranged along the clock line LC2. The signal line L1 is located just below the ground line LG2. That is, the clock line LC2 is configured to be a microstrip line by the ground line LG3.

  As shown in FIG. 5, the main microcomputer 110 receives a CPU 111 that executes processing based on a predetermined processing program, a ROM 113 that stores various control programs, and a RAM 115 that stores various data. An input / output port 119 having an A / D converter 117 for converting the voltage value of the analog signal into a digital value, a plurality of input ports for inputting various digital signals, and a plurality of output ports for outputting various digital signals. And a digital phase locked loop (DPLL) that multiplies the reference clock signal from the power supply IC 170 to a predetermined first multiplication number (64 times in the present embodiment) and generates the multiplied reference clock signal as an operation clock signal. Circuit 121, CPU 111, ROM 113, RAM 115, A / A bus 123 for connecting the transducer 117 and output port 119, and a reset terminal to which the second reset signal is input (not shown).

  Then, the CPU 111 enters a reset state when the second reset signal is at the low level, and when the second reset signal changes from the low level to the high level and a predetermined DPLL stabilization time t12 (see FIG. 5) elapses, the CPU 111 is in the reset state. Is configured to operate after being released.

  Next, the sub-microcomputer 140 includes a CPU 141 that executes processing based on a predetermined processing program, a ROM 143 that stores various control programs, a RAM 145 that stores various data, and a voltage value of an input analog signal. From an A / D converter 147 for converting a digital signal to a digital value, a plurality of input ports for inputting various digital signals, an input / output port 149 having a plurality of output ports for outputting various digital signals, and a power supply IC 170 A DPLL circuit 151 that multiplies the reference clock signal by a predetermined second multiplication number (32 times in the present embodiment) and generates the multiplied reference clock signal as an operation clock signal, and the CPU 141, ROM 143, RAM 145, A / D converter 147 and I / O port 149 for connecting bus 153 and the fourth reset And a reset terminal to which a signal is input (not shown).

  Then, the CPU 141 is in a reset state when the fourth reset signal is at the low level, and is reset when the fourth reset signal is changed from the low level to the high level and a predetermined DPLL stabilization time t14 (see FIG. 5) elapses. Is configured to operate after being released. The DPLL circuit 151 is configured to operate when supplied with a power supply voltage for a microcomputer.

The sub-microcomputer 140 performs monitoring control by performing data communication with the main microcomputer 110 via the input / output port 149 and the input / output port 119.
Next, the power supply IC 170 inputs a DC power supply voltage from the DC power supply VB, adjusts (steps down) the DC power supply voltage, and generates a microcomputer power supply voltage, and the microcomputer IC from the voltage adjustment section 171. The value of the power supply voltage is monitored, and the microcomputer power supply voltage is set in advance by predicting that the oscillation state of the reference clock signal will be stable after the power supply voltage for the microcomputer reaches a predetermined determination voltage value V1 (2.5 V in this embodiment) or more. When a predetermined reset release time t11 (see FIG. 5) elapses, a voltage monitoring unit 173 that changes the first reset signal from Low level to High level, and a clock that generates a reference clock signal having a predetermined frequency (1 MHz in this embodiment). An oscillation circuit 175 and an oscillation state determination unit 177 that determines the oscillation state of the reference clock signal output from the clock oscillation circuit 175 are provided.

  The clock oscillation circuit 175 includes an oscillator 175a disposed outside the power supply IC 170, and an oscillator 175b that drives the oscillator 175a and outputs a reference clock signal having a predetermined frequency.

  Further, as shown in FIG. 2B, the oscillation state determination unit 177 receives the reference clock signal output from the clock oscillation circuit 175, performs an up-count operation according to the reference clock signal, and according to the count value. The counter 177a that outputs a signal (count signal), the count value indicated by the count signal input from the counter 177a, and a preset predetermined oscillation state determination value C11 are compared, and this count value is determined as the predetermined oscillation state determination When the value is smaller than the value C11, the oscillation stabilization signal is set to the low level, and when the value is greater than the predetermined oscillation state determination value C11, the comparison circuit 177b is used to set the oscillation stabilization signal to the high level.

  In the engine control ECU 101 configured as described above, when the oscillator 175a outputs an oscillation signal (see FIG. 5D), the oscillation unit 175b generates a reference clock signal (frequency: 1 MHz) that matches the frequency of the oscillation signal. (See FIG. 5E), and this is supplied to the DPLL circuit 121 in the main microcomputer 110 and the DPLL circuit 151 in the sub-microcomputer 140.

  In the main microcomputer 10, the DPLL circuit 121 outputs an operation clock signal (frequency: 64 MHz) obtained by multiplying the frequency of the reference clock signal by 64 (see FIG. 5F), and the CPU 111 operates according to the operation clock signal. To do.

  On the other hand, in the sub-microcomputer 140, the DPLL circuit 151 outputs an operation clock signal (frequency: 32 MHz) obtained by multiplying the frequency of the reference clock signal by 32 (see FIG. 5G), and the CPU 141 operates in accordance with this operation clock signal. To do.

  Next, the operation of the engine control ECU 101 when the engine control ECU 101 is activated will be described with reference to FIG. FIG. 5 is a timing chart showing the operation of the engine control ECU 101 at the time of startup.

  5A shows the voltage waveform of the power supply voltage for the microcomputer, FIG. 5B shows the first reset signal, FIG. 5C shows the oscillation stabilization signal, FIG. 5D shows the oscillation signal waveform of the oscillator 175a, and FIG. 5E shows the reference clock signal. , (F) is an operation clock signal of the main microcomputer 110, (g) is an operation clock signal of the sub-microcomputer 140, (h) is a count signal, (i) is a waveform indicating the operation state of the CPU 111, and (j) is a third signal. A reset signal (k) is a waveform indicating the operating state of the CPU 141. When the waveform indicating the operation state of the CPU 111 (CPU 141) is at a high level, the CPU 111 (CPU 141) is in an operating state, and when the waveform is at a low level, it indicates an inactive state. ing.

  First, when an ignition switch (not shown) is turned on and the power supply voltage from the DC power supply VB is supplied to start the engine control ECU 101 (see time T11 in FIG. 5), as shown in FIG. The power supply voltage gradually rises from 0 V, and the oscillator 175a starts outputting the oscillation signal (see time T12 in FIG. 5D). When the value of the microcomputer power supply voltage reaches the predetermined determination voltage value V1 (2.5 V) after the start of the oscillation signal output (time T12), the voltage monitoring unit 173 outputs the first reset signal (FIG. 5). (See time T13 in (b)).

  Further, the counter 177a in the oscillation state determination unit 177 starts outputting a count signal that counts up according to the reference clock signal (see time T2 in FIG. 5 (h)). Thereafter, when the count value of the count signal reaches a predetermined oscillation state determination value C11 (see time T14 in FIG. 5 (h)), the comparison circuit 177b of the oscillation state determination unit 177 changes the oscillation stabilization signal from the low level to the high level. (See time T14 in FIG. 5C). That is, when the count value of the count signal reaches the predetermined oscillation state determination value C11, it is determined that the oscillation state of the reference clock signal is stable. In addition, the time t11 (refer FIG.5 (b)) from the time T13 to the time T14 is about 20 ms, for example.

  In addition, since the first reset signal is at the high level before the oscillation stabilization signal becomes the high level, the AND circuit 195 sets the second reset signal to the high level when the oscillation stabilization signal becomes the high level. To do. When a predetermined DPLL stabilization time t12 (3 ms in the present embodiment) elapses after the second reset signal becomes High level, the reset state of the CPU 111 is released and the CPU 111 starts operation (FIG. 5 (i ) (See time T15). The predetermined DPLL stabilization time t12 is a time for delaying the start of the operation of the CPU 111 until the operation of the DPLL circuit 121 is stabilized after the high level of the second reset signal.

  Further, when a predetermined initialization processing time t13 (2 ms in this embodiment) elapses after the reset state of the CPU 111 is released, the CPU 111 changes the third reset signal from the low level to the high level (FIG. 5). (See time T16 in (j)). That is, since the second reset signal is at the high level before the third reset signal is at the high level, the AND circuit 190 sends the fourth reset signal to the high level when the third reset signal is at the high level. To level. The predetermined initialization processing time t13 is an initialization process for setting a master / slave relationship between the main microcomputer 110 and the sub-microcomputer 140 (for initial setting of RAM, registers, etc.). This is the time for the sub-microcomputer 140 to operate before it operates.

  When a predetermined DPLL stabilization time t14 (3 ms in the present embodiment) elapses after the fourth reset signal becomes High level, the reset state of the CPU 141 is released and the CPU 141 starts operation (FIG. 5 ( (See time T17 of k)). The predetermined DPLL stabilization time t14 is a time for delaying the start of the operation of the CPU 141 until the operation of the DPLL circuit 151 is stabilized after the fourth reset signal becomes High level.

  In the engine control ECU 101 of this embodiment configured as described above, the main microcomputer 110 and the sub-microcomputer 140 are provided with the DPLL circuit 121 and the DPLL circuit 151, respectively. The frequency of the reference clock signal transmitted between the sub-microcomputers 140 can be made lower than the predetermined first operating frequency (64 MHz) and the predetermined second operating frequency (32 MHz). For this reason, the influence of noise can be reduced as compared with the case where the reference clock signals having the predetermined first operating frequency and the predetermined second operating frequency are transmitted to the main microcomputer 110 and the sub microcomputer 140, respectively. Therefore, the reliability of the operation of the main microcomputer 110 and the sub microcomputer 140 can be improved.

When the number of oscillations from the start of oscillation of the reference clock signal output from the clock oscillation circuit 175 reaches the predetermined oscillation state determination value C11, the CPU 141 starts operation.
That is, the engine control ECU 101 according to the present embodiment monitors the oscillation state of the reference clock signal, and until the engine control ECU 101 is activated and the oscillation state shifts from unstable to stable, the main microcomputer 110 and the sub microcomputer 140 Prohibit operation.

  That is, since the oscillation state of the reference clock signal is monitored, it is possible to prevent the main microcomputer 110 and the sub-microcomputer 140 from starting operation even though the oscillation state of the reference clock signal is unstable. . Therefore, the reliability of the operation of the main microcomputer 110 and the sub microcomputer 140 can be improved.

  The clock oscillation circuit 175 is provided in the power supply IC 170. For this reason, the main microcomputer 110 and the sub microcomputer 140 can be reduced in size because the main microcomputer 110 and the sub microcomputer 140 are not provided with the clock oscillation circuit 175. Further, the power supply IC 170 receives a power supply voltage having a voltage value higher than the microcomputer power supply voltage, and obtains a microcomputer power supply voltage by stepping down the power supply voltage. Therefore, the clock oscillation circuit 175 can be operated at a voltage higher than the microcomputer power supply voltage. That is, the clock oscillation circuit 175 can be operated more stably than when the clock oscillation circuit 175 is provided in the main microcomputer 110 and the sub microcomputer 140.

  Further, since the main microcomputer 110 and the sub-microcomputer 140 are arranged close to the power supply IC 170, the lengths of the clock lines LC1 and LC2 are short. Further, the clock line LC1 is configured as a coplanar line, and the clock line LC2 is configured as a coplanar line and a microstrip line. Therefore, the reference clock signal transmitted through the clock line LC1 and the clock line LC2 is not easily affected by noise generated from the surroundings.

  In the embodiment described above, the engine control ECU 101 is the electronic control device according to the present invention, the main microcomputer 110 and the sub-microcomputer 140 are the microcomputer according to the present invention, the clock oscillation circuit 175 is the oscillation means according to the present invention, the DPLL circuit 121 and the DPLL circuit 151. Is the multiplication means in the present invention, the oscillation state determination unit 177 is the operation prohibiting means in the present invention, the power supply IC 170 is the power supply means in the present invention, the clock lines LC1 and LC2 are the reference clock signal transmission lines in the present invention, the predetermined first operating frequency The predetermined second operating frequency is the predetermined operating frequency in the present invention.

(Third embodiment)
A third embodiment will be described below with reference to the drawings. In the third embodiment, only the parts different from the second embodiment will be described.

The engine control ECU 201 in the third embodiment is different from the engine control ECU 101 in the second embodiment in that a power supply IC 270 is provided instead of the power supply IC 170.
Therefore, the configuration of the power supply IC 270 will be described with reference to FIG. 6 and FIG. FIG. 6 is a block diagram showing the configuration of the engine control ECU 201, and FIG. 2C is a block diagram showing the configuration of the oscillation state determination unit 277.

  As shown in FIG. 6, the power supply IC 270 determines a voltage adjustment unit 171, a voltage monitoring unit 173, a clock oscillation circuit 275 that generates a reference clock signal, and an oscillation state of an oscillation signal output from the clock oscillation circuit 275. And an oscillation state determination unit 277 that performs the operation. The clock oscillation circuit 275 includes an oscillator 275a disposed outside the power supply IC 270, an oscillator 275b that drives the oscillator 275a and outputs an oscillation signal having a predetermined frequency (1 MHz in the present embodiment), and an oscillator. A CR oscillation circuit 275c that outputs an oscillation signal having a frequency lower than that of the oscillation signal output from 275b for backup.

  Further, as shown in FIG. 2C, the oscillation state determination unit 277 performs an up-counting operation according to an oscillation signal from the oscillation unit 275b (hereinafter referred to as an oscillation unit oscillation signal), and a signal corresponding to the count value. The counter 277a that outputs (hereinafter referred to as the first count signal), the count value indicated by the first count signal input from the counter 277a and the predetermined oscillation state determination value C11 are compared, and this count value is determined as the predetermined oscillation. When the oscillation stabilization signal is smaller than the state determination value C11, the oscillation stabilization signal is set to the Low level, and when it is greater than the predetermined oscillation state determination value C11, the oscillation stabilization signal is set to the High level and the oscillation unit oscillation signal from the oscillation unit 275b. The counter counts up and outputs a signal corresponding to the count value (hereinafter referred to as the second count signal). 277c and a count value indicated by the second count signal from the counter 277c (hereinafter referred to as a second count value) and a predetermined switching determination value C12 set in advance, and based on the comparison result, A comparison circuit 277d that outputs to the input / output port 119 and the input / output port 149 a reference clock selection signal indicating that an oscillation signal from the CR oscillation circuit 275c (hereinafter referred to as a CR oscillation signal) is output as a reference clock signal; The changeover switch 277e that receives the part oscillation signal and the CR oscillation signal and outputs either the oscillation part oscillation signal or the CR oscillation signal to the DPLL circuit 121 and the DPLL circuit 151 as a reference clock selection signal based on the reference clock selection signal. It consists of.

  The counter 277c receives the CR oscillation signal and resets the second value (sets it to 0) at the rising edge timing of the CR oscillation signal. Further, the comparison circuit 277d receives the CR oscillation signal, and compares the second count value with the predetermined switching determination value C12 at the timing of the falling edge of the CR oscillation signal. The predetermined switching determination value C12 is the counter 277c during the period from when the CR oscillation signal rises to when it falls (that is, 1/2 period of the CR oscillation signal) when the oscillation unit oscillation signal is normally oscillated. Is set slightly smaller than the value counted by.

  The comparison circuit 277d sets the reference clock selection signal to a low level when the second count value is larger than the predetermined switching determination value C12, and the reference clock selection signal when the second count value is smaller than the predetermined switching determination value C12. Is set to High level.

The changeover switch 277e switches so as to output the oscillation unit oscillation signal when the reference clock selection signal is at the Low level and output the CR oscillation signal when the reference clock selection signal is at the High level.
Further, the CPU 111 and the CPU 141 are configured to determine that the oscillation unit oscillation signal is abnormal when the reference clock selection signal becomes High level, and to execute processing corresponding to the abnormality. The processing corresponding to the abnormality is, for example, abnormality information storage processing or fail-safe processing.

  Next, in order to explain the method of determining the oscillation signal switching executed by the oscillation state determination unit 277, the operation of the oscillation state determination unit 277 when the oscillation signal output of the oscillator 275a stops halfway is described based on FIG. I will explain. FIG. 7 is a timing chart for illustrating the operation of the oscillation state determination unit 277.

  7A shows an oscillation signal waveform of the oscillator 275a, FIG. 7B shows an oscillation unit oscillation signal, FIG. 7C shows a second count signal, FIG. 7D shows a CR oscillation signal, FIG. 7E shows a reference clock selection signal, f) is a reference clock signal output from the changeover switch 277e.

  First, when the oscillator 275a outputs an oscillation signal (from the time when the engine control ECU 201 is activated until time T28 (see FIG. 7A)), the oscillation unit oscillation signal is output (FIG. 7B). The counter 277c outputs a second count signal that is up-counted according to the input of the oscillation unit oscillation signal (see FIG. 7C). At this time, the second count value is reset at the timing when the CR oscillation signal changes from the low level to the high level (see times T21, T23, T25, T27, and T30 in FIGS. 7C and 7D). . Furthermore, an oscillation unit oscillation signal is output as a reference clock signal from the changeover switch 277e (see FIG. 7F).

  Note that the comparison circuit 277d compares the second count value with the predetermined switching determination value C12 at the timing when the CR oscillation signal changes from the High level to the Low level (time T22 in FIGS. 7C and 7D). (See T24 and T26). At times T22, T24, and T26, since the second count value is larger than the predetermined switching determination value C12, the reference clock selection signal is set to the low level (see FIG. 7E).

  When the oscillation signal output from the oscillator 275a is stopped (see time T28 in FIG. 7A), the output of the oscillation unit oscillation signal is also stopped (see time T28 in FIG. 7B). The value is fixed to the value at time T28 (see time T28 in FIG. 7C).

  Thereafter, when the comparison circuit 277d compares the second count value with the predetermined switching determination value C12 at the timing when the CR oscillation signal changes from the Low level to the High level, the second count value is smaller than the predetermined switching determination value C12 ( The reference clock selection signal is set to a high level (see time T29 in FIG. 7E).

  When the reference clock selection signal becomes High level, a CR oscillation signal is output as a reference clock signal from the changeover switch 277e (see time T29 and thereafter in FIG. 7F).

  In the engine control ECU 201 of this embodiment configured as described above, even if the oscillation state of the oscillation unit oscillation signal is abnormal, the CR oscillation signal is output as the reference clock signal, so that the operation clock based on the CR oscillation signal The main microcomputer 110 and the sub microcomputer 140 can be operated in synchronization with the signal. For this reason, when the oscillation state of the oscillation unit oscillation signal is abnormal, it is possible to prevent the main microcomputer 110 and the sub-microcomputer 140 from stopping operation or performing unexpected operations.

  In addition, the CPU 111 and the CPU 141 know that the oscillation state of the oscillation unit oscillation signal is abnormal when the reference clock selection signal becomes High level, and execute processing corresponding to the abnormality. Even if the microcomputer 140 operates using a CR oscillation signal having a frequency lower than that of the oscillation unit oscillation signal as an operation clock signal, it is possible to suppress an unexpected operation.

  In the embodiment described above, the engine control ECU 201 is the electronic control device according to the present invention, the clock oscillation circuit 275, the counter 277c, the comparison circuit 277d and the changeover switch 277e are the oscillation means according to the present invention, and the counter 277a and the comparison circuit 277b are according to the present invention. The operation prohibiting means, the power supply IC 270 is the power supply means in the present invention, the oscillator 275a and the oscillation section 275b are the first oscillation section in the present invention, the CR oscillation circuit 275c is the second oscillation section in the present invention, the counter 277c and the comparison circuit 277d are It is an alerting | reporting means in this invention.

The oscillation unit oscillation signal is the first reference clock signal in the present invention, and the CR oscillation signal is the second reference clock signal in the present invention.
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, As long as it belongs to the technical scope of this invention, a various form can be taken.

For example, in the present embodiment, an electronic control device including two microcomputers is shown, but an electronic control device including three or more microcomputers may be used.
Moreover, in this embodiment, what applied this invention to engine control ECU which performs engine control was shown. However, in general, a vehicle performs various types of control such as transmission control in addition to engine control using a large number of microcomputers. For this reason, you may apply this invention to the microcomputer used by other control of engine control.

The block diagram which shows the structure of engine control ECU1. The block diagram which shows the structure of the oscillation state determination part 25,177,277. The timing chart which shows operation | movement of engine control ECU1. The block diagram which shows the structure of engine control ECU101. 4 is a timing chart showing the operation of the engine control ECU 101. The block diagram which shows the structure of engine control ECU201. 8 is a timing chart showing the operation of the oscillation state determination unit 277. Explanatory drawing which shows arrangement | positioning of the component of engine control ECU101.

Explanation of symbols

  1, 101, 201 ... Engine control ECU, 10, 110 ... Main microcomputer, 11, 41, 111, 141 ... CPU, 13, 43, 113, 143 ... ROM, 15, 45, 115, 145 ... RAM, 17, 47 , 117, 147 ... A / D converters, 19, 49, 119, 149 ... I / O ports, 21, 175, 275 ... clock oscillation circuits, 21a, 175a, 275a ... oscillators, 21b, 175b, 275b ... oscillation units , 23, 51, 121, 151... DPLL circuit, 25, 177, 277... Oscillation state determination unit, 25a, 177a, 277a, 277c... Counter, 25b, 177b, 277b, 277d. 153: Bus, 40, 140 ... Sub-microcomputer, 47 ... A / D converter, 49 ... I / O port, 70, 170, 70 ... Power supply IC, 71,171 ... Voltage adjustment unit, 73,173 ... Voltage monitoring unit, 90,190,195 ... AND circuit, 275c ... CR oscillation circuit, 277e ... Changeover switch, B1 (B1a, B1b, B1c) ... Substrate, L1... Signal line, LC1, LC2... Clock line, LG1, LG2, LG3.

Claims (9)

An electronic control device comprising a plurality of microcomputers that operate in synchronization with an operation clock signal having a preset predetermined operation frequency,
Oscillating means for outputting a reference clock signal that oscillates at a frequency set lower than the predetermined operating frequency;
Each of the plurality of microcomputers includes a multiplying unit that multiplies the frequency of the reference clock signal output from the oscillating unit to the predetermined operating frequency, and the reference clock signal multiplied by the multiplying unit is used as the operation clock signal. ,
An electronic control device characterized by that. The oscillation state of the reference clock signal output by the oscillating means is monitored, and the operation of the plurality of microcomputers is prohibited until the electronic control unit is activated and the oscillation state shifts from unstable to stable. Provided with operation prohibition means,
The electronic control device according to claim 1. The oscillation means is provided in any one of the plurality of microcomputers.
The electronic control device according to claim 1, wherein the electronic control device is an electronic control device. Power supply means for supplying power to each of the plurality of microcomputers;
The oscillation means is provided in the power supply means.
The electronic control device according to claim 1, wherein the electronic control device is an electronic control device. The oscillating means generates a first reference clock signal that oscillates at a frequency set lower than the predetermined operating frequency, and a second reference clock signal that oscillates at a frequency set lower than the predetermined operating frequency. A second oscillation unit for generating the first reference clock signal, and monitoring the oscillation state of the first reference clock signal, and outputting the first reference clock signal as the reference clock signal when the oscillation state is normal, When the oscillation state is abnormal, the second reference clock signal is output as the reference clock signal.
The electronic control device according to any one of claims 1 to 4, wherein A frequency of the second reference clock signal is set lower than the first reference clock signal;
In the case where the oscillation state of the first reference clock signal is abnormal, it is provided with an informing means for informing the microcomputer to that effect,
The plurality of microcomputers, when notified by the notification means that the oscillation state of the first reference clock signal is abnormal, executes processing corresponding to the abnormality of the oscillation state of the first reference clock signal.
The electronic control device according to claim 5. At least one of the plurality of microcomputers is disposed in proximity to the oscillating means;
The electronic control device according to claim 1, wherein the electronic control device is an electronic control device. The reference clock signal transmission line for transmitting the reference clock signal from the oscillating means to the plurality of microcomputers comprises a microstrip line or a coplanar line.
The electronic control device according to any one of claims 1 to 7, wherein The electronic control device is mounted on a vehicle.
The electronic control device according to claim 1, wherein the electronic control device is a device.

Images