JP2005295460A - Filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a filter circuit in which total circuit scale is not extremely increased, a filter characteristic frequency is made variable using a simple method and a fine resolution of about 1% of a signal bandwidth over 100 times or more and further, a frequency varying step is proportional to the filter characteristic frequency. <P>SOLUTION: In an R-2R resistor circuit network 12, a path where each branched current is made to flow to an integrator capacitor 14 of the next stage and a path where each branched current is made to flow to a low-impedance analog midpoint (ground potential) Vss, and a path can be selected for each branched current by digital control bit data Bn-B<SB>0</SB>. Thus, a characteristic frequency of a filter including an integrator as its component is variable at the interval of (1/2<SP>n+1</SP>)(Gm1)/Cf from (1/2<SP>n+1</SP>)(Gm1)/Cf to ((2<SP>n+1</SP>-1)/2<SP>n+1</SP>)(Gm1)/Cf, and a setting bit width is made into 7(n=6) at a maximum, thereby easily realizing a 100-times or more characteristic frequency variation width as a result. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a filter circuit such as a continuous-time analog integrated filter circuit, and more particularly to a Gm-C (Transconductance-C) filter circuit including an integrator as a constituent element, and relates to a cut-off frequency, a pole, and a zero. This relates to a method of realizing a method that can change the filter characteristic frequency over 100 times or more with a minute resolution of about 1% of the signal bandwidth.

Conventionally, as an analog integrated filter mainly using active elements, discrete-time filters represented by switched-capacitor filters (SCF) and transconductance-capacitances (Gm-C: Transconductance-C) A continuous time filter represented by a filter has been widely applied.
A discrete-time analog filter is based on a sampling operation using a clock, and its characteristic frequency varies and the reference clock frequency with extremely small fluctuations is determined by the ratio of capacitance element values with good matching. There is an advantage that a high filter characteristic frequency can be easily obtained.
On the other hand, a pre-filter for preventing aliasing due to sampling operation is indispensable, and a broadband operational amplifier is necessary to achieve circuit settling within a clock cycle. There is a drawback that power consumption tends to increase.

On the other hand, the continuous-time filter is based on open-loop operation like the Gm-C filter, can be configured without using an operational amplifier, is suitable for speeding up, and naturally has no aliasing problem.
For this reason, it can be said that a Gm-C filter, a MOSFET-C filter, etc., or a series of continuous time filters derived therefrom are particularly suitable for use in high-speed filters.

For example, in a signal reproduction system from an optical disk such as a CD (Compact Disk) or a DVD (Digital Versatile Disk), an equalization filter is used as preprocessing for converting a reproduction signal into a digital signal, and the continuous time filter is used.
The main purpose of this filter is to correct the pit pattern information distorted in the photoelectric conversion path by the frequency-gain characteristics of the filter and reproduce the pit pattern sequence written on the disc at a low error rate. is there.

The reproduction signal from the optical disc has a signal frequency bandwidth corresponding to the physical length of a pit or the like formed on the disc. On the other hand, the reproduction frequency itself changes according to the rotational speed or linear velocity of the disk during reproduction. For example, if playback is performed with the disc rotation speed doubled, the playback signal on the same disc track has a double frequency.
Optical disks such as CDs and DVDs are generally used for reproduction at several tens of times the standard reproduction frequency (in other words, the number of disk rotations) in order to shorten data transfer between storage media and transfer time during buffer reproduction. In this case, the characteristic frequency of the equalizing filter must also be proportional to the disk rotational speed.

Specifically, the cut-off frequency of the equalization filter at the time of standard reproduction of CD (CD 1 × speed) is about 0.7 MHz, the time of DVD standard reproduction (DVD 1 × speed) is about 4 MHz, and the DVD 16 × speed is about 70 MHz. .
Therefore, if a signal processing system capable of reproducing from CD 1 × speed to DVD 16 × speed is to be realized by a common equalization filter, the filter cutoff frequency needs to have a variable width of 100 times.

However, these continuous-time filters have basic parameters that determine their characteristic frequency, such as their cut-off frequency, pole, and zero, for example, gm / C (where gm is transconductance, C represents the integrator capacity), and the value of gm is determined by taking over the characteristics of the transconductance of the transistor itself as its circuit element. For example, in the case of a MOS transistor, the transconductance gm _MOS of the transistor itself is expressed by the following equation. Is done.

(Equation 1)
gm _MOS = 2K (V _GS -V _TH )

In other words, the fact that the integrator gm is variable by 100 times means that the transconductance gm _MOS of the transistor itself that is the circuit element is variable by 100 times. Here, K is a constant, V _GS is a gate-source bias potential, and V _TH is a threshold voltage determined at the time of manufacture.

As is apparent from the fact that K is normally expressed as K = (1/2) μC _OX (W / L), it is determined by the physical size of the transistor, the channel width W and the channel length L, and the carrier mobility μ and the gate oxide film The capacitance Cox is an invariable parameter in circuit design as a value unique to the element.

Actually, since the transistor characteristics do not change linearly with respect to the channel length L, the gm variable control by L has poor controllability, and the channel length L is fixed and the channel width W is varied to vary the gm _MOS . However, with respect to W as well, the transistor characteristics do not follow linearly in the region from the lower limit value to several times the lower limit value, and the lower limit size that can be used as transconductance is determined.
Since the physical size W cannot be changed at the time of circuit operation after manufacturing, in practice, a circuit having a certain reference size is made and operated in parallel as shown in FIG. 8 to obtain an integer ratio gm. .
However, for example, if it is intended to have a variable gm width of 100 times as described above, the number of circuits of the reference size installed in parallel becomes enormous, and in particular, the increase in parasitic capacitance due to parallelization is caused by the integrator capacitance value itself. It makes control difficult.

On the other hand, the variable width of V _GS is about 2 to 5 times at most. The lower limit of V _GS is determined by the distortion characteristics (or input dynamic range), and the upper limit is determined by the bias setting allowed from the power supply voltage and circuit configuration. Also, the gm characteristic with respect to V _GS is not actually linear.
Usually, as shown in FIG. 9, a method of changing the bias current of the transconductor Gm by a digital analog converter (DAC) is adopted.

Since the integrator capacity C cannot be changed during circuit operation after manufacturing, as in the case of W, the basic parameter gm / C is changed by appropriately switching the connection combination of reference capacitors prepared in parallel. It will be.
Also in this case, the capacitance value variable width means an element size variable width, which causes an increase in parasitic capacitance and an overall element size.

Furthermore, there may be a method of changing K, V _GS , and C at the same time. However, because of nonlinearity with respect to the gm value including the change of the parasitic capacitance, the gm value, the cut-off frequency, the pole, zero ( It is extremely difficult to change the characteristic frequency such as zero) linearly.
As a result, it is difficult to achieve the intended purpose of setting the filter characteristic frequency to a desired value including temperature change, power supply voltage fluctuation, and element variation.

Further, as described above, the reproduction signal from the optical disc has a signal frequency bandwidth corresponding to the physical length of pits formed on the disc. For example, if the playback medium (for example, CD or DVD) is determined and the disk rotation speed during playback is determined, the playback signal frequency has a bandwidth about 4 to 5 times.
As an example, in DVD 16 × speed, the reproduction signal has a signal bandwidth of about 16 MHz to 70 MHz. The effect of waveform shaping by the equalization filter varies depending on the setting of the cutoff frequency of the filter, and frequency setting in units of about 1% of the bandwidth is required.
The frequency setting increment is about 0.5 MHz in the above-mentioned DVD 16-times speed example, and about 5 kHz in the CD 1-times speed.
For this reason, it is difficult or undesirable to make the maximum reproduction signal frequency (70 MHz here) variable with the smallest possible frequency step width (here, about 5 kHz), which is not desirable. It is desirable that a method proportional to the band, that is, a logarithmic linear setting can be set.

  From the above, for applications that require a characteristic frequency variable width of 100 times or more, such as optical disc playback systems such as CD and DVD, a plurality of equalization filters are prepared and switched to increase the circuit scale and signal processing. It was complicated.

  From the above circumstances, regarding a continuous time analog integrated filter, in particular, a filter including an integrator composed of a transconductor Gm and a capacitor C as a component, the total circuit scale does not increase remarkably, and the cutoff frequency, pole (Pole), zero (zero) filter characteristic frequency over 100 times, and a mechanism that can be varied with a minute resolution of about 1% of the signal bandwidth, and further the frequency variable step is proportional to the filter characteristic frequency, There has been a demand for a mechanism in which the frequency variable step is logarithmically linear with respect to the filter characteristic frequency.

  The object of the present invention is that the total circuit scale does not increase remarkably, and the filter characteristic frequency can be varied by 100 times or more and with a minute resolution of about 1% of the signal bandwidth by a simple method. Is to provide a filter circuit proportional to the filter characteristic frequency.

  In order to achieve the above object, a first aspect of the present invention provides a transconductance that outputs a current proportional to an input voltage and an output of the transconductance according to characteristic frequency setting bit data having a width of (n + 1) bits. A resistor network that varies the characteristic frequency of the current with an accuracy of a bit width of (n + 1), an operational transconductance amplifier having an input terminal connected to the current output line of the resistor network, and an input of the operational transconductance amplifier An integrator capacitor connected between the terminal and the output terminal, and the resistor network includes (n + 1) branch nodes formed in a current propagation line for propagating the output current of the transconductance. , N first resistance elements connected between the branch nodes, respectively, and the corresponding (N + 1) second resistance elements each having one end connected to the branch node, a third resistance element connected between the branch node at the final stage and the low impedance analog midpoint potential, and the (n + 1) ) Bit width characteristic frequency setting (n + 1) switch circuits for connecting the other end of the second resistance element to the current output line or the low impedance analog midpoint potential according to the corresponding bit data of the bit data The resistance values of the second and third resistance elements are set to a multiple of the resistance value of the first resistance element.

  Preferably, the transconductance, the resistor network, the operational transconductance amplifier, and the integrator capacitor all have a differential configuration, and the resistor network and the input of the operational transconductance amplifier are output from the transconductance output. Is set by a common mode feedback circuit provided at the output section of the transconductance.

  According to a second aspect of the present invention, the characteristic frequency of the output current of the transconductance is set to (n + 1) according to the transconductance for outputting a current proportional to the input voltage and the characteristic frequency setting bit data having a width of (n + 1) bits. ), A resistor network that can be varied with an accuracy of bit width, a current follower having an input terminal connected to the current output line of the resistor network, and an integrator capacitance connected to the output terminal of the current follower. The resistance network includes (n + 1) branch nodes formed in a current propagation line for propagating the output current of the transconductance, and n first nodes connected between the branch nodes, respectively. A resistance element, (n + 1) second resistance elements each having one end connected to the corresponding branch node, and the branch node in the final stage The other end of the second resistance element corresponding to the third resistance element connected between the impedance analog midpoint potential and the bit data corresponding to the characteristic frequency setting bit data of the width of (n + 1) bits. Are connected to the current output line or the low-impedance analog midpoint potential, and the resistance values of the second and third resistance elements are the resistance values of the first resistance elements. Is set to multiple times.

  Preferably, the transconductance, the resistor network, the current follower, and the integrator capacitance all have a differential configuration, and the common-mode potential of the resistor network and the input of the current follower is determined from the output of the transconductance. , Set by the common-mode potential of the input terminal of the current follower.

  According to a third aspect of the present invention, the characteristic frequency of the output current of the transconductance is set to (n + 1) according to the transconductance that outputs a current proportional to the input voltage and the characteristic frequency setting bit data having a width of (n + 1) bits. ) With variable bit width accuracy, a current follower with an input terminal connected to the current output line of the resistor network, and an operational transconductance with an input terminal connected to the output terminal of the current follower. An amplifier and an integrator capacitor connected between an input terminal and an output terminal of the operational transconductance amplifier, and the resistor network is formed in a current propagation line for propagating the output current of the transconductance Between the (n + 1) branch nodes and the above branch nodes. N first resistance elements connected, (n + 1) second resistance elements each having one end connected to the corresponding branch node, the branch node in the final stage, and a low impedance analog midpoint potential The other end of the corresponding second resistance element is connected to the current output line by the third resistance element connected between and the bit data corresponding to the characteristic frequency setting bit data of the width of (n + 1) bits. Or (n + 1) switch circuits connected to the low-impedance analog midpoint potential, and the resistance values of the second and third resistance elements are set to a multiple of the resistance value of the first resistance element. Has been.

  Preferably, the transconductance, the resistor network, the current follower, the operational transconductance amplifier, and the integrator capacitor all have a differential configuration, and the resistor network and the current follower of the current follower are output from the transconductance output. The input common-mode potential is set by the common-mode potential of the input terminal of the current follower.

  Preferably, the switch circuit of the resistor network includes an analog switch using a field effect transistor.

  Preferably, the switch circuit of the resistor network and the first, second, and third resistor elements are formed by an analog switch using a field effect transistor and an on-resistance of the field effect transistor.

  Preferably, the low-impedance analog midpoint potential is formed by a low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching.

According to the present invention, for example, it is connected to the Nth (N = n) th branch node, and is divided into the second resistance element having the resistance value 2R and the first resistance element having the resistance value R, and flows to the second resistance element. The current is selectively propagated to the input terminal of the operational transconductance amplifier through the low impedance analog midpoint potential or the current output line via the switch circuit that is independently switched by the Nth control bit data Bn.
On the other hand, the current flowing in the first resistance element having the resistance value R further includes the second resistance element having the resistance value 2R and the first resistance value R connected to the (N−1) -th branch node of the next stage. The current that is shunted to the resistance element and flows to the second resistance element is switched to a low impedance analog midpoint potential or current output line via a switch circuit that is independently switched by the (N-1) th control bit data Bn-1. Is selectively propagated to the input terminal of the operational transconductance amplifier.
On the other hand, the current flowing through the first resistance element having the resistance value R further includes the second resistance element having the resistance value 2R connected to the (N-2) th branch node of the next stage and the first resistance element having the resistance value R. The current that is shunted to the resistance element and flows to the second resistance element is switched to a low impedance analog midpoint potential or current output line via a switch circuit that is independently switched by the (N-2) th control bit data Bn-2. Is selectively propagated to the input terminal of the operational transconductance amplifier.
This is sequentially repeated, and the current flowing in the second resistance element is divided into the second resistance element having the resistance value 2R and the third resistance element having the resistance value 2R connected to the branch node in the final stage. The signal is selectively propagated to the input terminal of the operational transconductance amplifier through a low impedance analog midpoint potential or current output line via a switch circuit that is independently switched by data B ₀ .
On the other hand, the current flowing through the third resistance element is directly propagated to the low impedance analog midpoint potential.
Integrating capacitor is connected between the input and output terminals of the operational transconductance amplifier, by performing connection switching by the control bit data Bn～B ₀ appropriately, the signal current flowing into the integrating capacitor from the transconductance, the resulting frequency characteristic The width and accuracy of N + 1 bits are variable.

  According to the present invention, the total circuit scale does not increase remarkably, and the filter characteristic frequency such as the cut-off frequency, pole, and zero is increased by 100 times or more in a simple method, and 1% of the signal bandwidth. A mechanism that can be varied with a minute resolution and that the frequency variable step is proportional to the filter characteristic frequency, that is, the frequency variable step is logarithmically linear with respect to the filter characteristic frequency can be easily realized.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a first embodiment of a filter circuit according to the present invention.

As shown in FIG. 1, the filter circuit 10 includes the transconductance (Gm1) 11 that outputs a current i _X proportional to the input voltage Vi and the characteristic frequency setting bit data having a width of (n + 1) bits. An R-2R resistor network 12 in which the characteristic frequency of the output current of the transconductance is variable with an accuracy of (n + 1) bit width, and an operational transformer having an input terminal connected to the current output line of the R-2R resistor network 12 A conductance amplifier (0perational Transconductance Amplifier, hereinafter referred to as OTA) 13 and an integrator capacitance (Cf) 14 connected between an input terminal (−) and an output terminal of the OTA 13 are provided.
However, n is an integer of 1 or more.

As shown in FIG. 1, the R-2R resistor network 12 includes (n + 1) branch nodes 122-n to 122-0 formed in a current propagation line 121 that propagates the output current i _X of the transconductance 11. The n first resistance elements 123-n to 123-1 connected between the branch nodes 122-n to 122-0, respectively, and one ends connected to the corresponding branch nodes 122-n to 122-1, respectively. (N + 1) second resistance elements 124-n to 124-0, and a third node connected between the final branch node 122-0 and the low impedance analog midpoint potential (ground potential Vss). the resistive element 125, the corresponding bit data of the (n + 1) characteristics of the width of the bit frequency setting bit data Bn～B _0, the other end 124-n~124-0 the corresponding second resistive element electrostatic (N + 1) switch circuits 126-n to 126-0 connected to the current output line 127 or the low impedance analog midpoint potential Vss.
The resistance values of the first resistance elements 123-n to 123-1 are set to R, and the resistance values of the second resistance elements 124-n to 124-0 and the third resistance element 124 are the first resistance values. It is set to 2R, which is twice the resistance value R of the resistance elements 123-n to 123-1.

  More specifically, the first resistance element R123-n is connected between the branch nodes 122-n and 122-n-1, and between the branch nodes 122-n-1 and 122-n-2. The first resistance element R123-n-1 is connected, and similarly, the first resistance element R123-2 is connected between the branch nodes 122-2 and 122-1, and the branch nodes 122-1 and 122 are connected. A first resistance element R123-1 is connected between the gate terminal and −0.

One end of the second resistance element 124-n is connected to the branch node 122-n, and the other end is connected to the fixed contact a of the switch circuit 126-n. One end of the second resistance element 124-n-1 is connected to the branch node 122-n-1, and the other end is connected to the fixed contact a of the switch circuit 126-n-1. Similarly, one end of the second resistance element 124-2 is connected to the branch node 122-2, and the other end is connected to the fixed contact a of the switch circuit 126-2. One end of the second resistance element 124-1 is connected to the branch node 122-1, and the other end is connected to the fixed contact a of the switch circuit 126-1. One end of the second resistance element 124-0 is connected to the branch node 122-0, and the other end is connected to the fixed contact a of the switch circuit 126-0.
The operation contacts b of the switch circuits 126-n to 126-0 are connected to the current output line 127, and the operation contacts c are connected to the low impedance analog midpoint potential (ground potential) Vss.

In this configuration, the output current of the transconductance 11 is connected to the Nth (N = n) branch node 122-n, the second resistance element 124-n having the resistance value 2R, and the first resistance value R having the first resistance value R. The current that is shunted to the resistance element 123-n and flows to the second resistance element 124-n passes through the switch circuit 126-n that is independently switched by the Nth control bit data Bn, or the low impedance analog midpoint potential or It is selectively propagated through the current output line 127 to the input terminal (−) of the OTA 13.
On the other hand, the current flowing through the first resistance element 123-n having the resistance value R is further connected to the (N-1) th branch node 122-n-1 of the next stage, and the second resistance element having the resistance value 2R. 124-n-1 and the first resistance element 123-n-1 having a resistance value R, and the current flowing through the second resistance element 124-n-1 is the (N-1) th control bit data Bn. Is selectively propagated to the input terminal (−) of the OTA 13 through the low-impedance analog midpoint potential or current output line 127 via the switch circuit 126-n−1 that is independently switched by −1.
On the other hand, the current flowing through the first resistance element 123-n-1 having the resistance value R is further supplied to the second resistor having the resistance value 2R connected to the next (N-2) th branch node 122-n-2. The current that is shunted to the resistance element 124-n-2 and the first resistance element 123-n-2 having the resistance value R and flows to the second resistance element 124-n-2 is the (N-2) th control bit. The signal is selectively propagated to the input terminal (−) of the OTA 13 through the low impedance analog midpoint potential or current output line 127 via the switch circuit 126-n-2 that is independently switched by the data Bn-2.
This is sequentially repeated, and the current is shunted to the second resistance element 124-0 having the resistance value 2R and the third resistance element 125 having the resistance value 2R connected to the zeroth branch node 122-n-2. The current flowing through the element 124-0 is input to the input terminal (−) of the OTA 13 through the low impedance analog midpoint potential or current output line 127 via the switch circuit 126-0 that is independently switched by the _0th control bit data B _0. Is propagated selectively.
On the other hand, the current flowing through the third resistance element 125 is directly propagated to the low impedance analog midpoint potential.
Integrating capacitor 14 is connected between the input and output terminals of the OTA 13, by performing a connection switching by the control bit data Bn～B ₀ of the 0th to N-th appropriately, transconductance (Gm) 11 to integrating capacitor 14 And, as a result, the characteristic frequency is variable with a width and accuracy of N + 1 bits.

As described above, the R-2R resistor network 12 has a path through which each branch current flows to the integrator capacitor 14 of the next stage and a path through which the branch current flows to the low impedance analog midpoint potential (ground potential) Vss. It has become possible route selected by the digital control bit data Bn～B ₀ to.
Here, the set bit width (n + 1) is arbitrary, but as an example, if the set bit width is 5 (n = 4) in the figure, B4 = B2 = B0 = 0 and B3 = B1 = 1, and the integrator a current i _y = (10/32) i _x flowing into the capacitor 14.
That is, in this case, by setting the digital control bit data Bn～B _0, so that can be set in (1/32) from i _x to (31/32) i _x (1/32) i _x increments.
This is because the unity gain frequency of this integrator, and hence the characteristic frequency of the filter having this integrator as a component, is from (1/32) (Gm1) / Cf to (31/32) (Gm1) / Cf (1 / 32) It can be varied in increments of (Gm1) / Cf.

  When generalized, the unity gain frequency of the integrator is expressed by the following equation.

This is from (1/2 ^{n + 1} ) (Gm1) / Cf to ((2 ^{n + 1} -1) / 2 ^{n + 1} )) (Gm1) / Cf (1/2 ^{n + 1} ) (Gm1) / Cf indicates that it can be changed in steps.
Therefore, by setting the set bit width to 7 (n = 6) at most, a characteristic frequency variable width of 100 times or more can be easily realized.

  In other words, by constructing a filter with the integrator as a component (Gm-R2R-OTA-C filter), the total circuit scale does not increase significantly, and the cutoff frequency, pole, zero ( It is possible to realize a filter that can change the filter characteristic frequency such as zero) by 100 times or more and with a minute resolution of about 1% of the signal bandwidth.

In addition, for the sake of simplicity, a single-ended configuration is shown here, but it is practical to use an equivalent differential circuit as shown in FIG.
In this case, a common mode feedback circuit is provided in the transconductance (Gm1) 11, and the output common-mode potential of the transconductance 11 and thus the input common-mode potential of the R-2R resistor network 12 and the OTA 13 are set to a desired potential.
In the case of a differential configuration, the low-impedance analog midpoint (ground potential), which is one of the shunt paths of the R-2R resistor network 12, may be short-circuited between the positive-phase shunt path and the reverse-phase shunt path. It is not necessary to explicitly connect to a low impedance DC node.
Here, as the most practical example, the resistance constituting R-2R is realized by the on-resistance of a MOS switch, which is an insulated gate field effect transistor, as will be described later.

In FIG. 2, the reference numeral MR indicates a MOS switch having an on-resistance R. The MOS switch is composed of an n-channel MOS transistor.
In the case of the differential configuration, 121-1 and 121-2 are provided as current propagation lines, and 127-1 and 127-2 are provided as current output lines.
Therefore, the branch nodes also have 122-n-1 to 122-0-1 and 122-n-2 to 122-0-2, and the first resistance elements also have 123-n-1 to 123-0-1 and 123-n-2 to 123-0-2, and the second resistance element also includes 124-n-1 to 124-0-1 and 124-n-2 to 124-0-2.

  The switch circuit and the second resistance element arranged in each branch path are formed so as to share the four MOS switches MRn1 to MRn4 that also function as analog switches.

Specifically, the second resistance element 124-n includes the Nth branch node 122-n-1 of the current propagation line 121-1, and the Nth branch node 122-n-2 of the current propagation line 121-2. Two MOS switches MRn1 and MRn2 having a resistance value R are connected in series, a MOS switch MRn3 is connected between the branch node 122-n-1 and the current output line 127-1, and a branch node 122-n is connected. -2 and the current output line 127-2 are connected to the MOS switch MRn4.
The digital control bit data Bn is supplied to the gate terminals of the MOS switches MRn1 and MRn2 through the inverter 128-n, and directly supplied to the gate terminals of the MOS switches MRn3 and MRn4 without passing through the inverter 128-n.
Thereby, according to the digital control bit data Bn, the low-phase analog midpoint is realized by short-circuiting the normal-phase shunt path and the reverse-phase shunt path by the MOS switches MRn1 and MRn2, and via the MOS switch MRn3. The current propagating through the current propagation line 121-1 is selectively propagated to the input terminal (−) of the OTA 13 through the current output line 127-1, and the current propagating through the current propagation line 121-2 through the MOS switch MRn4 is defined as current. The signal is selectively propagated to the input terminal (+) of the OTA 13 through the output line 127-2.

The second resistance element 124-n-1 includes the (N-1) th branch node 122-n-1-1 of the current propagation line 121-1, and the (N-1) th node of the current propagation line 121-2. Two MOS switches MR (n-1) 1, MR (n-1) 2 having a resistance value R are connected in series between the branch node 122-n-1 -2, and the branch node 122-n-1 -1 is connected. And a current output line 127-1 are connected to a MOS switch MR (n-1) 3, and a MOS switch MR ((1) -2) is connected between a branch node 122- (n-1) -2 and a current output line 127-2. n-1) 4 is connected.
Then, the digital control bit data Bn-1 is supplied to the gate terminals of the MOS switches MR (n-1) 1 and MR (n-1) 2 through the inverter 128-n-1, and passed through the inverter 128-n-1. Without being supplied directly to the gate terminals of the MOS switches MR (n-1) 3 and MR (n-1) 4.
As a result, according to the digital control bit data Bn-1, the normal phase shunt path and the reverse phase shunt path are short-circuited by the MOS switches MR (n-1) 1 and MR (n-1) 2 to reduce the low impedance analog. The midpoint is realized, and the current propagating through the current propagation line 121-1 through the MOS switch MR (n-1) 3 is selectively propagated to the input terminal (-) of the OTA 13 through the current output line 127-1. Then, the current propagating through the current propagation line 121-2 through the MOS switch MR (n-1) 4 is selectively propagated to the input terminal (+) of the OTA 13 through the current output line 127-2.

Similarly, the second resistance element 124-2 is connected between the second branch node 122-2-1 of the current propagation line 121-1 and the second branch node 122-2-2 of the current propagation line 121-2. Two MOS switches MR21 and MR22 having a resistance value R are connected in series, a MOS switch MR23 is connected between the branch node 122-2-1 and the current output line 127-1, and a branch node 122-2- The MOS switch MR24 is connected between the current output line 127-2 and the current output line 127-2.
The digital control bit data B2 is supplied to the gate terminals of the MOS switches MR21 and MR22 through the inverter 128-2, and directly supplied to the gate terminals of the MOS switches MR23 and MR24 without passing through the inverter 128-2.
As a result, according to the digital control bit data B2, the MOS-phase switches MR21 and MR22 short-circuit the normal-phase side diversion path and the reverse-phase side diversion path to realize a low impedance analog midpoint, and via the MOS switch MR23. The current propagating through the current propagation line 121-1 is selectively propagated to the input terminal (−) of the OTA 13 through the current output line 127-1, and the current propagating through the current propagation line 121-2 through the MOS switch MR24 is defined as current. The signal is selectively propagated to the input terminal (+) of the OTA 13 through the output line 127-2.

The second resistance element 124-1 has a resistance value R between the second branch node 122-1-1 of the current propagation line 121-1 and the second branch node 122-1-2 of the current propagation line 121-2. Are connected in series, a MOS switch MR13 is connected between the branch node 122-1-1 and the current output line 127-1, and the branch node 122-1-2 and the current output are connected. A MOS switch MR14 is connected to the line 127-2.
The digital control bit data B1 is supplied to the gate terminals of the MOS switches MR11 and MR12 through the inverter 128-1, and directly supplied to the gate terminals of the MOS switches MR13 and MR14 without passing through the inverter 128-1.
As a result, according to the digital control bit data B1, the low-phase analog midpoint is realized by short-circuiting the normal-phase shunt path and the reverse-phase shunt path by the MOS switches MR11 and MR12, and via the MOS switch MR13. The current propagating through the current propagation line 121-1 is selectively propagated to the input terminal (−) of the OTA 13 through the current output line 127-1, and the current propagating through the current propagation line 121-2 through the MOS switch MR14 is converted into current. The signal is selectively propagated to the input terminal (+) of the OTA 13 through the output line 127-2.

The second resistance element 124-0 has a resistance value R between the second branch node 122-0-1 of the current propagation line 121-1 and the second branch node 122-0-2 of the current propagation line 121-2. Are connected in series, a MOS switch MR03 is connected between the branch node 122-0-1 and the current output line 127-1, and the branch node 122-0-2 and the current output are connected. A MOS switch MR04 is connected to the line 127-2.
The digital control bit data B0 is supplied to the gate terminals of the MOS switches MR01 and MR02 through the inverter 128-0, and directly supplied to the gate terminals of the MOS switches MR03 and MR04 without passing through the inverter 128-0.
As a result, according to the digital control bit data B0, the normal phase side shunt path and the reverse phase shunt path are short-circuited by the MOS switches MR01 and MR02 to realize a low impedance analog midpoint, and via the MOS switch MR03. The current propagating through the current propagation line 121-1 is selectively propagated to the input terminal (−) of the OTA 13 through the current output line 127-1, and the current propagating through the current propagation line 121-2 through the MOS switch MR <b> 04 is converted into current. The signal is selectively propagated to the input terminal (+) of the OTA 13 through the output line 127-2.

The third resistance element 125 has a resistance value R between the 0th branch node 122-0-1 of the current propagation line 121-1 and the 0th branch node 122-0-2 of the current propagation line 121-2. These two MOS switches MR are connected to each other.
That is, the low-impedance analog midpoint (ground potential) is realized by short-circuiting the normal-phase side shunt path and the reverse-phase side shunt path with the two MOS switches MR.

Further, as a well-known problem for the OTA-C portion, a feedforward path can be formed by the feedback capacitor C, and RHP-zero (Right Half Plane-zero) due to this deteriorates the high frequency characteristics.
This is a problem common to capacitive feedback, and in order to solve this problem, various methods have been devised from the beginning with Pole-Zero cancellation, and these can also be applied to the OTA-C portion of the present invention.
For example, the method introduced in the book “High Frequency Continuous Time Filters in Digital CMOS Processes” by Pavan and Tsividis (FIG. 3.11-13) is also applicable to the present invention, and details thereof will not be discussed here. The essence of the present invention is that the virtual ground of the OTA input is a current sink from the -2R resistor network 12.

Second Embodiment
FIG. 3 is a circuit diagram showing a second embodiment of the filter circuit according to the present invention.

  The filter circuit 10A according to the second embodiment is different from the filter circuit 10 according to the first embodiment in that an input of the current follower 15 is input instead of connecting an OTA to the current output line of the R-2R resistor network 12. This is because an integrator capacitor 14 is connected between the output terminal of the current follower (CF) 15 and the low impedance analog midpoint (ground potential).

In the second embodiment, the R-2R resistor network 12 has a path through which each branch current flows to the current follower 15 in the next stage and a path through which the branch current flows to a low impedance analog midpoint (ground potential). and it enables routing by the digital control bit Bn～B ₀ to. Here, the setting bit width n + 1 is arbitrary, and the setting method is the same as in the first embodiment.

  That is, when generalized, when the current gain of the current follower 15 is 1, the unity gain frequency of the integrator is expressed by the following equation.

This is from (1/2 ^{n + 1} ) (Gm1) / Cf to ((2 ^{n + 1} -1) / 2 ^{n + 1} )) (Gm1) / Cf (1/2 ^{n + 1} ) (Gm1) / Cf indicates that it can be changed in steps.
Therefore, by setting the set bit width to 7 (n = 6) at most, a characteristic frequency variable width of 100 times or more can be easily realized.

In other words, by constructing a filter (Gm-R2R-CF-C filter) using the integrator as an element, the total circuit scale does not increase remarkably, and the cutoff frequency, pole, zero ( It is possible to realize a filter that can change the filter characteristic frequency such as zero) by 100 times or more and with a minute resolution of about 1% of the signal bandwidth.
Further, by making the input / output current ratio of the current follower, that is, the current gain variable, it is possible to further widen the characteristic frequency variable range.

  In addition, here, for simplicity, a single-ended configuration is shown. However, as in the first embodiment, as shown in FIG. 4, it is practical to use a differential circuit equivalent to the single-ended configuration. In this case, the low-impedance input potential of the current follower 15 can set the output common-mode potential of the transconductance (Gm1) 11 and the common-mode potential of the R-2R resistor network 12.

<Third Embodiment>
FIG. 5 is a circuit diagram showing a third embodiment of the filter circuit according to the present invention.

In the third embodiment, a method in which the first embodiment and the second embodiment are combined is adopted.
That is, the integrator capacity portion of the second embodiment can be realized by OTA-C as in the first embodiment (Gm-R2R-CF-OTA-C filter). Specifically, the input terminal of the OTA 13 is connected to the output terminal of the current follower 15, and the integrator capacitor 14 is connected between the input terminal and the output terminal of the OTA 13.

  The advantage of the third embodiment is that the input impedance can be sufficiently lowered by the current follower (CF) 15, and that the DC gain of the integrator can be set very large by the OTA 13, that is, the first pole frequency is set low. Thus, even if the number of R-2R stages is increased and the characteristic frequency is set low, good integrator characteristics can be secured.

Since the input impedance of the R-2R resistor network 12 is R in common with the first to third embodiments, the equivalent transconductance of the transconductance (Gm1) 11 is g _m1 / ((R / Z _O1 ) +1).
Here, Z _O1 is the output impedance of the transconductance (Gm1) 11. From this, it is desirable that R is sufficiently small with respect to Z _O1 without lowering the equivalent transconductance and avoiding the influence of fluctuations in the output impedance Z _O1 .
As a result, it is advantageous that the R-2R resistor network is realized by only the on-resistance of the MOS switch itself, rather than explicitly switching the resistor elements, and the value of R can be reduced.
At this time, the signal voltage amplitude at the output node of the transconductance (Gm1) 11 can also be reduced, which is advantageous in that the on-resistance of the MOS switch can be used in an amplitude region with good linearity. .

FIG. 6 is a diagram illustrating integrator characteristics and characteristic parameters of the first to third embodiments. In FIG. 6, the horizontal axis indicates the frequency, and the vertical axis indicates the relative level.
Here, ω ₀ is the unity gain frequency, ω _P1 , ω _P2 and ω _P3 are the first Pole frequencies in the first, second and third embodiments, respectively, g _m1 and Z _O1 are the transconductance and output of the first-stage transconductor. Impedance, R is the input resistance of the 2-2R resistor network, Z _OCF is the output impedance of the current follower (CF) 15, g _m2 , Z _O2 are the transconductance and output impedance of the OTA 13, and Cf is the integrator capacitance .
This characteristic diagram is an example in which the high-frequency phase characteristic of OTA-C is improved by Pole-Zero cancellation as described above.

FIG. 7 is a diagram showing the gain characteristics of the equalization filter configured by the integrator of the present invention. In FIG. 7, the horizontal axis indicates the frequency, and the vertical axis indicates the relative level.
As can be seen from FIG. 7, a characteristic frequency variable width of 100 times or more can be easily obtained by setting the characteristic frequency control bit.
In the example shown in the figure, only one of the characteristic frequency control bits is sequentially set to 1, and the rest are all set to 0. The frequency variable step is logarithmically linear with respect to the filter characteristic frequency. Of course, by setting the control bits to any combination, the characteristic frequency is changed from (1/2 ^{n + 1} ) (Gm1) / Cf to ((2 ^{n + 1} −1) / 2 ^{n + as described above. 1} )) Variable to (Gm1) / Cf in steps of (1/2 ^{n + 1} ) (Gm1) / Cf.

1 is a circuit diagram showing a first embodiment of a filter circuit according to the present invention. FIG. 2 is a circuit diagram in which the filter circuit of FIG. 1 has a differential configuration. It is a circuit diagram which shows 2nd Embodiment of the filter circuit based on this invention. FIG. 4 is a circuit diagram in which the filter circuit of FIG. 3 has a differential configuration. It is a circuit diagram which shows 3rd Embodiment of the filter circuit based on this invention. It is a figure which shows the integrator characteristic and each characteristic parameter of each of the first to third embodiments. It is a figure which shows the gain characteristic of the equalization filter comprised by the integrator of this invention. It is a figure for demonstrating the 1st example of the conventional characteristic frequency variable method. It is a figure for demonstrating the 2nd example of the conventional characteristic frequency variable method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A, 10B ... Filter circuit, 11 ... Transconductance (Gm1), R-2R resistance network, 121 ... Current propagation line, 122-n to 122-0 ... Branch node, 123-n to 123-1 ... 1 resistor element, 124-n to 124-0 ... second resistor element, 125 ... third resistor element, 126-n to 126-0 ... switch circuit, 127 ... current output line, 13 ... operational transconductance amplifier (OTA), 14 ... integrator capacity, 15 ... current follower.

Claims (27)

A transconductance that outputs a current proportional to the input voltage;
(N + 1) bit width characteristic frequency setting Resistor network that varies the characteristic frequency of the output current of the transconductance with the accuracy of the bit width of (n + 1) according to bit data,
An operational transconductance amplifier having an input terminal connected to the current output line of the resistor network;
An integrator capacitor connected between an input terminal and an output terminal of the operational transconductance amplifier,
The resistor network is
(N + 1) branch nodes formed in a current propagation line for propagating the output current of the transconductance;
N first resistance elements respectively connected between the branch nodes;
(N + 1) second resistance elements each having one end connected to the corresponding branch node;
A third resistance element connected between the branch node at the final stage and the low impedance analog midpoint potential;
The (n + 1) -bit width characteristic frequency setting bit data corresponding to the bit data corresponding to the other end of the corresponding second resistance element is connected to the current output line or the low impedance analog midpoint potential (n + 1). And a switch circuit of
The filter circuit in which the resistance values of the second and third resistance elements are set to a multiple of the resistance value of the first resistance element. The transconductance, resistive network, operational transconductance amplifier, and integrator capacitance all have a differential configuration,
2. The filter circuit according to claim 1, wherein the common-mode potential of the input of the resistance network and the operational transconductance amplifier is set by a common mode feedback circuit provided at the output of the transconductance from the output of the transconductance. The filter circuit according to claim 1, wherein the switch circuit of the resistor network includes an analog switch using a field effect transistor. The filter circuit according to claim 2, wherein the switch circuit of the resistor network includes an analog switch using a field effect transistor. 2. The filter circuit according to claim 1, wherein the switch circuit of the resistor circuit network and the first, second, and third resistor elements are formed by an analog switch using a field effect transistor and an on-resistance of the field effect transistor. 3. The filter circuit according to claim 2, wherein the switch circuit of the resistor network and the first, second, and third resistor elements are formed by an analog switch using a field effect transistor and an on-resistance of the field effect transistor. The filter circuit according to claim 2, wherein the low-impedance analog midpoint potential is formed by a low-impedance connection in a differential signal by short-circuiting the branched positive-phase node and the negative-phase node. The filter circuit according to claim 4, wherein the low-impedance analog midpoint potential is formed by a low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching. The filter circuit according to claim 6, wherein the low-impedance analog midpoint potential is formed by a low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching. A transconductance that outputs a current proportional to the input voltage;
(N + 1) bit width characteristic frequency setting Resistor network that varies the characteristic frequency of the output current of the transconductance with the accuracy of the bit width of (n + 1) according to bit data,
A current follower having an input terminal connected to the current output line of the resistor network;
An integrator capacitor connected to the output terminal of the current follower,
The resistor network is
(N + 1) branch nodes formed in a current propagation line for propagating the output current of the transconductance;
N first resistance elements respectively connected between the branch nodes;
(N + 1) second resistance elements each having one end connected to the corresponding branch node;
A third resistance element connected between the branch node at the final stage and the low impedance analog midpoint potential;
The (n + 1) -bit width characteristic frequency setting bit data corresponding to the bit data corresponding to the other end of the corresponding second resistance element is connected to the current output line or the low impedance analog midpoint potential (n + 1). And a switch circuit of
The filter circuit in which the resistance values of the second and third resistance elements are set to a multiple of the resistance value of the first resistance element. The transconductance, resistor network, current follower, and integrator capacitance all have a differential configuration,
The filter circuit according to claim 10, wherein the common-mode potential of the input of the resistor network and the current follower is set by the common-mode potential of the input terminal of the current follower from the output of the transconductance. The filter circuit according to claim 10, wherein the switch circuit of the resistor network includes an analog switch using a field effect transistor. The filter circuit according to claim 11, wherein the switch circuit of the resistor network includes an analog switch using a field effect transistor. The filter circuit according to claim 10, wherein the switch circuit of the resistor network and the first, second, and third resistor elements are formed by an analog switch using a field effect transistor and an on-resistance of the field effect transistor. 12. The filter circuit according to claim 11, wherein the switch circuit of the resistor network and the first, second, and third resistor elements are formed by an analog switch using a field effect transistor and an on-resistance of the field effect transistor. The filter circuit according to claim 11, wherein the low-impedance analog midpoint potential is formed by a low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching. The filter circuit according to claim 13, wherein the low-impedance analog midpoint potential is formed by low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching. The filter circuit according to claim 15, wherein the low-impedance analog midpoint potential is formed by low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching. A transconductance that outputs a current proportional to the input voltage;
(N + 1) bit width characteristic frequency setting Resistor network that varies the characteristic frequency of the output current of the transconductance with the accuracy of the bit width of (n + 1) according to bit data,
A current follower having an input terminal connected to the current output line of the resistor network;
An operational transconductance amplifier having an input terminal connected to the output terminal of the current follower;
An integrator capacitor connected between an input terminal and an output terminal of the operational transconductance amplifier,
The resistor network is
(N + 1) branch nodes formed in a current propagation line for propagating the output current of the transconductance;
N first resistance elements respectively connected between the branch nodes;
(N + 1) second resistance elements each having one end connected to the corresponding branch node;
A third resistance element connected between the branch node at the final stage and the low impedance analog midpoint potential;
The (n + 1) -bit width characteristic frequency setting bit data corresponding to the bit data corresponding to the other end of the corresponding second resistance element is connected to the current output line or the low impedance analog midpoint potential (n + 1). And a switch circuit of
The filter circuit in which the resistance values of the second and third resistance elements are set to a multiple of the resistance value of the first resistance element. All of the above transconductance, resistor network, current follower, operational transconductance amplifier, and integrator capacitance have a differential configuration,
The filter circuit according to claim 19, wherein the common-mode potential of the input of the resistor network and the current follower is set by the common-mode potential of the input terminal of the current follower from the output of the transconductance. The filter circuit according to claim 19, wherein the switch circuit of the resistor network includes an analog switch using a field effect transistor. The filter circuit according to claim 20, wherein the switch circuit of the resistor network includes an analog switch using a field effect transistor. The filter circuit according to claim 19, wherein the switch circuit of the resistor network and the first, second, and third resistor elements are formed by an analog switch using a field effect transistor and an on-resistance of the field effect transistor. The filter circuit according to claim 20, wherein the switch circuit of the resistor circuit network, and the first, second, and third resistor elements are formed by an analog switch using a field effect transistor and an on-resistance of the field effect transistor. The filter circuit according to claim 20, wherein the low-impedance analog midpoint potential is formed by a low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching. The filter circuit according to claim 22, wherein the low-impedance analog midpoint potential is formed by low-impedance connection in a differential signal by short-circuiting the branched positive-phase node and the negative-phase node. The filter circuit according to claim 24, wherein the low-impedance analog midpoint potential is formed by a low-impedance connection in a differential signal by short-circuiting the positive-phase node and the negative-phase node after branching.

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