JP2005294663A - Method of wiring semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of wiring a semiconductor integrated circuit where crosstalk measures can effectively be introduced at proper costs. <P>SOLUTION: A wiring which is the most excellent in crosstalk resistance characteristic in a plurality of kinds of usable wirings is assigned to a wiring positioned on a clock path (S103) to wire the circuit (S104). About an obtained wiring result, the resource quantity of the wiring positioned on the clock path is obtained (S105), and it is judged whether the obtained resource value is not larger than an allowable value (S106). When the obtained resource value is larger than the allowable value, a wiring positioned at the lower stage of the clock path is selected preferentially from among the wirings positioned on the clock path (S107), and a selected wiring is changed to a wiring of a degraded crosstalk resistance characteristic (S108). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring method for a semiconductor integrated circuit, and more particularly to a wiring method for a semiconductor integrated circuit using a plurality of types of wiring.

  Many semiconductor integrated circuits including a logic circuit operate in synchronization with an externally supplied clock signal or an internally generated clock signal based on an externally supplied signal. In general, a semiconductor integrated circuit includes a plurality of flip-flops and a circuit that generates a clock signal supplied to each flip-flop based on a given clock signal (hereinafter referred to as a clock circuit). In order for the semiconductor integrated circuit to operate correctly, it is necessary to correctly supply a clock signal to each flip-flop. In order to reduce the power consumption of the semiconductor integrated circuit, it is effective to stop the supply of the clock signal to the circuit block that is not operated. For this reason, the configuration of the clock circuit and the method for supplying the clock signal are recognized as important issues in the design of the semiconductor integrated circuit.

  Another problem with semiconductor integrated circuits is that the wiring is affected by crosstalk. When the wiring is affected by crosstalk, the waveform of a signal propagating on the wiring may be distorted, and a malfunction such as malfunction of the circuit may occur. In general, the longer the wiring length, the easier the wiring is affected by crosstalk, and the wiring on the clock path tends to be longer than the other wiring. For this reason, it can be said that the wiring on the clock path is more susceptible to crosstalk than the other wiring.

As a countermeasure against crosstalk in a semiconductor integrated circuit, for example, a method of wiring a circuit using wiring having excellent crosstalk resistance can be considered. In this method, a wide wiring, a wiring having a wiring interval, a shielded wiring, or the like is used as a wiring having excellent crosstalk resistance. As another method, Patent Document 1 discloses a method of setting an upper limit value of crosstalk noise when designing a layout of a semiconductor integrated circuit.
JP 2003-186934 A

  In a semiconductor integrated circuit, there is a trade-off relationship between the cost required for countermeasures against crosstalk and its effect. That is, if a sufficient crosstalk countermeasure is applied to the circuit, the cost of the circuit increases. Conversely, if the circuit cost is kept low, the effect of the countermeasure against the crosstalk becomes insufficient. However, conventionally, there is no known wiring method capable of effectively taking measures against crosstalk at an appropriate cost with respect to a wiring method of a semiconductor integrated circuit.

  Therefore, an object of the present invention is to provide a wiring method of a semiconductor integrated circuit that can effectively take measures against crosstalk at an appropriate cost.

  The invention that solves the above-described problem is that the wiring having the best crosstalk resistance among the plurality of types of wiring that can be used is assigned to the wiring on the clock path, and the wiring of the circuit is performed. If the wiring result does not meet the judgment criteria, the wiring in the lower stage of the clock path is preferentially selected from the wirings on the clock path and selected. This is a method for wiring a semiconductor integrated circuit, in which the above-described wiring is changed to a wiring having inferior crosstalk resistance.

  In this case, when determining the wiring result, the resource amount of the wiring on the clock path may be obtained based on the wiring result, and it may be determined whether or not the obtained resource amount is a predetermined allowable value or less, or The degree of influence of crosstalk on the circuit may be obtained based on the wiring result, and it may be determined whether or not the obtained degree of influence is less than a predetermined allowable value.

  According to the above invention, the crosstalk countermeasures can be effectively taken at an appropriate cost by using the wiring having excellent crosstalk resistance for a part of the wiring on the clock path that is easily affected by the crosstalk. be able to.

(First embodiment)
FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit according to the first embodiment of the present invention. The design method shown in FIG. 1 performs placement processing and wiring processing on a semiconductor integrated circuit after the logic design is completed, and is typically an EDA (Electronic Design) which is a semiconductor integrated circuit design apparatus. Automation) system.

  Prior to describing the details of each step shown in FIG. 1, the types of wiring used in the wiring processing included in the design method shown in FIG. 1 will be described. In the wiring process in FIG. 1, a plurality of types of wiring are used. More specifically, the wiring has one or more attributes (for example, wiring width, wiring interval, presence / absence of shield), and a plurality of types of wirings having different attribute values are prepared as usable wirings in advance. Hereinafter, in the present embodiment, as an example, the wiring has three attributes of wiring width, wiring interval, and presence / absence of shield, the wiring width is “1 ×” and “2 ×”, and the wiring interval is “ It is assumed that the values “1 ×” and “3 ×”, and the presence / absence of the shield can be “unshielded” and “with shield”, independently of other attribute values. In this case, eight types of wirings are prepared in advance.

  These eight types of wiring include wiring having relatively poor crosstalk resistance and wiring having relatively excellent crosstalk resistance. In general, a wiring with a narrow wiring width, a wiring with a narrow wiring interval, and a wiring that is not shielded are relatively inferior in crosstalk resistance, a wiring with a wide wiring width, a wiring with a wide wiring spacing, and a shielded wiring. The wiring is relatively excellent in crosstalk resistance. When applied to this embodiment, the wiring with a wiring width of 1 times, the wiring with a wiring spacing of 1 time, and the wiring without a shield are relatively inferior in crosstalk resistance, and the wiring with a wiring width of 2 times and the wiring spacing of 3 times These wirings and shielded wirings are relatively excellent in crosstalk resistance. Hereinafter, among the above eight types of wiring, the wiring having the worst inferior crosstalk characteristics (wiring 1 times the wiring width, wiring spacing 1 time, and unshielded wiring) is referred to as “normal wiring”, and has the highest crosstalk resistance. An excellent wiring (wiring width twice, wiring interval three times, and shielded wiring) is called “strongest wiring”.

  Details of each step shown in FIG. 1 will be described below. The method shown in FIG. 1 is executed when a netlist is obtained for a semiconductor integrated circuit to be designed. The netlist includes information related to cells included in the circuit to be designed and information related to wiring connecting the cells.

  In the method shown in FIG. 1, first, cells are arranged in a predetermined two-dimensional area based on a net list of a circuit to be designed according to a predetermined design rule (step S101). Next, a clock tree is extracted from the net list, and wiring on the clock path is obtained (step S102). The extracted clock tree is also used, for example, when performing timing analysis in steps not shown.

  Next, the wiring on the clock path obtained in step S102 is the strongest wiring (wiring width is doubled, wiring interval is tripled, and shielded wiring among the above eight types of wirings used as wiring. ) Is assigned (step S103).

  Next, according to a predetermined design rule, cells are wired based on the net list of the circuit to be designed (step S104). At this time, the wiring on the clock path is wired using the strongest wiring according to the assignment in step S103. Of the wirings other than the wiring on the clock path, the wiring for connecting the cell output terminal and the input terminal is a normal wiring (wiring width is 1 times, wiring interval is 1 time, and unless otherwise specified, and Wiring using unshielded wiring).

  Next, for the wiring result obtained in step S104, the resource amount of the wiring on the clock path is obtained (step S105). For example, in the wiring result obtained in step S104, when the number of wiring tracks occupied by the wiring on the clock path is A, and all the wirings on the clock path are changed to normal wiring, the wiring track occupied by the changed wiring is When the number is B, in step S105, the value A / B is calculated as the resource amount of the wiring on the clock path.

  Next, it is determined whether or not the resource amount obtained in step S105 is equal to or less than a predetermined allowable value (step S106). If the obtained resource amount is less than or equal to the allowable value (YES in step S106), the process ends. On the other hand, when the obtained resource amount exceeds the allowable value (NO in step S106), the process proceeds to step S107.

  In the latter case, the wiring at the lower stage of the clock path is preferentially selected from the wirings on the clock path (step S107), and the selected wiring is changed to a wiring having inferior crosstalk resistance (step S108). . However, in step S108, the selected wiring is changed to a wiring that differs from the wiring in only one attribute. Thereby, for example, when a wiring having a double wiring width is selected in step S107, a wiring having a single wiring width is used as the changed wiring in step S108. In addition, when a wiring having a wiring interval of 3 times is selected in step S107, a wiring having a wiring interval of 1 is used in step S108, and when a wiring with a shield is selected in step S107, in step S108, a wiring with a shield is selected. Unshielded wiring is used.

  Next, the process proceeds to step S105. As a result, the four steps of selecting the wiring, changing the wiring, calculating the resource amount, and comparing the resource amount and the allowable value are repeated until it is determined in step S106 that the resource amount is less than or equal to the allowable value. Executed.

  Hereinafter, the wiring and attribute selection order in steps S107 and S108 will be described. As described above, one wiring is selected in step S107, and one attribute of the selected wiring is selected in step S108. In the selection of the wiring in step S107, the wiring at the lower stage of the clock tree is preferentially selected over the wiring at the upper stage of the clock tree. Further, in the selection of the attribute in step S108, when the attribute value is changed to one having an inferior crosstalk characteristic, an attribute having a large effect of reducing the amount of resources or an attribute having a small degree of deterioration in the crosstalk characteristic is obtained. It is preferentially selected over attributes that have a small effect of reducing the amount of resources and attributes that have a large degree of deterioration in crosstalk resistance.

  As an example, consider a case where a semiconductor integrated circuit including the clock tree shown in FIG. 2 is designed using the design method according to the present embodiment. The clock tree shown in FIG. 2 has three buffers and three types of wiring on each clock path from the clock terminal 10 to each flip-flop 14. Hereinafter, these three types of wirings are referred to as a first level wiring 11, a second level wiring 12, and a third level wiring 13 in order from the top of the clock path. These three types of wiring are wired using any of the above eight types of wiring.

  In this example, as the wiring and attribute selection order in steps S107 and S108, for example, one of the two orders shown in FIG. 3 can be used. First, in the order by level priority (FIG. 3A), after all attributes are selected for a certain level of wiring, one attribute is selected for the next level of wiring. Specifically, according to the order in which priority is given to the level, the presence or absence of the shield of the third level wiring 13, the wiring interval of the third level wiring 13, the wiring width of the third level wiring 13, and the second level wiring 12 Wiring and attributes are selected in the order of the presence / absence of the shield, the wiring interval of the second level wiring 12, and so on. In contrast, in the attribute priority order (FIG. 3B), after a certain attribute is selected for all levels of wiring, the next attribute is selected for each level of wiring. Specifically, according to the order of attribute priority, the third level wiring 13 is shielded, the second level wiring 12 is shielded, the first level wiring 11 is shielded, and the third level wiring is shielded. Wiring and attributes are selected in the order of the wiring interval of the wiring 13, the wiring interval of the second level wiring 12, and so on. Note that the order of selecting wirings and attributes may be other than the above as long as wirings lower in the clock path are preferentially selected.

  As described above, according to the method for designing a semiconductor integrated circuit according to the present embodiment, one of the wirings on the clock path that is easily affected by crosstalk is determined based on the resource amount of the wiring on the clock path. By using wiring with excellent crosstalk resistance for the part, crosstalk countermeasures can be effectively taken at an appropriate cost.

(Second Embodiment)
FIG. 4 is a flowchart showing a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention. Similar to the design method according to the first embodiment, the design method shown in FIG. 4 performs placement processing and wiring processing on the semiconductor integrated circuit after the logic design is completed. It is implemented using an EDA system.

  Among steps shown in FIG. 4, steps S201 to S204, S207, and S208 are the same as steps S101 to S104, S107, and S108 shown in FIG.

  In the design method according to the present embodiment, after wiring between cells in step S204, the degree of influence of crosstalk on the circuit is determined for the wiring result obtained in step S204 (step S205). In step S205, for example, the amount of change in the delay time of the wiring on the clock path when crosstalk occurs is calculated as the degree of influence of crosstalk. Specifically, a result such as a 6% increase in wiring delay time is calculated when crosstalk occurs.

  Next, it is determined whether or not the influence obtained in step S205 is equal to or less than a predetermined allowable value (step S206). If the determined influence is less than or equal to the allowable value (YES in step S206), the process ends. On the other hand, when the obtained influence degree exceeds the allowable value (NO in step S206), the process proceeds to step S207.

  As a result, in the design method shown in FIG. 4 as well, as in the design method according to the first embodiment (FIG. 1), the wiring until the influence of the crosstalk is determined to be less than or equal to the allowable value in step S206. The four steps of selection, wiring change, resource amount calculation, and comparison between the resource amount and the allowable value are repeatedly executed.

  As described above, according to the design method of the semiconductor integrated circuit according to the present embodiment, a part of the wiring on the clock path that is easily affected by the crosstalk, using the degree of influence of the crosstalk on the circuit as a criterion. In addition, by using wiring having excellent crosstalk resistance, it is possible to effectively take measures against crosstalk at an appropriate cost.

  In each of the above embodiments, the resource amount of the wiring on the clock path or the influence of crosstalk on the circuit is used as a criterion for determining whether to change the wiring. Instead, any value that can be calculated based on the results of the placement process and the wiring process may be used as the determination criterion. For example, the amount of wiring resources on the clock path and the degree of influence of crosstalk on the circuit may be combined and used as the determination criterion.

  The method for designing a semiconductor integrated circuit according to the present invention has an effect of being able to effectively take measures against crosstalk at an appropriate cost. Therefore, it can be used for an EDA system used when designing various semiconductor integrated circuits. it can.

1 is a flowchart of a method for designing a semiconductor integrated circuit according to a first embodiment of the present invention. The figure which shows the clock tree contained in the semiconductor integrated circuit designed using the design method of the semiconductor integrated circuit concerning the 1st Embodiment of this invention The figure which shows the selection order of wiring and an attribute in the design method of the semiconductor integrated circuit concerning the 1st Embodiment of this invention Flowchart of a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Clock terminal 11 ... 1st level wiring 12 ... 2nd level wiring 13 ... 3rd level wiring 14 ... Flip-flop

Claims (3)

A method of wiring a semiconductor integrated circuit using a plurality of types of wiring,
Assigning the wiring with the best crosstalk resistance among the available types of wiring to the wiring on the clock path, and wiring the circuit;
Determining whether the obtained wiring result satisfies a predetermined criterion;
When the wiring result does not satisfy the determination criterion, the wiring at the lower stage of the clock path is preferentially selected from the wirings on the clock path, and the selected wiring is changed to a wiring having poor crosstalk resistance. And a wiring method for a semiconductor integrated circuit.   The step of determining the wiring result is characterized in that a resource amount of a wiring on a clock path is obtained based on the wiring result, and it is determined whether or not the obtained resource amount is a predetermined allowable value or less. The wiring method of the semiconductor integrated circuit according to claim 1. The step of determining the wiring result is characterized in that a degree of influence of crosstalk on the circuit is obtained based on the wiring result, and it is determined whether or not the obtained degree of influence is a predetermined allowable value or less. Item 2. A method of wiring a semiconductor integrated circuit according to Item 1.

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