JP2006172488A - Semiconductor integrated circuit design apparatus, semiconductor integrated circuit design method, semiconductor integrated circuit manufacturing method, and readable recording media - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely suppress noise within a predetermined range by adding a bypass capacitor having necessary capacitance in the vicinity of a noise source in an effective circuit block. <P>SOLUTION: In LSI design, function specification information 65, standard cell library information 70, and bias capacitor capacitance restriction 68 of a circuit block of an LSI chip are inputted; the inputted function specification information is converted to gate level logic circuit information; a mapping process for allocating inputted cells to the converted logic gate is executed; the mounting capacity of the logic circuit having subjected to the mapping process is compared with the capacity restriction 68; if the mounting capacity is greater than the capacity restriction 68, the processing is ended; and if the mounting capacity is not greater than the capacity restriction 68, logic gates in the circuit block are selected and the cells allocated to the selected logic gates are changed and added. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit design apparatus for generating a pattern of a semiconductor integrated circuit such as an LSI having a bypass capacitor for reducing power supply noise and substrate noise, a semiconductor integrated circuit design method using the same, and a circuit design of this method procedure. The present invention relates to a method for manufacturing a semiconductor integrated circuit used in the present invention and a computer-readable readable recording medium on which the method procedure is recorded.

  Conventionally, power supply noise is generated when a power supply current that flows when a CMOS logic circuit switches passes through an inductor of a bonding wire of a package. This power supply noise occurs frequently in digital circuits, and adversely affects other devices due to electromagnetic unnecessary radiation (EMI). Furthermore, in the analog / digital (A / D) mixed LSI, there is a problem that noise generated in the digital circuit is transmitted to the analog circuit through the substrate and adversely affects the performance of the analog circuit. This is called substrate noise.

Such a power noise generation mechanism will be described with reference to FIG.
In FIG. 16, the power supply terminal 121 and the ground terminal 122 on the LSI chip 120 side are connected to the external power supply 150 on the package 130 side through bonding wires (inductors 140A and 140B) having inductance components. Further, in the LSI chip 120, an inverter circuit 131 having a CMOS structure, an internal load 90 (90cp, 90cn), and a bypass capacitor 111 are provided in parallel.

  When the input voltage to the internal circuit of the LSI chip 120 changes from the “L” level to the “H” level, a discharge current flows. The current path at this time is formed through the node 132 at the output end of the inverter circuit 131 as shown by the arrow in FIG.

  In this case, the direction of the current passing through the inductor 140A connected to the power supply terminal 121 and the inductor 140B connected to the ground terminal 122 works in opposite directions as seen from the inside of the LSI chip 120 due to the change of the input voltage. 121 and the ground terminal 122 generate noises of opposite phases. Assuming that the power supply voltage is Vdd, the ground voltage is Vss, and the maximum voltage fluctuation width due to noise is Vn, an initial voltage fluctuation of Vdd−Vn occurs at the power supply terminal 121 and Vss + Vn occurs at the ground terminal 122, and then the RLC circuit. A ringing operation appears, and symmetric noise with opposite phases appears at the power supply terminal 121 and the ground terminal 122.

  By the way, a typical method for reducing such power supply noise is to provide a bypass capacitor 111 between the power supply terminal 121 and the ground terminal 122. FIG. 16 shows a bypass capacitor 111 inside the LSI chip 120. Since the internal load 90 is driven using the electric charge stored in the bypass capacitor 111, fluctuations in the amount of current supplied from the external power source 150 through the inductors 140A and 140B can be suppressed, and noise can be reduced.

  Further, the closer the bypass capacitor 111 is located to a noise source (for example, a bonding wire), the more effective the noise is reduced. Ideally, when the bypass capacitor 111 is disposed at the same location as the operating circuit, the noise generation amount is reduced most. Can do.

As a conventional method of providing such a bypass capacitor 111 in the LSI chip 120, Patent Document 1 discloses a method of creating a bypass capacitor in an empty area after layout design.
However, there may be a case where a bypass capacitor having a necessary capacity cannot be secured only by an empty area after layout design.

  On the other hand, as a method for mounting the bypass capacitor 111 having the necessary capacity, Non-Patent Document 1 discloses a method for optimizing the capacity of the bypass capacitor while repeating the circuit simulation and the floor plan.

  That is, first, an initial arrangement of functional blocks is input to the floor planner. Next, a region n where a lot of noise is generated is identified by circuit simulation, and the size of the capacitance Cn of the bypass capacitor necessary to reduce the noise generation amount to a specified value or less in the specified region n is calculated. To do.

Next, it is a method of modeling as one or more virtual blocks bk in which the total number of bypass capacitors to be added becomes greater than or equal to the capacitance Cn, and inserting the virtual blocks bk between the arranged functional blocks.
JP 2000-208634 A Howard H. Chan et al., "Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design", Design Automation Conference ), 1997

  However, in the conventional configuration described above, even if a bypass capacitor having a necessary capacity is arranged in an empty area after the layout design, the place where the bypass capacitor is arranged is between the circuit blocks. There is a problem that the noise reduction effect is low because it is far from the noise source in the circuit block.

  The present invention solves the above-described conventional problem, and by adding a bypass capacitor having a necessary capacity near a noise source in a more effective circuit block, the amount of noise generation is reliably suppressed within a predetermined range. Semiconductor integrated circuit design apparatus, semiconductor integrated circuit design method using the same, semiconductor integrated circuit manufacturing method using this method procedure for circuit design, and computer-readable readable recording medium recorded with this method procedure The purpose is to provide.

  In order to solve the above problems, a semiconductor integrated circuit design apparatus according to the present invention is a semiconductor integrated circuit design apparatus that automatically generates a pattern of a semiconductor integrated circuit under the control of a computer. Capacitance constraint, which is the capacity of the bypass capacitor for reducing power supply noise and substrate noise, required to be mounted in the circuit block in order to keep the functional specification information, standard cell library information, and noise generation amount within a predetermined range. For input means for input processing, gate level conversion means for converting functional specification information of the logic circuit into gate level logic circuit information based on function levels, and for all logic gates in the gate level logic circuit, respectively Mapping process to allocate cells in the standard cell library information In the comparison by the mapping processing means, the mounting capacity that is the capacity of the bypass capacitor mounted in the logic circuit mapped by the mapping processing means, the comparison means for comparing the capacity constraints, and the comparison by the comparison means, When the mounting capacity is larger than the capacity constraint, a predetermined processing is performed when the mounting capacity is equal to or less than the capacity constraint in the comparison by the processing ending means for automatically generating the pattern of the semiconductor integrated circuit and the comparison means. Logic gate selection means for selecting a logic gate having a noise generation amount or more, and the mapping cell and logic assigned in the mapping process are equivalently mounted on the logic gate selected by the logic gate selection means. Change the assignment to another cell with a different bypass capacitor capacity, Others, the mapping change processing means for assigning a bypass capacitor cell comprising only a bypass capacitor to the mapping cell in addition, are those having the above-described object can be achieved.

  Furthermore, the semiconductor integrated circuit design apparatus of the present invention is a semiconductor integrated circuit design apparatus that automatically generates a pattern of a semiconductor integrated circuit under the control of a computer. Cell library information including a bypass capacitor cell consisting only of at least one bypass capacitor for reducing substrate noise, and for reducing power generation noise and substrate noise that are required to be mounted on the circuit block in order to reduce the amount of noise generation An input unit that inputs a capacity constraint that is a capacity of a bypass capacitor, a cell placement unit that arranges cells in a plurality of parallel cell rows according to the netlist information, and a bypass capacitor mounted on the circuit block Capacity that is capacity, and the capacity constraint In the comparison by the comparison means, a processing end means for ending the process of automatically generating a pattern of the semiconductor integrated circuit when the mounted capacity is larger than the capacity constraint, and a comparison by the comparison means And the bypass capacitor cell adding means for inserting a bypass capacitor cell in the cell row when the mounted capacity is equal to or less than the total capacity constraint, and thereby the above object is achieved.

  Next, the semiconductor integrated circuit design method of the present invention is a semiconductor integrated circuit design method in which a pattern of a semiconductor integrated circuit is automatically generated under the control of a computer, and functional specification information and standards of logic circuit blocks constituting the semiconductor integrated circuit. An input step for input processing of cell library information and a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted on the circuit block in order to suppress the amount of noise generation within a predetermined range. A gate level conversion step of converting functional specification information of the logic circuit into gate level logic circuit information based on the function level, and the standard cell library information for all the logic gates in the gate level logic circuit, respectively. Mapping that assigns the cell in the mapping process A comparison step comparing a processing step, a mounting capacity that is a capacity of a bypass capacitor mounted in the mapped logic circuit, and the capacity constraint, and as a result of the comparison, the mounting capacity is greater than the capacity constraint. When the size is larger, a process end step for ending the process of automatically generating the pattern of the semiconductor integrated circuit is selected, and if the result of the comparison indicates that the mounted capacity is less than the capacity constraint, a logic gate having a predetermined noise generation amount or more is selected. A logic gate selection step, and for the selected logic gate, the mapping cell allocated in the mapping process is equivalent to the logic and the allocation is changed to another cell having a different capacity of the internal bypass capacitor. Or a bypass capacitor consisting only of a bypass capacitor in the mapping cell. A mapping change processing step for additionally assigning sensor cells, and in the mapping change processing step, the assignment is changed to the other cell, or the bypass capacitor cell is additionally assigned, and then the processing returns to the comparison step. The capacity restriction is compared with the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block in which the allocation is changed to the other cell or the bypass capacitor cell is additionally allocated. Yes, and the above objective is achieved.

  Preferably, the standard cell library information in the semiconductor integrated circuit design method of the present invention is cell library information used for designing a semiconductor integrated circuit, and the circuit logic is equivalent and the capacity of a bypass capacitor mounted therein is different. At least one set of cell information with a bypass capacitor is included.

  Furthermore, the semiconductor integrated circuit design method of the present invention is a semiconductor integrated circuit design method in which a pattern of a semiconductor integrated circuit is automatically generated under the control of a computer. Cell library information including a bypass capacitor cell consisting only of at least one bypass capacitor for reducing substrate noise, and for reducing power generation noise and substrate noise that are required to be mounted on the circuit block in order to reduce the amount of noise generation An input step for inputting a capacity constraint that is a capacity of a bypass capacitor, a cell placement step for placing cells in a plurality of parallel cell rows according to the netlist information, and a bypass capacitor mounted on the circuit block Mounting capacity, which is a capacity, A comparison step for comparing a quantity constraint, a process end step for terminating a process of automatically generating a pattern of the semiconductor integrated circuit when the mounted capacity is larger than the capacity constraint as a result of the comparison, and a result of the comparison A bypass capacitor cell adding step of inserting a bypass capacitor cell in the cell row when the mounted capacity is less than or equal to the total capacity constraint, and after inserting the bypass capacitor cell in the bypass capacitor cell adding step, Returning to the comparison step, the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block in which the bypass capacitor cell is inserted, is compared with the capacity constraint, thereby achieving the above object. The

  Next, a method for manufacturing a semiconductor integrated circuit according to the present invention uses a semiconductor integrated circuit design method for automatically generating a pattern of a semiconductor integrated circuit controlled by a computer for circuit design. A method of designing a semiconductor integrated circuit, wherein the circuit block is used to suppress functional specification information, standard cell library information, and noise generation amount of a logic circuit block constituting the semiconductor integrated circuit within a predetermined range. An input step for inputting a capacity constraint, which is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted on the circuit, and functional specification information of the logic circuit based on the function level. A gate level conversion step for converting into information, and all logic gates in the gate level logic circuit; On the other hand, a mapping process step for performing a mapping process for allocating cells in the standard cell library information, a mounting capacity that is a capacity of a bypass capacitor mounted in the mapped logic circuit, and the capacity constraint, A comparison step for comparing, a processing ending step for ending processing for automatically generating a pattern of the semiconductor integrated circuit when the mounting capacity is larger than the capacity constraint as a result of the comparison, and a result of the comparison, the mounting capacity A logic gate selection step of selecting a logic gate that is equal to or greater than a predetermined noise generation amount when the capacity is less than the capacity constraint, and the mapping cell and logic assigned in the mapping process for the selected logic gate are equivalent and internal The capacity of the bypass capacitor mounted on the A mapping change processing step of assigning a bypass capacitor cell consisting of only a bypass capacitor to the mapping cell, and assigning the mapping cell to the other cell in the mapping change processing step. Or after the additional allocation of the bypass capacitor cell, return to the comparison step and change the allocation to the other cell or mount the bypass capacitor cell in the additionally allocated circuit block The above-mentioned object is achieved by comparing the mounted capacity, which is the capacity of the bypass capacitor, and the capacity constraint.

  According to another aspect of the present invention, there is provided a semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit by using a semiconductor integrated circuit design method for automatically generating a semiconductor integrated circuit pattern controlled by a computer. A method of designing a semiconductor integrated circuit, comprising: a cell library including a bypass capacitor cell comprising only at least one bypass capacitor for reducing netlist information, power supply noise and substrate noise of circuit blocks constituting the semiconductor integrated circuit; An input step for inputting and processing a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted in the circuit block in order to reduce information and noise generation amount, and the netlist information Place cells in multiple cell rows parallel to each other A placement step, a comparison step for comparing the capacitance of the bypass capacitor mounted on the circuit block with the capacitance constraint, and, as a result of the comparison, if the installed capacitance is greater than the capacitance constraint A process ending step for automatically generating a pattern of the semiconductor integrated circuit, and a bypass capacitor that inserts a bypass capacitor cell in the cell row when the mounted capacity is less than or equal to the total capacity constraint as a result of the comparison A cell addition step, and after inserting the bypass capacitor cell in the bypass capacitor cell addition step, the process returns to the comparison step and the capacitance of the bypass capacitor mounted on the circuit block in which the bypass capacitor cell is inserted. A comparison between a certain installed capacity and the capacity constraint And in certain ones, the objects can be achieved.

  Next, a readable recording medium according to the present invention is a readable recording medium in which a semiconductor integrated circuit design program for causing a computer to perform a process of designing a semiconductor integrated circuit is recorded in a computer-readable manner. The program includes functional noise information, standard cell library information, and power generation noise necessary to be mounted on the circuit block in order to keep the noise generation amount within a predetermined range. An input step of inputting a capacitance constraint that is a capacitance of a bypass capacitor for reducing substrate noise; a gate level conversion step of converting functional specification information of the logic circuit into gate level logic circuit information based on a function level; and For all logic gates in the gate level logic circuit, respectively A mapping process step for performing a mapping process for allocating cells in the standardized cell library information, a comparison step for comparing the mounted capacity, which is the capacity of a bypass capacitor mounted in the mapped logic circuit, and the capacity constraint; As a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit, and as a result of the comparison, the mounting capacity is less than or equal to the capacity constraint. In this case, a logic gate selection step for selecting a logic gate having a predetermined noise generation amount or more, and the mapping cell and logic assigned in the mapping process are equivalently mounted inside the selected logic gate. Change assignment to another cell with different bypass capacitor capacity Or a mapping change processing step for additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the mapping cell, and in the mapping change processing step, the assignment is changed to the other cell, or After the additional allocation of the bypass capacitor cell, the process returns to the comparison step, and the allocation of the bypass capacitor mounted in the circuit block to which the allocation is changed to the other cell or the bypass capacitor cell is additionally allocated The installed capacity, which is a capacity, is compared with the capacity constraint, and the above object is achieved.

  The readable recording medium of the present invention is a readable recording medium in which a semiconductor integrated circuit design program for causing a computer to perform a process of designing a semiconductor integrated circuit is recorded so as to be readable by a computer. To reduce netlist information of circuit blocks constituting the semiconductor integrated circuit, cell library information including a bypass capacitor cell composed of at least one bypass capacitor for reducing power supply noise and substrate noise, and noise generation amount An input step for inputting a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted on the circuit block, and a plurality of cell rows parallel to each other according to the netlist information Cell placement step to be placed on and before A comparison step of comparing the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block, with the capacity constraint; and, as a result of the comparison, if the mounting capacity is greater than the capacity constraint, the semiconductor integrated circuit A process ending step for ending the process of automatically generating a pattern, and a bypass capacitor cell adding step for inserting a bypass capacitor cell in the cell row when the mounted capacity is less than or equal to the total capacity constraint as a result of the comparison, Including, after inserting the bypass capacitor cell in the bypass capacitor cell addition step, returning to the comparison step, mounting capacity that is the capacity of the bypass capacitor mounted on the circuit block in which the bypass capacitor cell is inserted, and Which is a comparison with capacity constraints The above-mentioned object can be achieved by the.

The operation of the present invention will be described with the above configuration.
In the present invention, a bypass capacitor having a required capacity can be added near a noise source inside a more effective circuit block, so that noise can be reliably suppressed within a predetermined range.

  Furthermore, even when there is no cell with the desired bypass capacitor capacity in the standard cell library and a new cell with the desired bypass capacitor capacity is newly added, the current when several types of bypass capacitor capacity are changed Since the current waveform of the additional cell can be obtained by calculation using the waveform data table, it becomes easy to add the cell.

  In addition, while satisfying the bypass capacitor capacity constraint for the entire circuit block, a cell with a bypass capacitor can be assigned to a logic gate with a larger amount of noise generation, so that the required amount of bypass capacitors can be placed in a more effective circuit block. A logic synthesis method can be obtained that can be added near the noise source and can reliably suppress noise within a specified range.

  In addition, if this cell library is used, a bypass capacitor can be mounted in the cells constituting the circuit block, so that the bypass capacitor can be arranged near the noise source, and noise can be effectively reduced. it can. In addition, since cells with equivalent logic and different bypass capacitor capacities are included, by using different bypass capacitor capacities according to the amount of noise generated, semiconductor integration such as LSI chips can be achieved by adding unnecessary bypass capacitors. An increase in the chip area of the circuit can be eliminated.

  Furthermore, since the bypass capacitor cell can be inserted in the cell row in the circuit block, a place for placing the bypass capacitor near the noise source can be secured, and the noise is surely kept within a predetermined range. Can be suppressed.

  As described above, according to the semiconductor integrated circuit design apparatus of the present invention, in the semiconductor integrated circuit design apparatus that automatically generates the pattern of the semiconductor integrated circuit under the control of the computer, the functional specification information of the logic circuit block constituting the semiconductor integrated circuit In addition, the standard cell library information and the capacity constraint, which is the capacity of the bypass capacitor for reducing power supply noise and substrate noise, required to be mounted in the circuit block in order to suppress the noise generation amount within a predetermined range are input processed. Input means; gate level conversion means for converting functional specification information of the logic circuit into gate level logic circuit information based on the function level; and the standard cells for all logic gates in the gate level logic circuit, respectively. Map that performs mapping to assign cells in library information In the comparison by the comparison processing means, the mounting capacity that is the capacity of the bypass capacitor mounted in the logic circuit mapped by the mapping processing means, the comparison means that compares the capacity constraints, and the comparison by the comparison means When the capacity is larger than the capacity constraint, a predetermined noise is generated when the mounting capacity is equal to or less than the capacity constraint in the comparison by the processing end means for automatically generating the pattern of the semiconductor integrated circuit and the comparison means. A logic gate selection means for selecting a logic gate more than the generation amount, and a bypass that is mounted in the mapping cell and logic allocated in the mapping process equivalent to the logic gate selected by the logic gate selection means. Change the assignment to another cell with a different capacity, or Mapping changing processing means for additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the mapping cell, so that the circuit block as a whole further satisfies the capacity constraint of the bypass capacitor and further generates noise. Cell with the bypass capacitor can be assigned to a large logic gate, thereby adding the required amount of bypass capacitor near the noise source in the more effective circuit block, resulting in semiconductor integration The amount of noise generated in the circuit can be reliably suppressed within a predetermined range. In addition, since cells that have the same logic and different bypass capacitor capacities are included, depending on the amount of noise generated, the bypass capacitors can be used properly, so that an unnecessary large number of bypass capacitors can be added to an LSI chip or other semiconductor integrated circuit. An increase in chip area can be eliminated.

  Further, according to the semiconductor integrated circuit design device of the present invention, in the semiconductor integrated circuit design device which automatically generates the pattern of the semiconductor integrated circuit under the control of the computer, the net list information of the circuit block constituting the semiconductor integrated circuit, the power supply Cell library information including a bypass capacitor cell consisting only of at least one bypass capacitor for noise and substrate noise reduction, and power supply noise and substrate noise reduction required to be mounted on the circuit block in order to reduce noise generation amount Input means for inputting a capacity constraint that is a capacity of a bypass capacitor for use, cell placement means for placing cells in a plurality of parallel cell rows according to the netlist information, and a bypass mounted in the circuit block Mounting capacity, which is the capacity of the capacitor, and the capacity A comparison means for comparing about, a processing ending means for ending processing for automatically generating a pattern of the semiconductor integrated circuit when the mounting capacity is larger than the capacity constraint in the comparison by the comparison means, and the comparison means When the mounted capacity is less than or equal to the total capacity constraint, the circuit has a bypass capacitor cell adding means for inserting a bypass capacitor cell in the cell row, and is disposed in the circuit block. The bypass capacitor can be inserted into the cell row, which makes it possible to secure a place for placing the bypass capacitor near the noise source, and increase the area of the semiconductor integrated circuit by adding the bypass capacitor cell. In addition, the noise of the semiconductor integrated circuit can be surely suppressed within a predetermined range. That.

  Next, according to the semiconductor integrated circuit design method of the present invention, in the semiconductor integrated circuit design method in which the pattern of the semiconductor integrated circuit is automatically generated under the control of the computer, the functional specification information of the logic circuit block constituting the semiconductor integrated circuit In addition, the standard cell library information and the capacity constraint, which is the capacity of the bypass capacitor for reducing power supply noise and substrate noise, required to be mounted in the circuit block in order to suppress the noise generation amount within a predetermined range are input processed. An input step; a gate level conversion step for converting functional specification information of the logic circuit into gate level logic circuit information based on a function level; and the standard cells for all logic gates in the gate level logic circuit, respectively. A mapping process that assigns cells in library information A comparison step of comparing the capacity constraint with a capacity of a bypass capacitor mounted on the mapped logic circuit and the capacity constraint, and the result of the comparison is that the mounted capacity is the capacity constraint. A process end step of ending the process of automatically generating the pattern of the semiconductor integrated circuit when the value is larger, and, as a result of the comparison, if the mounted capacity is equal to or less than the capacity constraint, a logic gate having a predetermined noise generation amount or more is set. Selecting a logic gate to be selected, and assigning the selected logic gate to another cell in which the mapping cell assigned in the mapping process is equivalent to the logic and the capacity of the bypass capacitor mounted inside is different. Change or the mapping cell consists of a bypass capacitor only A mapping change processing step for additionally assigning capacitor cells, and in the mapping change processing step, the assignment is changed to the other cell, or after the bypass capacitor cell is additionally assigned, the comparison step is performed. Return to compare the capacity constraint with the mounted capacity, which is the capacity of the bypass capacitor mounted in the circuit block to which the allocation is changed to the other cell or the bypass capacitor cell is additionally allocated. As a result, the circuit block as a whole can allocate the cell with the bypass capacitor to the logic gate having a larger amount of noise generation while satisfying the capacity restriction of the bypass capacitor. In a more effective circuit block The noise generation amount of the semiconductor integrated circuit can be reliably suppressed within a predetermined range.

  Furthermore, according to the semiconductor integrated circuit design method of the present invention, the standard cell library information is cell library information used for designing the semiconductor integrated circuit, and the capacitance of the bypass capacitor mounted therein is equivalent to the logic of the circuit. Since at least one set of cell information with bypass capacitors is included, if the cell library is used, a bypass capacitor can be mounted in a cell constituting the circuit block, and thereby, near a noise source. The bypass capacitor can be disposed, and noise can be effectively reduced. In addition, since cells with the same logic and different bypass capacitor capacity are included, the bypass capacitor capacity can be selected according to the amount of noise generated, and the LSI chip area can be increased by adding unnecessary bypass capacitors. Can be eliminated.

  According to the semiconductor integrated circuit design method of the present invention, in the semiconductor integrated circuit design method for automatically generating the pattern of the semiconductor integrated circuit controlled by a computer, the net list information of the circuit block constituting the semiconductor integrated circuit, the power supply Cell library information including a bypass capacitor cell consisting only of at least one bypass capacitor for noise and substrate noise reduction, and power supply noise and substrate noise reduction required to be mounted on the circuit block in order to reduce noise generation amount An input step for input processing of a capacitance constraint that is a capacity of a bypass capacitor, a cell placement step for placing cells in a plurality of parallel cell rows according to the netlist information, and a bypass mounted in the circuit block Mounting capacity, which is the capacity of the capacitor, A comparison step for comparing the storage capacity with the storage capacity restriction, and a process end step for ending the process of automatically generating the pattern of the semiconductor integrated circuit when the mounted capacity is larger than the capacity restriction as a result of the comparison, and the comparison As a result, when the mounted capacity is less than or equal to the total capacity constraint, a bypass capacitor cell addition step of inserting a bypass capacitor cell into the cell row, and after inserting the bypass capacitor cell in the bypass capacitor cell addition step Returning to the comparison step, the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block in which the bypass capacitor cell is inserted, is compared with the capacity constraint, so that it is arranged in the circuit block. Inserting the bypass capacitor in the cell row This makes it possible to secure a place for placing the bypass capacitor near the noise source, suppress the increase in the area of the semiconductor integrated circuit due to the addition of the bypass capacitor cell, and reduce the noise of the semiconductor integrated circuit within a predetermined range. The following can be surely suppressed.

  Next, according to the method for manufacturing a semiconductor integrated circuit of the present invention, a semiconductor integrated circuit for manufacturing a semiconductor integrated circuit using a semiconductor integrated circuit design method for automatically generating a pattern of the semiconductor integrated circuit controlled by a computer for circuit design. A method of manufacturing a circuit, wherein the semiconductor integrated circuit design method is configured to suppress the functional specification information, standard cell library information, and noise generation amount of a logic circuit block constituting the semiconductor integrated circuit within a predetermined range. An input step for inputting a capacity constraint, which is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted on a circuit block, and functional specification information of the logic circuit based on the function level. Gate level conversion step for converting into logic circuit information, and all logic in the gate level logic circuit A mapping processing step for performing mapping processing for allocating cells in the standard cell library information to each of the ports, a mounting capacity that is a capacity of a bypass capacitor mounted in the mapped logic circuit, and the capacity A comparison step for comparing a constraint, and a result of the comparison, a process end step for ending a process of automatically generating a pattern of the semiconductor integrated circuit when the mounted capacity is larger than the capacity constraint, and the comparison result, When the mounted capacity is less than or equal to the capacity constraint, a logic gate selection step of selecting a logic gate having a predetermined noise generation amount or more, and the mapping cell and logic allocated to the selected logic gate in the mapping process are Equivalent and internally mounted bypass capacitors have different capacities A mapping change processing step for changing the assignment to another cell, or additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the mapping cell, and in the mapping change processing step, to the another cell After the assignment is changed, or the bypass capacitor cell is additionally assigned, the circuit returns to the comparison step and the assignment is changed to the other cell, or the bypass capacitor cell is additionally assigned. Since the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit, is compared with the capacity constraint, the circuit block as a whole satisfies the capacity constraint of the bypass capacitor and further generates noise. The bypass circuit is connected to a large logic gate. A cell with a capacitor can be allocated, thereby adding a necessary amount of bypass capacitors near the noise source in the circuit block to manufacture a semiconductor integrated circuit that can reliably suppress noise within a predetermined range. It becomes possible to do.

  According to the method for manufacturing a semiconductor integrated circuit of the present invention, a semiconductor integrated circuit for manufacturing a semiconductor integrated circuit using a semiconductor integrated circuit design method for automatically generating a pattern of the semiconductor integrated circuit controlled by a computer for circuit design. The method for designing a semiconductor integrated circuit includes a bypass capacitor cell including only netlist information of circuit blocks constituting the semiconductor integrated circuit, at least one bypass capacitor for reducing power supply noise and substrate noise. An input step for inputting and processing cell library information and a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted in the circuit block in order to reduce the amount of noise generated; Arrange cells in multiple cell rows parallel to each other according to the list information. A cell placement step, a comparison step for comparing the capacitance, which is a capacitance of a bypass capacitor mounted in the circuit block, and the capacitance constraint, and the result of the comparison is that the installed capacitance is greater than the capacitance constraint And a process end step of ending the process of automatically generating the pattern of the semiconductor integrated circuit, and a bypass for inserting a bypass capacitor cell into the cell row when the mounted capacity is less than or equal to the total capacity constraint as a result of the comparison. A capacitor cell adding step, and after inserting the bypass capacitor cell in the bypass capacitor cell adding step, returning to the comparison step, the capacitance of the bypass capacitor mounted on the circuit block in which the bypass capacitor cell is inserted Compare the installed capacity with the capacity constraint The bypass capacitor can be inserted into the cell row arranged in the circuit block, thereby securing a place for placing the bypass capacitor near the noise source. Thus, it becomes possible to manufacture a semiconductor integrated circuit in which the bypass capacitor cell is inserted at the arrangement location and the noise can be surely suppressed to a predetermined range or less.

  Next, according to the readable recording medium of the present invention, there is provided a readable recording medium in which a semiconductor integrated circuit design program for causing a computer to execute a process of designing a semiconductor integrated circuit is recorded so as to be readable by the computer. The circuit design program is a power supply that is required to be mounted on the circuit block in order to keep the functional specification information, standard cell library information, and noise generation amount of the logic circuit block constituting the semiconductor integrated circuit within a predetermined range. An input step of inputting a capacitance constraint that is a capacitance of a bypass capacitor for reducing noise and substrate noise, and a gate level conversion step of converting functional specification information of the logic circuit into gate level logic circuit information based on the function level; , For all logic gates in the gate level logic circuit, respectively. A mapping process step for performing a mapping process for allocating cells in the standard cell library information, a comparison step for comparing the capacity constraint with a mounting capacity that is a capacity of a bypass capacitor mounted in the logic circuit subjected to the mapping process And, as a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit, and as a result of the comparison, the mounting capacity is determined to be the capacity constraint. In the following cases, a logic gate selection step for selecting a logic gate having a predetermined noise generation amount or more, and the mapping cell and logic assigned in the mapping process for the selected logic gate are equivalently mounted internally. Assigned to another cell with different bypass capacitor capacity Or a mapping change processing step for additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the mapping cell, and in the mapping change processing step, the assignment has been changed to the other cell, Alternatively, after the additional allocation of the bypass capacitor cell, the process returns to the comparison step and the allocation is changed to the other cell, or the bypass capacitor mounted in the circuit block to which the bypass capacitor cell is additionally allocated Since the circuit board as a whole satisfies the capacity restriction of the bypass capacitor, the logic gate having a larger noise generation amount is compared with the circuit board as a whole. Split cell with bypass capacitor This makes it possible to add the required amount of bypass capacitors close to the noise source in the more effective circuit block. As a result, the amount of noise generated in the semiconductor integrated circuit is within a predetermined range. It can be surely suppressed. In addition, since cells that have the same logic and different bypass capacitor capacities are included, depending on the amount of noise generated, the bypass capacitors can be used properly, so that an unnecessary large number of bypass capacitors can be added to an LSI chip or other semiconductor integrated circuit. An increase in chip area can be eliminated.

  According to the readable recording medium of the present invention, there is provided a readable recording medium in which a semiconductor integrated circuit design program for causing a computer to execute a process of designing a semiconductor integrated circuit is recorded so as to be readable by a computer. The design program reduces net list information of circuit blocks constituting the semiconductor integrated circuit, cell library information including a bypass capacitor cell including only at least one bypass capacitor for reducing power supply noise and substrate noise, and noise generation amount. In order to input a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is necessary to be mounted on the circuit block, and according to the netlist information, a plurality of cells parallel to each other Cell placement step to place in cell row A comparison step of comparing the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block, with the capacity constraint; and, as a result of the comparison, if the mounting capacity is greater than the capacity constraint, the semiconductor integrated circuit A process ending step for ending the process of automatically generating a circuit pattern; and, as a result of the comparison, a bypass capacitor cell adding step for inserting a bypass capacitor cell in the cell row when the mounted capacity is less than or equal to the total capacity constraint; And, after inserting the bypass capacitor cell in the bypass capacitor cell addition step, return to the comparison step, and mounting capacity that is the capacity of the bypass capacitor mounted on the circuit block in which the bypass capacitor cell is inserted; , To compare with the capacity constraint Thus, the bypass capacitor can be inserted into the cell row arranged in the circuit block, thereby making it possible to secure a place for placing the bypass capacitor near the noise source. An increase in the area of the semiconductor integrated circuit due to the addition of cells can be suppressed, and the noise of the semiconductor integrated circuit can be reliably suppressed to a predetermined range or less.

  Hereinafter, a case where the first to fourth embodiments of the semiconductor integrated circuit design apparatus of the present invention are applied to a low noise LSI design apparatus will be sequentially described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of a main part of a low noise LSI design apparatus according to Embodiment 1 of the present invention.
In FIG. 1, a low noise LSI design apparatus 10 includes a ROM 11 as a first storage unit (readable recording medium) in which a circuit design control program and data are stored, and a RAM 12 as a second storage unit that functions as a work memory. A database 13 in which various data for circuit design are recorded, an operation input unit 14 that allows a user to input various operation commands (including circuit design start or end commands), and an initial screen for circuit design. The display unit 15 that can display screen information and the control unit 16 that controls each unit based on the control program and data support circuit design of the semiconductor integrated circuit.

  The control unit 16 includes a CPU (central processing unit), and includes an input unit 161, a noise analysis unit 162, a noise determination unit 163, a processing end unit 164, a logic gate selection unit 165, and a bypass capacitor. The processing circuit pattern to which the bypass capacitor 94 is added is automatically generated by repeating a series of processes from the noise analysis process to the bypass capacitor addition process until the entire process is completed.

  The input means 161 receives various circuit design information (see FIG. 2 described later) such as gate level logic circuit information 60, standard cell library information 70, and package information 80 of circuit blocks constituting a semiconductor integrated circuit (LSI). Input from the database 13 as noise analysis information.

  The noise analysis means 162 performs noise analysis processing of each circuit block constituting the semiconductor integrated circuit (LSI) using the inputted various circuit design information.

  In addition, the noise analysis means 162 determines the input pattern of the logic gate and the capacitance of the bypass capacitor mounted in the logic gate with respect to the logic gate in each circuit block constituting the semiconductor integrated circuit (LSI). A data table in which at least one current waveform of the power supply current and the substrate current in the logic gate at the time of change is recorded may be created, and noise analysis may be performed using the created data table.

  Based on the result of the noise analysis processing by the noise analysis unit 162, the noise determination unit 163 determines whether or not the noise generation amount (noise voltage level, noise generation number, etc.) of the logic gate in each circuit block is within a predetermined range. Determine. Then, as a result of the determination by the noise determination unit 163, the processing end unit 164 automatically generates a pattern of the semiconductor integrated circuit when the amount of noise generation is within a predetermined range. End processing.

  When the noise generation amount exceeds a predetermined range as a result of the determination by the noise determination unit 163, the logic gate selection unit 165 selects a logic gate that is equal to or greater than the predetermined noise generation amount in each circuit block.

  For example, the logic gate selection unit 165 generates the maximum noise generation amount (maximum noise voltage level, maximum noise generation number, etc.) in each circuit block based on the noise analysis processing result by the noise analysis unit 162. Select.

  The bypass capacitor adding unit 166 adds a bypass capacitor for reducing power supply noise and substrate noise to the logic gate selected by the logic gate selecting unit 165.

The operation of the above configuration will be described below.
FIG. 2 is a flowchart showing the operation of the low noise LSI design apparatus 10 according to the first embodiment of the present invention. In the first embodiment, analysis of substrate noise will be described as an example.

  As shown in FIG. 2, first, the control unit 16 performs gate level logic circuit information 60 of a circuit block constituting the LSI device and a standard cell library to be used as noise analysis information input processing in step S1 based on a control program. Information 70 and LSI device package information 80 are input from the database 13.

  Next, the control part 16 performs the noise analysis process of step S2 based on a control program. As this noise analysis processing, since it is difficult to implement noise analysis by a circuit simulator in terms of processing time and required memory capacity, methods other than circuit simulation have been proposed.

  As the noise analysis processing (substrate noise analysis processing) of step S2, for example, at the 2000 Design Automation Conference, MV Heijingen et al. ) Can be used. This will be described with reference to FIGS.

  As shown in FIG. 3, first, in the characterization process in step S <b> 21, a macro model as shown in FIG. 4 is generated for each cell of the input standard cell library 70.

  Here, the macro model of FIG. 4 will be described. In FIG. 4, a resistor 91 is a resistor between the ground (Vss) terminal 122 and the P-type substrate 120A, and a capacitor 92 is a reverse bias PN junction capacitor between the N-well and the P-type substrate 120A. A capacitance 93 is parasitically formed between the power supply (Vdd) terminal 121 and the ground (Vss) terminal 122. The current source 101 models the current supplied from the power source, and the current source 102 models the current flowing from the switching node to the P-type substrate 120A.

The first embodiment is characterized in that the bypass capacitor 94 is intentionally mounted inside the cell. In order to clearly show this, the macro model in FIG. 94 is added.
The values of the resistor 91 and the capacitors 92 to 94 can be obtained from the layout of each cell using a parasitic capacitance extraction tool.

  Further, the current source 101 and the current source 102 can be obtained by executing a circuit simulation for each cell and recording the power source current waveform and the substrate current waveform in all input patterns, respectively.

  Further, the substrate current waveform and the power supply current waveform when the capacitance value of the bypass capacitor 94 mounted in the cell is changed in several types are also recorded as a data table by executing a circuit simulation. Note that the substrate current waveform and the power supply current waveform for the other capacitance values of the bypass capacitor 94 for which the circuit simulation has not been executed can be obtained by interpolation based on the data table.

  In the standard cell library 70, as shown in FIG. 5, how many types (for example, 78A, 78B) of bypass capacitor-attached cells 78 having the same logic and different sizes of the bypass capacitors 94 (for example, 94A, 94B) are provided. Even when a bypass capacitor 94 having a size other than that is required by the noise analysis process, the current waveform can be easily calculated by interpolation based on the data table as described above. Therefore, it is possible to easily add the cell 78 with a bypass capacitor required when it becomes necessary to the macro model of FIG.

  A collection of macro models of all the cells of the input standard cell library 70 created in this way is called a substrate noise macro model library 71. This is recorded in the database 13.

  Then, after performing the noise analysis processing as described above, in the logic simulation processing in the next step S22 in FIG. 3, a logic simulation is performed using the input gate level logic circuit information 60 and the input pattern, and all cells Are recorded in the database 13 and the switching event database 62 is created.

  Further, in the equivalent circuit creation process in step S23 of FIG. 3, an equivalent circuit of a circuit block constituting the LSI device is created using the substrate noise macro model library 71, the switching database 62, and the package information 80.

  For example, if the P-type substrate 120A of the LSI device has a low resistance (ρ≈1 mΩcm), the P-type substrate 120A can be approximated as one electrode. Connect in parallel. Further, an equivalent circuit of the package that can be created from the package information 80 is connected to the circuit thus created, and an equivalent circuit of the LSI device and the entire package is created. An equivalent circuit obtained in this way is shown in FIG.

  In FIG. 6, the resistor 123 is a ground wiring resistance in the LSI chip 120, and the resistor 124 is a power supply wiring resistance in the LSI chip 120. Further, the resistor 291 in the LSI chip 120 is a combination of the Vss terminals of each standard cell and the resistor 91 between the P-type substrates 120A, and the capacitor 292 is between the N-well of each standard cell and the P-type substrate 120A. The reverse bias PN junction capacitance 92 is summarized, the capacitance 293 is a summary of the parasitic capacitance 93 between Vdd and Vss of each standard cell, the capacitance 294 is a summary of the bypass capacitor 94 of each standard cell, and the current source 201 Is a group of current sources 101 supplied from the power supply of each standard cell, and a current source 202 is a group of current sources 102 flowing from the switching nodes of the standard cells to the substrate.

  On the other hand, between the resistors 123 and 124 on the LSI chip 120 side, the inductor 140 of one bonding wire on the package 130 side, the ground wiring resistor 95, the external power source 150, the power wiring resistor 96, and the other bonding wire are connected. An inductor 140 is connected in series.

  In the simulation process of step S24 in FIG. 3, the board noise analysis can be performed by analyzing the equivalent circuit created in the equivalent circuit creation process (step S23) using a circuit simulator.

  Next, in step S3 of FIG. 2, the control unit 16 performs a noise determination process for determining whether or not the amount of noise generated in the logic gate in the circuit block is within a predetermined range based on the control program.

  Here, from the noise analysis result of the noise analysis process in step S2, if the noise generation amount (noise voltage level, noise generation number, etc.) is within a predetermined range, the noise determination process ends (process end step), and the noise generation occurs. If the amount (noise voltage level, number of noise occurrences, etc.) exceeds a predetermined range, the process proceeds to the logic gate selection process in the next step S4.

  In the logic gate selection process in step S4, more noise than the predetermined value is generated in the logic gate (hereinafter referred to as the instance cell 76) in the circuit block (or the noise voltage level is higher than the predetermined value). The instance cell 76 (see FIGS. 14 and 15 to be described later) is selected, and the instance cell 76 that can be expected to have a high noise reduction effect when the bypass capacitor 94 is added is selected.

Since a plurality of methods can be considered for selecting the instance cell 76 described later, some examples will be shown below.
The first method is a method of selecting the instance cell 76 generating the maximum noise (such as the noise voltage level and the number of noise occurrences) from the processing result of the noise analysis process (step S2). In the case of substrate noise, since the noise receiving circuit is an analog circuit, the influence of each instance cell 76 on the analog circuit is analyzed by noise analysis processing (step S2), and the instance cell 76 having the maximum noise influence degree is analyzed. Select.

  The second method is not based on the result of actual noise analysis, but the power supply current waveform and substrate current waveform of each cell in the substrate noise macro model library 71, the switching event database 62, and the LSI chip 120. This is a method of calculating the noise influence level defined by the degree of influence of each instance cell 76 regarding the noise generation from the floor plan, and selecting the instance cell 76 having the maximum noise influence degree.

When substrate noise is targeted, the following four items are considered as the noise influence degree of each instance cell 76.
(1) ΔI / Δt of power supply current waveform
This may be obtained using the circuit simulation result as it is.
Alternatively, many techniques for approximating the power supply current waveform with a triangle have been proposed, and for example, disclosed in “di / dt Noise in CMOS Integrated Circuits” Kluwer Academic Publishers (hereinafter referred to as Conventional Example 4).

  7A shows the voltage waveform Vout of the output node of the inverter circuit of FIG. 5 (see the node 132 at the output end of FIG. 16), and FIG. 7B shows the power supply current waveform at the power supply terminal 121 (or the ground terminal 122). Represents a triangle approximation line of lout.

  7A and 7B, tf is the fall time of the node 132 at the output end, T is the time until the current at the power supply terminal 121 (or the ground terminal 122) peaks, and Ip is the power supply terminal. 121 is the peak current at 121 (or ground terminal 122).

If the power supply current is approximated by a triangle as shown in FIG. 7B, ΔI / Δt can be approximated by (Equation 1).
ΔI / Δt ≒ Ip / T (Formula 1)
In the first embodiment, ΔI / Δt can be calculated using (Equation 1) if the current source 101 in the macro model shown in FIG.

(2) Average substrate current This is obtained from a macro model.

(3) Average power consumption
Pave = Ps * Cload * Vdd * f (Formula 2)
Here, Cload is the load capacity of the logic gate, Vdd is the power supply voltage, Ps is the switching probability, and f is the clock frequency.
This is obtained from the switching event database 62 and the gate level logic circuit information 60.

(4) Distance to analog circuit that receives substrate noise This is obtained from floor plan information of the LSI device.
Therefore, the noise influence degree S is obtained by using, for example, the four items (1) to (4) described above and the parameters a, b, c, and d.
S = a * (1) + b * (2) + c * (3) + d * (4) (Formula 3)
Can be defined in

  The noise influence degree S (predetermined noise generation amount) of each instance cell 76 is calculated using (Equation 3), and the instance cell 76 having the maximum noise influence degree S is selected.

  Then, after selecting the instance cell 76 having the maximum noise influence level (a large amount of noise generation) as described above, the control unit 16 adds the bypass capacitor in step S5 of FIG. 2 based on the control program. In the process, a bypass capacitor 94 is added to the instance cell 76 selected in the logic gate selection process (step S4).

This bypass capacitor addition process will be described with reference to FIG.
As shown in FIG. 5, the standard cell library 70 has cells 78A and 78B with bypass capacitors. The logic of these two cells 78A and 78B is equivalent, and the capacitance values of the bypass capacitors 94A and 94B are different from each other. The capacitance value of the bypass capacitor 94A is smaller than the capacitance value of the bypass capacitor 94B. And

  Here, it is assumed that the cell 78A in the standard cell library 70 is assigned to the instance cell 76 selected in the logic gate selection process in step S4 of FIG. In such a case, in the bypass capacitor addition process in step S5, the capacity of the cell 78B is changed to a capacity that is equivalent to the logic and the capacity of the bypass capacitor 94 is larger than the capacity of the cell 78A before the change.

  If there is no cell 78 having the desired bypass capacitor capacity 94 in the standard cell library 70, a cell 78 having the desired bypass capacitor capacity 94 may be newly added to the standard cell library 70.

  Thereafter, the process returns from the bypass capacitor addition process in step S5 in FIG. 2 to the noise analysis process in step S2, and the processes in steps S2 to S5 are repeated in the noise determination process in step S3 until the noise generation amount falls within a predetermined range. If the noise generation amount falls within the predetermined range, the process is terminated.

  As described above, according to the first embodiment, the bypass capacitor 94 having the necessary capacity can be added near the noise source inside the circuit block constituting the semiconductor integrated circuit more effectively. Can be surely suppressed. Further, since the bypass capacitor 94 is added based on the noise analysis result of each circuit block constituting the semiconductor integrated circuit, the bypass capacitor 94 having a necessary capacity is mounted in a highly accurate and effective place. Therefore, an increase in the chip area of the LSI due to the addition of the bypass capacitor 94 having an unnecessarily large capacity can be eliminated.

  Further, if the semiconductor integrated circuit design method according to the first embodiment is used for circuit design to manufacture a semiconductor integrated circuit, the noise is surely kept within a predetermined range without increasing the chip area of the LSI. It is possible to manufacture a semiconductor integrated circuit that can be suppressed to a minimum.

(Embodiment 2)
FIG. 8 is a block diagram showing a configuration example of a main part of a low noise LSI design apparatus according to Embodiment 2 of the present invention.
In FIG. 8, a low noise LSI design apparatus 20 includes a ROM 21 as a third storage unit (readable recording medium) in which a circuit design control program and data are stored, and a RAM 22 as a fourth storage unit functioning as a work memory. A database 23 in which various data for circuit design are recorded, an operation input unit 24 that allows a user to input operation commands (including circuit design start and end commands), and an initial screen for circuit design. A display unit 25 that can display screen information and a control unit 26 that controls each unit based on the control program and data are provided to support circuit design of the semiconductor integrated circuit.

  The control unit 26 is composed of a CPU (Central Processing Unit), and includes input means 261, noise estimation means 262, capacity constraint designation means 263, comparison means 264, processing end means 265, and logic gate selection means. 266 and the bypass capacitor adding means 267, and a series of processes from the comparison of the mounting capacity and the capacity constraint by the comparing means 264 to the bypass capacitor adding process by the bypass capacitor adding means 267 until the entire process is completed. By repeating the process, a circuit pattern to which the bypass capacitor 94 is added is automatically generated.

  The input means 261 receives various circuit design information (see FIG. 9 described later) such as gate level logic circuit information 60, standard cell library information 70, and package information 80 of circuit blocks constituting the LSI device (LSI chip). Input from the database 23 as noise estimation information.

  The noise estimation unit 262 estimates the amount of noise generated (such as the noise voltage level and the number of noises) generated in the LSI device (LSI chip) using the various circuit design information input.

  The capacity constraint designating unit 263 may be mounted on a circuit block constituting the LSI device (LSI chip) based on the estimation result by the noise estimating unit 262 in order to suppress the noise generation amount within a predetermined range. A capacity constraint which is the capacity of the bypass capacitor 94 for reducing necessary power supply noise and substrate noise is designated and processed.

  The comparison unit 264 compares the mounting capacity, which is the capacity of the bypass capacitor 94 mounted on the circuit block, with the capacity constraint specified by the capacity control specifying unit 263. Then, as a result of the comparison by the comparison means 264, the processing end means 265 finishes the entire process of designing the semiconductor integrated circuit, which automatically generates the pattern of the semiconductor integrated circuit when the mounted capacity is larger than the capacity constraint. To process.

  The logic gate selection unit 266 selects and processes logic gates having a predetermined noise generation amount or more in the circuit block when the mounted capacity is equal to or less than the capacity constraint as a result of the comparison by the comparison unit 264.

  For example, the logic gate selection unit 266 calculates the noise influence level of each logic gate in the circuit block by using the information obtained by adding the floor plan information of the LSI chip to the input information, and the logic level having the maximum noise influence level is calculated. Select the gate.

  The bypass capacitor adding unit 267 adds the bypass capacitor 94 to the logic gate selected by the logic gate selecting unit 266.

The operation of the above configuration will be described below.
FIG. 9 is a flowchart showing a processing procedure of the low noise LSI design method according to the second embodiment of the present invention. In the second embodiment, an analysis of power supply noise will be described as an example.

  As shown in FIG. 9, first, the control unit 26 performs gate-level logic circuit information 60 of a circuit block constituting an LSI chip (semiconductor integrated circuit) as a noise estimation information input process in step S11 based on a control program. , Input standard cell library information 70 and LSI chip package information 80 to be used. Also, the floor plan information of the LSI chip is input as necessary.

  Next, based on the control program, the control unit 26 performs gate-level logic circuit information 60, standard cell library information 70, which is input in the noise estimation information input process in step S11 in the noise estimation process in step S12. The amount of generated noise (noise voltage level Vn and the number of generated noises) is estimated from noise estimation information such as LSI chip package information 80. As this estimation method, the method disclosed in the conventional example 4 can be used.

In FIG. 6, for example, the maximum noise voltage level Vnmax of the noise voltage level Vn generated at the power supply terminal 121 and the ground terminal 122 is
Vnmax <= (Cload) x Vdd / 2 (Cd + Cload) (Formula 4)
It is expressed.
Here, Cload is a load capacity 90, and when the output changes from “L” to “H”, Cload = Cn, and when the output changes from “H” to “L”, Cload = Cp. .

  Next, based on the control program, the control unit 26 determines a bypass capacitor capacity necessary for setting the noise generation amount (maximum noise voltage level) Vnmax to be equal to or less than a predetermined range in the bypass capacitor capacity restriction specifying process in step S13. Specify capacity constraints. This is done by calculating and specifying the required bypass capacitor capacitance Cd using (Equation 4) described above.

  Next, the control unit 26, based on the control program, in the mounting capacity determination process in step S14, the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block, and the bypass capacitor capacity constraint designation process (step S13). ), The processing ends when the installed capacity is larger than the capacity constraint (NO), and when the installed capacity is less than or equal to the capacity constraint (YES), Then, the process proceeds to the logic gate selection process in step S15.

  Then, in the cell selection process (logic gate selection process) in step S15, the instance cell 76 having a large noise generation amount in the logic gate (hereinafter referred to as the instance cell 76) in the circuit block is added, and a bypass capacitor is added. Then, the instance cell 76 that seems to have a high noise reduction effect is selected.

  This is a method of calculating the noise influence level that defines the degree of influence of each instance cell 76 regarding the occurrence of power supply noise, and selecting the instance cell 76 having the maximum noise influence level.

For power supply noise, the noise influence degree of each instance cell 76 can be calculated in consideration of the following one item.
ΔI / Δt of power supply current waveform

If the triangular approximation of the power supply current described in the logic gate selection process (step S4) of the first embodiment is obtained for all the cells, ΔI / Δt can be calculated using (Equation 1).
ΔI / Δt ≒ Ip / T (Formula 1)

Here, T is the time until the current at the power supply terminal 121 reaches a peak, and Ip is the peak current at the power supply terminal.
Therefore, the noise influence degree S is
S = Ip / T (Formula 5)
Can be defined in
The noise influence degree S of each instance cell 76 is calculated using (Formula 5), and the instance cell 76 having the maximum noise influence degree S is selected.

  Then, based on the control program, the control unit 26 adds the bypass capacitor 94 to the instance cell 76 selected in the cell selection process (step S15) in the bypass capacitor addition process in step S16 of FIG. This can be realized, for example, by changing the selected instance cell 76 to a cell having a larger capacity of the bypass capacitor 94 than before the change, and the bypass capacitor addition process (step S5) described in the first embodiment is performed. The same can be done.

  Thereafter, the process returns to the mounting capacity determination process in step S14 in FIG. 9, and the processes in steps S14 to S16 are repeated until the mounting capacity becomes larger than the capacity constraint in step S14.

  As described above, according to the second embodiment, the bypass capacitor 94 having the necessary capacity can be added near the noise source inside the circuit block constituting the LSI device more effectively. Can be surely suppressed. Further, in order to give a capacitance restriction of the bypass capacitor necessary for making the amount of noise generation below a predetermined range by estimating noise in advance, there is no need to repeat each processing and perform noise analysis as in the first embodiment. , Processing can be performed in a shorter time.

  Further, if the semiconductor integrated circuit is manufactured by using the semiconductor integrated circuit design method according to the second embodiment for circuit design, a semiconductor integrated circuit capable of reliably suppressing noise within a predetermined range is obtained. It becomes possible to manufacture in a shorter time.

(Embodiment 3)
FIG. 10 is a block diagram showing a configuration example of a main part of a low noise LSI design apparatus according to Embodiment 3 of the present invention.
In FIG. 10, a low noise LSI design device 30 includes a ROM 31 as a fifth storage unit (readable recording medium) storing a control program and data for circuit design, and a RAM 32 as a sixth storage unit functioning as a work memory. A database 33 in which various data for circuit design are recorded, an operation input unit 34 that allows a user to input an operation command, a display unit 35 that can display various screen information such as an initial screen, a control program, And a control unit 36 for controlling each unit based on the data to support circuit design of the semiconductor circuit.

  The control unit 36 is constituted by a CPU (Central Processing Unit), and includes input means 361, gate level conversion means 362, mapping processing means 363, comparison means 364, processing end means 365, and logic gate selection means. 366 and mapping change processing means 367, and a series of processes from comparison processing for comparing the installed capacity by the comparison means 364 with the capacity constraint until the entire processing is completed, and until the mapping change processing by the mapping change means 367. By repeating this process, a circuit pattern to which the bypass capacitor 94 is added is automatically generated.

  The input means 361 controls the logic block functional specification information (HDL) 65, the standard cell library information 70, and the noise generation amount of circuit blocks constituting the LSI device (LSI chip) within a predetermined range. A capacity constraint 68 (see FIG. 11 described later), which is the capacity of a bypass capacitor 94 for reducing power supply noise and substrate noise that must be mounted on the circuit block, is input from the database 33.

The gate level conversion means 362 converts the logic circuit into a gate level logic circuit based on the function level.
The mapping processing means 363 performs mapping processing for allocating cells in the standard cell library information 70 to all the logic gates in the gate level logic circuit.

  The comparing means 364 compares the mounting capacity, which is the capacity of the bypass capacitor 94 mounted on the logic circuit, with the capacity constraint. Then, the processing end means 365 outputs the gate level logic circuit information 66 to the database 33 and stores it in the database 33 when the mounted capacity is larger than the capacity constraint as a result of the comparison in the comparison means 364. Then, all the processes of the semiconductor integrated circuit for automatically generating the pattern of the semiconductor integrated circuit are completed.

  The logic gate selection unit 366 selects a logic gate having a predetermined noise generation amount or more when the mounted capacity is equal to or less than the capacity constraint as a result of the comparison by the comparison unit 364.

  The mapping change processing unit 367 is equivalent to the bypass capacitor 94 mounted on the inside with the same mapping cell and logic assigned in the mapping processing by the mapping processing unit 363 with respect to the logic gate selected by the logic gate selection unit 366. The allocation is changed to another cell having a different capacity, or a process of additionally allocating a bypass capacitor cell including only the bypass capacitor 94 to the mapping cell is performed.

The operation of the above configuration will be described below.
FIG. 11 is a flowchart showing a processing procedure of the low noise LSI design method according to the third embodiment of the present invention.

  As shown in FIG. 11, in the logic synthesis process in step S100 based on the control program, the control unit 36 firstly includes functional specification information (HDL) 65 of the logic circuit, standard cell library information 70, and bypass capacitor capacity constraint. 68 is input from the database 33.

  Here, the capacity restriction 68 of the bypass capacitor 94 is a restriction on the capacity of the bypass capacitor 94 to be mounted in the circuit block in order to reduce the amount of noise generation (noise voltage level, number of noise generations, etc.). It can also be specified and stored in the database 33.

Also, using the functional specification information (HDL) 65 of the input logic circuit, the power consumption P of the circuit block is estimated with a commercially available power consumption estimation tool, and the load of the circuit block is calculated using (Equation 6) shown below. The capacitance Cload is obtained, and the obtained load capacitance Cload is input to (Equation 4) described in the second embodiment to calculate the required bypass capacitor capacitance Cd, which is designated as the bypass capacitor capacitance constraint 68. Also good.
Cload = P / f * Vdd2 (Formula 6)
Here, Cload is the load capacity of the logic gate, P is power consumption, f is the clock frequency, and Vdd is the power supply voltage.

  The standard cell library 70 is provided with cells 78 with bypass capacitors having the same logic and different capacities of the bypass capacitors 94 included therein. For example, the standard cell library 70 described with reference to FIG. 5 in the first embodiment is an example.

  Further, the standard cell library 70 may include a bypass capacitor cell 77 (see FIG. 15 described later) including only the bypass capacitor 94.

The logic synthesis process in step S100 includes the following processes.
First, the gate level conversion process in step S101 after the input process is a process of converting the logic circuit from the functional specification (HDL) to the gate level.

  Next, in the technology mapping process in step S102, a mapping process is performed in which all logic gates in the circuit block of the LSI device are allocated to cells in the standard cell library 70 to be used.

  A feature of the third embodiment is that the entire cell allocation is performed so as to satisfy the given bypass capacitor capacity constraint 68. A logic gate to which a cell is assigned is called an instance cell 76.

  Next, in the mounting capacity determination process in step S103, the mounting capacity that is the total capacity of the bypass capacitors 94 currently mounted in the circuit block 300 (see FIGS. 14 and 15) and the bypass capacitor capacity constraint 68 are determined. In comparison, if the mounted capacity is larger than the bypass capacitor capacity constraint 68, the gate level logic circuit information 66 is output to the database 33, and the process is terminated.

  On the other hand, in the mounting capacity determination process in step S103, if the current mounting capacity is smaller than the bypass capacitor capacity constraint 68, the process proceeds to the next logic gate selection process in step S104.

Next, in the logic gate selection process of step S104, the instance cell 76 that is considered to have generated a noise generation amount larger than a predetermined value among the instance cells 76 in the circuit block, and the noise is most reduced. The instance cell 76 that is likely to be generated and the instance cell 76 that is considered to have a high noise reduction effect when the bypass capacitor 94 is increased is selected.
This can be performed in the same manner as the logic gate selection process (step S15) described in the second embodiment.

  In the subsequent mapping change processing in step S105, assignment is made to the cells 78 in the standard cell library 70 which are equivalent in logic to the selected instance cell 76 and different in the size of the bypass capacitor 94. Perform the mapping change process to be changed.

  Now, it is assumed that the cell 78A in the standard cell library 70 shown in FIG. 5 is assigned to the instance cell 76 selected in the logic gate selection process (step S104) in the technology mapping process (step S102). .

  In such a case, in this mapping change process (step S105), the assignment is changed to the cell 78B whose logic is equivalent and the capacity of the bypass capacitor 94 is larger than the cell 78A before the change.

  Alternatively, in this mapping change process (step S105), a bypass capacitor cell 77 consisting only of the bypass capacitor 94 can be additionally allocated to the instance cell 76 selected in the logic gate selection process (step S104). That is, the instance cell 76 is assigned with two cells, that is, the cell 78A and the bypass capacitor cell 77 including only the bypass capacitor 94.

  Thereafter, the process returns to the mounting capacity determination process in step S103, and the processes in steps S103 to S105 are repeated until the process is completed.

  As described above, according to the third embodiment, since the circuit block constituting the LSI device can satisfy the bypass capacitor capacity constraint 68, the cell with the bypass capacitor can be allocated to the logic gate having a larger noise generation amount. To obtain a logic synthesis method that can add a necessary amount of bypass capacitors 94 near the noise source in the circuit block more effectively, and can reliably suppress the amount of noise generation within a specified range. Can do.

  Further, if a semiconductor integrated circuit is manufactured by using the semiconductor integrated circuit design method according to the third embodiment for circuit design, a necessary amount of bypass capacitors are added near the noise source in the circuit block. Thus, it is possible to manufacture a semiconductor integrated circuit capable of reliably suppressing noise within a predetermined range.

(Embodiment 4)
FIG. 12 is a block diagram showing a configuration example of a main part of a low noise LSI design apparatus according to Embodiment 4 of the present invention.
In FIG. 12, a low noise LSI design apparatus 40 includes a ROM 41 as a seventh storage unit (readable recording medium) in which a circuit design control program and data are stored, and a RAM 42 as an eighth storage unit functioning as a work memory. A database 43 in which various data for circuit design are recorded, an operation input unit 44 that allows a user to input operation commands, a display unit 45 that can display various screen information such as an initial screen, a control program, And a control unit 46 that controls each unit based on the data, and supports circuit design of the semiconductor integrated circuit.

  The control unit 46 is composed of a CPU (central processing unit), and includes an input unit 461, a cell placement unit 462, a comparison unit 463, a processing end unit 464, and a bypass capacitor cell addition unit 465. Until the entire process is completed, a circuit pattern is automatically obtained by repeating a series of processes from the process of comparing the mounting capacity and the capacity constraint by the comparison unit 463 to the bypass capacitor cell insertion process by the bypass capacitor cell addition unit 465. Generate.

  The input means 461 includes a netlist 63 of a circuit block constituting a semiconductor integrated circuit (LSI chip), a cell library 72 including a bypass capacitor cell including at least one bypass capacitor for reducing power supply noise and substrate noise, and noise. In order to reduce the generation amount (noise voltage level and the number of noise occurrences), a bypass capacitor capacity constraint 68 (see FIG. 13 described later), which is a capacity of a bypass capacitor that is required to be mounted on the circuit block, is obtained from the database 43. Input processing.

The cell placement unit 462 places the cells in a plurality of parallel cell rows according to the netlist 63.
The comparison unit 463 compares the mounting capacity, which is the capacity of the bypass capacitor mounted on the circuit block, with the bypass capacitor capacity constraint 68. Then, as a result of the comparison in the comparison unit 463, the processing end unit 464 automatically generates a pattern of the semiconductor integrated circuit when the mounted capacitance is larger than the bypass capacitor capacity constraint. End processing.

  The bypass capacitor cell adding means 465 inserts a bypass capacitor cell in the cell row when the comparison is made by the comparison means 463 and the mounted capacity is not more than the bypass capacitor capacity constraint.

The operation of the above configuration will be described below.
FIG. 13 is a flowchart showing a processing procedure of a low noise LSI layout design method according to the fourth embodiment of the present invention.

  As shown in FIG. 13, first, the control unit 46 creates a netlist 63 of circuit blocks constituting the LSI chip and a bypass capacitor cell 77 consisting only of a bypass capacitor in the input process of step S1001 based on the control program. The cell library information 72 including at least one and the capacity restriction 68 of the bypass capacitor to be mounted on the circuit block are input from the database 43.

  For example, as a bypass capacitor cell 77 (see FIG. 15) included in the cell library 72, a cell 77 whose bypass capacitor capacity is A, for example, is prepared.

  The bypass capacitor capacity constraint 68 can be manually specified using, for example, past design know-how. Here, a description will be given assuming that, for example, 3A is specified as the bypass capacitor capacity restriction.

  Next, in accordance with the control program, the control unit 46 converts the cells 76 (see FIGS. 14 and 15) in the circuit block 300 into a plurality of parallel cell rows in accordance with the netlist 63 in the cell placement process in step S1002. 210. FIG. 14 shows the state after cell placement. In FIG. 14, the cells 76 in the circuit block 300 are arranged in three cell rows 210 parallel to each other.

  Further, based on the control program, the control unit 46 specifies the mounting capacity that is the total of the bypass capacitors 94 currently mounted in the circuit block 300 and the input processing S1001 in the mounting capacity determination process in step S1003. The bypass capacitor capacity constraint 68 is compared, and if the mounted capacity is larger than the bypass capacitor capacity constraint 68, the process ends. On the other hand, if the mounted capacity is smaller than the bypass capacitor capacity constraint 68, the process proceeds to the bypass capacitor cell insertion process in the next step S1004.

  In the bypass capacitor cell insertion processing in step S1004, the bypass capacitor cell 77 is inserted into the arranged cell row 210.

FIG. 15 shows a state where the bypass capacitor cell 77 is inserted into the circuit block 300 of FIG. Reference numeral 220 denotes an empty area in the circuit block 300.
The bypass capacitor cell 77 may be inserted anywhere, but it is preferable to insert the bypass capacitor cell 77 near the cell 76 that generates a large noise.

  Therefore, in FIG. 15, as an insertion position of the bypass capacitor cell 77, it is predicted that the larger the area, the larger the size of the transistor included therein, and thus the larger the area, the higher the possibility of generating large noise. It arrange | positioned beside large cell 76A, 76B, 76C.

  The bypass capacitor cell insertion process (step S1004) is repeated until the mounting capacity in the circuit block 300 exceeds the bypass capacitor cell capacity constraint 68.

  For example, here, 3A is given as the bypass capacitor capacity constraint 68, and the bypass capacitor cell 77 includes a capacity of A in one cell. Therefore, as shown in FIG. When the three bypass capacitor cells 77 are arranged, the entire process is completed.

  As described above, according to the fourth embodiment, the bypass capacitor cell 77 can be inserted in the cell row 210 arranged in the circuit block 300 as shown in FIG. A place to place the capacitor can be secured, and the amount of noise generation can be reliably suppressed to a predetermined range or less.

  Further, if the semiconductor integrated circuit design method according to the fourth embodiment is used for circuit design to manufacture a semiconductor integrated circuit, a place for disposing a bypass capacitor in the vicinity of the noise source is ensured, and the arrangement is made. By inserting a bypass capacitor cell at a location, it becomes possible to manufacture a semiconductor integrated circuit capable of reliably suppressing noise below a predetermined range.

In the first embodiment, (Equation 3) is given as an example of the calculation of the noise influence degree, but the present invention is not limited to this.
In the first embodiment, a circuit simulator may be used for noise analysis.
Further, in the second embodiment, (Equation 5) is given as an example of the calculation of the noise influence degree, but the present invention is not limited to this.
Further, in the fourth embodiment, in order to satisfy the bypass capacitor capacity restriction 68, an empty area of the circuit block may be used.

  More specifically, for example, in FIG. 15, the bypass capacitor 94 can be formed in the empty area 220 where the cell row 210 is not arranged in the circuit block 300, so that the bypass capacitor capacity constraint 68 is satisfied. In addition, this empty area 220 can be used.

  If the capacity of the bypass capacitor 94 mounted in the free space 220 is, for example, B and 3A is specified as the bypass capacitor capacity constraint 68, for example, it is considered that the bypass capacitor capacity constraint 68 is obtained by subtracting B from 3A. Since the bypass capacitor cell 77 has only to be arranged, an increase in area due to the addition of the bypass capacitor cell 77 can be suppressed.

  Furthermore, in the said Embodiment 4, although demonstrated using one type of cell containing the capacity | capacitance A as the bypass capacitor cell 77, the same effect can be acquired even if it uses multiple bypass capacitor cells with a different capacity | capacitance.

  INDUSTRIAL APPLICABILITY The present invention is useful as a device capable of automatically generating a semiconductor integrated circuit pattern in which the amount of noise generation is reliably suppressed within a predetermined range.

It is a block diagram which shows the principal part structural example of the low noise LSI design apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process sequence of the low noise LSI design method which concerns on Embodiment 1 of this invention. It is a flowchart which shows an example of the noise analysis process (step S2) of FIG. FIG. 4 is an equivalent circuit diagram of a macro model of a cell generated in the characterization process (step S21) of FIG. FIG. 3 is an equivalent circuit diagram showing a cell with a bypass capacitor in the standard cell library of FIG. 2. FIG. 4 is an equivalent circuit diagram of the LSI chip and the entire package obtained by the equivalent circuit creation processing of FIG. 3. 5A is a voltage waveform diagram at the output node of the inverter circuit of FIG. 5, and FIG. 4B is a power supply current waveform diagram at the power supply terminal. It is a block diagram which shows the principal part structural example of the low noise LSI design apparatus which concerns on Embodiment 2 of this invention. It is a flowchart which shows the process sequence of the low noise LSI design method which concerns on Embodiment 2 of this invention. It is a block diagram which shows the principal part structural example of the low noise LSI design apparatus which concerns on Embodiment 3 of this invention. It is a flowchart which shows the process sequence of the low noise LSI design method which concerns on Embodiment 3 of this invention. It is a block diagram which shows the principal part structural example of the low noise LSI design apparatus which concerns on Embodiment 4 of this invention. It is a flowchart which shows the process sequence of the low noise LSI design method which concerns on Embodiment 4 of this invention. It is a figure which shows the state after cell arrangement | positioning. It is a figure which shows the state which has arrange | positioned the bypass capacitor cell in a cell row. It is an equivalent circuit diagram of the LSI chip and the entire package for explaining a conventional power supply noise generating mechanism.

Explanation of symbols

10, 20, 30, 40 Low noise LSI design device 11, 21, 31, 41 ROM
12, 22, 32, 42 RAM
13, 23, 33, 43 Database 14, 24, 34, 44 Operation input unit 15, 25, 35, 45 Display unit 16, 26, 36, 46 Control unit 161, 261, 361, 461 Input unit 162 Noise analysis unit 163 Noise determination means 164, 265, 365, 464 Processing end means 165, 266, 366 Logic gate selection means 166, 267 Bypass capacitor addition means 262 Noise estimation means 263 Capacity constraint designation means 264, 364, 463 Comparison means 362 Gate level conversion means 363 Mapping processing means 367 Mapping change processing means 462 Cell placement means 465 Bypass capacitor cell addition means 60 Circuit block gate level logic circuit information 62 Switching event database 63 Netlist information 65 Logic circuit information Functional specification information 66 Gate level logic circuit information 68 Bypass capacitor capacity constraint 70 Standard cell library information 71 Substrate noise macro model library 72 Cell library including at least one bypass capacitor cell 77 76 Instance cells 76A, 76B, 76C Generates large noise Instance cell to perform 77 Bypass capacitor cell 78 Cell with bypass capacitor 90 LSI chip internal load 80 LSI chip package information 91 Resistance between Vss and substrate 92 Reverse bias PN junction capacitance between N-well and P substrate 93 Vdd and Vss Capacitance formed in a parasitic manner 94 Bypass capacitor 95 Ground wiring resistance 96 Power supply wiring resistance 101 Current source representing current supplied from the power supply 102 Current flowing from the switching node to the substrate Current source 120 LSI chip 120A Substrate 121 Power supply terminal 122 Ground terminal 123 In-LSI ground wiring resistance 124 In-LSI power wiring resistance 130 Package 140 Inductor of bonding wire 150 External power supply 201 Indicates current supplied from the power supply of each standard cell Current source 202 including current source 101 Current source (substrate current) 102 representing current flowing from the switching node to the substrate of each standard cell 210 Current cell 210 Cell row 220 Free space in circuit block 300 291 Each standard cell 292 Summarizing resistance 91 between Vss terminal and P-type substrate 292 Capacitance of reverse bias PN junction capacitance 92 between N-well and P substrate of each standard cell 293 Parasitic capacitance between Vdd and Vss of each standard cell Capacity of 93 294 Capacitance of bypass capacitors 94 for each standard cell 300 circuit block

Claims (9)

In a semiconductor integrated circuit design apparatus that is controlled by a computer and automatically generates a pattern of a semiconductor integrated circuit,
Reduction of power supply noise and substrate noise required to be mounted on the circuit block in order to keep the functional specification information, standard cell library information, and noise generation amount of the logic circuit block constituting the semiconductor integrated circuit within a predetermined range. An input means for inputting a capacity constraint that is a capacity of a bypass capacitor for
Gate level conversion means for converting the functional specification information of the logic circuit into gate level logic circuit information based on the function level;
Mapping processing means for performing mapping processing for allocating cells in the standard cell library information to all logic gates in the gate level logic circuit;
A mounting capacity which is a capacity of a bypass capacitor mounted on the logic circuit mapped by the mapping processing means, and a comparison means for comparing the capacity constraint;
In the comparison by the comparison means, when the mounting capacity is larger than the capacity constraint, a process ending means for ending the process of automatically generating the pattern of the semiconductor integrated circuit;
In the comparison by the comparison means, when the mounted capacity is less than or equal to the capacity constraint, logic gate selection means for selecting a logic gate having a predetermined noise generation amount or more;
Whether the assignment is changed to another cell in which the logic and the mapping cell assigned in the mapping process are equivalent to the logic gate selected by the logic gate selection means and the capacity of the bypass capacitor mounted inside is different. Or a mapping change processing means for additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the mapping cell,
A semiconductor integrated circuit design apparatus. In a semiconductor integrated circuit design apparatus that is controlled by a computer and automatically generates a pattern of a semiconductor integrated circuit,
Netlist information of circuit blocks constituting the semiconductor integrated circuit, cell library information including a bypass capacitor cell composed of at least one bypass capacitor for reducing power supply noise and substrate noise, and the circuit for reducing noise generation An input means for performing input processing of a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted on the block;
Cell placement means for placing cells in a plurality of parallel cell rows according to the netlist information;
Comparison means for comparing the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block, with the capacity constraint;
In the comparison by the comparison means, when the mounting capacity is larger than the capacity constraint, a process ending means for ending the process of automatically generating the pattern of the semiconductor integrated circuit;
In the comparison by the comparison means, when the mounted capacity is equal to or less than the total capacity constraint, there is a bypass capacitor cell addition means for inserting a bypass capacitor cell in the cell row,
A semiconductor integrated circuit design apparatus. In a semiconductor integrated circuit design method for automatically generating a pattern of a semiconductor integrated circuit controlled by a computer,
Reduction of power supply noise and substrate noise required to be mounted on the circuit block in order to keep the functional specification information, standard cell library information, and noise generation amount of the logic circuit block constituting the semiconductor integrated circuit within a predetermined range. An input step for processing a capacity constraint that is the capacity of the bypass capacitor for
A gate level conversion step of converting the functional specification information of the logic circuit into gate level logic circuit information based on the function level;
A mapping process step for performing a mapping process for allocating cells in the standard cell library information to all the logic gates in the gate level logic circuit;
A comparison step of comparing the mounting capacity, which is the capacity of a bypass capacitor mounted in the mapped logic circuit, with the capacity constraint;
As a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit;
As a result of the comparison, when the mounted capacity is less than or equal to the capacity constraint, a logic gate selection step of selecting a logic gate having a predetermined noise generation amount or more;
For the selected logic gate, the mapping cell assigned in the mapping process is equivalent to the mapping cell, and the allocation is changed to another cell having a different capacity of the bypass capacitor mounted therein, or the mapping is changed. A mapping change processing step for additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the cell,
In the mapping change processing step, the assignment has been changed to the other cell, or after additionally assigning the bypass capacitor cell, returning to the comparison step, the assignment has been changed to the other cell, or A comparison is made between the capacity restriction and the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block to which the bypass capacitor cell is additionally allocated,
A method for designing a semiconductor integrated circuit. The semiconductor integrated circuit design method according to claim 3,
The standard cell library information is cell library information used for designing the semiconductor integrated circuit, and includes at least one set of bypass capacitor-attached cell information in which the circuit logic is equivalent and the capacity of the bypass capacitor mounted therein is different.
A method for designing a semiconductor integrated circuit. In a semiconductor integrated circuit design method for automatically generating a pattern of a semiconductor integrated circuit controlled by a computer,
Netlist information of circuit blocks constituting the semiconductor integrated circuit, cell library information including a bypass capacitor cell composed of at least one bypass capacitor for reducing power supply noise and substrate noise, and the circuit for reducing noise generation An input step for inputting a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise that needs to be mounted on the block;
A cell placement step of placing cells in a plurality of parallel cell rows according to the netlist information;
A comparison step of comparing the mounting capacity, which is the capacity of a bypass capacitor mounted in the circuit block, with the capacity constraint;
As a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit;
A bypass capacitor cell adding step of inserting a bypass capacitor cell in the cell row when the mounted capacity is equal to or less than the total capacity constraint as a result of the comparison, and
After the bypass capacitor cell is inserted in the bypass capacitor cell adding step, the process returns to the comparison step, and a mounting capacity that is a capacity of the bypass capacitor mounted on the circuit block in which the bypass capacitor cell is inserted, and the capacity constraint Compare with
A method for designing a semiconductor integrated circuit. A semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit using a semiconductor integrated circuit design method controlled by a computer to automatically generate a semiconductor integrated circuit pattern for circuit design,
The semiconductor integrated circuit design method needs to be mounted on the circuit block in order to keep the functional specification information, standard cell library information, and noise generation amount of the logic circuit block constituting the semiconductor integrated circuit within a predetermined range. An input step for inputting a capacity constraint which is a capacity of a bypass capacitor for reducing power supply noise and substrate noise,
A gate level conversion step of converting the functional specification information of the logic circuit into gate level logic circuit information based on the function level;
A mapping process step for performing a mapping process for allocating cells in the standard cell library information to all the logic gates in the gate level logic circuit;
A comparison step of comparing the mounting capacity, which is the capacity of a bypass capacitor mounted in the mapped logic circuit, with the capacity constraint;
As a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit;
As a result of the comparison, when the mounted capacity is less than or equal to the capacity constraint, a logic gate selection step of selecting a logic gate having a predetermined noise generation amount or more;
For the selected logic gate, the mapping cell assigned in the mapping process is equivalent to the mapping cell, and the allocation is changed to another cell having a different capacity of the bypass capacitor mounted therein, or the mapping is changed. A mapping change processing step for additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the cell,
In the mapping change processing step, the assignment has been changed to the other cell, or after additionally assigning the bypass capacitor cell, returning to the comparison step, the assignment has been changed to the other cell, or The bypass capacitor cell is to compare the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block additionally allocated, and the capacity constraint.
A method of manufacturing a semiconductor integrated circuit. A semiconductor integrated circuit manufacturing method for manufacturing a semiconductor integrated circuit using a semiconductor integrated circuit design method controlled by a computer to automatically generate a semiconductor integrated circuit pattern for circuit design,
The semiconductor integrated circuit design method includes: netlist information of circuit blocks constituting the semiconductor integrated circuit; cell library information including a bypass capacitor cell including only at least one bypass capacitor for reducing power supply noise and substrate noise; and noise generation An input step for inputting a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted on the circuit block in order to reduce the amount;
A cell placement step of placing cells in a plurality of parallel cell rows according to the netlist information;
A comparison step of comparing the mounting capacity, which is the capacity of a bypass capacitor mounted in the circuit block, with the capacity constraint;
As a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit;
A bypass capacitor cell adding step of inserting a bypass capacitor cell in the cell row when the mounted capacity is equal to or less than the total capacity constraint as a result of the comparison, and
After the bypass capacitor cell is inserted in the bypass capacitor cell adding step, the process returns to the comparison step, and a mounting capacity that is a capacity of the bypass capacitor mounted on the circuit block in which the bypass capacitor cell is inserted, and the capacity constraint Is a comparison with
A method of manufacturing a semiconductor integrated circuit. A readable recording medium in which a semiconductor integrated circuit design program for causing a computer to design a semiconductor integrated circuit is recorded in a computer-readable manner,
The semiconductor integrated circuit design program needs to be installed in the circuit block in order to keep the functional specification information, standard cell library information, and noise generation amount of the logic circuit block constituting the semiconductor integrated circuit within a predetermined range. An input step for inputting a capacity constraint which is a capacity of a bypass capacitor for reducing power supply noise and substrate noise,
A gate level conversion step of converting the functional specification information of the logic circuit into gate level logic circuit information based on the function level;
A mapping process step for performing a mapping process for allocating cells in the standard cell library information to all the logic gates in the gate level logic circuit;
A comparison step of comparing the mounting capacity, which is the capacity of a bypass capacitor mounted in the mapped logic circuit, with the capacity constraint;
As a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit;
As a result of the comparison, when the mounted capacity is less than or equal to the capacity constraint, a logic gate selection step of selecting a logic gate having a predetermined noise generation amount or more;
For the selected logic gate, the mapping cell assigned in the mapping process is equivalent to the mapping cell, and the allocation is changed to another cell having a different capacity of the bypass capacitor mounted therein, or the mapping is changed. A mapping change processing step for additionally assigning a bypass capacitor cell consisting only of a bypass capacitor to the cell,
In the mapping change processing step, the assignment has been changed to the other cell, or after additionally assigning the bypass capacitor cell, returning to the comparison step, the assignment has been changed to the other cell, or The bypass capacitor cell is to compare the mounting capacity, which is the capacity of the bypass capacitor mounted in the circuit block additionally allocated, and the capacity constraint.
A readable recording medium characterized by the above. A readable recording medium in which a semiconductor integrated circuit design program for causing a computer to design a semiconductor integrated circuit is recorded in a computer-readable manner,
The semiconductor integrated circuit design program includes: netlist information of circuit blocks constituting the semiconductor integrated circuit; cell library information including a bypass capacitor cell including at least one bypass capacitor for reducing power supply noise and substrate noise; and noise generation An input step for inputting a capacity constraint that is a capacity of a bypass capacitor for reducing power supply noise and substrate noise, which is required to be mounted on the circuit block in order to reduce the amount;
A cell placement step of placing cells in a plurality of parallel cell rows according to the netlist information;
A comparison step of comparing the mounting capacity, which is the capacity of a bypass capacitor mounted in the circuit block, with the capacity constraint;
As a result of the comparison, when the mounting capacity is larger than the capacity constraint, a process ending step of ending the process of automatically generating the pattern of the semiconductor integrated circuit;
A bypass capacitor cell adding step of inserting a bypass capacitor cell in the cell row when the mounted capacity is equal to or less than the total capacity constraint as a result of the comparison, and
After the bypass capacitor cell is inserted in the bypass capacitor cell adding step, the process returns to the comparison step, and a mounting capacity that is a capacity of the bypass capacitor mounted on the circuit block in which the bypass capacitor cell is inserted, and the capacity constraint Is a comparison with
A readable recording medium characterized by the above.

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