JP2005038400A - Method and device for estimating simultaneous switching output noise of semiconductor integrated circuit,and method and device for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for estimating SSO noise capable of estimating the SSO (simultaneous switching output) noise of a semiconductor integrated circuit by analytical calculation in a short time without performing circuit simulation. <P>SOLUTION: The method and device for estimating the SSO noise of the semiconductor integrated circuit, A SSO noise calculation means 27 calculates based on electrical-characteristics information on a package (inductance of a lead, inductance of a bonding wire) stored in a package electrical-characteristics information storage means 23, constitution information on an input/output circuit (kind and number of a signal circuit, a kind and number of a power supply circuit) stored in an input/output circuit configuration information storage means 24, the electrical-characteristics information on the package and a parameter for estimating the SSO noise stored in a parameter storage means 25 for estimating the SSO noise. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method and apparatus for estimating a simultaneous switching output (hereinafter referred to as SSO [simultaneous switching output]) noise of a semiconductor integrated circuit suitable for use in designing a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit. .

  A semiconductor integrated circuit (LSI) is mounted on a package for connection to a printed circuit board, protection from external contamination, and the like. FIG. 29 is a schematic perspective view showing an example of a state in which a semiconductor integrated circuit is mounted on a package. In FIG. 29, 1 is a semiconductor integrated circuit, 2 is a pad, 3 is an input / output circuit, and 4 is a core part. Reference numeral 5 denotes a package on which the semiconductor integrated circuit 1 is mounted, 6 is a pin, 7 is a lead, and 8 is a bonding wire.

  The input / output circuit 3 includes a signal circuit and a power supply circuit. The signal circuit includes an output circuit that only outputs signals to the outside, an input circuit that only inputs signals from the outside, and a bidirectional circuit that can both output signals to the outside and input signals from outside. There is. The power supply circuit includes a VDD power supply circuit for inputting the power supply voltage VDD and a GND power supply circuit for inputting the ground voltage GND.

  The power supply circuit must supply a constant voltage to the semiconductor integrated circuit 1, but in reality the voltage is not constant due to an electrical parasitic element. In general, resistance, inductance, and capacitance are parasitic on the metal wiring. The same applies to the metal wiring in the package 5. These electric parasitic elements cause various problems that hinder the operation of the semiconductor integrated circuit 1.

  FIG. 30 is a diagram in which the semiconductor integrated circuit 1 and the package 5 shown in FIG. 29 are modeled by electric elements. In FIG. 30, 9 is an external power supply, 10 is a ground, 11 is a resistance component of the lead 7 and the bonding wire 8, 12 is an inductance component of the lead 7 and the bonding wire 8, 13 is an input circuit, 14 is an output circuit, and 15 is both Direction circuit, 16 is a VDD power supply circuit, and 17 is a GND power supply circuit.

  Reference numeral 18 denotes a model of a part of the core unit 4. Reference numeral 19 denotes a VDD power supply wiring model that models the VDD power supply wiring. Reference numeral 20 denotes a GND power supply wiring model that models the GND power supply wiring. Reference numeral 21 denotes a VDD power supply wiring model 19. A current consumption model that models the current consumed by a logic gate or the like existing between the GND power supply wiring model 20, and 22 models the capacity that exists between the VDD power supply wiring model 19 and the GND power supply wiring model 20. Capacity model.

  When the plurality of output circuits 14 of the semiconductor integrated circuit 1 and the output circuit 15A of the plurality of bidirectional circuits 15 are simultaneously switched to the same phase, a large current flows through the VDD power supply wiring or the GND power supply wiring. When a current change occurs in the inductance component 12, a voltage represented by V = Ldi / dt is induced at both ends of the inductance component 12 of the lead 7 and the bonding wire 8. Here, L is the inductance of the inductance component 12.

  For example, when the L level signal is output simultaneously from the state in which the output circuits 15A,..., 15A in the plurality of output circuits 14,. As shown in FIG. 31A, currents ia,..., Are connected to the GND power supply wiring from the outside via a plurality of output circuits 14,..., 14 and a plurality of bidirectional circuits 15,. ia flows in. As a result, a large current IA flows from the GND power supply wiring to the ground 10 via the GND power supply circuit 17, the bonding wire 8 and the lead 7. At this time, the voltage of the GND power supply line rises by Ldi / dt from the ground voltage GND as shown in FIG. 31B.

  On the other hand, the H level signal is simultaneously output from the state in which the output circuits 15A,..., 15A in the plurality of output circuits 14,. When output, as shown in FIG. 32A, the current ib is externally supplied from the VDD power supply wiring through the plurality of output circuits 14,..., 14 and the output circuits 15A in the plurality of bidirectional circuits 15,. ..., ib flows out. As a result, a large current IB flows from the external power supply 9 to the VDD power supply wiring via the lead 7 and the bonding wire 8. At this time, the voltage of the VDD power supply line drops by Ldi / dt from the power supply voltage VDD as shown in FIG. 32B.

As described above, in a packaged semiconductor integrated circuit, when a plurality of output circuits are simultaneously switched to the same phase, the voltage of the VDD power supply wiring or the GND power supply wiring fluctuates. The fluctuations of the voltages VDD and GND are generally called SSO noise. Since fluctuations in the power supply voltages VDD and GND cause malfunction of the semiconductor integrated circuit and a decrease in operation speed, efforts have been made to reduce SSO noise, which is one of fluctuations in the power supply voltages VDD and GND. (For example, refer to Patent Document 1).
JP 2002-223077 A

  In recent years, the life cycle of products has become shorter, so the time-to-market requirements (for those developing / designing semiconductor integrated circuits, demands from customers to meet deadlines) have become stricter, but semiconductor integrated circuits are as specified. If it doesn't work, you will be forced to deal with the trouble, and you will be forced to spend extra money. In a thin semiconductor integrated circuit, excessive cost generation causes a deficit. Also, if a failure occurs, the delivery date of the semiconductor integrated circuit is delayed, leading to missed business opportunities.

  Here, semiconductor integrated circuits tend to be highly integrated, which is a factor for lowering the operating voltage. When the operating voltage of the semiconductor integrated circuit is lowered, the noise tolerance of the semiconductor integrated circuit becomes weak and the noise margin is lowered. For this reason, the frequency of occurrence of a failure that the semiconductor integrated circuit malfunctions due to noise or does not operate with the performance according to the specification is increasing.

  Therefore, in the semiconductor integrated circuit, the importance of designing considering noise is increasing. Even if the design is not designed in consideration of noise, the semiconductor integrated circuit may operate normally, but this is only a coincidence. In order for a semiconductor integrated circuit to operate normally, it is necessary to design the semiconductor integrated circuit by a design technique including noise countermeasures.

  One of the obstacle factors of the semiconductor integrated circuit is the SSO noise described above. In a semiconductor integrated circuit, the current flowing through the VDD power supply wiring and the GND power supply wiring tends to increase due to the increase in the number of pins. In addition, the current change rate per unit time of the final stage transistor of the output circuit tends to increase due to the increase in speed. As a result, SSO noise tends to increase, and countermeasures are indispensable.

  In the past, efforts to reduce SSO noise have improved the mounting technology of semiconductor integrated circuits so that the inductance components of bonding wires and lead frames are reduced, so that capacitors are built in the connection between the input / output circuit and the external power supply / ground. The semiconductor device has been improved (hardware improvement) such as mounting a semiconductor integrated circuit and attaching a circuit for suppressing SSO noise to the output circuit. However, in order to reduce the SSO noise, it is necessary to suppress the SSO noise by a software approach at the design stage of the semiconductor integrated circuit in addition to the improvement of the hardware.

  In order to suppress the SSO noise at the design stage of the semiconductor integrated circuit, a method for estimating the SSO noise is required. As a method for estimating the SSO noise, for example, there is a method using a circuit simulator. However, in this method, it is necessary to perform circuit simulation many times under different conditions, and it takes a very long time (for example, 3 per simulation). Takes ~ 5 hours). That is, in the circuit simulation, only the noise value is obtained, and the parameters necessary for suppressing the SSO noise are not calculated. Therefore, it is necessary to perform circuit simulation many times under different conditions. A lot of man-hours.

  Further, regarding the insertion of the power supply circuit, since there is no optimum arrangement means of the power supply circuit, there is a case where noise is biased or peak noise is locally increased. For this reason, it is necessary to perform power supply circuit arrangement according to practice or to confirm several power supply circuit arrangement patterns by circuit simulation. The former is not a reasonable solution. The latter requires a simulation cost and requires a large number of design steps.

  In view of the above, the present invention is necessary for SSO noise estimation method and apparatus for semiconductor integrated circuit capable of estimating SSO noise in a short time by analytical calculation without performing circuit simulation, and for suppressing SSO noise. An object of the present invention is to provide a semiconductor integrated circuit design method and apparatus capable of taking measures.

  The semiconductor integrated circuit SSO noise estimation method and apparatus according to the present invention calculates SSO noise based on input / output circuit configuration information of a semiconductor integrated circuit, package electrical characteristic information, and SSO noise estimation parameters. .

  According to the semiconductor integrated circuit design method and apparatus of the present invention, the SSO noise exceeds the specified value based on the information of the signal circuit group in the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the parameter for estimating the SSO noise. This is to calculate the number of power supply circuits necessary for avoiding this.

  According to the SSO noise estimation method and apparatus for a semiconductor integrated circuit of the present invention, the SSO noise is calculated based on the configuration information of the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the SSO noise estimation parameters. Therefore, SSO noise can be estimated in a short time by analytical calculation without performing circuit simulation.

  According to the semiconductor integrated circuit design method and apparatus of the present invention, the SSO noise has a specified value based on the information of the signal circuit group in the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the parameter for estimating the SSO noise. Since the number of power supply circuits necessary to avoid exceeding this value is calculated, it is possible to take measures necessary for suppressing SSO noise at the design stage of the semiconductor integrated circuit without performing circuit simulation.

  1 to 28, the first and second embodiments of the SSO noise estimation method and apparatus for a semiconductor integrated circuit according to the present invention and the method and apparatus for designing a semiconductor integrated circuit according to the present invention will be described below. An embodiment will be described.

(First Embodiment of SSO Noise Estimation Method and Device for Semiconductor Integrated Circuit of the Present Invention)
FIG. 1 is a schematic configuration diagram of a first embodiment of an SSO noise estimation apparatus for a semiconductor integrated circuit according to the present invention. The first embodiment of the SSO noise estimation apparatus for a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit according to the present invention. It is for implementing 1st Embodiment of the SSO noise estimation method of a circuit.

  In FIG. 1, 23 is a package electrical characteristic information storage means, 24 is an input / output circuit configuration information storage means, 25 is an SSO noise estimation parameter storage means, 26 is a parameter acquisition environment, 27 is an SSO noise calculation means, and 28 is an SSO. This is noise estimated value storage means.

  In the first embodiment of the SSO noise estimation device for a semiconductor integrated circuit of the present invention, the inductance of the lead of the package on which the semiconductor integrated circuit subject to SSO noise estimation is mounted and the inductance of the bonding wire are packaged as the electrical characteristic information of the package. It is stored in the electrical characteristic information storage means 23.

  Also, the types of signal circuits (output circuit, input circuit, bidirectional circuit) in the input / output circuit included in the semiconductor integrated circuit subject to SSO noise estimation, the number of each type, and the types of power supply circuits (VDD power supply circuit, GND power supply) Circuit) and the number of each type are stored in the input / output circuit configuration information storage unit 24 as configuration information of the input / output circuit.

  Further, the SSO noise estimation parameter included in the SSO noise estimation formula shown in Equation 9 is stored in the SSO noise estimation parameter storage means 25. The SSO noise estimation parameter is acquired from the parameter acquisition environment 26.

  In the SSO noise calculation means 27, the package electrical characteristic information stored in the package electrical characteristic information storage means 23, the input / output circuit configuration information stored in the input / output circuit configuration information storage means 24, and the SSO noise estimation parameters. Based on the SSO noise estimation parameters stored in the storage unit 25, an estimated value of SSO noise is calculated by analytical calculation.

  The estimated SSO noise value calculated by the SSO noise calculating unit 27 is stored in the SSO noise estimated value storage unit 28. These example procedures are the first embodiment of the SSO noise estimation method for a semiconductor integrated circuit according to the present invention.

Here, assuming that the inductance of the package per power supply circuit is L, and the number of output circuits that change simultaneously in phase is the SSO number, the SSO noise peak V _{SSO _NOISE} is

It can be expressed as. However, “i” is a current that flows when one output circuit switches. The “number of power supply circuits” is the number of power supply circuits to which output circuits that change in phase at the same time are assigned. When the output circuit performs a pull-up operation (when an H level signal is output), the VDD power supply circuit When the pull-down operation is performed (when an L level signal is output), the number of GND power supply circuits.

  “L” is the inductance of the bonding wire and lead on the VDD power supply circuit side when the output circuit performs a pull-up operation, and the bonding wire and lead inductance on the GND power supply circuit side when the output circuit performs a pull-down operation. is there.

Further, the current change rate di / dt can be obtained from the I _DS (drain current) -V _DS (drain voltage) characteristic of the final stage transistor of the output circuit, and FIGS. 2 and 3 are for explaining this. FIG.

2A and 3A show a part of the output circuit. 29 is an NMOS transistor that performs a pull-down operation among the final stage transistors of the output circuit, 30 is a GND power supply wiring, 31 is an external load, and 32 is an NMOS transistor 29. An input signal to the gate, 33 is an output signal from the NMOS transistor 29, and 34 is SSO noise. 2B and 3B show the I _DS -V _DS characteristics of the NMOS transistor 29.

In particular, Figure 2 is for illustrating the drain current I _DS of the NMOS transistor 29 in a state where no SSO noise is generated in the GND power lines 30 figure 3 when the SSO noise is generated in the GND power lines 30 it is a diagram for explaining a drain current I _DS of the NMOS transistor 29.

When the input signal 32 changes from L level to H level and the output signal 33 changes from H level to L level, the NMOS transistor 29 within the time when the gate voltage V _GS of the NMOS transistor 29 changes from L level to H level. Assuming that the operation region is a saturation region, it is assumed that the drain current I _DS of the NMOS transistor 29 changes as shown by the arrow P1 in FIG. it can.

Here, the drain current I _DS of the NMOS transistor 29 in the saturation region of the NMOS transistor 29 can be obtained by setting the threshold voltage of the NMOS transistor 29 to V _TH .

It is represented by Where β _n is

Μ _n is the effective mobility of carriers (electrons), ε _ox is the dielectric constant of the gate oxide film, t _ox is the thickness of the gate oxide film, W _n is the effective gate width, and L _n is the gate length.

In contrast, when the input signal 32 changes from the L level to the H level and the output signal 33 changes from the H level to the L level, when SSO noise occurs in the GND power supply wiring 30, the NMOS transistor 29 Since the gate voltage V _GS decreases by the SSO noise voltage V _{SSO —NOISE} , it can be assumed that the drain current I _DS of the NMOS transistor 29 changes as shown by the arrow P2 in FIG. 3B.

Therefore, the drain current I _DS of the NMOS transistor 29 in this case is

It can be expressed as. As shown in FIG. 3A, assuming that the waveform of the gate voltage V _GS is a saturated ramp waveform and the waveform of the SSO noise 34 is a triangular pulse waveform, the rate of change of the drain current I _DS of the NMOS transistor 29 is

It becomes. However, “Slope” is the slope of the input signal 32, and when the change of the gate voltage V _GS is finished, the drain current change rate dI _DS / dt of the NMOS transistor 29 becomes maximum.

Therefore, when the rising time of the gate voltage V _GS of time and NMOS transistor 29 SSO noise 34 to peak V _SSO _ _NOISE is assumed to be the same, the drain current change rate dI _DS / dt of the NMOS transistor 29,

It becomes. However, V _CC is the operating voltage of the NMOS transistor 29. Here, when the drain current change rate dI _DS / dt shown in Equation 6 is substituted into Equation 1,

It becomes. Solving this,

Is obtained. Expanding Equation 8, the peak V _SSO _ _NOISE of SSO noise 34,

It expresses. However, the “simultaneous SW (switching) coefficient” is a coefficient representing the relative intensity of the SSO noise of the output circuit, and is proportional to “Slope” and “β”. “PVT (σ) coefficient” is a coefficient representing process variation, “PVT (T) coefficient” is a coefficient representing a difference depending on temperature, B is a saturation noise voltage coefficient, and L _j is a package inductance of the power source.

  A similar equation can be derived for a PMOS transistor that performs a pull-up operation among the final stage transistors of the output circuit. Therefore, in this embodiment, the SSO noise calculation unit 27 uses Equation 9 as the SSO noise estimation formula.

  Here, for example, as shown in FIG. 4, for the semiconductor integrated circuit 35, 352 input / output circuits N <b> 1 to N <b> 352 are formed in the peripheral portion of the core circuit 36. Assume that the switching coefficient and the inductance of the package are as shown in Table 1, and the parameters of the SSO noise estimation formula are as shown in Table 2.

In Table 2, “SS”, “TT”, and “FF” are the contents of the index σ for selecting V _TH and PVT (σ), and “SS” indicates that the operation speed of the transistor is slow due to process variation. In this case, “TT” is a case where the operation speed of the transistor is within the range of the design value, and “FF” is a case where the operation speed of the transistor is increased due to process variations.

  Therefore, for example, when calculating SSO noise on each side of the semiconductor integrated circuit 35 with σ being FF, temperature being 25 ° C., and operating voltage being 3.3 V, the SSO noise generated in the GND power supply wiring is 0. 391V, the lower side is 0.468V, the right side is 0.407V, the upper side is 0.415V, and the SSO noise generated in the VDD power supply wiring is 1.138V on the left side, 1.269V on the lower side, 1.167V on the right side, and the upper side Then, it becomes 1.180V.

  Here, the SSO noise estimation formula shown in Equation 9 used in the present embodiment is derived from the current-voltage characteristics of the transistor and is based on a rational basis, so there are few errors. FIG. 5 is a diagram showing the SSO noise estimation accuracy according to the present embodiment.

  FIG. 5A shows the SSO noise value based on the SSO noise estimation formula used in this embodiment and the SSO noise value based on the HSPICE simulation. The SSO noise value based on the SSO noise estimation formula used in this embodiment is the simulation result. Almost matches. On the other hand, the equation obtained by linearly approximating the simulation result that has been used conventionally has a greater divergence from the simulation result as the sum of the simultaneous switching coefficients increases.

  FIG. 5B compares the SSO noise value when the operating voltage is changed with respect to the sum of the five simultaneous switching coefficients between the case of using the SSO noise estimation formula used in this embodiment and the case of using the HSPICE simulation. It is shown. The SSO noise value according to the SSO noise estimation formula used in the present embodiment substantially matches the simulation result. In the conventional linear approximation, the operating voltage is not included in the parameters of the equation.

  When an LSI is guaranteed under its recommended operating conditions, it must be ensured that the SSO noise falls within a specified value within the operating voltage range of the recommended operating conditions. Therefore, it is very effective in practical use that the operating voltage is included in the parameters of the estimation formula and has sufficient accuracy.

  According to this embodiment, in designing a semiconductor integrated circuit, it is possible to estimate SSO noise in a short time without performing circuit simulation. For example, when the SSO noise estimation work of a semiconductor integrated circuit having 300 signal circuits is performed, it takes about 16 hours in the case of circuit simulation, but it takes about 1 hour in the case of this embodiment. In other words, according to the present embodiment, the work time for estimating the SSO noise is about one-sixteenth that required by the circuit simulation. Note that the difference in peak value of SSO noise between the case of circuit simulation and the case of this embodiment is 10 to 15%.

  As described above, according to the present embodiment, the SSO noise calculation means is based on the types of input / output circuits (output circuit, input circuit, bidirectional circuit) and the number of each type, package inductance, and SSO noise estimation parameters. 27, the SSO noise is calculated by the equation (9). Therefore, the SSO noise can be estimated in a short time by analytical calculation without performing circuit simulation.

  Note that the SSO noise calculation unit 27 calculates the SSO noise by the SSO noise calculation unit 27 based on the type and number of input / output circuits, the package inductance, and the SSO noise estimation parameters, and the computer functions as the SSO noise calculation unit 27. Can be achieved by the program

(Second Embodiment of SSO Noise Estimation Method and Apparatus for Semiconductor Integrated Circuit of the Present Invention)
FIG. 6 is a schematic configuration diagram of a second embodiment of the SSO noise estimation apparatus for a semiconductor integrated circuit according to the present invention. The second embodiment of the SSO noise estimation apparatus for a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit according to the present invention. It is for implementing 2nd Embodiment of the SSO noise estimation method of a circuit.

  In the present embodiment, the signal circuit grouping unit 100 that groups signal circuits from the input / output circuit configuration information stored in the input / output circuit configuration information storage unit 24 and the signal circuit group information grouped by the signal circuit grouping unit 100 are stored. Signal circuit group information storage means 101-1 to 101-N are provided.

  In the present embodiment, the SSO noise calculation means 27 is the signal circuit group information stored in the signal circuit group information storage means 101-1 to 101 -N, and the package electrical characteristic information stored in the package electrical characteristic information storage means 23. Based on the SSO noise estimation parameters stored in the SSO noise estimation parameter storage means 25, an estimated value of SSO noise is calculated by analytical calculation for each signal circuit group. The rest of the configuration is the same as that of the first embodiment of the SSO noise estimation device for a semiconductor integrated circuit according to the present invention.

  The signal circuit grouping unit 100 groups signal circuits in the input / output circuit according to type and operating frequency based on the input / output circuit configuration information stored in the input / output circuit configuration information storage unit 24. The type of signal circuit is determined by the connection destination and cell standard. If the connection destination or cell standard is different, the type of signal circuit is different. However, if the cell standards are the same, the types of signal circuits may be the same even if the connection destination is different. For example, the local bus and the SDRAM interface (SDRAM-IF) are different signal circuit types.

  7 and 8 are diagrams for explaining a signal circuit grouping method employed by the signal circuit grouping means 100. FIG. First, look at the signal circuit array from the left end (or right end) of the input / output circuit array. Signal circuits with the same operating frequency as the previous signal circuit are in the same signal circuit group. A new signal circuit group is not included in the signal circuit group.

  Next, look again at the type of signal circuit from the left end (or right end) of the input / output circuit array. If the signal circuit type is the same as the previous signal circuit, the signal circuit group is the same, and In this case, a new signal circuit group is not included in the conventional signal circuit group.

  FIG. 7 shows an example in which the output circuits a to k are grouped by the operating frequency. In this example, the output circuits a to h are grouped into a signal circuit group having an operating frequency = 133 MHz, and the output circuits i to k are They are grouped into signal circuit groups with an operating frequency of 66 MHz.

  FIG. 8 shows an example in which the output circuits a to k are grouped by the operation frequency and then grouped by the signal circuit type. In this example, the output circuits a to d have the signal circuit type = SDRAM-IF and the operation frequency = The signal circuit group is grouped into a 133 MHz signal circuit group, the output circuits e to h are grouped into a signal circuit type = processor core control terminal and a signal circuit group with an operating frequency of 133 MHz, and the output circuits i to k are a signal circuit type = local bus. , And grouped into a signal circuit group of operating frequency = 66 MHz. FIG. 9 shows an example in which the entire output circuits around the core portion of the semiconductor integrated circuit are grouped.

  Here, for example, as shown in FIG. 10, for the semiconductor integrated circuit 35, 352 output circuits N1 to N352 are formed in the peripheral portion of the core circuit 36, and the simultaneous switching coefficient is set for these output circuits N1 to N352. The package inductance is as shown in Table 1, and the parameters of the SSO noise estimation formula are as shown in Table 2.

  At this time, the SSO noise at each side of the core circuit 36 of FIG. 10 is calculated. If the process variation FF, the temperature is 25 ° C., and the operating voltage is 3.3 V, the SSO noise generated in the GND power supply wiring of the output circuit group A is calculated as shown in Expression 10 using the SSO noise estimation formula shown in Expression 9. And is determined to be 0.379V.

  Similarly, the output circuit group B is 0.430 V, the output circuit group C is 0.486 V, and the output circuit group D is 0.403 V. When the SSO noise generated in the VDD power supply wiring is calculated, the output circuit group A is 1.237 V, the output circuit group B is 1.178 V, the output circuit group C is 1.332 V, and the output circuit group D is 1.160 V.

  As described above, according to the present embodiment, the SSO noise is calculated by the SSO noise calculation unit 27 based on the signal circuit group information, the electrical characteristic information of the package, and the SSO noise estimation parameter. As in the first embodiment of the SSO noise estimation apparatus of the present invention (or the first embodiment of the SSO noise estimation method of the present invention), SSO noise is estimated in a short time by analytical calculation without performing circuit simulation. Since the SSO noise is estimated for each signal circuit group, the SSO noise with higher accuracy than the first embodiment of the SSO noise estimation device of the present invention (or the first embodiment of the SSO noise estimation method of the present invention) is obtained. Noise estimation can be performed.

  Note that the signal circuit grouping process in the signal circuit grouping unit 100 performed based on the types of input / output circuits and the number of each type, and the grouping results by the signal circuit grouping unit 100, the package inductance and the SSO noise estimation The calculation of the SSO noise by Equation 9 in the SSO noise calculation means 27 performed based on the parameters for use can be achieved by a program that causes the computer to function as the signal circuit grouping means 100 and the SSO noise calculation means 27.

(One Embodiment of Semiconductor Integrated Circuit Design Method and Apparatus of the Present Invention)
FIG. 11 is a schematic configuration diagram of an embodiment of a semiconductor integrated circuit design apparatus according to the present invention. One embodiment of the semiconductor integrated circuit design apparatus according to the present invention is a semiconductor integrated circuit design method according to the present invention. It is for implementing embodiment.

  In FIG. 11, reference numeral 37 denotes package electrical characteristic information storage means, 38 denotes input / output circuit configuration information storage means, 39 denotes signal circuit grouping means, 40-1 to 40-N denote signal circuit group information storage means, and 41 denotes SSO noise. Estimating parameter storage means, 42 a parameter acquisition environment, 43 power supply circuit number calculation means, 44-1 to 44-N input / output circuit configuration information storage means, 45 power supply circuit insertion means, and 46 input / output circuit arrangement information It is a storage means.

  In one embodiment of a semiconductor integrated circuit design apparatus according to the present invention, package electrical characteristic information storage means includes package lead inductance and bonding wire inductance as package electrical characteristic information on which a semiconductor integrated circuit to be designed is mounted. 37.

  Further, the type (output circuit, input circuit, bidirectional circuit) of the signal circuit in the input / output circuit included in the design target semiconductor integrated circuit and the number of each type are input / output circuit configuration information storage means 38 as the input / output circuit configuration information. Is remembered.

  Further, the SSO noise estimation parameter included in the SSO noise estimation formula shown in Equation 9 is stored in the SSO noise estimation parameter storage means 41. The SSO noise estimation parameter is acquired from the parameter acquisition environment 42.

  Then, in the signal circuit grouping means 39, based on the input / output circuit configuration information stored in the input / output circuit configuration information storage means 38, the signal circuit in the input / output circuit is connected to the connection destination, operating frequency, cell standard name (LVCMOS, (ANALOG, USB, etc.) and driving capability (high-speed LVCMOS, normal-speed LVCMOS) are grouped into groups, and for each signal circuit group, the type of signal circuit and the number of each type are signaled as information of each signal circuit group. It is stored in the circuit group information storage means 40-1 to 40-N.

Next, in the power circuit number calculation means 43, the package electrical characteristic information stored in the package electrical characteristic storage means 37 and the signal circuit group information stored in the signal circuit group information storage means 40-1 to 40-N are stored. based on the information and the SSO noise estimate parameters stored in the SSO noise estimate parameter storage unit 41, the power supply circuit number required to ensure that SSO noise does not exceed a specified value V _noise _ _tolerable is VDD power supply circuit and It is calculated for each GND power supply circuit.

  The type of power supply circuit (VDD power supply circuit, GND power supply circuit) calculated by the power supply circuit number calculating means 43 and the number of each type together with the type of signal circuit and the number of each type are configured for each signal circuit group. Information is stored in the input / output circuit configuration information storage means 44-1 to 44-N.

  Next, in the power supply circuit insertion means 45, based on the input / output circuit configuration information (type / number of signal circuits, type / number of power supply circuits) stored in the input / output circuit configuration information storage means 44-1 to 44-N. Then, the power supply circuit is inserted for each signal circuit group, and the result is stored in the input / output circuit arrangement information storage means 46 as the arrangement information of the input / output circuit (signal circuit / power supply circuit). A series of these procedures is one embodiment of the method for designing a semiconductor integrated circuit of the present invention.

Here, assuming that the inductance components of the bonding wires and leads connected to the power supply circuit are the same for all power supply circuits, and assuming that it is L, the SSO noise V _{SS0 _NOISE} is equal to the specified value V _noise \ _tolerable . The conditional expression for not exceeding

It becomes. Therefore, the number of power supply circuits required for the SSO noise V _{SS0 — NOISE} not to exceed the specified value V _{noise — tolerable} is:

It becomes. In this embodiment, the calculation of the number of power supply circuits performed by the power supply circuit number calculation means 43 is performed using the power supply circuit number calculation formula shown in Expression 12. However, the number of power supply circuits is an integer.

  Further, in the present embodiment, for example, as shown in FIG. 12, half of the sum of the simultaneous switching coefficients of the output circuit between one power supply circuit and the adjacent power supply circuit of the same type is one. The power supply circuit is inserted so that the sum of the simultaneous switching coefficients of the output circuit handled by the power supply circuit is obtained.

  In the example of FIG. 12, since the sum of the simultaneous switching coefficients of the output circuit between the VDD power supply circuits 47 and 49 is 20, the sum of the simultaneous switching coefficients of the output circuits handled by the VDD power supply circuit 48 is 20/2 = 10. In this way, a VDD power supply circuit 48 is arranged. Note that the sum of the simultaneous switching coefficients of the left output circuit handled by the VDD power supply circuit 48 is 5, and the sum of the simultaneous switching coefficients of the right output circuit handled by the VDD power supply circuit 48 is 5.

  Here, the sum of the simultaneous switching coefficients that one VDD power supply circuit (or GND power supply circuit) basically takes is:

The simultaneous switching coefficient of the output circuit on one side, which is basically handled by one power supply circuit, can be obtained by dividing the result of Equation 13 by 2.

  Further, in this embodiment, as shown in FIG. 13, the power supply circuit is placed between the output circuits so that the sum of the simultaneous switching coefficients of one power supply circuit in one signal circuit group is substantially equal. insert. That is, the non-uniformity of the simultaneous switching coefficients of one power supply circuit is used as a cost function, and the insertion position of the power supply circuit that minimizes the cost function is obtained as a solution by an optimization algorithm.

  The example of FIG. 13 shows the case where the number of output circuits = 21, the sum of simultaneous switching coefficients = 60, and the number of VDD power supply circuits = 6. In this example, six VDD power supply circuits 50, 51, 52 are shown. , 53, 54, and 55 are inserted so that the sum of the simultaneous switching coefficients that are respectively handled is approximately equal to 10, 10, 9.5, 9.5, 11, and 10.

  FIG. 14 shows an example in which a VDD power supply circuit and a GND power supply circuit are inserted. In this case, the number of output circuits = 21, the sum of simultaneous switching coefficients = 60, the number of VDD power supply circuits = 6, and the number of GND power supply circuits = 10. Show.

  In the example shown in FIGS. 12 to 14, there is no restriction on the arrangement of the power supply circuit, but there may be a restriction on the arrangement of the power supply circuit determined from a viewpoint other than the SSO noise in the design. In such a case, the arrangement constraint of the power supply circuit is used as the constraint condition, and the power supply circuit insertion position where the cost function is minimized is obtained as a solution by the optimization algorithm.

  15 and 16 are diagrams for explaining the power circuit insertion algorithm. In the signal circuit grouping means 39, based on the input / output circuit configuration information stored in the input / output circuit configuration information storage means 38, the signal circuits in the input / output circuit are grouped by connection destination, operating frequency and cell standard name. However, FIG. 15A shows a case where the output circuit in the input / output circuit (including the output circuit in the bidirectional circuit) is divided into four output circuit groups G1 to G4.

  Here, for example, index σ = FF, temperature = 25 ° C., operating voltage = 3.3V, GND power supply wiring package inductance = 5 nH, VDD power supply wiring package inductance = 6 nH, GND power supply wiring SSO noise specified value When the number of GND power supply circuits and the number of VDD power supply circuits satisfying the SSO noise specified value are calculated by using Equation 12, the number of VDD power supply circuits and the number of VDD power supply circuits are calculated as shown in Table 3. Become.

  Therefore, when the VDD power supply circuit and the GND power supply circuit are arranged so that the SSO noise is most suppressed by the optimization algorithm, for example, as shown in FIG. 15B.

  In the output circuit group G1, the sum of the simultaneous switching coefficients of the GND power supply circuits 56, 57, 58, 59, 60, 61 is set to 14, 14, 14, 15, 13, 12 respectively, and the VDD power supply circuits 62, 63, The sum of the simultaneous switching coefficients handled by 64 is 28, 28, and 26, respectively.

  In the output circuit group G2, the sum of the simultaneous switching coefficients of the GND power supply circuits 65, 66, 67, 68 and 69 is 11.5, 11.5, 12, 13, and 13, respectively, and the VDD power supply circuits 70, 71, The sum of the simultaneous switching coefficients of 72 is 19, 20.5, and 21.5, respectively.

  In the output circuit group G3, the sum of the simultaneous switching coefficients of the GND power supply circuits 73, 74, and 75 is 9, 10.5, and 10.5, respectively, and the sum of the simultaneous switching coefficients of the VDD power supply circuits 76 and 77 is respectively 15.5 and 14.5.

  In the output circuit group G4, the sum of the simultaneous switching coefficients of the GND power supply circuits 78, 79, 80, 81, 82, 83, 84 is 14, 14, 14, 13, 14, 13, 14, respectively. The sum of the simultaneous switching coefficients of 85, 86, 87, and 88 is 24, 24, 24, and 24, respectively.

  FIG. 16A shows a case where the output circuit in the input / output circuit (including the output circuit in the bidirectional circuit) is divided into four output circuit groups A to D. Output circuit group A is signal circuit type = SDRAM-IF, operation frequency = 133 MHz signal circuit group, output circuit group B is signal circuit type = memory device control terminal, operation frequency = 66 MHz signal circuit group, and output circuit group C is A signal circuit type = processor core control terminal, a signal circuit group with an operating frequency = 133 MHz, and an output circuit group D are a signal circuit group with a signal circuit type = local bus and an operating frequency = 66 MHz.

  Here, for example, index σ = FF, temperature = 25 ° C., operating voltage = 3.3V, GND power supply wiring package inductance = 5 nH, VDD power supply wiring package inductance = 6 nH, GND power supply wiring SSO noise specified value Table 4 shows that the number of GND power supply circuits and the number of VDD power supply circuits satisfying the SSO noise specified value are calculated using Equation 12 with = 0.4V and the SSO noise specified value of the VDD power supply wiring = 1.1V. Become. A calculation example of the output circuit group A is shown in Formula 14.

  Next, when the simultaneous switching coefficient of one power source is calculated by Equation 13, Table 5 and Table 6 are obtained.

  Therefore, when the VDD power supply circuit and the GND power supply circuit are arranged so that the SSO noise is most suppressed by the optimization algorithm, for example, as shown in FIG. 16B.

  In the output circuit group A, the sum of the simultaneous switching coefficients of the GND power supply circuits 102, 103, 104, 105, 106, and 107 is set to 14, 14, 14, 15, 13, and 12, respectively, and the VDD power supply circuits 108, 109, The sum of the simultaneous switching coefficients of 110 and 111 is 20, 20, 21, and 21, respectively.

  In the output circuit group B, the sum of the simultaneous switching coefficients of the GND power supply circuits 112, 113, 114, 115, and 116 is 11.5, 11.5, 12, 13, and 13, respectively, and the VDD power supply circuits 117, 118, The sum of the simultaneous switching coefficients handled by 119 is 19, 20.5, and 21.5, respectively.

  In the output circuit group C, the sum of the simultaneous switching coefficients of the GND power supply circuits 120, 121, 122 is 9, 10.5, 10.5, respectively, and the sum of the simultaneous switching coefficients of the VDD power supply circuits 123, 124 is respectively 15.5 and 14.5.

  In the output circuit group D, the sum of the simultaneous switching coefficients of the GND power supply circuits 125, 126, 127, 128, 129, 130, and 131 is 14, 14, 14, 13, 14, 13, and 14, respectively. The sum of the simultaneous switching coefficients of 132, 133, 134, and 135 is 24, 24, 24, and 24, respectively.

  Here, the power circuit insertion position optimization algorithm adopted by this embodiment will be described. In this embodiment, while adding a simultaneous switching coefficient from the left end (or right end) of an output circuit group to a certain output circuit group, Compared to the simultaneous switching coefficient on one side of the VDD power supply circuit (or GND power supply circuit)

Thus, an algorithm of inserting a VDD power supply circuit (or a GND power supply circuit) is employed.

  FIG. 17 is a flowchart showing a power circuit insertion position optimization algorithm. In step S1, the target output circuit group selection means refers to the output circuit group group file 136 holding the output circuit group group information, selects the output circuit group into which the power supply circuit is inserted, and uses this as the target output circuit group. And

  In step S2, the simultaneous switching coefficient calculation means refers to the simultaneous switching coefficient file 137 holding the simultaneous switching coefficient information and the power supply circuit insertion number file 138 holding the power supply circuit insertion number information. The simultaneous switching coefficient that the power supply circuit is responsible for is calculated, and the result is held in the power supply circuit responsible simultaneous switching coefficient file 139.

  In step S3, the target output circuit determining means determines the target output circuit with reference to the output circuit arrangement file 140 that holds the output circuit arrangement information in the target output circuit group. Initially, the output circuit at the left end (or right end) of the target output circuit group is determined as the target output circuit.

  In step S4, the simultaneous switching coefficient adding means refers to the simultaneous switching coefficient file 137 and adds the simultaneous switching coefficient of the target output circuit. Initially, only the output circuit at the left end (or right end) of the target output circuit group is the target output circuit.

  In step S5, the simultaneous switching coefficient comparison unit compares the simultaneous switching coefficient on one side of the power supply circuit with the total of the simultaneous switching coefficients of the target output circuit with reference to the simultaneous switching coefficient file 139 that is responsible for the power supply circuit. As a result of the comparison, if the power circuit has more responsibility, the process returns to step S3, and the adjacent output circuit is added to the target output circuit, thereby adding the target output circuit. If the power supply circuit is small, the process proceeds to step S6.

  In step S6, the power supply circuit inserting means refers to the simultaneous switching coefficient file 137 and the output circuit arrangement file 140, adds half of the simultaneous switching coefficients of the next output circuit to the simultaneous switching coefficients of the output circuit of interest so far, Compared with the responsibility on one side of the power supply circuit, if the responsibility on one side of the power supply circuit is larger, insert the power supply circuit after the target output circuit, and if smaller, insert the power supply circuit before the target output circuit, The information is held in the power supply circuit / output circuit arrangement file 141. Here, the insertion position of the power supply circuit is determined.

  In step S7, the power supply circuit insertion number determination means refers to the power supply circuit insertion number file 138, compares the number of inserted power supply circuits with the number of power supply circuit insertions, and determines whether all power supply circuit insertions have been inserted. If all are not inserted, the process proceeds to the next power supply circuit. If all are inserted, the power supply circuit insertion for the target output circuit group is completed.

  In step S8, the power supply circuit inserted output circuit group determining means determines whether power supply circuit insertion processing has been performed for all output circuit groups, and power supply circuits are inserted for all output circuit groups. If so, the power supply circuit insertion processing is terminated. Otherwise, the process returns to step S1, and the power supply circuit insertion process is executed for the next output circuit group.

  In the following, a case where the simultaneous switching coefficient which one side of the VDD power supply circuit (or the GND power supply circuit) takes as a general rule is 5 will be described as an example.

  FIG. 18 shows output circuit groups, and a to k are output circuits. In this case, for example, when a power supply circuit is inserted on the right side of the output circuit d, the switching coefficient of one side of the power supply circuit on the left side of the power supply circuit is exceeded. In such a case, half of the simultaneous switching coefficient of the output circuit d is added to the total of the simultaneous switching coefficients of the output circuits a to c and compared with the simultaneous switching coefficient on one side of the power supply circuit.

  When the value obtained by adding half of the simultaneous switching coefficients of the output circuit d to the total of the simultaneous switching coefficients of the output circuits a to c exceeds the simultaneous switching coefficient on one side of the power supply circuit, the power supply is connected to the left side of the output circuit d. If a circuit is inserted and does not exceed, a power supply circuit is inserted on the right side of the output circuit d. In the example of FIG. 18, since the sum of the simultaneous switching coefficients of the output circuits a to c (= 3) + half the simultaneous switching coefficient of the output circuit d (= 3/2) = 4.5, as shown in FIG. The power supply circuit 89 is inserted on the right side of the output circuit d.

  When the power supply circuit 89 is inserted as shown in FIG. 19, since the power supply circuit 89 takes charge of the simultaneous switching coefficient 6 on the left side, the share of the simultaneous switching coefficient on the right side of the inserted power supply circuit 89 is 10−. Let 6 = 4. As a result, the power supply circuit 89 is responsible for up to half of the output circuit e and the output circuit f on the right side. FIG. 20 shows the insertion position of the second power supply circuit 90.

  By repeating the above processing, all the necessary number of power supply circuits are inserted into the output circuit group. The above example is inserted from the left side, but can be inserted from the right side by the same method. Moreover, although the case of the same side is taken as an example, it can be inserted by the same method when straddling the side.

  FIG. 21 shows a case where there is a different potential power supply circuit already placed when the power supply circuit is inserted. As shown in FIG. 21, when the different potential power supply circuit 91 already exists when the power supply circuit is inserted, equalization of the simultaneous switching coefficient and pair arrangement of the VDD power supply circuit and the GND power supply circuit are considered.

  That is, in the example shown in FIG. 18, it is determined whether the power supply circuit 89 is inserted to the left or right of the output circuit d, and the power supply circuit 89 is inserted on the right side of the output circuit d as shown in FIG. In the example shown in FIG. 21, in this way, the different potential power supply circuit 91 exists via the output circuit d on the left side of the insertion position of the power supply circuit 89. In such a case, for example, as shown in FIG. 22, the power supply circuit 89 to be inserted is inserted on the right side of the different potential power supply circuit 91.

  When the power supply circuit 89 is inserted as shown in FIG. 22, since the power supply circuit 89 takes charge of 3 as the simultaneous switching coefficient on the left side, the share of the simultaneous switching coefficient on the right side of the power supply circuit 89 is 10−3 = 7. To do. As a result, the power supply circuit 89 is responsible for up to half of the output circuits d and e and the output circuit f.

  Further, for example, as shown in FIG. 23A, the output circuits a to d on the left side of the different-potential power circuit 92 are covered by the share of the simultaneous switching coefficient on one side of the power circuit to be inserted (in this example, 5). Even if there is not, if the share of the simultaneous switching coefficient on both sides (10 in this example) can be covered, the power supply circuit 93 to be inserted is inserted next to the different potential power supply circuit 92 as shown in FIG. Give priority to power supply circuit pair arrangement.

  When the power supply circuit 93 is inserted as shown in FIG. 23B, the simultaneous switching coefficient that the power supply circuit 93 takes on the left side is 8. Therefore, the share of the right side switching coefficient of the power supply circuit 93 is 10−8 = 2. To do. For this reason, the power supply circuit 93 takes charge of the output circuit e.

  FIG. 24 shows a case where there is an existing equipotential power supply circuit when the power supply circuit is inserted. As shown in FIG. 24, when there is a power supply circuit 94 having the same potential as the power supply circuit to be inserted, the same potential power supply circuit 94 performs the insertion processing by regarding the simultaneous switching coefficient as 0.

  FIG. 25 shows a case where the simultaneous switching coefficient of the output circuit is large. As shown in FIG. 25A, for example, when the simultaneous switching coefficient of the output circuit a is not large enough to be handled by one power supply circuit, a plurality of power supply circuits 95 are arranged on the left side of the output circuit a as shown in FIG. 25B. 96 are inserted.

  In the above method, the method of determining the insertion position of the power supply circuit by comparing the size of the simultaneous switching coefficient of the output circuit with the size of the simultaneous switching coefficient on one side of the power supply circuit is shown. It can also be inserted by looking at the balance of the simultaneous switching coefficients.

  For example, in FIG. 26, the sum of the simultaneous switching coefficients of the output circuits a to c is 3, and the sum of the simultaneous switching coefficients of the output circuits a to d is 6. That is, when a power supply circuit is inserted on the left side of the output circuit d, the simultaneous switching coefficient on the left side which the power supply circuit takes charge does not exceed the simultaneous switching coefficient which one side of the power supply circuit takes on principle. When a power supply circuit is inserted on the right side, the simultaneous switching coefficient on the left side that the power supply circuit takes over exceeds the simultaneous switching coefficient that the one side of the power supply circuit takes on in principle.

  In this case, the left and right simultaneous switching coefficients that the power circuit has when the power circuit is inserted on the left side of the output circuit d, and the left and right simultaneous switching coefficients that the power circuit has when the power circuit is inserted on the right side of the output circuit d. Find the sum of coefficients.

  When a power supply circuit is inserted on the left side of the output circuit d, the simultaneous switching coefficient on the left side of the power supply circuit is the simultaneous switching coefficient of the output circuit a (= 1) + the simultaneous switching coefficient of the output circuit b (= 1) + The simultaneous switching coefficient of the output circuit c (= 1) = 3, and the simultaneous switching coefficient on the right side is the simultaneous switching coefficient of the output circuit d (= 3) + the simultaneous switching coefficient of the output circuit e (= 3) + the output circuit f Half of the simultaneous switching coefficient (= 2) = 7.

  On the other hand, when the power supply circuit is inserted on the right side of the output circuit d, the simultaneous switching coefficient on the left side of the power supply circuit is the simultaneous switching coefficient of the output circuit a (= 1) + the simultaneous switching coefficient of the output circuit b. (= 1) + simultaneous switching coefficient of output circuit c (= 1) + simultaneous switching coefficient of output circuit d (= 3) = 6, and the simultaneous switching coefficient on the right side is the simultaneous switching coefficient of output circuit e (= 3) + Half of simultaneous switching coefficients (= 2) of the output circuit f = 4.

  Here, when the absolute value of the difference between the left and right simultaneous switching coefficients of the power supply circuit is taken, it is 4 when the power supply circuit is inserted on the left side of the output circuit d, and when the power supply circuit is inserted on the right side of the output circuit d. 2 and inserting the power supply circuit on the right side of the output circuit d balances the right and left simultaneous switching coefficients of the power supply circuit. Accordingly, in this case, the right side of the output circuit d is set as the insertion position. You may make it insert a power supply by repeating this process.

  By using the power supply circuit insertion position optimization algorithm as described above, the noise peak value can be suppressed by about 10%, and noise bias can be suppressed as compared with the case where the power supply circuits are arranged in an even distribution. be able to.

  FIG. 27 is a diagram showing a distribution of ground noise (noise generated in the GND power supply wiring) when an output circuit having a small simultaneous switching coefficient is arranged on the left side and lower side of the LSI and a large simultaneous switching coefficient is arranged on the right side and the upper side. 27A shows a case where the GND power supply circuit is arranged by the power supply circuit insertion position optimization algorithm used in the present embodiment, and FIG. 27B shows a case where the GND power supply circuit is arranged by equal distribution. P1 to P6 indicate the magnitude of noise, and P1 <P2 <... <P6.

  FIG. 28 is a diagram showing a distribution of power supply noise (noise generated in the VDD power supply wiring) when an output circuit having a small simultaneous switching coefficient is arranged on the left side and bottom side of the LSI and a large simultaneous switching coefficient is arranged on the right side and top side. 28A shows a case where the VDD power supply circuit is arranged by the power supply circuit insertion position optimization algorithm used in the present embodiment, and FIG. 28B shows a case where the VDD power supply circuit is arranged in an even distribution. In addition, Q1-Q8 shows the magnitude | size of noise, It has the relationship of Q1 <Q2 <... <Q8.

  In addition, by using the power circuit insertion position optimization algorithm adopted by the present embodiment, the work time for power circuit insertion is about 1/24 compared to the case where the power circuit insertion position optimization is achieved by simulation. It can be.

  Further, according to the data shown below, the uneven distribution of noise on the chip can be more accurately estimated by the grouping of the output circuit. 27 and 28, the output circuit group A composed of only output circuits having a simultaneous switching coefficient of 1 and the output circuit group B composed of only output circuits having a simultaneous switching coefficient of 16 Table 7 shows the results of applying the SSO noise estimation formula when grouping and when grouping the whole without grouping.

  When grouping is not performed, a uniform noise peak value that is averaged over the whole is estimated. On the other hand, when the noise peak value is obtained for each group, the noise peak value is unevenly distributed between the A group having a small simultaneous switching coefficient and the B group having a large simultaneous switching coefficient. Estimated. The difference between the SSO noise estimated in the output circuit group A and the output circuit group B reaches 10 times.

  As described above, according to the present embodiment, the SSO noise is defined based on the types of input / output circuits (output circuit, input circuit, bidirectional circuit), the number of each type, package inductance, and SSO noise estimation parameters. Since the number of power supply circuits necessary to prevent the value from being exceeded is calculated, it is possible to take measures necessary for suppressing SSO noise at the design stage of the semiconductor integrated circuit without performing circuit simulation.

  The calculation of the number of power supply circuits in the power supply circuit number calculation means 43 performed based on the configuration information of the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the SSO noise estimation parameter, and one power supply Power supply insertion in the power supply circuit insertion means 45 for inserting the power supply circuit by finding the power supply circuit insertion position where the cost function is minimized under the constraint condition where the non-uniformity of the total SSO noise relative strength of the The processing can be achieved by a program that causes the computer to function as the power circuit number calculation unit 43 and the power circuit insertion unit 45.

  Here, when the present invention is organized, the present invention includes at least a semiconductor integrated circuit SSO noise estimation method and apparatus, a semiconductor integrated circuit design method and apparatus, and a program described below.

(Supplementary Note 1) A step of storing the configuration information of the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the SSO noise estimation parameter by the storage unit, and the input / output circuit of the semiconductor integrated circuit stored by the storage unit An SSO noise estimation method for a semiconductor integrated circuit, characterized in that the SSO noise calculation means has a step of calculating SSO noise based on the configuration information, the electrical characteristic information of the package and the SSO noise estimation parameter.

(Supplementary Note 2) The configuration information of the input / output circuit is information on the type of the input / output circuit and the number of each type, and the electrical characteristic information of the package is information on the pins of the package and the pads of the semiconductor integrated circuit. 2. The SSO noise estimation method for a semiconductor integrated circuit according to appendix 1, wherein the information is inductance information of a line between them.

(Supplementary Note 3) A step of storing a signal circuit group information in the input / output circuit of the semiconductor integrated circuit, package electrical characteristic information, and an SSO noise estimation parameter by the storage unit, and the semiconductor integrated circuit stored by the storage unit A semiconductor integrated circuit characterized in that the SSO noise calculation means calculates SSO noise based on information on signal circuit groups in the input / output circuit, electrical characteristic information on the package, and the SSO noise estimation parameter. SSO noise estimation method.

(Supplementary note 4) The SSO noise estimation method for a semiconductor integrated circuit according to supplementary note 1 or 3, wherein the calculation of the SSO noise by the SSO noise calculation means is performed using a calculation formula shown in Formula 16.

  However, A is the slope of the input signal to the gate of the final stage transistor of β × output circuit. β is

Where μ is the effective carrier mobility, ε _ox is the dielectric constant of the gate oxide film, t _ox is the thickness of the gate oxide film, W is the effective gate width, and L is the gate length. V _CC is the operating voltage of the final stage transistor of the output circuit, V _TH (σ, T) is the threshold voltage at the operating speed mode σ and temperature T of the final stage transistor of the output circuit, B is the saturation noise voltage coefficient, γ Is

It is. However, the simultaneous SW coefficient is a coefficient indicating the relative intensity of the SSO noise generated by the output circuit, the PVT (σ) coefficient is a coefficient indicating process variation, the PVT (T) coefficient is a coefficient indicating a difference depending on temperature, and L _j is a package of the power source. Inductance.

(Supplementary Note 5) Storage means for storing configuration information of input / output circuit of semiconductor integrated circuit, package electrical characteristic information and SSO noise estimation parameter, and configuration of input / output circuit of semiconductor integrated circuit stored by said storage means An SSO noise estimation device for a semiconductor integrated circuit, comprising: SSO noise calculation means for calculating SSO noise based on the information, the electrical characteristic information of the package and the SSO noise estimation parameter.

(Supplementary Note 6) Storage means for storing signal circuit group information in the input / output circuit of the semiconductor integrated circuit, package electrical characteristic information, and SSO noise estimation parameters, and input of the semiconductor integrated circuit stored by the storage means SSO noise estimation means for semiconductor integrated circuit, characterized by comprising SSO noise calculation means for calculating SSO noise based on information of signal circuit group in output circuit, electrical characteristic information of package and SSO noise estimation parameter apparatus.

(Supplementary note 7) A program for causing a computer to function as SSO noise calculation means for calculating SSO noise based on input / output circuit configuration information of a semiconductor integrated circuit, package electrical characteristic information, and SSO noise estimation parameters.

(Supplementary Note 8) To cause a computer to function as SSO noise calculation means for calculating SSO noise based on signal circuit group information in the input / output circuit of the semiconductor integrated circuit, package electrical characteristic information, and SSO noise estimation parameters. Program.

(Supplementary Note 9) A step of storing a signal circuit group information in the input / output circuit of the semiconductor integrated circuit, package electrical characteristic information, and an SSO noise estimation parameter by the storage unit, and the semiconductor integrated circuit stored by the storage unit The number of power supply circuits required to prevent the SSO noise from exceeding a specified value based on the information of the signal circuit group in the input / output circuit, the electrical characteristic information of the package, and the SSO noise estimation parameter A design method of a semiconductor integrated circuit, comprising a step of calculating by a number calculating means.

(Supplementary note 10) The method for designing a semiconductor integrated circuit according to supplementary note 9, wherein the electrical characteristic information of the package is inductance information of a line between a pin of the package and a pad of the semiconductor integrated circuit.

(Supplementary Note 11) A power supply circuit is inserted by finding a power supply circuit insertion position where the cost function is minimized under a constraint condition where the cost function is a non-uniform sum of SSO noise relative intensities of one power supply circuit. The method for designing a semiconductor integrated circuit according to appendix 9, wherein the method comprises a step.

(Supplementary Note 12) Storage means for storing signal circuit group information in the input / output circuit of the semiconductor integrated circuit, package electrical characteristic information, and SSO noise estimation parameters, and input of the semiconductor integrated circuit stored by the storage means A power supply circuit that calculates the number of power supply circuits necessary to prevent the SSO noise from exceeding a specified value based on the information of the signal circuit group in the output circuit, the electrical characteristic information of the package, and the SSO noise estimation parameter An apparatus for designing a semiconductor integrated circuit, comprising a number calculating means.

(Supplementary note 13) A power supply circuit is inserted by finding a power supply circuit insertion position where the cost function is minimized under a constraint condition in which the nonuniformity of the total SSO noise relative intensity that one power supply circuit handles is a cost function. The apparatus for designing a semiconductor integrated circuit according to appendix 12, further comprising power supply circuit insertion means.

(Supplementary Note 14) In order to prevent the SSO noise from exceeding the specified value based on the information of the signal circuit group in the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the parameter for estimating the SSO noise. A program for functioning as a means for calculating the number of power supply circuits for calculating the required number of power supply circuits.

(Supplementary Note 15) In order to prevent the SSO noise from exceeding the specified value based on the information of the signal circuit group in the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the parameter for estimating the SSO noise. Power supply circuit number calculation means for calculating the number of necessary power supply circuits, and a power supply circuit insertion position at which the cost function is minimized under a constraint condition where the unequality of the total SSO noise relative intensity of one power supply is a cost function A program for functioning as power supply circuit insertion means for inserting a power supply circuit as a solution.

1 is a schematic configuration diagram of a first embodiment of an SSO noise estimation device for a semiconductor integrated circuit according to the present invention. Explaining that the current change rate included in the SSO noise estimation formula used in one embodiment of the SSO noise estimation method of the semiconductor integrated circuit of the present invention can be obtained from the drain current-drain voltage characteristics of the final stage transistor of the output circuit. It is a figure for doing. Explaining that the current change rate included in the SSO noise estimation formula used in one embodiment of the SSO noise estimation method of the semiconductor integrated circuit of the present invention can be obtained from the drain current-drain voltage characteristics of the final stage transistor of the output circuit. It is a figure for doing. It is a figure which shows the semiconductor integrated circuit of SSO noise estimation object. It is a figure which shows the SSO noise estimation precision by 1st Embodiment of the SSO noise estimation method of the semiconductor integrated circuit of this invention. It is a schematic block diagram of 2nd Embodiment of the SSO noise estimation apparatus of the semiconductor integrated circuit of this invention. It is a figure for demonstrating the grouping method of the signal circuit which the signal circuit grouping means with which 2nd Embodiment of the SSO noise estimation apparatus of the semiconductor integrated circuit of this invention is provided. It is a figure for demonstrating the grouping method of the signal circuit which the signal circuit grouping means with which 2nd Embodiment of the SSO noise estimation apparatus of the semiconductor integrated circuit of this invention is provided. It is a figure which shows the example which grouped the whole output circuit of the periphery of the core part of a semiconductor integrated circuit by the signal circuit grouping means with which 2nd Embodiment of the SSO noise estimation apparatus of the semiconductor integrated circuit of this invention is provided. It is a figure which shows the semiconductor integrated circuit of SSO noise estimation object. 1 is a schematic configuration diagram of an embodiment of a semiconductor integrated circuit design apparatus of the present invention. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. 5 is a flowchart schematically showing a power circuit insertion algorithm employed by an embodiment of a semiconductor integrated circuit design method of the present invention. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure for demonstrating the power supply circuit insertion algorithm which one Embodiment of the design method of the semiconductor integrated circuit of this invention employ | adopts. It is a figure which shows distribution of ground noise (noise which generate | occur | produces in a GND power supply wiring). It is a figure which shows distribution of power supply noise (noise which generate | occur | produces in VDD power supply wiring). It is a schematic perspective view which shows an example of the mounting state to the package of a semiconductor integrated circuit. It is the figure which modeled the semiconductor integrated circuit and package shown in FIG. 29 with the electric element. FIG. 31 is a diagram for describing a case where SSO noise occurs in a GND power supply wiring in the semiconductor integrated circuit shown in FIG. 30. FIG. 31 is a diagram for describing a case where SSO noise occurs in the VDD power supply wiring in the semiconductor integrated circuit shown in FIG. 30.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 2 ... Pad 3 ... Input / output circuit 4 ... Core part 5 ... Package 6 ... Pin 7 ... Lead 8 ... Bonding wire 9 ... External power supply 10 ... Ground 11 ... Resistance component of lead and bonding wire 12 ... Lead and Inductance component of bonding wire 13 ... Input circuit 14 ... Output circuit 15 ... Bidirectional circuit 16 ... VDD power supply circuit 17 ... GND power supply circuit 18 ... Model of a part of the core part 19 ... VDD power supply wiring model 20 ... GND power supply wiring model 21 ... Current consumption model 22 ... Capacity model 23 ... Package electrical characteristic information storage means 24 ... Input / output circuit configuration information storage means 25 ... SSO noise estimation parameter storage means 26 ... Parameter acquisition environment 27 ... SSO noise calculation means 28 ... SSO noise estimation Value storage means 29 ... NMOS transistor Transistor 30 ... GND power supply wiring 31 ... External load 32 ... Input signal to gate of NMOS transistor 29 33 ... Output signal from NMOS transistor 29 34 ... SSO noise 35 ... Semiconductor integrated circuit 36 ... Core part 37 ... Package electrical characteristic information Storage means 38 ... Input / output circuit configuration information storage means 39 ... Signal circuit grouping means 40-1 to 40-N ... Signal circuit group information storage means 41 ... SSO noise estimation parameter storage means 43 ... Power supply circuit number calculation means 44-1 44-N ... I / O circuit configuration information storage means 45 ... Power supply circuit insertion means 46 ... I / O circuit arrangement information storage means 100 ... Signal circuit grouping means 101-1 to 101-N ... Signal circuit group information storage means

Claims (5)

A storage means for storing the configuration information of the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the parameter for simultaneous switching output noise estimation;
The simultaneous switching output noise calculation means calculates the simultaneous switching output noise based on the configuration information of the input / output circuit of the semiconductor integrated circuit stored in the storage means, the electrical characteristic information of the package, and the parameters for estimating the simultaneous switching output noise. A method for estimating a simultaneous switching output noise of a semiconductor integrated circuit, comprising the step of:   Program for causing computer to function as simultaneous switching output noise calculating means for calculating simultaneous switching output noise based on configuration information of input / output circuit of semiconductor integrated circuit, package electrical characteristic information and simultaneous switching output noise estimation parameter . A storage means for storing signal circuit group information in the input / output circuit of the semiconductor integrated circuit, electrical characteristic information of the package, and parameters for estimating simultaneous switching output noise; and
Simultaneous switching output noise calculation means performs simultaneous switching based on signal circuit group information in the input / output circuit of the semiconductor integrated circuit stored in the storage means, electrical characteristic information of the package, and parameters for estimating the simultaneous switching output noise. A method for estimating simultaneous switching output noise of a semiconductor integrated circuit, comprising a step of calculating output noise.   The computer functions as a simultaneous switching output noise calculation means for calculating the simultaneous switching output noise based on the information of the signal circuit group in the input / output circuit of the semiconductor integrated circuit, the electrical characteristic information of the package, and the parameter for estimating the simultaneous switching output noise. Program to let you. A storage means for storing signal circuit group information in the input / output circuit of the semiconductor integrated circuit, electrical characteristic information of the package, and parameters for estimating simultaneous switching output noise; and
The simultaneous switching output noise exceeds a specified value based on the signal circuit group information in the input / output circuit of the semiconductor integrated circuit stored in the storage means, the electrical characteristic information of the package, and the parameter for estimating the simultaneous switching output noise. A method for designing a semiconductor integrated circuit, comprising: a step of calculating the number of power supply circuits necessary for preventing the number of power supply circuits from being calculated.

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