JP2005294658A - Method and device for exposure and method of manufacturing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for exposure by which the manufacturing cost of a mask can be suppressed to a low cost by improving the method of forming a device pattern on the mask. <P>SOLUTION: On three masks 10-1, 10-2, and 10-3, mask patterns A, A', B, B', C, C', D, D', E, E', F, and F' are formed in this order by dividing the areas on the masks 10-1, 10-2, and 10-3 into four mechanical stripes 49-1 to 49-12. The mask patterns A and A', B and B', C and C', D and D', E and E', and F and F' are respectively identical to each other. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention mainly relates to an exposure method in lithography of a semiconductor integrated circuit or the like. In particular, the present invention relates to an exposure method and the like that can improve the method of forming a device pattern on a mask and keep the manufacturing cost of the mask low.

  In recent years, the degree of integration of semiconductor integrated circuits has been increasing, and the circuit patterns have become finer. At present, optical steppers are mainly used for pattern transfer of semiconductor wafers. Usually, a mask serving as an original for the transfer is drawn and created with an electron beam. In order to expose a highly integrated and ultrafine pattern, it has been proposed to use electron beam exposure for exposure of each wafer.

  However, electron beam exposure has a drawback of low throughput, and various technical developments have been made to eliminate this drawback. At present, a graphic part batch exposure method called cell projection, character projection, or block exposure has been put into practical use. In the figure partial batch exposure method, a repeatable circuit small pattern (about 5 μm square on the wafer) is repeatedly transferred using one mask as a unit using a mask on which a plurality of similar small patterns are formed. Perform exposure. However, even in this method, the variable molding method is drawn for a pattern portion having no repeatability.

  On the other hand, as an electron beam transfer exposure method aiming at dramatically higher throughput than the figure partial batch exposure method, a mask with a circuit pattern of one entire semiconductor chip is prepared, and an electron beam is irradiated to a certain area of the mask. There has been proposed an electron beam reduction transfer device that reduces and transfers a pattern of the irradiation range using a projection lens.

  With this type of apparatus, if the entire chip pattern is transferred at once by irradiating the entire range of the mask with an electron beam, the pattern cannot be transferred with high accuracy. In addition, it is difficult to produce a mask as an original plate. Therefore, a method that has been energetically studied recently is not to expose a single die (chip on a wafer) or a plurality of dies at once, but to divide the pattern into small regions (subfields) and perform transfer exposure to obtain a wafer. In the above method, the entire chip pattern is formed by connecting the pattern images on the sub-fields (hereinafter referred to as a divided transfer method). By performing aberration correction and magnification / position correction of the optical system for each subfield transfer, high-precision pattern formation can be performed. When each subfield is exposed, the electron beam is deflected in the electron optical system or the mask or wafer is mechanically moved.

  By the way, with the increase in accuracy of device patterns, there is a high possibility that defects in the original pattern formed on the mask will occur. In particular, when a thin film mask is used as in an electron beam exposure apparatus, the probability of occurrence of defects in the mask manufacturing process increases. When a mask defect is found, it is necessary to recreate the entire mask, which increases the cost of the mask.

  The present invention has been made in view of such problems, and provides an exposure method and the like that can improve the method of forming a device pattern on a mask and can keep the manufacturing cost of the mask low. Objective.

  In order to solve the above-described problems, an exposure method of the present invention divides a device pattern to be transferred onto a sensitive substrate into a plurality of partial areas, forms them on a mask, and sequentially exposes the partial areas on the mask. An exposure method for transferring the entire device pattern by transferring the pattern image of partial regions on the mask on the sensitive substrate; transferring at least one of the device patterns on the mask; Forming redundantly overlapping portions, inspecting the redundantly formed patterns, and selecting and exposing a healthy portion of the pattern on the mask based on the inspection data. Features.

  Since there is almost no defect in both of the plurality of redundantly formed patterns, there is almost no need to remake the mask, and the mask manufacturing cost can be reduced.

  In the exposure method, a plurality of sets of the device patterns are formed on the mask, each divided into a plurality of partial areas, and a healthy partial area of the plurality of sets of device patterns is selected and exposed. preferable.

  In the above exposure method, it is preferable to form the plurality of sets of device patterns on a plurality of masks.

  In the exposure method of the present invention, a device pattern to be transferred onto a sensitive substrate is divided into a plurality of partial areas and formed on a plurality of masks, and the partial areas on the mask are sequentially exposed and transferred to the sensitive substrate, On the sensitive substrate, an exposure method for transferring the entire device pattern by joining pattern images of partial areas on the mask; performing a defect inspection of the device pattern formed on the mask; Based on the data, a healthy alternative pattern that replaces the defective pattern on the mask is formed on a mask different from the mask, and the patterns on the two masks are selected and exposed. You can also.

  Since only the defective pattern is newly formed on the mask, it is not necessary to form redundant patterns for all patterns.

  In the above exposure method, the device pattern may be divided into a plurality of stripe regions and formed on the mask, and an alternative pattern may be formed for each stripe.

  In the above exposure method, the device pattern can be divided into a plurality of subfield regions and formed on the mask, and an alternative pattern can be formed for each subfield.

  In the above exposure method, the device pattern is formed on the mask by dividing it into a plurality of partial regions, the same device pattern is formed on a mask different from the mask, and the devices on the two masks A healthy partial area in the pattern can also be selected and exposed.

  An exposure apparatus of the present invention includes a mask stage on which a plurality of masks having a pattern to be transferred onto a sensitive substrate, an illumination optical system that illuminates the mask with a charged particle beam, and a charged particle beam that has passed through the mask. A charged particle beam exposure apparatus comprising: a projection optical system that forms an image on the sensitive substrate; a sensitive substrate stage on which the sensitive substrate is placed; and a controller that controls each part; It is formed on the plurality of masks by being divided into regions and alternative patterns, and a healthy portion of the patterns on all the masks is selected and exposed.

  The device manufacturing method of the present invention includes a lithography step using the exposure method according to any one of the above aspects.

  As is clear from the above description, according to the present invention, it is possible to improve the method for forming a device pattern on a mask and to keep the mask manufacturing cost low.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the outline of the divided transfer type electron beam projection exposure technique will be described with reference to the drawings.

FIG. 10 is a diagram showing an outline of the imaging relationship and the control system in the entire optical system of the divided transfer type electron beam projection exposure apparatus.
The electron gun 1 arranged at the uppermost stream of the optical system emits an electron beam downward. Below the electron gun 1, two-stage condenser lenses 2 and 3 are provided, and the electron beam is converged by these condenser lenses 2 and 3 and forms an image of the crossover CO in the blanking opening 7.

  A rectangular opening 4 is provided below the second-stage condenser lens 3. This rectangular aperture (illumination beam shaping aperture) 4 allows only the illumination beam that illuminates one subfield (pattern small area that becomes one unit of exposure) of the mask 10 to pass through. The image of the opening 4 is formed on the mask 10 by the lens 9.

A blanking deflector 5 is disposed below the beam shaping opening 4. The deflector 5 deflects the illumination beam when necessary and hits the non-opening portion of the blanking opening 7 so that the beam does not hit the mask 10.
An illumination beam deflector 8 is disposed below the blanking opening 7. The deflector 8 scans the illumination beam mainly in the horizontal direction (X direction) in FIG. 10 to illuminate each subfield of the mask 10 in the field of view of the illumination optical system. An illumination lens 9 is disposed below the deflector 8. The illumination lens 9 images the beam shaping aperture 4 on the mask 10.

The mask 10 actually extends (described later with reference to FIG. 11) in the optical axis vertical plane (XY plane), and has a large number of subfields. A pattern (chip pattern) forming one semiconductor device chip as a whole is formed on the mask 10. Of course, a pattern forming one semiconductor device chip may be divided and arranged on a plurality of masks.
The mask 10 is placed on a movable mask stage 11, and by moving the mask 10 in the direction perpendicular to the optical axis (XY direction), each subfield on the mask extends over a wider range than the field of view of the illumination optical system. Can be illuminated.
The mask stage 11 is provided with a position detector 12 using a laser interferometer, so that the position of the mask stage 11 can be accurately grasped in real time.

  Projection lenses 15 and 19 and a deflector 16 are provided below the mask 10. The electron beam that has passed through one subfield of the mask 10 is imaged at a predetermined position on the wafer 23 by the projection lenses 15 and 19 and the deflector 16. Detailed operations of the projection lenses 15 and 19 and the deflector 16 (image position adjusting deflector) will be described later with reference to FIG. An appropriate resist is applied on the wafer 23, a dose of an electron beam is given to the resist, and the pattern on the mask is reduced and transferred onto the wafer 23.

  A crossover C.O. is formed at a point that internally divides the mask 10 and the wafer 23 by a reduction ratio, and a contrast opening 18 is provided at the crossover position. The opening 18 blocks the electron beam scattered by the non-patterned portion of the mask 10 from reaching the wafer 23.

  A backscattered electron detector 22 is disposed immediately above the wafer 23. The reflected electron detector 22 detects the amount of electrons reflected by the exposed surface of the wafer 23 or the mark on the stage. For example, the relative positional relationship between the masks 10 and 23 can be known by scanning the mark on the wafer 23 with a beam that has passed through the mark pattern on the mask 10 and detecting the reflected electrons from the mark at that time.

  The wafer 23 is placed on a wafer stage 24 that can move in the XY directions via an electrostatic chuck (not shown). By synchronously scanning the mask stage 11 and the wafer stage 24 in opposite directions, each part in the chip pattern extending beyond the field of view of the projection optical system can be sequentially exposed. The wafer stage 24 is also equipped with a position detector 25 similar to that of the mask stage 11 described above.

  The lenses 2, 3, 9, 15, 19 and the deflectors 5, 8, 16 are controlled by the controller 31 via the coil power control units 2a, 3a, 9a, 15a, 19a and 5a, 8a, 16a. Controlled. The mask stage 11 and the wafer stage 24 are also controlled by the controller 31 via the stage controllers 11a and 24a. The stage position detectors 12 and 25 send signals to the controller 31 via interfaces 12a and 25a including amplifiers and A / D converters. The backscattered electron detector 22 also sends a signal to the controller 31 via the same interface 22a.

  The controller 31 grasps the control error of the stage position and corrects the error by the image position adjusting deflector 16. As a result, the reduced image of the subfield on the mask 10 is accurately transferred to the target position on the wafer 23. Then, the subfield images are joined on the wafer 23, and the entire chip pattern on the mask is transferred onto the wafer.

Next, a detailed example of the mask used for the electron beam projection exposure of the divided transfer method will be described with reference to FIG.
FIG. 11 is a diagram schematically showing a configuration example of an electron beam projection exposure mask. (A) is a plan view of the whole, (B) is a partial perspective view, and (C) is a plan view of one small membrane region. Such a mask can be manufactured, for example, by performing electron beam drawing / etching on a silicon wafer.

  FIG. 11A shows an entire pattern division arrangement state in the mask 10. A region indicated by a large number of squares 41 in the drawing is a small membrane region (thickness 0.1 μm to several μm) including a pattern region corresponding to one subfield. As shown in FIG. 11C, the small membrane region 41 is composed of a central pattern region (subfield) 42 and a peripheral frame-shaped non-pattern region (skirt 43). The subfield 42 is a portion where a pattern to be transferred is formed. The skirt 43 is a portion where no pattern is formed and hits the edge portion of the illumination beam. As a form of pattern formation, there are a stencil type in which perforations are provided in the membrane and a scattering membrane type in which a pattern layer made of a high scatterer of electron beams is formed on the membrane.

  One sub-field 42 has a size of about 0.5 to 5 mm square on the mask as currently considered. Assuming that the reduction ratio of projection is 1/5, the size of the projection image obtained by reducing and projecting the subfield onto the wafer is 0.1 to 1 mm square. A portion 45 called an orthogonal lattice-shaped glage around the small membrane region 41 is, for example, a beam having a thickness of about 0.5 to 1 mm for maintaining the mechanical strength of the mask. The width of the glage 45 is, for example, about 0.1 mm. Note that the width of the skirt 43 is, for example, about 0.05 mm.

  As shown in FIG. 11A, a large number of small membrane regions 41 are arranged in the horizontal direction (X direction) in the figure to form one group (electrical stripe 44), and such an electrical stripe 44 is formed in the vertical direction of the figure. One mechanical stripe 49 is formed side by side in the direction (Y direction). The length of the electrical stripe 44 (the width of the mechanical stripe 49) is limited by the size of the deflectable field of view of the illumination optical system. A method in which a non-pattern region such as a skirt or a gray area is not provided between adjacent subfields in one electrical stripe 44 has been studied.

A plurality of mechanical stripes 49 exist in parallel in the X direction.
A thick beam shown as a strut 47 between adjacent mechanical stripes 49 is for keeping the deflection of the entire mask small. The strut 47 is integral with the grage 45.

  According to the method considered to be dominant at present, the columns of the subfields 42 in the X direction (electrical stripes 44) in one mechanical stripe (hereinafter simply referred to as a stripe) 49 are sequentially exposed by electron beam deflection. On the other hand, the columns in the Y direction in the stripes 49 are sequentially exposed by continuous stage scanning.

  FIG. 12 is a perspective view schematically showing a state of pattern transfer from the mask to the wafer. One stripe 49 on the mask 10 is shown at the top of the figure. The stripe 49 is formed with a number of subfields 42 (the skirt is not shown) and the grage 45 as described above. In the lower part of the drawing, a wafer 23 facing the mask 10 is shown.

In this figure, the subfield 42-1 at the left corner of the deflection band 44 in front of the stripe 49 on the mask is illuminated by the illumination beam IB from above. The pattern beam PB that has passed through the subfield 42-1 is reduced and projected onto a predetermined region 52-1 on the wafer 23 by the action of the two-stage projection lens and the image position adjusting deflector (see FIG. 10). .
The pattern beam PB is deflected between the mask 10 and the wafer 23 by a two-stage projection lens from the direction parallel to the optical axis to the direction intersecting the optical axis and vice versa.

The transfer position of the subfield image on the wafer 23 is determined by the deflector (reference numeral 16 in FIG. 10) provided in the optical path between the mask 10 and the wafer 23, and the transferred small area corresponding to each pattern small area 42. 52 are adjusted to contact each other. That is, only by converging the pattern beam PB that has passed through the pattern small region 42 on the mask onto the wafer 23 by the first projection lens and the second projection lens, not only the pattern small region 42 of the mask 10 but also the glanger 45 and the skirt. Even the image is transferred at a predetermined reduction ratio, and an unexposed area corresponding to a non-pattern area such as the grease 45 is generated between each transferred small area 52. To prevent this, the pattern image transfer position is shifted by an amount corresponding to the width of the non-pattern area.
One position adjusting deflector is provided for each of the X direction and the Y direction.

  Hereinafter, an embodiment of an exposure method according to an embodiment of the present invention will be described with reference to the drawings.

Example 1
FIG. 1 is a diagram for explaining a wafer and mask pattern forming method according to a first embodiment of the present invention. FIG. 1A is a plan view showing a device pattern on the wafer, and FIG. 1B is a plan view showing a mask pattern formed on the mask.
FIG. 1A shows one chip 50 on the wafer 23. The device pattern on the chip 50 is divided into six mechanical stripes 59-1 to 59-6. A device pattern of A, B, C, D, E, and F is formed in order on each of the mechanical stripes 59-1 to 59-6.

  FIG. 1B shows three masks 10-1, 10-2, and 10-3 placed on the mask stage 11 (see FIG. 10). In this example, the device pattern to be transferred onto the chip 50 is divided and formed on three masks. These three masks are all mounted on the mask.

  The region on the mask 10-1 is divided into four mechanical stripes 49-1 to 49-4. A mask pattern of A, A ′, B, and B ′ is formed in order on each of the mechanical stripes 49-1 to 49-4. Mask pattern A ′ and mask pattern A are exactly the same pattern, and are arranged in adjacent mechanical stripes. The mask pattern B ′ and the mask pattern B are exactly the same pattern, and are arranged in adjacent mechanical stripes. Mask patterns A and A ′ correspond to pattern A on mechanical stripe 59-1, and mask patterns B and B ′ correspond to pattern B on mechanical stripe 59-1.

  The region on the mask 10-2 is also divided into four mechanical stripes 49-5 to 8-8, respectively. A mask pattern of C, C ′, D, and D ′ is formed in order on each of the mechanical stripes 49-5 to 49-8. The mask pattern C ′ and the mask pattern C, and the mask pattern D ′ and the mask pattern D are exactly the same pattern, and are arranged in adjacent mechanical stripes. The mask patterns C and C ′ correspond to the pattern C on the mechanical stripe 59-1, and the mask patterns D and D ′ correspond to the pattern D on the mechanical stripe 59-1.

  The region on the mask 10-3 is also divided into four mechanical stripes 49-9 to 12-12, respectively. In each of the mechanical stripes 49-9 to 12, mask patterns of E, E ′, F, and F ′ are formed in order. The mask pattern E ′ and the mask pattern E, and the mask pattern F ′ and the mask pattern F are exactly the same pattern, and are arranged in adjacent mechanical stripes. The mask patterns E and E ′ correspond to the pattern E on the mechanical stripe 59-1, and the mask patterns F and F ′ correspond to the pattern F on the mechanical stripe 59-1.

  On each of the masks 10-1, 2 and 3, a defective portion 61 of several mask patterns is shown. Among these, the reference numeral 61-1 is given to the defective portion above the mechanical stripe 49-1, and the reference numeral 61-2 is assigned to the defective portion below the mechanical stripe 49-2.

  In this example, the device pattern on the chip 50 is divided into six mechanical stripes, and the corresponding mask patterns are formed on the mechanical stripes on the mask. However, it is also possible to divide the device pattern on the chip 50 into a plurality of electrical stripes 54 and to form a mask pattern corresponding to each of the electrical stripes on the mask.

  As described above, by forming the same mask pattern on adjacent mechanical stripes, the throughput during exposure can be improved and the overlay accuracy can be improved.

Next, an exposure method according to the first embodiment will be described with reference to FIG.
FIG. 2 is a flowchart showing a mask manufacturing procedure used in the exposure method according to the first embodiment.
In FIG. 2, first, data of an exposure layer to be formed on a wafer is produced by LSI-CAD or the like (step 21), and data conversion for assigning the produced data to a desired area on the mask and drawing is performed. Perform (step 22). Based on the conversion data, three masks 10-1, 2, 3 are produced (step 23), and defect inspection is performed for each of them (step 24).

  As a result of the inspection, if one of the adjacent stripes formed with the same pattern is defect-free (step 25), the data "Use defect-free stripe for exposure" is output to create exposure data. (Step 26). In this case, only a stripe having no defect is scanned, and a desired device pattern is transferred onto the wafer. This is the case, for example, when the defective portion 60-1 on the mechanical stripe 49-1 in FIG. 1B does not exist and the mechanical stripe 49-1 has no defect. In FIG. 1B, other mechanical stripes 49-4, 6, 7, 10, and 11 are defect-free, and patterns B ′, C ′, D, E ′, and F exist in each of them. Therefore, all defect-free patterns to be transferred onto the wafer are prepared, and a desired device pattern can be transferred by scanning these defect-free stripes.

  If both adjacent stripes are defective (step 25), it is investigated whether either defect can be repaired (step 27). For example, in FIG. 1B, the defect portion 60-1 on the mechanical stripe 49-1 on which the pattern A is formed on the mask 10-1 and the pattern A ′ identical to the pattern A are formed. This is a case where there is a defective portion 60-2 on the mechanical stripe 49-2. If it can be repaired, the defective portion of one stripe is repaired, and data “use the repaired stripe for exposure” is output to create exposure data (step 26). In this case, only the repaired stripe and the defect-free stripe are scanned, and a desired device pattern is transferred onto the wafer.

  Next, a case where both adjacent stripes are defective and are not in the same location (step 29) will be described. For example, in FIG. 1B, the defect portion 60-1 on the mechanical stripe 49-1 on which the pattern A is formed on the mask 10-1 and the pattern A ′ identical to the pattern A are formed. This is a case where the defective portion 60-2 on the mechanical stripe 49-2 is in a different location (subfield 42). In this case, "position information of the defective portion 60-1 on the mechanical stripe 49-1 and position information of the defective portion 60-2 on the mechanical stripe 49-2" is output to create exposure data (step 26). ).

  In this case, at the time of exposure (step 30), first, the mechanical stripe 49-1 is scanned to transfer the mask pattern A onto the wafer. At that time, blanking is performed when the defective area 60-1 is transferred so as not to transfer the defective pattern. Thereafter, the mechanical stripe 49-2 is scanned to transfer the mask pattern A ′ onto the wafer 23. Blanking is performed when transferring a region other than the region corresponding to the defective portion 60-1, so that the patterns are not transferred in duplicate. Then, blanking is canceled when the region corresponding to the defective portion 60-1 is transferred, and only the region corresponding to the defective portion 60-1 is transferred onto the wafer 23. Thus, by scanning the mechanical stripes 49-1 and 49-2, the device pattern A having no defect is transferred to the mechanical stripe 59-1 on the wafer 23. When scanning the mechanical stripe 49-2, all the subfields 42 on the mechanical stripe 49-2 may be sequentially scanned, or the mask stage 11 is moved to a region corresponding to the defective portion 60-1. Thus, only the region corresponding to the defective portion 60-1 may be transferred.

  A case will be described where both adjacent stripes are defective (step 25), cannot be repaired (step 27), and are in the same location (step 29). This is because, for example, in FIG. 1B, the defect portion 60-1 in the region where the pattern A is formed on the mask 10-1 and the defect portion 60 in the region where the same pattern A ′ as the pattern A is formed. -2 is the same location (subfield 42). In this case, it is necessary to return to step 23 to recreate the defective mask. However, in practice, the probability that a defect will occur at the same location is extremely low, and it can be said that there is almost no need to remake the mask.

Example 2
FIG. 3 is a view for explaining a wafer and mask pattern forming method according to a second embodiment of the present invention.
FIG. 3 shows three masks 10-1, 10-2, and 10-3. The area on each of the masks 10-1, 2 and 3 is divided into four mechanical stripes 49-1 to 4-12. A mask pattern of A, B, C, and D is formed in order on the mechanical stripes 49-1 to 49-4. On the mechanical stripes 49-5 to 8, mask patterns E, F, A ′, and B ′ are sequentially formed. Mask patterns C ′, D ′, E ′, and F ′ are formed in order on the mechanical stripes 49-9 to 12. Mask patterns A 'and A, B' and B, C 'and C, D' and D, E 'and E, and F' and F are the same pattern.

  Similarly to FIG. 1A, the chip 50 is divided into six mechanical stripes 59-1 to 59-6, and device patterns A, B, C, D, E, and F are formed in order. The mask manufacturing procedure used for the exposure method is the same as in the first embodiment.

  As described above, by forming the same mask pattern on different masks, when the mask is to be recreated in step 29 of FIG. 2, four mask patterns can be recreated by one sheet.

Example 3
FIG. 4 is a diagram for explaining a wafer and mask pattern forming method according to a third embodiment of the present invention. FIG. 4A is a plan view showing a device pattern on the wafer, and FIG. 4B is a plan view showing a mask pattern formed on the mask.
FIG. 4A shows one chip 50 on the wafer 23. The device pattern on the chip 50 is divided into eight mechanical stripes 59-1-8. Device patterns A, B, C, D, E, F, G, and H are formed in order on the mechanical stripes 59-1 to 59-8.

  FIG. 4B shows three masks 10-1, 10-2, and 10-3 placed on the mask stage 11. The area on each of the masks 10-1, 2 and 3 is divided into four mechanical stripes 49-1 to 4-12. A mask pattern of A, B, C, and D is formed in order on the mechanical stripes 49-1 to 49-4. E, F, G, and H mask patterns are sequentially formed on the mechanical stripes 49-5 to 8-8. In this embodiment, a defective portion 60 is shown on the mask patterns A, C, F, and H. A mask pattern of A ′, C ′, F ′, and H ′ is formed in order on the mechanical stripes 49-9 to 12. Mask patterns A ′ and A, C ′ and C, F ′ and F, and H ′ and H are the same pattern.

Next, an exposure method according to the third embodiment will be described with reference to FIG.
FIG. 5 is a flowchart showing a mask manufacturing procedure used in the exposure method according to the third embodiment.
In FIG. 5, first, data of an exposure layer to be formed on a wafer is produced by LSI-CAD or the like (step 41), and data conversion for assigning the produced data to a desired area on a mask and drawing is performed. Perform (step 42). Based on the conversion data, two masks 10-1 and 10-2 are prepared (step 43), and defect inspection is performed for each of them (step 44).

  As a result of the inspection, if there are four or more defective mechanical stripes 49 (step 45), it is not possible to recreate an alternative pattern on the third mask 10-3. Therefore, it is necessary to return to step 43 and remake the defective masks 10-1 and 10-2.

  As a result of the inspection, if the number of defective mechanical stripes 49 is within 4 (for example, mechanical stripes 49-1, 3, 6, and 8 in FIG. 4B) (step 45), the defective stripes are removed. It is formed on the third mask 10-3 (step 46), and defect inspection is performed (step 47). If the mask 10-3 is defective (step 48), it is necessary to return to step 46 and recreate the defective mask 10-3.

  If there is no defect in the mask 10-3 (step 48), the positional information of the defective mechanical stripe on the masks 10-1 and 10-2 is output to create exposure data (step 49).

  At the time of exposure (step 50), first, the mechanical stripes 49-2, 4, 5, and 7 having no defects are scanned to transfer the mask patterns B, D, E, and G onto the wafer 23. At that time, the defective mechanical stripes 49-1, 3, 6, 8 are skipped for scanning. Thereafter, the mechanical stripes 49-9, 10, 11, and 12 on the mask 10-3 are scanned to transfer the mask patterns A ′, C ′, F ′, and H ′ onto the wafer 23.

  As described above, since only the defective stripe is formed on the mask 10-3, it is not necessary to form a pattern redundantly, and the number of mask patterns formed on the mask can be increased.

Example 4
FIG. 6 is a diagram for explaining a wafer and mask pattern forming method according to a fourth embodiment of the present invention. 6A is a plan view showing a device pattern on the wafer, and FIG. 6B is a plan view showing a mask pattern formed on the mask.
FIG. 6A shows one chip 50 on the wafer 23. The device pattern on the chip 50 is divided into eight mechanical stripes 59-1 to 5-8 as in the third embodiment, and in order of A, B, C, D, E, F, G, H A device pattern is formed.

  FIG. 6B shows three masks 10-1, 10-2, and 10-3. The regions on the masks 10-1 and 10-2 are each divided into four mechanical stripes 49-1 to 49-8. A mask pattern of A, B, C, and D is formed in order on the mechanical stripes 49-1 to 49-4. E, F, G, and H mask patterns are sequentially formed on the mechanical stripes 49-5 to 8-8. Defect subfields 42-1, 3, 6, and 8 are shown on mechanical stripes 49-1, 3, 6, and 8. On the mask 10-3, sound patterns corresponding to the defect subfields 42-1, 3, 6, and 8 on the masks 10-1 and 10-2 are formed. In the present embodiment, sound patterns corresponding to the defect subfields 42-1, 3, 6, and 8 are arranged in a jumping manner. However, for example, they can be formed from the upper left of the drawing.

Next, an exposure method according to the fourth embodiment will be described with reference to FIG.
FIG. 7 is a flowchart showing a mask manufacturing procedure used in the exposure method according to the fourth embodiment.
In FIG. 7, first, data of an exposure layer to be formed on a wafer is produced by LSI-CAD or the like (step 61), and data conversion for assigning the produced data to a desired area on the mask and drawing is performed. Perform (step 62). Based on the conversion data, two masks 10-1 and 10-2 are produced (step 63), and defect inspection is performed for each of them (step 64).

  As a result of the inspection, data of a subfield having a defect is output, and data conversion is performed for assigning the produced data to a desired region on the mask 10-3 and drawing (step 65). Based on the conversion data, a mask 10-3 is produced (step 66), and a defect inspection is performed for each of them (step 67).

  If the mask 10-3 is defective (step 68), it is necessary to return to step 66 and remake the mask 10-3.

  If there is no defect in the mask 10-3 (step 68), the positional information of the defective subfield on the masks 10-1 and 10-2 is output to create exposure data (step 69).

  At the time of exposure (step 70), first, the mask patterns on the masks 10-1 and 10-2 are transferred onto the wafer. At that time, blanking is performed when the defect subfields 42-1, 3, 6, and 8 are transferred so that a defective pattern is not transferred. Thereafter, the subfield on the mask 10-3 is scanned, and a healthy pattern corresponding to the defect subfields 42-1, 3, 6, and 8 is transferred onto the wafer 23.

  As described above, since only the defective subfield is formed on the mask 10-3, the number of redundantly formed patterns is small.

Example 5
FIG. 8 is a diagram for explaining a wafer and mask pattern forming method according to a fifth embodiment of the present invention. FIG. 8A is a plan view showing a device pattern on the wafer, and FIG. 8B is a plan view showing a mask pattern formed on the mask.
FIG. 8A shows one chip 50 on the wafer 23. The device pattern on the chip 50 is divided into four mechanical stripes 59-1 to 59-4, and A, B, C, and D device patterns are formed in this order.

  FIG. 8B shows two masks 10-1 and 10-2. The regions on the masks 10-1 and 10-2 are each divided into four mechanical stripes 49-1 to 49-8. A mask pattern of A, B, C, and D is formed in order on the mechanical stripes 49-1 to 49-4. On the mechanical stripes 49-5 to 8, mask patterns A ′, B ′, C ′, and D ′ are formed in this order. Mask patterns A ′ and A, B ′ and B, C ′ and C, and D ′ and D are the same pattern. That is, the masks 10-1 and 10-2 are exactly the same. The mechanical stripes 49-1, 4, 5, and 6 show defect portions 60-1, 4, 5, and 6, respectively.

Next, an exposure method according to the fifth embodiment will be described with reference to FIG.
FIG. 9 is a flowchart showing a mask manufacturing procedure used in the exposure method according to the fifth embodiment.
In FIG. 9, first, data of an exposure layer to be formed on a wafer is produced by LSI-CAD or the like (step 81), and data conversion for assigning the produced data to a desired area on the mask for drawing is performed. Perform (step 82). Based on the conversion data, two masks 10-1 and 10-2 are prepared (step 83), and defect inspection is performed for each of them (step 84).

  A case where there is a defective portion (step 85) in the same place (electrical stripe 44 or subfield 42) of the same pattern will be described. For example, in FIG. 8B, the defect portion 60-1 in the region where the pattern A is formed on the mask 10-1 and the defect portion 60 in the region where the same pattern A ′ as the pattern A is formed. This is the case where −5 is exactly the same location. In this case, it is necessary to return to step 83 and recreate two masks.

  Next, the case where the defective portion is not in the same location (step 85) will be described. In this case, position information of the defective portions 60-1, 4, 5, and 6 is output and exposure data is created (step 86).

  At the time of exposure (step 87), first, the mechanical stripe 49-1 is scanned to transfer the mask pattern A onto the wafer. At that time, blanking is performed when the defective area 60-1 is transferred so as not to transfer the defective pattern. Thereafter, the mechanical stripes 49-2, 3, and 4 are scanned, and the mask pattern is transferred onto the wafer 23. When scanning the mechanical stripe 5, only the region corresponding to the defective portion 60-1 is transferred onto the wafer 23.

  As described above, by preparing two identical masks, the risk of remaking the masks can be avoided.

  In the above description, the viewpoint of replacing the defective portion has been described. However, in the exposure method of the present invention, even if it does not go to the defect, a highly accurate pattern is selected and transferred. By doing so, the pattern formation accuracy can be increased.

Next, an embodiment of a device manufacturing method using the above-described electron beam transfer exposure apparatus will be described.
FIG. 13 shows a flow of manufacturing a microdevice (a semiconductor chip such as an IC or LSI, a liquid crystal panel, a CCD, a thin film magnetic head, a micromachine, etc.).

In step 1 (circuit design), a semiconductor device circuit is designed.
In step 2 (mask production), a mask on which the designed circuit pattern is formed is produced. At this time, beam blur correction due to the proximity effect or space charge effect may be performed by locally resizing the pattern.
On the other hand, in step 3 (wafer manufacture), a wafer is manufactured using a material such as silicon.

  Step 4 (oxidation) oxidizes the wafer's surface. In step 5 (CVD), an insulating film is formed on the wafer surface. In step 6 (electrode formation), an electrode is formed on the wafer by vapor deposition. In step 7 (ion implantation), ions are implanted into the wafer. In step 8 (resist process), a photosensitive agent is applied to the wafer. In step 9 (electron beam exposure), the circuit pattern of the mask is printed onto the wafer by an electron beam transfer apparatus using the mask prepared in step 2. At that time, the above-described exposure method is used. In step 10 (light exposure), the circuit pattern of the mask is printed onto the wafer by an optical stepper using the light exposure mask produced in step 2 in the same manner. Before or after this, proximity effect correction exposure for making the back scattered electrons of the electron beam uniform may be performed.

  In step 11 (development), the exposed wafer is developed. In step 12 (etching), portions other than the resist image are selectively scraped off. In step 13 (resist stripping), the resist that has become unnecessary after etching is removed. By repeatedly performing Step 4 to Step 13, multiple circuit patterns are formed on the wafer.

  Step 14 (assembly) is called a post-process, and is a process for forming a semiconductor chip using the wafer produced by the above process, and is a process such as an assembly process (dicing, bonding), a packaging process (chip encapsulation), or the like. including. In step 15 (inspection), the semiconductor device manufactured in step 14 undergoes inspections such as an operation confirmation test and a durability test. A semiconductor device is completed through these processes and shipped (step 16).

  Although the exposure method according to the embodiment of the present invention has been described with reference to FIGS. 1 to 13 above, the present invention is not limited to this, and various modifications can be made as follows. .

It is a figure explaining the pattern formation method of the wafer and mask which concerns on the 1st Example of this invention. FIG. 1A is a plan view showing a device pattern on the wafer, and FIG. 1B is a plan view showing a mask pattern formed on the mask. It is a flowchart which shows the mask preparation procedure used for the exposure method which concerns on a 1st Example. It is a figure explaining the pattern formation method of the wafer and mask which concerns on the 2nd Example of this invention. It is a figure explaining the pattern formation method of the wafer and mask which concerns on the 3rd Example of this invention. FIG. 4A is a plan view showing a device pattern on the wafer, and FIG. 4B is a plan view showing a mask pattern formed on the mask. It is a flowchart which shows the mask preparation procedure used for the exposure method which concerns on a 3rd Example. It is a figure explaining the pattern formation method of the wafer and mask which concerns on the 4th Example of this invention. 6A is a plan view showing a device pattern on the wafer, and FIG. 6B is a plan view showing a mask pattern formed on the mask. It is a flowchart which shows the mask preparation procedure used for the exposure method which concerns on a 4th Example. It is a figure explaining the pattern formation method of the wafer and mask which concerns on the 5th Example of this invention. FIG. 8A is a plan view showing a device pattern on the wafer, and FIG. 8B is a plan view showing a mask pattern formed on the mask. It is a flowchart which shows the mask preparation procedure used for the exposure method which concerns on a 5th Example. It is a figure which shows the outline of the imaging relationship in the whole optical system of the electron beam projection exposure apparatus of a division | segmentation transfer system, and a control system. It is a figure which shows typically the structural example of the mask for electron beam projection exposure. (A) is an overall plan view, (B) is a partial perspective view, and (C) is a plan view of one small membrane region. It is a perspective view which shows typically the mode of the pattern transfer from a mask to a wafer. A flow of manufacturing a microdevice (a semiconductor chip such as an IC or LSI, a liquid crystal panel, a CCD, a thin film magnetic head, a micromachine, etc.) is shown.

Explanation of symbols

1 Electron gun 2, 3 Condenser lens 4 Illumination beam shaping aperture 5 Blanking deflector 7 Blanking aperture 8 Illumination beam deflector
DESCRIPTION OF SYMBOLS 9 Condenser lens 10 Mask 11 Mask stage 12 Mask stage position detector 15 1st projection lens 16 Image position adjustment deflector 18 Contrast opening 19 2nd projection lens 22 Backscattered electron detector 23 Wafer 24 Wafer stage 25 Wafer stage position detector 31 controller
41 Small membrane area 42 Subfield
43 Skirt 44 Electrical stripe 45 Grage 47 Strut
49 Mechanical stripe 50 chips
52 subfield 59 stripe
60 defective parts

Claims (9)

A device pattern to be transferred onto a sensitive substrate is divided into a plurality of partial areas and formed on a mask.
The partial areas on the mask are sequentially exposed and transferred to the sensitive substrate,
An exposure method for transferring the entire device pattern on the sensitive substrate by stitching pattern images of partial areas on the mask;
Forming at least part of the device pattern redundantly overlapping on the mask;
Inspecting the redundantly formed pattern,
An exposure method comprising: selecting and exposing a healthy portion of a pattern on a mask based on the inspection data. A plurality of device patterns are formed on the mask, each divided into a plurality of partial regions,
2. The exposure method according to claim 1, wherein a healthy partial region of the plurality of sets of device patterns is selected and exposed.   3. The exposure method according to claim 2, wherein the plurality of sets of device patterns are formed on a plurality of masks. A device pattern to be transferred onto a sensitive substrate is divided into a plurality of partial areas and formed on a plurality of masks.
The partial areas on the mask are sequentially exposed and transferred to the sensitive substrate,
An exposure method for transferring the entire device pattern on the sensitive substrate by stitching pattern images of partial areas on the mask;
Perform a defect inspection of the device pattern formed on the mask,
Based on the inspection data, a healthy alternative pattern is formed in a mask different from the mask to replace the defective pattern on the mask,
An exposure method comprising: selecting and exposing a pattern on the two masks. Dividing the device pattern into a plurality of stripe regions and forming on the mask;
5. The exposure method according to claim 4, wherein an alternative pattern is formed for each stripe. Dividing the device pattern into a plurality of subfield regions and forming on the mask;
5. The exposure method according to claim 4, wherein an alternative pattern is formed for each subfield. The mask is formed by dividing the device pattern into a plurality of partial regions,
Form exactly the same device pattern on a different mask from the mask,
2. The exposure method according to claim 1, wherein a healthy partial area in the device pattern on the two masks is selected and exposed. A mask stage on which a plurality of masks having a pattern to be transferred are placed on a sensitive substrate;
An illumination optical system for illuminating the mask with a charged particle beam;
A projection optical system that forms an image of the charged particle beam that has passed through the mask on the sensitive substrate;
A sensitive substrate stage on which the sensitive substrate is placed;
A controller that controls each part;
A charged particle beam exposure apparatus comprising:
The pattern is divided into a plurality of regions and alternative patterns and formed on the plurality of masks;
An exposure apparatus for selecting and exposing a healthy portion of the patterns on all the masks.   A device manufacturing method comprising a lithography step using the exposure method according to claim 1.

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