JP2005294283A - Slurry for polishing used for chemical mechanical polishing (cmp) of copper - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a slurry for polishing which has less of the conventional defects and is improved which is used for chemical mechanical polishing (CMP) to be used for manufacturing a semiconductor integrated circuit, and to provide a polishing method using the same. <P>SOLUTION: The slurry for polishing has a composition which uses colloidal silica instead of the conventional aerosol silica for the material of an abrasive, and uses a corrosion inhibitor while not using an oxidant which has been conventionally used. For wafer interconnection fabrication, a damask inlay method is employed. In the polishing method, a damask inlay structure and a polishing pad are prepared. The slurry is applied on the interface between the structure and the pad, and polishing is performed by a chemical mechanical polishing apparatus using the polishing parameters of the apparatus to remove at least part of a metal layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates generally to the field of chemical-mechanical polishing (CMP) processing used in the manufacture of semiconductor integrated circuits, and more particularly to slurry compositions and methods used, for example, in copper CMP.

  Without limiting the scope of the invention, its background will be described by way of example in connection with chemical-mechanical polishing and polishing slurries.

  Developments in semiconductor technology have led to the manufacture of integrated circuit (IC) wafers using circuits with multiple levels of interconnect. A variety of new materials have been introduced into the method of manufacturing ICs to reduce the RC delay caused by the interconnect. For example, copper is used instead of aluminum due to its low resistance and good electron transfer resistance. Low dielectric constant materials (low k) such as fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), organosilicate glass (OSG), black diamond (registered trademark), SiLK (registered trademark) Used to reduce capacitance coupling between wires. Due to the difficulty of etching copper in a plasma etch chamber, the damascene process is typically used to make copper wiring.

  In the damascene process, open passages in the dielectric layer are formed by patterning and etching processes. In one damascene structure, the open passage is a trench or a via, and in a double damascene structure, the open passage is a groove and passage together. The open passage is then coated with a barrier layer such as Ta or TaN to prevent copper diffusion and improve adhesion, and then a copper seed layer is formed. The The open passage is then filled with copper, for example by electroplating. A chemical mechanical polishing (CMP) process is used to remove excess copper and planarize the surface.

  In the CMP process, material removal is accomplished by interaction between the polishing pad, the polishing slurry, and the wafer. The polishing slurry is an important part of the polishing system. To a great extent it determines the polishing performance. The copper CMP process is typically a multi-step process. In the first step, a slurry having a high polishing rate for copper and a low polishing rate for the barrier is used to remove most or all of the excess copper from the wafer surface. The high selectivity of the copper removal rate relative to the barrier removal rate is designed so that polishing stops at the barrier layer. Thus, non-uniformities from electrochemical plating will not translate into variations in final copper thickness. In the second step of the CMP process, the barrier layer is removed to completely break undesigned connections between the wiring in the layer. The slurry used in the barrier removal step is called a barrier slurry and is typically different from the slurry used in the first step.

  Currently, there are two types of barrier slurries: high selectivity slurries (HSS) and low selectivity slurries (LSS). The HSS slurry has a removal rate for the barrier layer that is higher than the removal rate for the copper and dielectric layers. The LSS slurry polishes copper, dielectric material and barrier layer at similar rates. Sometimes a third process, called the (air) huff process, is used to improve the defects.

  Typically, the copper CMP barrier slurry is an abrasive material (such as silica or alumina), a corrosion inhibitor (such as benzotriazole (BTA)), an oxidizing agent (such as hydrogen peroxide, potassium iodate). And one or more of a multi-item additive including surfactants, stabilizers, complexing agents, biocides, and the like. In order to achieve the desired selectivity and low defects, various chemical agents and abrasive particles are used to balance polishing and passivation reactions at the wafer / pad interface.

SUMMARY OF THE INVENTION However, current barrier slurries used in copper CMP processes have disadvantages. One problem encountered with current slurries used in the industry is polishing-induced defects. Scratches from the CMP process are a major cause of the defects and copper is more sensitive to CMP scratches due to the properties of the material. Because of their susceptibility to sheering, most barrier slurries with fumed silica are difficult to handle (pump and filter) in a production environment. Large undesired particles (agglomerates) are considered to be a major cause of defects.

  Another problem encountered with current barrier slurries is selectivity. For low selectivity slurries (LSS), the polishing rates for copper, barrier and dielectric materials should be similar. In order to achieve such polishing rate identity, it is common practice today to add an oxidant to the slurry to increase the copper removal rate. Certain stabilizers are also typically added to the slurry to maintain the polishing rate for copper and reduce oxidant decay.

  However, it was recognized in this invention that the addition of an oxidizer, even in the presence of a stabilizer, can result in polishing rate instability and limited pot life. It has also been observed that oxidants will chemically invade copper and cause undesirable copper corrosion. It has further been observed that the polishing rate identity (parity) between the copper, barrier and dielectric achieved on the pilot wafer may not be achieved on the patterned wafer.

  Therefore, what is needed in copper CMP is a barrier slurry that provides lower defectivity and the desired selectivity for patterned wafers. In one embodiment of the invention, colloidal silica is used in the barrier slurry in place of the fumed silica abrasive material. In another embodiment of the invention, the oxidant is removed from the barrier slurry and the desired selectivity for the patterned wafer is between the abrasive particles (colloidal silica) and the corrosion inhibitor (BTA). This is achieved by controlling the mixing ratio.

  One advantage of the polishing slurry aspect of the present invention is lower defectivity. The use of colloidal silica allows for stronger filtration at the slurry recirculation loop and point of use (POU). A second advantage of the slurry of the present invention is a reduction in unwanted invasion to copper by the barrier slurry. Another advantage of the present invention is the significant improvement in ability and pot life to achieve the desired selectivity for patterned wafers. Yet another advantage of the present invention is the reduction in costs associated with the manufacture and delivery of barrier slurries.

  More specifically, the present invention provides a polishing slurry comprising a dispersing medium, colloidal silicon suspended in the dispersing medium, and a corrosion inhibitor in the polishing slurry medium.

  The present invention also provides a method of polishing a damascene structure using a chemical-mechanical polishing (CMP) apparatus. In addition to the polishing pad, a damascene structure is provided. The polishing slurry is applied to the interface between the damascene structure and the polishing pad. Next, polishing is performed using polishing parameters of the CMP apparatus to remove at least a portion of the metal layer.

For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention, taken together with the accompanying drawings, in which corresponding numerical values in different drawings designate corresponding parts. In the figure,
FIG. 1 is a cross-sectional illustration of a damascene structure prior to copper CMP processing.
FIG. 2 is an illustration of a cross-sectional view of a damascene structure after copper CMP first step, polishing stop on the barrier.
FIG. 3 is a cross-sectional view of the damascene structure after removal of the barrier.
FIG. 4 is a graph showing the removal rate and the dependence of the removal rate on the changing concentration of the composition according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION Although the creation and use of various aspects of the present invention are described in detail below, the present invention can be embodied in a wide variety of specific relationships and many applicable inventive concepts. Should be recognized. The specific embodiments described herein are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

  For simplicity, only one damascene groove structure is illustrated in FIG. The situation is similar for a damascene with only one passage, or a double damascene where the groove and passage are formed together. FIG. 1 is a cross-sectional view of a wafer 10 depicting a conventional damascene structure for a groove. The damascene structure was built on top of an inter-level dielectric layer (ILD) 11. An intra-metal dielectric layer (IMD) 14 is drawn on top of the ILD layer 11. Patterning and etching are performed to make the grooves 16. The barrier layer 18 is deposited as a method for improving the adhesion between the metal layer 12 and the dielectric layer 14. The barrier layer 18 also serves as a diffusion barrier for the metal layer 12. Wafer 10 is coated with a thin conductive layer of copper, called a seed layer, and immersed in a solution containing cupric ions for electroplating. The plated metal layer 12 covers the entire wafer surface 10 and fills the grooves 16.

  A CMP process is then used to remove excess copper and planarize the surface. The copper CMP process is typically a multi-step process. In the first step, a highly selective slurry of copper relative to the barrier is used to remove most or all of the excess copper from the wafer surface. The high selectivity of the copper removal rate relative to the barrier removal rate is designed so that polishing can stop at the barrier layer. Thus, non-uniform electrochemical deposition will not translate into final copper thickness variations.

  FIG. 2 is a cross-sectional view of the damascene structure after the first step of a typical copper CMP process. Typically, after removal of excess copper in the copper layer 12, some of the copper layer disposed within the trench is also removed due to the curvature of the polishing pad. The undesirably thinning of the copper inside the groove, known as “dish dishing”, is shown as a dished depression 20. In the second step of the CMP process, the barrier layer is removed to completely disconnect any undesigned or unintended connections between the wiring in the layer. The slurry used in the barrier removal step is called a barrier slurry, which is typically different from the slurry used in the first step. There are currently two types of barrier slurries: high selectivity slurry (HSS) and low selectivity slurry (LSS). The HSS slurry has a removal rate for the barrier that is higher than the removal rate for the copper and dielectric layers. The LSS slurry polishes copper, dielectric materials and barrier layers at similar rates. A low selectivity slurry polishes away any copper residue remaining from the previous step, providing a relatively wide processing limit. It also planarizes the surface at the expense of dielectric material removal and reduces dishing.

  FIG. 3 is a cross-sectional illustration of a damascene structure after barrier removal using the ESS method. The thinning of the dielectric layer 14 and the reduction of the dish-shaped depression 20 are illustrated. Slurries used for barrier polishing in copper CMP processes need to give patterned wafers lower defects and designed selectivity. The present invention provides such a low defect slurry. In this invention, colloidal silica is used to provide abrasive particles in place of the fumed silica typically used in slurries. The use of colloidal silica reduces the risk of shearing and allows for strong filtration at the slurry recirculation loop and point of use (POU).

  In the prior art, oxidizing agents are typically added to the barrier slurry to increase the polishing rate for copper and to achieve the desired selectivity. One problem with that prior art is that the oxidant decays over time, causing a decrease in the copper polishing rate over time. This will give limited pot life to the mixed slurry. Another problem with that prior art is that the oxidant infiltrates the copper, thereby causing undesirable copper corrosion. A third problem with that prior art is that the slurry polishing rate test was typically performed on a pilot wafer (a blank wafer with no pattern applied).

  The present invention recognizes that the removal rate on the pilot wafer is not necessarily equal to the removal rate on the patterned wafer. It is possible for the barrier slurry to achieve the desired selectivity on the patterned wafer without adding an oxidant.

  In one embodiment of the present invention, the barrier slurry is on the platen with an abrasive component and a BTA component (eg, 330 ppm by weight) of a colloidal silica slurry (eg, Rodel CUSI2OIA, 30% solids) at different mixing ratios. Achieved by on-platen mixing. The mixing ratio is, in one exemplary case, 150 ml / min of the abrasive component and 50 ml / min of the BTA component, and in another exemplary case, 100 ml / min of the abrasive component and 100 ml of the BTA component. And in the third exemplary case, 50 ml / min of the abrasive component and 150 ml / min of the BTA component. The velocity on the pilot wafer is obtained by measuring the difference in thickness before and after polishing. A method for obtaining a polishing rate on a patterned wafer is illustrated in FIG.

  In order to obtain a polishing rate on the patterned wafer, a series of patterned wafers are polished by a primary slurry (eg, Cabot's Microelectronics iCue® 5001) and stopped by an optical endpoint signal. Which indicates that the copper is removed. The wafer was then designed with different polishing times (eg 0.25 minutes (15 seconds), 0.5 minutes (30 seconds), 0.75 minutes (45 seconds) and 1 minute (60 seconds)). It can be polished using a barrier slurry. As illustrated for the exemplary method in FIG. 4, the resulting thickness is measured and plotted against the time polished. In FIG. 4, the horizontal axis is the polishing time in minutes and the vertical axis is the subsequent thickness in angstroms. The slope of the plot represents the removal rate on the patterned wafer in angstroms / minute.

  In another embodiment of the invention, the barrier slurry is premixed from the abrasive and BTA components of a colloidal silica slurry (eg, Rodel CUSI2OIA, 30% solids). The premixed slurry has, for example, 15% solids but has different BTA concentrations (eg, 200 ppm, 800 ppm and 1000 ppm, all by weight).

  Although this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Exemplary aspects of the invention, as well as various modifications and combinations of other aspects, will become apparent to those skilled in the art upon reference to the description. Accordingly, the claims are intended to cover all such modifications or aspects.

The following content is further disclosed regarding the present invention.
(1) Dispersion medium;
Colloidal silica suspended in a dispersion medium; and a corrosion inhibitor in the dispersion medium;
A slurry for polishing.
(2) The polishing slurry according to item (1), wherein the slurry contains no oxidizing agent.
(3) The polishing slurry according to (1) above, wherein a surfactant is added to the slurry.
(4) The polishing slurry according to item (1), wherein the corrosion inhibitor contains benzotriazole.
(5) The polishing slurry according to item (1), comprising about 0.005 to 0.2% by weight of BTA and about 1 to 30% by weight of SiO ₂ .
(6) Prepare damascene structures;
Prepare a polishing pad;
Prepare colloidal silica and corrosion inhibitor;
Applying a polishing slurry to the interface between the damascene structure and the polishing pad; and polishing using polishing parameters of a CMP apparatus, wherein at least a portion of the metal is removed;
A method of polishing a damascene structure using a chemical-mechanical polishing apparatus comprising a step.
(7) The method according to (6) above, wherein the slurry does not contain an oxidizing agent.
(8) The method of the above item (6), wherein a surfactant is added to the slurry.
(9) The method according to item (6), wherein the corrosion inhibitor comprises benzotriazole.
(10) The method of item (6) above, wherein the slurry contains about 0.005 to 0.2% by weight of BTA and about 1 to 30% by weight of SiO ₂ .
(11) A polishing slurry for chemical-mechanical polishing (CMP) processing used in an integrated circuit manufacturing method is disclosed. The slurry of the present invention can contain colloidal silica (SiO ₂ ) as abrasive particles and a corrosion inhibitor (eg, benzotriazole (BTA)). The slurry does not require an antioxidant. The slurry can be used as a barrier slurry in a copper CMP process; and it has similar polishing rates for copper (16), barrier (18) and dielectric material (14) on a patterned wafer (11). . The slurry of the present invention also reduces CMP defects on the polished wafer.

It is a figure which illustrates the cross section of the damascene structure before a copper CMP process. It is a figure which illustrates the cross section of the damascene structure after the 1st process of copper CMP, polishing stop (stop) on a barrier. It is a figure which illustrates the cross section of the damascene structure after barrier removal. 2 is a graph showing the removal rate and the dependence of the removal rate on the changing concentration of the composition according to the invention.

Explanation of symbols

10 Wafer 11 (between horizontal planes) Dielectric layer (ILD)
12 Metal layer 14 (Inside metal) Dielectric layer (IMD)
16 groove 18 barrier layer 20 dish-shaped depression

Claims (2)

Dispersion medium;
Colloidal silica suspended in a dispersion medium; and a corrosion inhibitor in the dispersion medium;
A slurry for polishing. Prepare damascene structures;
Prepare a polishing pad;
Prepare colloidal silica and corrosion inhibitor;
Applying a polishing slurry to the interface between the damascene structure and the polishing pad;
And polishing using polishing parameters of the CMP apparatus, wherein at least a portion of the metal layer is removed;
A method of polishing a damascene structure using a chemical-mechanical polishing apparatus comprising a step.

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